1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 70 71 static int smu_sys_get_pp_feature_mask(void *handle, 72 char *buf) 73 { 74 struct smu_context *smu = handle; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 return smu_get_pp_feature_mask(smu, buf); 80 } 81 82 static int smu_sys_set_pp_feature_mask(void *handle, 83 uint64_t new_mask) 84 { 85 struct smu_context *smu = handle; 86 87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 88 return -EOPNOTSUPP; 89 90 return smu_set_pp_feature_mask(smu, new_mask); 91 } 92 93 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 94 { 95 if (!smu->ppt_funcs->get_gfx_off_status) 96 return -EINVAL; 97 98 *value = smu_get_gfx_off_status(smu); 99 100 return 0; 101 } 102 103 int smu_set_soft_freq_range(struct smu_context *smu, 104 enum smu_clk_type clk_type, 105 uint32_t min, 106 uint32_t max) 107 { 108 int ret = 0; 109 110 if (smu->ppt_funcs->set_soft_freq_limited_range) 111 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 112 clk_type, 113 min, 114 max); 115 116 return ret; 117 } 118 119 int smu_get_dpm_freq_range(struct smu_context *smu, 120 enum smu_clk_type clk_type, 121 uint32_t *min, 122 uint32_t *max) 123 { 124 int ret = -ENOTSUPP; 125 126 if (!min && !max) 127 return -EINVAL; 128 129 if (smu->ppt_funcs->get_dpm_ultimate_freq) 130 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 131 clk_type, 132 min, 133 max); 134 135 return ret; 136 } 137 138 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 139 { 140 if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu) 141 return -EOPNOTSUPP; 142 143 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 144 } 145 146 static u32 smu_get_mclk(void *handle, bool low) 147 { 148 struct smu_context *smu = handle; 149 uint32_t clk_freq; 150 int ret = 0; 151 152 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 153 low ? &clk_freq : NULL, 154 !low ? &clk_freq : NULL); 155 if (ret) 156 return 0; 157 return clk_freq * 100; 158 } 159 160 static u32 smu_get_sclk(void *handle, bool low) 161 { 162 struct smu_context *smu = handle; 163 uint32_t clk_freq; 164 int ret = 0; 165 166 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 167 low ? &clk_freq : NULL, 168 !low ? &clk_freq : NULL); 169 if (ret) 170 return 0; 171 return clk_freq * 100; 172 } 173 174 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 175 bool enable) 176 { 177 struct smu_power_context *smu_power = &smu->smu_power; 178 struct smu_power_gate *power_gate = &smu_power->power_gate; 179 int ret = 0; 180 181 if (!smu->ppt_funcs->dpm_set_vcn_enable) 182 return 0; 183 184 if (atomic_read(&power_gate->vcn_gated) ^ enable) 185 return 0; 186 187 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 188 if (!ret) 189 atomic_set(&power_gate->vcn_gated, !enable); 190 191 return ret; 192 } 193 194 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 195 bool enable) 196 { 197 struct smu_power_context *smu_power = &smu->smu_power; 198 struct smu_power_gate *power_gate = &smu_power->power_gate; 199 int ret = 0; 200 201 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 202 return 0; 203 204 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 205 return 0; 206 207 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 208 if (!ret) 209 atomic_set(&power_gate->jpeg_gated, !enable); 210 211 return ret; 212 } 213 214 /** 215 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 216 * 217 * @handle: smu_context pointer 218 * @block_type: the IP block to power gate/ungate 219 * @gate: to power gate if true, ungate otherwise 220 * 221 * This API uses no smu->mutex lock protection due to: 222 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 223 * This is guarded to be race condition free by the caller. 224 * 2. Or get called on user setting request of power_dpm_force_performance_level. 225 * Under this case, the smu->mutex lock protection is already enforced on 226 * the parent API smu_force_performance_level of the call path. 227 */ 228 static int smu_dpm_set_power_gate(void *handle, 229 uint32_t block_type, 230 bool gate) 231 { 232 struct smu_context *smu = handle; 233 int ret = 0; 234 235 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 236 dev_WARN(smu->adev->dev, 237 "SMU uninitialized but power %s requested for %u!\n", 238 gate ? "gate" : "ungate", block_type); 239 return -EOPNOTSUPP; 240 } 241 242 switch (block_type) { 243 /* 244 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 245 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 246 */ 247 case AMD_IP_BLOCK_TYPE_UVD: 248 case AMD_IP_BLOCK_TYPE_VCN: 249 ret = smu_dpm_set_vcn_enable(smu, !gate); 250 if (ret) 251 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 252 gate ? "gate" : "ungate"); 253 break; 254 case AMD_IP_BLOCK_TYPE_GFX: 255 ret = smu_gfx_off_control(smu, gate); 256 if (ret) 257 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 258 gate ? "enable" : "disable"); 259 break; 260 case AMD_IP_BLOCK_TYPE_SDMA: 261 ret = smu_powergate_sdma(smu, gate); 262 if (ret) 263 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 264 gate ? "gate" : "ungate"); 265 break; 266 case AMD_IP_BLOCK_TYPE_JPEG: 267 ret = smu_dpm_set_jpeg_enable(smu, !gate); 268 if (ret) 269 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 270 gate ? "gate" : "ungate"); 271 break; 272 default: 273 dev_err(smu->adev->dev, "Unsupported block type!\n"); 274 return -EINVAL; 275 } 276 277 return ret; 278 } 279 280 /** 281 * smu_set_user_clk_dependencies - set user profile clock dependencies 282 * 283 * @smu: smu_context pointer 284 * @clk: enum smu_clk_type type 285 * 286 * Enable/Disable the clock dependency for the @clk type. 287 */ 288 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 289 { 290 if (smu->adev->in_suspend) 291 return; 292 293 if (clk == SMU_MCLK) { 294 smu->user_dpm_profile.clk_dependency = 0; 295 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 296 } else if (clk == SMU_FCLK) { 297 /* MCLK takes precedence over FCLK */ 298 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 299 return; 300 301 smu->user_dpm_profile.clk_dependency = 0; 302 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 303 } else if (clk == SMU_SOCCLK) { 304 /* MCLK takes precedence over SOCCLK */ 305 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 306 return; 307 308 smu->user_dpm_profile.clk_dependency = 0; 309 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 310 } else 311 /* Add clk dependencies here, if any */ 312 return; 313 } 314 315 /** 316 * smu_restore_dpm_user_profile - reinstate user dpm profile 317 * 318 * @smu: smu_context pointer 319 * 320 * Restore the saved user power configurations include power limit, 321 * clock frequencies, fan control mode and fan speed. 322 */ 323 static void smu_restore_dpm_user_profile(struct smu_context *smu) 324 { 325 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 326 int ret = 0; 327 328 if (!smu->adev->in_suspend) 329 return; 330 331 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 332 return; 333 334 /* Enable restore flag */ 335 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 336 337 /* set the user dpm power limit */ 338 if (smu->user_dpm_profile.power_limit) { 339 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 340 if (ret) 341 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 342 } 343 344 /* set the user dpm clock configurations */ 345 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 346 enum smu_clk_type clk_type; 347 348 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 349 /* 350 * Iterate over smu clk type and force the saved user clk 351 * configs, skip if clock dependency is enabled 352 */ 353 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 354 smu->user_dpm_profile.clk_mask[clk_type]) { 355 ret = smu_force_smuclk_levels(smu, clk_type, 356 smu->user_dpm_profile.clk_mask[clk_type]); 357 if (ret) 358 dev_err(smu->adev->dev, 359 "Failed to set clock type = %d\n", clk_type); 360 } 361 } 362 } 363 364 /* set the user dpm fan configurations */ 365 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 366 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 367 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 368 if (ret != -EOPNOTSUPP) { 369 smu->user_dpm_profile.fan_speed_pwm = 0; 370 smu->user_dpm_profile.fan_speed_rpm = 0; 371 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 372 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 373 } 374 375 if (smu->user_dpm_profile.fan_speed_pwm) { 376 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 377 if (ret != -EOPNOTSUPP) 378 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 379 } 380 381 if (smu->user_dpm_profile.fan_speed_rpm) { 382 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 383 if (ret != -EOPNOTSUPP) 384 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 385 } 386 } 387 388 /* Restore user customized OD settings */ 389 if (smu->user_dpm_profile.user_od) { 390 if (smu->ppt_funcs->restore_user_od_settings) { 391 ret = smu->ppt_funcs->restore_user_od_settings(smu); 392 if (ret) 393 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 394 } 395 } 396 397 /* Disable restore flag */ 398 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 399 } 400 401 static int smu_get_power_num_states(void *handle, 402 struct pp_states_info *state_info) 403 { 404 if (!state_info) 405 return -EINVAL; 406 407 /* not support power state */ 408 memset(state_info, 0, sizeof(struct pp_states_info)); 409 state_info->nums = 1; 410 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 411 412 return 0; 413 } 414 415 bool is_support_sw_smu(struct amdgpu_device *adev) 416 { 417 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 418 if (adev->asic_type == CHIP_VEGA20) 419 return false; 420 421 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 422 return true; 423 424 return false; 425 } 426 427 bool is_support_cclk_dpm(struct amdgpu_device *adev) 428 { 429 struct smu_context *smu = adev->powerplay.pp_handle; 430 431 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 432 return false; 433 434 return true; 435 } 436 437 438 static int smu_sys_get_pp_table(void *handle, 439 char **table) 440 { 441 struct smu_context *smu = handle; 442 struct smu_table_context *smu_table = &smu->smu_table; 443 444 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 445 return -EOPNOTSUPP; 446 447 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 448 return -EINVAL; 449 450 if (smu_table->hardcode_pptable) 451 *table = smu_table->hardcode_pptable; 452 else 453 *table = smu_table->power_play_table; 454 455 return smu_table->power_play_table_size; 456 } 457 458 static int smu_sys_set_pp_table(void *handle, 459 const char *buf, 460 size_t size) 461 { 462 struct smu_context *smu = handle; 463 struct smu_table_context *smu_table = &smu->smu_table; 464 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 465 int ret = 0; 466 467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 468 return -EOPNOTSUPP; 469 470 if (header->usStructureSize != size) { 471 dev_err(smu->adev->dev, "pp table size not matched !\n"); 472 return -EIO; 473 } 474 475 if (!smu_table->hardcode_pptable) { 476 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 477 if (!smu_table->hardcode_pptable) 478 return -ENOMEM; 479 } 480 481 memcpy(smu_table->hardcode_pptable, buf, size); 482 smu_table->power_play_table = smu_table->hardcode_pptable; 483 smu_table->power_play_table_size = size; 484 485 /* 486 * Special hw_fini action(for Navi1x, the DPMs disablement will be 487 * skipped) may be needed for custom pptable uploading. 488 */ 489 smu->uploading_custom_pp_table = true; 490 491 ret = smu_reset(smu); 492 if (ret) 493 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 494 495 smu->uploading_custom_pp_table = false; 496 497 return ret; 498 } 499 500 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 501 { 502 struct smu_feature *feature = &smu->smu_feature; 503 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 504 int ret = 0; 505 506 /* 507 * With SCPM enabled, the allowed featuremasks setting(via 508 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 509 * That means there is no way to let PMFW knows the settings below. 510 * Thus, we just assume all the features are allowed under 511 * such scenario. 512 */ 513 if (smu->adev->scpm_enabled) { 514 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 515 return 0; 516 } 517 518 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 519 520 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 521 SMU_FEATURE_MAX/32); 522 if (ret) 523 return ret; 524 525 bitmap_or(feature->allowed, feature->allowed, 526 (unsigned long *)allowed_feature_mask, 527 feature->feature_num); 528 529 return ret; 530 } 531 532 static int smu_set_funcs(struct amdgpu_device *adev) 533 { 534 struct smu_context *smu = adev->powerplay.pp_handle; 535 536 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 537 smu->od_enabled = true; 538 539 switch (adev->ip_versions[MP1_HWIP][0]) { 540 case IP_VERSION(11, 0, 0): 541 case IP_VERSION(11, 0, 5): 542 case IP_VERSION(11, 0, 9): 543 navi10_set_ppt_funcs(smu); 544 break; 545 case IP_VERSION(11, 0, 7): 546 case IP_VERSION(11, 0, 11): 547 case IP_VERSION(11, 0, 12): 548 case IP_VERSION(11, 0, 13): 549 sienna_cichlid_set_ppt_funcs(smu); 550 break; 551 case IP_VERSION(12, 0, 0): 552 case IP_VERSION(12, 0, 1): 553 renoir_set_ppt_funcs(smu); 554 break; 555 case IP_VERSION(11, 5, 0): 556 vangogh_set_ppt_funcs(smu); 557 break; 558 case IP_VERSION(13, 0, 1): 559 case IP_VERSION(13, 0, 3): 560 case IP_VERSION(13, 0, 8): 561 yellow_carp_set_ppt_funcs(smu); 562 break; 563 case IP_VERSION(13, 0, 4): 564 smu_v13_0_4_set_ppt_funcs(smu); 565 break; 566 case IP_VERSION(13, 0, 5): 567 smu_v13_0_5_set_ppt_funcs(smu); 568 break; 569 case IP_VERSION(11, 0, 8): 570 cyan_skillfish_set_ppt_funcs(smu); 571 break; 572 case IP_VERSION(11, 0, 2): 573 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 574 arcturus_set_ppt_funcs(smu); 575 /* OD is not supported on Arcturus */ 576 smu->od_enabled =false; 577 break; 578 case IP_VERSION(13, 0, 2): 579 aldebaran_set_ppt_funcs(smu); 580 /* Enable pp_od_clk_voltage node */ 581 smu->od_enabled = true; 582 break; 583 case IP_VERSION(13, 0, 0): 584 smu_v13_0_0_set_ppt_funcs(smu); 585 break; 586 case IP_VERSION(13, 0, 7): 587 smu_v13_0_7_set_ppt_funcs(smu); 588 break; 589 default: 590 return -EINVAL; 591 } 592 593 return 0; 594 } 595 596 static int smu_early_init(void *handle) 597 { 598 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 599 struct smu_context *smu; 600 601 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 602 if (!smu) 603 return -ENOMEM; 604 605 smu->adev = adev; 606 smu->pm_enabled = !!amdgpu_dpm; 607 smu->is_apu = false; 608 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 609 smu->smu_baco.platform_support = false; 610 smu->user_dpm_profile.fan_mode = -1; 611 612 mutex_init(&smu->message_lock); 613 614 adev->powerplay.pp_handle = smu; 615 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 616 617 return smu_set_funcs(adev); 618 } 619 620 static int smu_set_default_dpm_table(struct smu_context *smu) 621 { 622 struct smu_power_context *smu_power = &smu->smu_power; 623 struct smu_power_gate *power_gate = &smu_power->power_gate; 624 int vcn_gate, jpeg_gate; 625 int ret = 0; 626 627 if (!smu->ppt_funcs->set_default_dpm_table) 628 return 0; 629 630 vcn_gate = atomic_read(&power_gate->vcn_gated); 631 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 632 633 ret = smu_dpm_set_vcn_enable(smu, true); 634 if (ret) 635 return ret; 636 637 ret = smu_dpm_set_jpeg_enable(smu, true); 638 if (ret) 639 goto err_out; 640 641 ret = smu->ppt_funcs->set_default_dpm_table(smu); 642 if (ret) 643 dev_err(smu->adev->dev, 644 "Failed to setup default dpm clock tables!\n"); 645 646 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 647 err_out: 648 smu_dpm_set_vcn_enable(smu, !vcn_gate); 649 return ret; 650 } 651 652 static int smu_apply_default_config_table_settings(struct smu_context *smu) 653 { 654 struct amdgpu_device *adev = smu->adev; 655 int ret = 0; 656 657 ret = smu_get_default_config_table_settings(smu, 658 &adev->pm.config_table); 659 if (ret) 660 return ret; 661 662 return smu_set_config_table(smu, &adev->pm.config_table); 663 } 664 665 static int smu_late_init(void *handle) 666 { 667 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 668 struct smu_context *smu = adev->powerplay.pp_handle; 669 int ret = 0; 670 671 smu_set_fine_grain_gfx_freq_parameters(smu); 672 673 if (!smu->pm_enabled) 674 return 0; 675 676 ret = smu_post_init(smu); 677 if (ret) { 678 dev_err(adev->dev, "Failed to post smu init!\n"); 679 return ret; 680 } 681 682 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 683 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 684 return 0; 685 686 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 687 ret = smu_set_default_od_settings(smu); 688 if (ret) { 689 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 690 return ret; 691 } 692 } 693 694 ret = smu_populate_umd_state_clk(smu); 695 if (ret) { 696 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 697 return ret; 698 } 699 700 ret = smu_get_asic_power_limits(smu, 701 &smu->current_power_limit, 702 &smu->default_power_limit, 703 &smu->max_power_limit); 704 if (ret) { 705 dev_err(adev->dev, "Failed to get asic power limits!\n"); 706 return ret; 707 } 708 709 if (!amdgpu_sriov_vf(adev)) 710 smu_get_unique_id(smu); 711 712 smu_get_fan_parameters(smu); 713 714 smu_handle_task(smu, 715 smu->smu_dpm.dpm_level, 716 AMD_PP_TASK_COMPLETE_INIT); 717 718 ret = smu_apply_default_config_table_settings(smu); 719 if (ret && (ret != -EOPNOTSUPP)) { 720 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 721 return ret; 722 } 723 724 smu_restore_dpm_user_profile(smu); 725 726 return 0; 727 } 728 729 static int smu_init_fb_allocations(struct smu_context *smu) 730 { 731 struct amdgpu_device *adev = smu->adev; 732 struct smu_table_context *smu_table = &smu->smu_table; 733 struct smu_table *tables = smu_table->tables; 734 struct smu_table *driver_table = &(smu_table->driver_table); 735 uint32_t max_table_size = 0; 736 int ret, i; 737 738 /* VRAM allocation for tool table */ 739 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 740 ret = amdgpu_bo_create_kernel(adev, 741 tables[SMU_TABLE_PMSTATUSLOG].size, 742 tables[SMU_TABLE_PMSTATUSLOG].align, 743 tables[SMU_TABLE_PMSTATUSLOG].domain, 744 &tables[SMU_TABLE_PMSTATUSLOG].bo, 745 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 746 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 747 if (ret) { 748 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 749 return ret; 750 } 751 } 752 753 /* VRAM allocation for driver table */ 754 for (i = 0; i < SMU_TABLE_COUNT; i++) { 755 if (tables[i].size == 0) 756 continue; 757 758 if (i == SMU_TABLE_PMSTATUSLOG) 759 continue; 760 761 if (max_table_size < tables[i].size) 762 max_table_size = tables[i].size; 763 } 764 765 driver_table->size = max_table_size; 766 driver_table->align = PAGE_SIZE; 767 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 768 769 ret = amdgpu_bo_create_kernel(adev, 770 driver_table->size, 771 driver_table->align, 772 driver_table->domain, 773 &driver_table->bo, 774 &driver_table->mc_address, 775 &driver_table->cpu_addr); 776 if (ret) { 777 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 778 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 779 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 780 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 781 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 782 } 783 784 return ret; 785 } 786 787 static int smu_fini_fb_allocations(struct smu_context *smu) 788 { 789 struct smu_table_context *smu_table = &smu->smu_table; 790 struct smu_table *tables = smu_table->tables; 791 struct smu_table *driver_table = &(smu_table->driver_table); 792 793 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 794 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 795 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 796 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 797 798 amdgpu_bo_free_kernel(&driver_table->bo, 799 &driver_table->mc_address, 800 &driver_table->cpu_addr); 801 802 return 0; 803 } 804 805 /** 806 * smu_alloc_memory_pool - allocate memory pool in the system memory 807 * 808 * @smu: amdgpu_device pointer 809 * 810 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 811 * and DramLogSetDramAddr can notify it changed. 812 * 813 * Returns 0 on success, error on failure. 814 */ 815 static int smu_alloc_memory_pool(struct smu_context *smu) 816 { 817 struct amdgpu_device *adev = smu->adev; 818 struct smu_table_context *smu_table = &smu->smu_table; 819 struct smu_table *memory_pool = &smu_table->memory_pool; 820 uint64_t pool_size = smu->pool_size; 821 int ret = 0; 822 823 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 824 return ret; 825 826 memory_pool->size = pool_size; 827 memory_pool->align = PAGE_SIZE; 828 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 829 830 switch (pool_size) { 831 case SMU_MEMORY_POOL_SIZE_256_MB: 832 case SMU_MEMORY_POOL_SIZE_512_MB: 833 case SMU_MEMORY_POOL_SIZE_1_GB: 834 case SMU_MEMORY_POOL_SIZE_2_GB: 835 ret = amdgpu_bo_create_kernel(adev, 836 memory_pool->size, 837 memory_pool->align, 838 memory_pool->domain, 839 &memory_pool->bo, 840 &memory_pool->mc_address, 841 &memory_pool->cpu_addr); 842 if (ret) 843 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 844 break; 845 default: 846 break; 847 } 848 849 return ret; 850 } 851 852 static int smu_free_memory_pool(struct smu_context *smu) 853 { 854 struct smu_table_context *smu_table = &smu->smu_table; 855 struct smu_table *memory_pool = &smu_table->memory_pool; 856 857 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 858 return 0; 859 860 amdgpu_bo_free_kernel(&memory_pool->bo, 861 &memory_pool->mc_address, 862 &memory_pool->cpu_addr); 863 864 memset(memory_pool, 0, sizeof(struct smu_table)); 865 866 return 0; 867 } 868 869 static int smu_alloc_dummy_read_table(struct smu_context *smu) 870 { 871 struct smu_table_context *smu_table = &smu->smu_table; 872 struct smu_table *dummy_read_1_table = 873 &smu_table->dummy_read_1_table; 874 struct amdgpu_device *adev = smu->adev; 875 int ret = 0; 876 877 dummy_read_1_table->size = 0x40000; 878 dummy_read_1_table->align = PAGE_SIZE; 879 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 880 881 ret = amdgpu_bo_create_kernel(adev, 882 dummy_read_1_table->size, 883 dummy_read_1_table->align, 884 dummy_read_1_table->domain, 885 &dummy_read_1_table->bo, 886 &dummy_read_1_table->mc_address, 887 &dummy_read_1_table->cpu_addr); 888 if (ret) 889 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 890 891 return ret; 892 } 893 894 static void smu_free_dummy_read_table(struct smu_context *smu) 895 { 896 struct smu_table_context *smu_table = &smu->smu_table; 897 struct smu_table *dummy_read_1_table = 898 &smu_table->dummy_read_1_table; 899 900 901 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 902 &dummy_read_1_table->mc_address, 903 &dummy_read_1_table->cpu_addr); 904 905 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 906 } 907 908 static int smu_smc_table_sw_init(struct smu_context *smu) 909 { 910 int ret; 911 912 /** 913 * Create smu_table structure, and init smc tables such as 914 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 915 */ 916 ret = smu_init_smc_tables(smu); 917 if (ret) { 918 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 919 return ret; 920 } 921 922 /** 923 * Create smu_power_context structure, and allocate smu_dpm_context and 924 * context size to fill the smu_power_context data. 925 */ 926 ret = smu_init_power(smu); 927 if (ret) { 928 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 929 return ret; 930 } 931 932 /* 933 * allocate vram bos to store smc table contents. 934 */ 935 ret = smu_init_fb_allocations(smu); 936 if (ret) 937 return ret; 938 939 ret = smu_alloc_memory_pool(smu); 940 if (ret) 941 return ret; 942 943 ret = smu_alloc_dummy_read_table(smu); 944 if (ret) 945 return ret; 946 947 ret = smu_i2c_init(smu); 948 if (ret) 949 return ret; 950 951 return 0; 952 } 953 954 static int smu_smc_table_sw_fini(struct smu_context *smu) 955 { 956 int ret; 957 958 smu_i2c_fini(smu); 959 960 smu_free_dummy_read_table(smu); 961 962 ret = smu_free_memory_pool(smu); 963 if (ret) 964 return ret; 965 966 ret = smu_fini_fb_allocations(smu); 967 if (ret) 968 return ret; 969 970 ret = smu_fini_power(smu); 971 if (ret) { 972 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 973 return ret; 974 } 975 976 ret = smu_fini_smc_tables(smu); 977 if (ret) { 978 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 979 return ret; 980 } 981 982 return 0; 983 } 984 985 static void smu_throttling_logging_work_fn(struct work_struct *work) 986 { 987 struct smu_context *smu = container_of(work, struct smu_context, 988 throttling_logging_work); 989 990 smu_log_thermal_throttling(smu); 991 } 992 993 static void smu_interrupt_work_fn(struct work_struct *work) 994 { 995 struct smu_context *smu = container_of(work, struct smu_context, 996 interrupt_work); 997 998 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 999 smu->ppt_funcs->interrupt_work(smu); 1000 } 1001 1002 static int smu_sw_init(void *handle) 1003 { 1004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1005 struct smu_context *smu = adev->powerplay.pp_handle; 1006 int ret; 1007 1008 smu->pool_size = adev->pm.smu_prv_buffer_size; 1009 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1010 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1011 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1012 1013 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1014 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1015 atomic64_set(&smu->throttle_int_counter, 0); 1016 smu->watermarks_bitmap = 0; 1017 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1018 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1019 1020 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1021 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1022 1023 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1024 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1025 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1026 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1027 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1028 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1029 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1030 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1031 1032 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1033 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1034 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1035 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1036 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1037 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1038 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1039 smu->display_config = &adev->pm.pm_display_cfg; 1040 1041 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1042 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1043 1044 ret = smu_init_microcode(smu); 1045 if (ret) { 1046 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1047 return ret; 1048 } 1049 1050 ret = smu_smc_table_sw_init(smu); 1051 if (ret) { 1052 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1053 return ret; 1054 } 1055 1056 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1057 ret = smu_get_vbios_bootup_values(smu); 1058 if (ret) { 1059 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1060 return ret; 1061 } 1062 1063 ret = smu_init_pptable_microcode(smu); 1064 if (ret) { 1065 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1066 return ret; 1067 } 1068 1069 ret = smu_register_irq_handler(smu); 1070 if (ret) { 1071 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1072 return ret; 1073 } 1074 1075 /* If there is no way to query fan control mode, fan control is not supported */ 1076 if (!smu->ppt_funcs->get_fan_control_mode) 1077 smu->adev->pm.no_fan = true; 1078 1079 return 0; 1080 } 1081 1082 static int smu_sw_fini(void *handle) 1083 { 1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1085 struct smu_context *smu = adev->powerplay.pp_handle; 1086 int ret; 1087 1088 ret = smu_smc_table_sw_fini(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1091 return ret; 1092 } 1093 1094 smu_fini_microcode(smu); 1095 1096 return 0; 1097 } 1098 1099 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1100 { 1101 struct amdgpu_device *adev = smu->adev; 1102 struct smu_temperature_range *range = 1103 &smu->thermal_range; 1104 int ret = 0; 1105 1106 if (!smu->ppt_funcs->get_thermal_temperature_range) 1107 return 0; 1108 1109 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1110 if (ret) 1111 return ret; 1112 1113 adev->pm.dpm.thermal.min_temp = range->min; 1114 adev->pm.dpm.thermal.max_temp = range->max; 1115 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1116 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1117 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1118 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1119 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1120 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1121 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1122 1123 return ret; 1124 } 1125 1126 static int smu_smc_hw_setup(struct smu_context *smu) 1127 { 1128 struct smu_feature *feature = &smu->smu_feature; 1129 struct amdgpu_device *adev = smu->adev; 1130 uint32_t pcie_gen = 0, pcie_width = 0; 1131 uint64_t features_supported; 1132 int ret = 0; 1133 1134 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1135 dev_info(adev->dev, "dpm has been enabled\n"); 1136 /* this is needed specifically */ 1137 switch (adev->ip_versions[MP1_HWIP][0]) { 1138 case IP_VERSION(11, 0, 7): 1139 case IP_VERSION(11, 0, 11): 1140 case IP_VERSION(11, 5, 0): 1141 case IP_VERSION(11, 0, 12): 1142 ret = smu_system_features_control(smu, true); 1143 if (ret) 1144 dev_err(adev->dev, "Failed system features control!\n"); 1145 break; 1146 default: 1147 break; 1148 } 1149 return ret; 1150 } 1151 1152 ret = smu_init_display_count(smu, 0); 1153 if (ret) { 1154 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1155 return ret; 1156 } 1157 1158 ret = smu_set_driver_table_location(smu); 1159 if (ret) { 1160 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1161 return ret; 1162 } 1163 1164 /* 1165 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1166 */ 1167 ret = smu_set_tool_table_location(smu); 1168 if (ret) { 1169 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1170 return ret; 1171 } 1172 1173 /* 1174 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1175 * pool location. 1176 */ 1177 ret = smu_notify_memory_pool_location(smu); 1178 if (ret) { 1179 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1180 return ret; 1181 } 1182 1183 ret = smu_setup_pptable(smu); 1184 if (ret) { 1185 dev_err(adev->dev, "Failed to setup pptable!\n"); 1186 return ret; 1187 } 1188 1189 /* smu_dump_pptable(smu); */ 1190 1191 /* 1192 * With SCPM enabled, PSP is responsible for the PPTable transferring 1193 * (to SMU). Driver involvement is not needed and permitted. 1194 */ 1195 if (!adev->scpm_enabled) { 1196 /* 1197 * Copy pptable bo in the vram to smc with SMU MSGs such as 1198 * SetDriverDramAddr and TransferTableDram2Smu. 1199 */ 1200 ret = smu_write_pptable(smu); 1201 if (ret) { 1202 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1203 return ret; 1204 } 1205 } 1206 1207 /* issue Run*Btc msg */ 1208 ret = smu_run_btc(smu); 1209 if (ret) 1210 return ret; 1211 1212 /* 1213 * With SCPM enabled, these actions(and relevant messages) are 1214 * not needed and permitted. 1215 */ 1216 if (!adev->scpm_enabled) { 1217 ret = smu_feature_set_allowed_mask(smu); 1218 if (ret) { 1219 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1220 return ret; 1221 } 1222 } 1223 1224 ret = smu_system_features_control(smu, true); 1225 if (ret) { 1226 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1227 return ret; 1228 } 1229 1230 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1231 if (ret) { 1232 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1233 return ret; 1234 } 1235 bitmap_copy(feature->supported, 1236 (unsigned long *)&features_supported, 1237 feature->feature_num); 1238 1239 if (!smu_is_dpm_running(smu)) 1240 dev_info(adev->dev, "dpm has been disabled\n"); 1241 1242 /* 1243 * Set initialized values (get from vbios) to dpm tables context such as 1244 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1245 * type of clks. 1246 */ 1247 ret = smu_set_default_dpm_table(smu); 1248 if (ret) { 1249 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1250 return ret; 1251 } 1252 1253 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1254 pcie_gen = 3; 1255 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1256 pcie_gen = 2; 1257 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1258 pcie_gen = 1; 1259 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1260 pcie_gen = 0; 1261 1262 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1263 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1264 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1265 */ 1266 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1267 pcie_width = 6; 1268 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1269 pcie_width = 5; 1270 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1271 pcie_width = 4; 1272 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1273 pcie_width = 3; 1274 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1275 pcie_width = 2; 1276 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1277 pcie_width = 1; 1278 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1279 if (ret) { 1280 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1281 return ret; 1282 } 1283 1284 ret = smu_get_thermal_temperature_range(smu); 1285 if (ret) { 1286 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1287 return ret; 1288 } 1289 1290 ret = smu_enable_thermal_alert(smu); 1291 if (ret) { 1292 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1293 return ret; 1294 } 1295 1296 ret = smu_notify_display_change(smu); 1297 if (ret) { 1298 dev_err(adev->dev, "Failed to notify display change!\n"); 1299 return ret; 1300 } 1301 1302 /* 1303 * Set min deep sleep dce fclk with bootup value from vbios via 1304 * SetMinDeepSleepDcefclk MSG. 1305 */ 1306 ret = smu_set_min_dcef_deep_sleep(smu, 1307 smu->smu_table.boot_values.dcefclk / 100); 1308 1309 return ret; 1310 } 1311 1312 static int smu_start_smc_engine(struct smu_context *smu) 1313 { 1314 struct amdgpu_device *adev = smu->adev; 1315 int ret = 0; 1316 1317 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1318 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1319 if (smu->ppt_funcs->load_microcode) { 1320 ret = smu->ppt_funcs->load_microcode(smu); 1321 if (ret) 1322 return ret; 1323 } 1324 } 1325 } 1326 1327 if (smu->ppt_funcs->check_fw_status) { 1328 ret = smu->ppt_funcs->check_fw_status(smu); 1329 if (ret) { 1330 dev_err(adev->dev, "SMC is not ready\n"); 1331 return ret; 1332 } 1333 } 1334 1335 /* 1336 * Send msg GetDriverIfVersion to check if the return value is equal 1337 * with DRIVER_IF_VERSION of smc header. 1338 */ 1339 ret = smu_check_fw_version(smu); 1340 if (ret) 1341 return ret; 1342 1343 return ret; 1344 } 1345 1346 static int smu_hw_init(void *handle) 1347 { 1348 int ret; 1349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1350 struct smu_context *smu = adev->powerplay.pp_handle; 1351 1352 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1353 smu->pm_enabled = false; 1354 return 0; 1355 } 1356 1357 ret = smu_start_smc_engine(smu); 1358 if (ret) { 1359 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1360 return ret; 1361 } 1362 1363 if (smu->is_apu) { 1364 smu_dpm_set_vcn_enable(smu, true); 1365 smu_dpm_set_jpeg_enable(smu, true); 1366 smu_set_gfx_cgpg(smu, true); 1367 } 1368 1369 if (!smu->pm_enabled) 1370 return 0; 1371 1372 ret = smu_get_driver_allowed_feature_mask(smu); 1373 if (ret) 1374 return ret; 1375 1376 ret = smu_smc_hw_setup(smu); 1377 if (ret) { 1378 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1379 return ret; 1380 } 1381 1382 /* 1383 * Move maximum sustainable clock retrieving here considering 1384 * 1. It is not needed on resume(from S3). 1385 * 2. DAL settings come between .hw_init and .late_init of SMU. 1386 * And DAL needs to know the maximum sustainable clocks. Thus 1387 * it cannot be put in .late_init(). 1388 */ 1389 ret = smu_init_max_sustainable_clocks(smu); 1390 if (ret) { 1391 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1392 return ret; 1393 } 1394 1395 adev->pm.dpm_enabled = true; 1396 1397 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1398 1399 return 0; 1400 } 1401 1402 static int smu_disable_dpms(struct smu_context *smu) 1403 { 1404 struct amdgpu_device *adev = smu->adev; 1405 int ret = 0; 1406 bool use_baco = !smu->is_apu && 1407 ((amdgpu_in_reset(adev) && 1408 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1409 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1410 1411 /* 1412 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1413 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1414 */ 1415 switch (adev->ip_versions[MP1_HWIP][0]) { 1416 case IP_VERSION(13, 0, 0): 1417 case IP_VERSION(13, 0, 7): 1418 return 0; 1419 default: 1420 break; 1421 } 1422 1423 /* 1424 * For custom pptable uploading, skip the DPM features 1425 * disable process on Navi1x ASICs. 1426 * - As the gfx related features are under control of 1427 * RLC on those ASICs. RLC reinitialization will be 1428 * needed to reenable them. That will cost much more 1429 * efforts. 1430 * 1431 * - SMU firmware can handle the DPM reenablement 1432 * properly. 1433 */ 1434 if (smu->uploading_custom_pp_table) { 1435 switch (adev->ip_versions[MP1_HWIP][0]) { 1436 case IP_VERSION(11, 0, 0): 1437 case IP_VERSION(11, 0, 5): 1438 case IP_VERSION(11, 0, 9): 1439 case IP_VERSION(11, 0, 7): 1440 case IP_VERSION(11, 0, 11): 1441 case IP_VERSION(11, 5, 0): 1442 case IP_VERSION(11, 0, 12): 1443 case IP_VERSION(11, 0, 13): 1444 return 0; 1445 default: 1446 break; 1447 } 1448 } 1449 1450 /* 1451 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1452 * on BACO in. Driver involvement is unnecessary. 1453 */ 1454 if (use_baco) { 1455 switch (adev->ip_versions[MP1_HWIP][0]) { 1456 case IP_VERSION(11, 0, 7): 1457 case IP_VERSION(11, 0, 0): 1458 case IP_VERSION(11, 0, 5): 1459 case IP_VERSION(11, 0, 9): 1460 case IP_VERSION(13, 0, 7): 1461 return 0; 1462 default: 1463 break; 1464 } 1465 } 1466 1467 /* 1468 * For gpu reset, runpm and hibernation through BACO, 1469 * BACO feature has to be kept enabled. 1470 */ 1471 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1472 ret = smu_disable_all_features_with_exception(smu, 1473 SMU_FEATURE_BACO_BIT); 1474 if (ret) 1475 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1476 } else { 1477 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1478 if (!adev->scpm_enabled) { 1479 ret = smu_system_features_control(smu, false); 1480 if (ret) 1481 dev_err(adev->dev, "Failed to disable smu features.\n"); 1482 } 1483 } 1484 1485 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1486 adev->gfx.rlc.funcs->stop) 1487 adev->gfx.rlc.funcs->stop(adev); 1488 1489 return ret; 1490 } 1491 1492 static int smu_smc_hw_cleanup(struct smu_context *smu) 1493 { 1494 struct amdgpu_device *adev = smu->adev; 1495 int ret = 0; 1496 1497 cancel_work_sync(&smu->throttling_logging_work); 1498 cancel_work_sync(&smu->interrupt_work); 1499 1500 ret = smu_disable_thermal_alert(smu); 1501 if (ret) { 1502 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1503 return ret; 1504 } 1505 1506 ret = smu_disable_dpms(smu); 1507 if (ret) { 1508 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1509 return ret; 1510 } 1511 1512 return 0; 1513 } 1514 1515 static int smu_hw_fini(void *handle) 1516 { 1517 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1518 struct smu_context *smu = adev->powerplay.pp_handle; 1519 1520 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1521 return 0; 1522 1523 smu_dpm_set_vcn_enable(smu, false); 1524 smu_dpm_set_jpeg_enable(smu, false); 1525 1526 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1527 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1528 1529 if (!smu->pm_enabled) 1530 return 0; 1531 1532 adev->pm.dpm_enabled = false; 1533 1534 return smu_smc_hw_cleanup(smu); 1535 } 1536 1537 static void smu_late_fini(void *handle) 1538 { 1539 struct amdgpu_device *adev = handle; 1540 struct smu_context *smu = adev->powerplay.pp_handle; 1541 1542 kfree(smu); 1543 } 1544 1545 static int smu_reset(struct smu_context *smu) 1546 { 1547 struct amdgpu_device *adev = smu->adev; 1548 int ret; 1549 1550 ret = smu_hw_fini(adev); 1551 if (ret) 1552 return ret; 1553 1554 ret = smu_hw_init(adev); 1555 if (ret) 1556 return ret; 1557 1558 ret = smu_late_init(adev); 1559 if (ret) 1560 return ret; 1561 1562 return 0; 1563 } 1564 1565 static int smu_suspend(void *handle) 1566 { 1567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1568 struct smu_context *smu = adev->powerplay.pp_handle; 1569 int ret; 1570 1571 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1572 return 0; 1573 1574 if (!smu->pm_enabled) 1575 return 0; 1576 1577 adev->pm.dpm_enabled = false; 1578 1579 ret = smu_smc_hw_cleanup(smu); 1580 if (ret) 1581 return ret; 1582 1583 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1584 1585 smu_set_gfx_cgpg(smu, false); 1586 1587 return 0; 1588 } 1589 1590 static int smu_resume(void *handle) 1591 { 1592 int ret; 1593 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1594 struct smu_context *smu = adev->powerplay.pp_handle; 1595 1596 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1597 return 0; 1598 1599 if (!smu->pm_enabled) 1600 return 0; 1601 1602 dev_info(adev->dev, "SMU is resuming...\n"); 1603 1604 ret = smu_start_smc_engine(smu); 1605 if (ret) { 1606 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1607 return ret; 1608 } 1609 1610 ret = smu_smc_hw_setup(smu); 1611 if (ret) { 1612 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1613 return ret; 1614 } 1615 1616 smu_set_gfx_cgpg(smu, true); 1617 1618 smu->disable_uclk_switch = 0; 1619 1620 adev->pm.dpm_enabled = true; 1621 1622 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1623 1624 return 0; 1625 } 1626 1627 static int smu_display_configuration_change(void *handle, 1628 const struct amd_pp_display_configuration *display_config) 1629 { 1630 struct smu_context *smu = handle; 1631 int index = 0; 1632 int num_of_active_display = 0; 1633 1634 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1635 return -EOPNOTSUPP; 1636 1637 if (!display_config) 1638 return -EINVAL; 1639 1640 smu_set_min_dcef_deep_sleep(smu, 1641 display_config->min_dcef_deep_sleep_set_clk / 100); 1642 1643 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1644 if (display_config->displays[index].controller_id != 0) 1645 num_of_active_display++; 1646 } 1647 1648 return 0; 1649 } 1650 1651 static int smu_set_clockgating_state(void *handle, 1652 enum amd_clockgating_state state) 1653 { 1654 return 0; 1655 } 1656 1657 static int smu_set_powergating_state(void *handle, 1658 enum amd_powergating_state state) 1659 { 1660 return 0; 1661 } 1662 1663 static int smu_enable_umd_pstate(void *handle, 1664 enum amd_dpm_forced_level *level) 1665 { 1666 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1667 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1668 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1669 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1670 1671 struct smu_context *smu = (struct smu_context*)(handle); 1672 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1673 1674 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1675 return -EINVAL; 1676 1677 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1678 /* enter umd pstate, save current level, disable gfx cg*/ 1679 if (*level & profile_mode_mask) { 1680 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1681 smu_gpo_control(smu, false); 1682 smu_gfx_ulv_control(smu, false); 1683 smu_deep_sleep_control(smu, false); 1684 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1685 } 1686 } else { 1687 /* exit umd pstate, restore level, enable gfx cg*/ 1688 if (!(*level & profile_mode_mask)) { 1689 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1690 *level = smu_dpm_ctx->saved_dpm_level; 1691 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1692 smu_deep_sleep_control(smu, true); 1693 smu_gfx_ulv_control(smu, true); 1694 smu_gpo_control(smu, true); 1695 } 1696 } 1697 1698 return 0; 1699 } 1700 1701 static int smu_bump_power_profile_mode(struct smu_context *smu, 1702 long *param, 1703 uint32_t param_size) 1704 { 1705 int ret = 0; 1706 1707 if (smu->ppt_funcs->set_power_profile_mode) 1708 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1709 1710 return ret; 1711 } 1712 1713 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1714 enum amd_dpm_forced_level level, 1715 bool skip_display_settings) 1716 { 1717 int ret = 0; 1718 int index = 0; 1719 long workload; 1720 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1721 1722 if (!skip_display_settings) { 1723 ret = smu_display_config_changed(smu); 1724 if (ret) { 1725 dev_err(smu->adev->dev, "Failed to change display config!"); 1726 return ret; 1727 } 1728 } 1729 1730 ret = smu_apply_clocks_adjust_rules(smu); 1731 if (ret) { 1732 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1733 return ret; 1734 } 1735 1736 if (!skip_display_settings) { 1737 ret = smu_notify_smc_display_config(smu); 1738 if (ret) { 1739 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1740 return ret; 1741 } 1742 } 1743 1744 if (smu_dpm_ctx->dpm_level != level) { 1745 ret = smu_asic_set_performance_level(smu, level); 1746 if (ret) { 1747 dev_err(smu->adev->dev, "Failed to set performance level!"); 1748 return ret; 1749 } 1750 1751 /* update the saved copy */ 1752 smu_dpm_ctx->dpm_level = level; 1753 } 1754 1755 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1756 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1757 index = fls(smu->workload_mask); 1758 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1759 workload = smu->workload_setting[index]; 1760 1761 if (smu->power_profile_mode != workload) 1762 smu_bump_power_profile_mode(smu, &workload, 0); 1763 } 1764 1765 return ret; 1766 } 1767 1768 static int smu_handle_task(struct smu_context *smu, 1769 enum amd_dpm_forced_level level, 1770 enum amd_pp_task task_id) 1771 { 1772 int ret = 0; 1773 1774 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1775 return -EOPNOTSUPP; 1776 1777 switch (task_id) { 1778 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1779 ret = smu_pre_display_config_changed(smu); 1780 if (ret) 1781 return ret; 1782 ret = smu_adjust_power_state_dynamic(smu, level, false); 1783 break; 1784 case AMD_PP_TASK_COMPLETE_INIT: 1785 case AMD_PP_TASK_READJUST_POWER_STATE: 1786 ret = smu_adjust_power_state_dynamic(smu, level, true); 1787 break; 1788 default: 1789 break; 1790 } 1791 1792 return ret; 1793 } 1794 1795 static int smu_handle_dpm_task(void *handle, 1796 enum amd_pp_task task_id, 1797 enum amd_pm_state_type *user_state) 1798 { 1799 struct smu_context *smu = handle; 1800 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1801 1802 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1803 1804 } 1805 1806 static int smu_switch_power_profile(void *handle, 1807 enum PP_SMC_POWER_PROFILE type, 1808 bool en) 1809 { 1810 struct smu_context *smu = handle; 1811 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1812 long workload; 1813 uint32_t index; 1814 1815 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1816 return -EOPNOTSUPP; 1817 1818 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1819 return -EINVAL; 1820 1821 if (!en) { 1822 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1823 index = fls(smu->workload_mask); 1824 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1825 workload = smu->workload_setting[index]; 1826 } else { 1827 smu->workload_mask |= (1 << smu->workload_prority[type]); 1828 index = fls(smu->workload_mask); 1829 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1830 workload = smu->workload_setting[index]; 1831 } 1832 1833 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1834 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1835 smu_bump_power_profile_mode(smu, &workload, 0); 1836 1837 return 0; 1838 } 1839 1840 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1841 { 1842 struct smu_context *smu = handle; 1843 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1844 1845 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1846 return -EOPNOTSUPP; 1847 1848 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1849 return -EINVAL; 1850 1851 return smu_dpm_ctx->dpm_level; 1852 } 1853 1854 static int smu_force_performance_level(void *handle, 1855 enum amd_dpm_forced_level level) 1856 { 1857 struct smu_context *smu = handle; 1858 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1859 int ret = 0; 1860 1861 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1862 return -EOPNOTSUPP; 1863 1864 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1865 return -EINVAL; 1866 1867 ret = smu_enable_umd_pstate(smu, &level); 1868 if (ret) 1869 return ret; 1870 1871 ret = smu_handle_task(smu, level, 1872 AMD_PP_TASK_READJUST_POWER_STATE); 1873 1874 /* reset user dpm clock state */ 1875 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1876 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1877 smu->user_dpm_profile.clk_dependency = 0; 1878 } 1879 1880 return ret; 1881 } 1882 1883 static int smu_set_display_count(void *handle, uint32_t count) 1884 { 1885 struct smu_context *smu = handle; 1886 1887 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1888 return -EOPNOTSUPP; 1889 1890 return smu_init_display_count(smu, count); 1891 } 1892 1893 static int smu_force_smuclk_levels(struct smu_context *smu, 1894 enum smu_clk_type clk_type, 1895 uint32_t mask) 1896 { 1897 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1898 int ret = 0; 1899 1900 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1901 return -EOPNOTSUPP; 1902 1903 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1904 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1905 return -EINVAL; 1906 } 1907 1908 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1909 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1910 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1911 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1912 smu_set_user_clk_dependencies(smu, clk_type); 1913 } 1914 } 1915 1916 return ret; 1917 } 1918 1919 static int smu_force_ppclk_levels(void *handle, 1920 enum pp_clock_type type, 1921 uint32_t mask) 1922 { 1923 struct smu_context *smu = handle; 1924 enum smu_clk_type clk_type; 1925 1926 switch (type) { 1927 case PP_SCLK: 1928 clk_type = SMU_SCLK; break; 1929 case PP_MCLK: 1930 clk_type = SMU_MCLK; break; 1931 case PP_PCIE: 1932 clk_type = SMU_PCIE; break; 1933 case PP_SOCCLK: 1934 clk_type = SMU_SOCCLK; break; 1935 case PP_FCLK: 1936 clk_type = SMU_FCLK; break; 1937 case PP_DCEFCLK: 1938 clk_type = SMU_DCEFCLK; break; 1939 case PP_VCLK: 1940 clk_type = SMU_VCLK; break; 1941 case PP_DCLK: 1942 clk_type = SMU_DCLK; break; 1943 case OD_SCLK: 1944 clk_type = SMU_OD_SCLK; break; 1945 case OD_MCLK: 1946 clk_type = SMU_OD_MCLK; break; 1947 case OD_VDDC_CURVE: 1948 clk_type = SMU_OD_VDDC_CURVE; break; 1949 case OD_RANGE: 1950 clk_type = SMU_OD_RANGE; break; 1951 default: 1952 return -EINVAL; 1953 } 1954 1955 return smu_force_smuclk_levels(smu, clk_type, mask); 1956 } 1957 1958 /* 1959 * On system suspending or resetting, the dpm_enabled 1960 * flag will be cleared. So that those SMU services which 1961 * are not supported will be gated. 1962 * However, the mp1 state setting should still be granted 1963 * even if the dpm_enabled cleared. 1964 */ 1965 static int smu_set_mp1_state(void *handle, 1966 enum pp_mp1_state mp1_state) 1967 { 1968 struct smu_context *smu = handle; 1969 int ret = 0; 1970 1971 if (!smu->pm_enabled) 1972 return -EOPNOTSUPP; 1973 1974 if (smu->ppt_funcs && 1975 smu->ppt_funcs->set_mp1_state) 1976 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1977 1978 return ret; 1979 } 1980 1981 static int smu_set_df_cstate(void *handle, 1982 enum pp_df_cstate state) 1983 { 1984 struct smu_context *smu = handle; 1985 int ret = 0; 1986 1987 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1988 return -EOPNOTSUPP; 1989 1990 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1991 return 0; 1992 1993 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1994 if (ret) 1995 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1996 1997 return ret; 1998 } 1999 2000 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2001 { 2002 int ret = 0; 2003 2004 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2005 return -EOPNOTSUPP; 2006 2007 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2008 return 0; 2009 2010 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2011 if (ret) 2012 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2013 2014 return ret; 2015 } 2016 2017 int smu_write_watermarks_table(struct smu_context *smu) 2018 { 2019 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2020 return -EOPNOTSUPP; 2021 2022 return smu_set_watermarks_table(smu, NULL); 2023 } 2024 2025 static int smu_set_watermarks_for_clock_ranges(void *handle, 2026 struct pp_smu_wm_range_sets *clock_ranges) 2027 { 2028 struct smu_context *smu = handle; 2029 2030 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2031 return -EOPNOTSUPP; 2032 2033 if (smu->disable_watermark) 2034 return 0; 2035 2036 return smu_set_watermarks_table(smu, clock_ranges); 2037 } 2038 2039 int smu_set_ac_dc(struct smu_context *smu) 2040 { 2041 int ret = 0; 2042 2043 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2044 return -EOPNOTSUPP; 2045 2046 /* controlled by firmware */ 2047 if (smu->dc_controlled_by_gpio) 2048 return 0; 2049 2050 ret = smu_set_power_source(smu, 2051 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2052 SMU_POWER_SOURCE_DC); 2053 if (ret) 2054 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2055 smu->adev->pm.ac_power ? "AC" : "DC"); 2056 2057 return ret; 2058 } 2059 2060 const struct amd_ip_funcs smu_ip_funcs = { 2061 .name = "smu", 2062 .early_init = smu_early_init, 2063 .late_init = smu_late_init, 2064 .sw_init = smu_sw_init, 2065 .sw_fini = smu_sw_fini, 2066 .hw_init = smu_hw_init, 2067 .hw_fini = smu_hw_fini, 2068 .late_fini = smu_late_fini, 2069 .suspend = smu_suspend, 2070 .resume = smu_resume, 2071 .is_idle = NULL, 2072 .check_soft_reset = NULL, 2073 .wait_for_idle = NULL, 2074 .soft_reset = NULL, 2075 .set_clockgating_state = smu_set_clockgating_state, 2076 .set_powergating_state = smu_set_powergating_state, 2077 }; 2078 2079 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2080 { 2081 .type = AMD_IP_BLOCK_TYPE_SMC, 2082 .major = 11, 2083 .minor = 0, 2084 .rev = 0, 2085 .funcs = &smu_ip_funcs, 2086 }; 2087 2088 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2089 { 2090 .type = AMD_IP_BLOCK_TYPE_SMC, 2091 .major = 12, 2092 .minor = 0, 2093 .rev = 0, 2094 .funcs = &smu_ip_funcs, 2095 }; 2096 2097 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2098 { 2099 .type = AMD_IP_BLOCK_TYPE_SMC, 2100 .major = 13, 2101 .minor = 0, 2102 .rev = 0, 2103 .funcs = &smu_ip_funcs, 2104 }; 2105 2106 static int smu_load_microcode(void *handle) 2107 { 2108 struct smu_context *smu = handle; 2109 struct amdgpu_device *adev = smu->adev; 2110 int ret = 0; 2111 2112 if (!smu->pm_enabled) 2113 return -EOPNOTSUPP; 2114 2115 /* This should be used for non PSP loading */ 2116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2117 return 0; 2118 2119 if (smu->ppt_funcs->load_microcode) { 2120 ret = smu->ppt_funcs->load_microcode(smu); 2121 if (ret) { 2122 dev_err(adev->dev, "Load microcode failed\n"); 2123 return ret; 2124 } 2125 } 2126 2127 if (smu->ppt_funcs->check_fw_status) { 2128 ret = smu->ppt_funcs->check_fw_status(smu); 2129 if (ret) { 2130 dev_err(adev->dev, "SMC is not ready\n"); 2131 return ret; 2132 } 2133 } 2134 2135 return ret; 2136 } 2137 2138 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2139 { 2140 int ret = 0; 2141 2142 if (smu->ppt_funcs->set_gfx_cgpg) 2143 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2144 2145 return ret; 2146 } 2147 2148 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2149 { 2150 struct smu_context *smu = handle; 2151 int ret = 0; 2152 2153 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2154 return -EOPNOTSUPP; 2155 2156 if (!smu->ppt_funcs->set_fan_speed_rpm) 2157 return -EOPNOTSUPP; 2158 2159 if (speed == U32_MAX) 2160 return -EINVAL; 2161 2162 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2163 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2164 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2165 smu->user_dpm_profile.fan_speed_rpm = speed; 2166 2167 /* Override custom PWM setting as they cannot co-exist */ 2168 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2169 smu->user_dpm_profile.fan_speed_pwm = 0; 2170 } 2171 2172 return ret; 2173 } 2174 2175 /** 2176 * smu_get_power_limit - Request one of the SMU Power Limits 2177 * 2178 * @handle: pointer to smu context 2179 * @limit: requested limit is written back to this variable 2180 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2181 * @pp_power_type: &pp_power_type type of power 2182 * Return: 0 on success, <0 on error 2183 * 2184 */ 2185 int smu_get_power_limit(void *handle, 2186 uint32_t *limit, 2187 enum pp_power_limit_level pp_limit_level, 2188 enum pp_power_type pp_power_type) 2189 { 2190 struct smu_context *smu = handle; 2191 struct amdgpu_device *adev = smu->adev; 2192 enum smu_ppt_limit_level limit_level; 2193 uint32_t limit_type; 2194 int ret = 0; 2195 2196 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2197 return -EOPNOTSUPP; 2198 2199 switch(pp_power_type) { 2200 case PP_PWR_TYPE_SUSTAINED: 2201 limit_type = SMU_DEFAULT_PPT_LIMIT; 2202 break; 2203 case PP_PWR_TYPE_FAST: 2204 limit_type = SMU_FAST_PPT_LIMIT; 2205 break; 2206 default: 2207 return -EOPNOTSUPP; 2208 break; 2209 } 2210 2211 switch(pp_limit_level){ 2212 case PP_PWR_LIMIT_CURRENT: 2213 limit_level = SMU_PPT_LIMIT_CURRENT; 2214 break; 2215 case PP_PWR_LIMIT_DEFAULT: 2216 limit_level = SMU_PPT_LIMIT_DEFAULT; 2217 break; 2218 case PP_PWR_LIMIT_MAX: 2219 limit_level = SMU_PPT_LIMIT_MAX; 2220 break; 2221 case PP_PWR_LIMIT_MIN: 2222 default: 2223 return -EOPNOTSUPP; 2224 break; 2225 } 2226 2227 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2228 if (smu->ppt_funcs->get_ppt_limit) 2229 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2230 } else { 2231 switch (limit_level) { 2232 case SMU_PPT_LIMIT_CURRENT: 2233 switch (adev->ip_versions[MP1_HWIP][0]) { 2234 case IP_VERSION(13, 0, 2): 2235 case IP_VERSION(11, 0, 7): 2236 case IP_VERSION(11, 0, 11): 2237 case IP_VERSION(11, 0, 12): 2238 case IP_VERSION(11, 0, 13): 2239 ret = smu_get_asic_power_limits(smu, 2240 &smu->current_power_limit, 2241 NULL, 2242 NULL); 2243 break; 2244 default: 2245 break; 2246 } 2247 *limit = smu->current_power_limit; 2248 break; 2249 case SMU_PPT_LIMIT_DEFAULT: 2250 *limit = smu->default_power_limit; 2251 break; 2252 case SMU_PPT_LIMIT_MAX: 2253 *limit = smu->max_power_limit; 2254 break; 2255 default: 2256 break; 2257 } 2258 } 2259 2260 return ret; 2261 } 2262 2263 static int smu_set_power_limit(void *handle, uint32_t limit) 2264 { 2265 struct smu_context *smu = handle; 2266 uint32_t limit_type = limit >> 24; 2267 int ret = 0; 2268 2269 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2270 return -EOPNOTSUPP; 2271 2272 limit &= (1<<24)-1; 2273 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2274 if (smu->ppt_funcs->set_power_limit) 2275 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2276 2277 if (limit > smu->max_power_limit) { 2278 dev_err(smu->adev->dev, 2279 "New power limit (%d) is over the max allowed %d\n", 2280 limit, smu->max_power_limit); 2281 return -EINVAL; 2282 } 2283 2284 if (!limit) 2285 limit = smu->current_power_limit; 2286 2287 if (smu->ppt_funcs->set_power_limit) { 2288 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2289 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2290 smu->user_dpm_profile.power_limit = limit; 2291 } 2292 2293 return ret; 2294 } 2295 2296 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2297 { 2298 int ret = 0; 2299 2300 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2301 return -EOPNOTSUPP; 2302 2303 if (smu->ppt_funcs->print_clk_levels) 2304 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2305 2306 return ret; 2307 } 2308 2309 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2310 { 2311 enum smu_clk_type clk_type; 2312 2313 switch (type) { 2314 case PP_SCLK: 2315 clk_type = SMU_SCLK; break; 2316 case PP_MCLK: 2317 clk_type = SMU_MCLK; break; 2318 case PP_PCIE: 2319 clk_type = SMU_PCIE; break; 2320 case PP_SOCCLK: 2321 clk_type = SMU_SOCCLK; break; 2322 case PP_FCLK: 2323 clk_type = SMU_FCLK; break; 2324 case PP_DCEFCLK: 2325 clk_type = SMU_DCEFCLK; break; 2326 case PP_VCLK: 2327 clk_type = SMU_VCLK; break; 2328 case PP_DCLK: 2329 clk_type = SMU_DCLK; break; 2330 case OD_SCLK: 2331 clk_type = SMU_OD_SCLK; break; 2332 case OD_MCLK: 2333 clk_type = SMU_OD_MCLK; break; 2334 case OD_VDDC_CURVE: 2335 clk_type = SMU_OD_VDDC_CURVE; break; 2336 case OD_RANGE: 2337 clk_type = SMU_OD_RANGE; break; 2338 case OD_VDDGFX_OFFSET: 2339 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2340 case OD_CCLK: 2341 clk_type = SMU_OD_CCLK; break; 2342 default: 2343 clk_type = SMU_CLK_COUNT; break; 2344 } 2345 2346 return clk_type; 2347 } 2348 2349 static int smu_print_ppclk_levels(void *handle, 2350 enum pp_clock_type type, 2351 char *buf) 2352 { 2353 struct smu_context *smu = handle; 2354 enum smu_clk_type clk_type; 2355 2356 clk_type = smu_convert_to_smuclk(type); 2357 if (clk_type == SMU_CLK_COUNT) 2358 return -EINVAL; 2359 2360 return smu_print_smuclk_levels(smu, clk_type, buf); 2361 } 2362 2363 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2364 { 2365 struct smu_context *smu = handle; 2366 enum smu_clk_type clk_type; 2367 2368 clk_type = smu_convert_to_smuclk(type); 2369 if (clk_type == SMU_CLK_COUNT) 2370 return -EINVAL; 2371 2372 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2373 return -EOPNOTSUPP; 2374 2375 if (!smu->ppt_funcs->emit_clk_levels) 2376 return -ENOENT; 2377 2378 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2379 2380 } 2381 2382 static int smu_od_edit_dpm_table(void *handle, 2383 enum PP_OD_DPM_TABLE_COMMAND type, 2384 long *input, uint32_t size) 2385 { 2386 struct smu_context *smu = handle; 2387 int ret = 0; 2388 2389 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2390 return -EOPNOTSUPP; 2391 2392 if (smu->ppt_funcs->od_edit_dpm_table) { 2393 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2394 } 2395 2396 return ret; 2397 } 2398 2399 static int smu_read_sensor(void *handle, 2400 int sensor, 2401 void *data, 2402 int *size_arg) 2403 { 2404 struct smu_context *smu = handle; 2405 struct smu_umd_pstate_table *pstate_table = 2406 &smu->pstate_table; 2407 int ret = 0; 2408 uint32_t *size, size_val; 2409 2410 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2411 return -EOPNOTSUPP; 2412 2413 if (!data || !size_arg) 2414 return -EINVAL; 2415 2416 size_val = *size_arg; 2417 size = &size_val; 2418 2419 if (smu->ppt_funcs->read_sensor) 2420 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2421 goto unlock; 2422 2423 switch (sensor) { 2424 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2425 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2426 *size = 4; 2427 break; 2428 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2429 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2430 *size = 4; 2431 break; 2432 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2433 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2434 *size = 8; 2435 break; 2436 case AMDGPU_PP_SENSOR_UVD_POWER: 2437 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2438 *size = 4; 2439 break; 2440 case AMDGPU_PP_SENSOR_VCE_POWER: 2441 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2442 *size = 4; 2443 break; 2444 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2445 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2446 *size = 4; 2447 break; 2448 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2449 *(uint32_t *)data = 0; 2450 *size = 4; 2451 break; 2452 default: 2453 *size = 0; 2454 ret = -EOPNOTSUPP; 2455 break; 2456 } 2457 2458 unlock: 2459 // assign uint32_t to int 2460 *size_arg = size_val; 2461 2462 return ret; 2463 } 2464 2465 static int smu_get_power_profile_mode(void *handle, char *buf) 2466 { 2467 struct smu_context *smu = handle; 2468 2469 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2470 !smu->ppt_funcs->get_power_profile_mode) 2471 return -EOPNOTSUPP; 2472 if (!buf) 2473 return -EINVAL; 2474 2475 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2476 } 2477 2478 static int smu_set_power_profile_mode(void *handle, 2479 long *param, 2480 uint32_t param_size) 2481 { 2482 struct smu_context *smu = handle; 2483 2484 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2485 !smu->ppt_funcs->set_power_profile_mode) 2486 return -EOPNOTSUPP; 2487 2488 return smu_bump_power_profile_mode(smu, param, param_size); 2489 } 2490 2491 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2492 { 2493 struct smu_context *smu = handle; 2494 2495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2496 return -EOPNOTSUPP; 2497 2498 if (!smu->ppt_funcs->get_fan_control_mode) 2499 return -EOPNOTSUPP; 2500 2501 if (!fan_mode) 2502 return -EINVAL; 2503 2504 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2505 2506 return 0; 2507 } 2508 2509 static int smu_set_fan_control_mode(void *handle, u32 value) 2510 { 2511 struct smu_context *smu = handle; 2512 int ret = 0; 2513 2514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2515 return -EOPNOTSUPP; 2516 2517 if (!smu->ppt_funcs->set_fan_control_mode) 2518 return -EOPNOTSUPP; 2519 2520 if (value == U32_MAX) 2521 return -EINVAL; 2522 2523 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2524 if (ret) 2525 goto out; 2526 2527 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2528 smu->user_dpm_profile.fan_mode = value; 2529 2530 /* reset user dpm fan speed */ 2531 if (value != AMD_FAN_CTRL_MANUAL) { 2532 smu->user_dpm_profile.fan_speed_pwm = 0; 2533 smu->user_dpm_profile.fan_speed_rpm = 0; 2534 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2535 } 2536 } 2537 2538 out: 2539 return ret; 2540 } 2541 2542 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2543 { 2544 struct smu_context *smu = handle; 2545 int ret = 0; 2546 2547 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2548 return -EOPNOTSUPP; 2549 2550 if (!smu->ppt_funcs->get_fan_speed_pwm) 2551 return -EOPNOTSUPP; 2552 2553 if (!speed) 2554 return -EINVAL; 2555 2556 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2557 2558 return ret; 2559 } 2560 2561 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2562 { 2563 struct smu_context *smu = handle; 2564 int ret = 0; 2565 2566 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2567 return -EOPNOTSUPP; 2568 2569 if (!smu->ppt_funcs->set_fan_speed_pwm) 2570 return -EOPNOTSUPP; 2571 2572 if (speed == U32_MAX) 2573 return -EINVAL; 2574 2575 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2576 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2577 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2578 smu->user_dpm_profile.fan_speed_pwm = speed; 2579 2580 /* Override custom RPM setting as they cannot co-exist */ 2581 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2582 smu->user_dpm_profile.fan_speed_rpm = 0; 2583 } 2584 2585 return ret; 2586 } 2587 2588 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2589 { 2590 struct smu_context *smu = handle; 2591 int ret = 0; 2592 2593 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2594 return -EOPNOTSUPP; 2595 2596 if (!smu->ppt_funcs->get_fan_speed_rpm) 2597 return -EOPNOTSUPP; 2598 2599 if (!speed) 2600 return -EINVAL; 2601 2602 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2603 2604 return ret; 2605 } 2606 2607 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2608 { 2609 struct smu_context *smu = handle; 2610 2611 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2612 return -EOPNOTSUPP; 2613 2614 return smu_set_min_dcef_deep_sleep(smu, clk); 2615 } 2616 2617 static int smu_get_clock_by_type_with_latency(void *handle, 2618 enum amd_pp_clock_type type, 2619 struct pp_clock_levels_with_latency *clocks) 2620 { 2621 struct smu_context *smu = handle; 2622 enum smu_clk_type clk_type; 2623 int ret = 0; 2624 2625 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2626 return -EOPNOTSUPP; 2627 2628 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2629 switch (type) { 2630 case amd_pp_sys_clock: 2631 clk_type = SMU_GFXCLK; 2632 break; 2633 case amd_pp_mem_clock: 2634 clk_type = SMU_MCLK; 2635 break; 2636 case amd_pp_dcef_clock: 2637 clk_type = SMU_DCEFCLK; 2638 break; 2639 case amd_pp_disp_clock: 2640 clk_type = SMU_DISPCLK; 2641 break; 2642 default: 2643 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2644 return -EINVAL; 2645 } 2646 2647 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2648 } 2649 2650 return ret; 2651 } 2652 2653 static int smu_display_clock_voltage_request(void *handle, 2654 struct pp_display_clock_request *clock_req) 2655 { 2656 struct smu_context *smu = handle; 2657 int ret = 0; 2658 2659 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2660 return -EOPNOTSUPP; 2661 2662 if (smu->ppt_funcs->display_clock_voltage_request) 2663 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2664 2665 return ret; 2666 } 2667 2668 2669 static int smu_display_disable_memory_clock_switch(void *handle, 2670 bool disable_memory_clock_switch) 2671 { 2672 struct smu_context *smu = handle; 2673 int ret = -EINVAL; 2674 2675 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2676 return -EOPNOTSUPP; 2677 2678 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2679 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2680 2681 return ret; 2682 } 2683 2684 static int smu_set_xgmi_pstate(void *handle, 2685 uint32_t pstate) 2686 { 2687 struct smu_context *smu = handle; 2688 int ret = 0; 2689 2690 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2691 return -EOPNOTSUPP; 2692 2693 if (smu->ppt_funcs->set_xgmi_pstate) 2694 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2695 2696 if(ret) 2697 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2698 2699 return ret; 2700 } 2701 2702 static int smu_get_baco_capability(void *handle, bool *cap) 2703 { 2704 struct smu_context *smu = handle; 2705 2706 *cap = false; 2707 2708 if (!smu->pm_enabled) 2709 return 0; 2710 2711 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2712 *cap = smu->ppt_funcs->baco_is_support(smu); 2713 2714 return 0; 2715 } 2716 2717 static int smu_baco_set_state(void *handle, int state) 2718 { 2719 struct smu_context *smu = handle; 2720 int ret = 0; 2721 2722 if (!smu->pm_enabled) 2723 return -EOPNOTSUPP; 2724 2725 if (state == 0) { 2726 if (smu->ppt_funcs->baco_exit) 2727 ret = smu->ppt_funcs->baco_exit(smu); 2728 } else if (state == 1) { 2729 if (smu->ppt_funcs->baco_enter) 2730 ret = smu->ppt_funcs->baco_enter(smu); 2731 } else { 2732 return -EINVAL; 2733 } 2734 2735 if (ret) 2736 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2737 (state)?"enter":"exit"); 2738 2739 return ret; 2740 } 2741 2742 bool smu_mode1_reset_is_support(struct smu_context *smu) 2743 { 2744 bool ret = false; 2745 2746 if (!smu->pm_enabled) 2747 return false; 2748 2749 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2750 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2751 2752 return ret; 2753 } 2754 2755 bool smu_mode2_reset_is_support(struct smu_context *smu) 2756 { 2757 bool ret = false; 2758 2759 if (!smu->pm_enabled) 2760 return false; 2761 2762 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2763 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2764 2765 return ret; 2766 } 2767 2768 int smu_mode1_reset(struct smu_context *smu) 2769 { 2770 int ret = 0; 2771 2772 if (!smu->pm_enabled) 2773 return -EOPNOTSUPP; 2774 2775 if (smu->ppt_funcs->mode1_reset) 2776 ret = smu->ppt_funcs->mode1_reset(smu); 2777 2778 return ret; 2779 } 2780 2781 static int smu_mode2_reset(void *handle) 2782 { 2783 struct smu_context *smu = handle; 2784 int ret = 0; 2785 2786 if (!smu->pm_enabled) 2787 return -EOPNOTSUPP; 2788 2789 if (smu->ppt_funcs->mode2_reset) 2790 ret = smu->ppt_funcs->mode2_reset(smu); 2791 2792 if (ret) 2793 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2794 2795 return ret; 2796 } 2797 2798 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2799 struct pp_smu_nv_clock_table *max_clocks) 2800 { 2801 struct smu_context *smu = handle; 2802 int ret = 0; 2803 2804 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2805 return -EOPNOTSUPP; 2806 2807 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2808 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2809 2810 return ret; 2811 } 2812 2813 static int smu_get_uclk_dpm_states(void *handle, 2814 unsigned int *clock_values_in_khz, 2815 unsigned int *num_states) 2816 { 2817 struct smu_context *smu = handle; 2818 int ret = 0; 2819 2820 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2821 return -EOPNOTSUPP; 2822 2823 if (smu->ppt_funcs->get_uclk_dpm_states) 2824 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2825 2826 return ret; 2827 } 2828 2829 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2830 { 2831 struct smu_context *smu = handle; 2832 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2833 2834 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2835 return -EOPNOTSUPP; 2836 2837 if (smu->ppt_funcs->get_current_power_state) 2838 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2839 2840 return pm_state; 2841 } 2842 2843 static int smu_get_dpm_clock_table(void *handle, 2844 struct dpm_clocks *clock_table) 2845 { 2846 struct smu_context *smu = handle; 2847 int ret = 0; 2848 2849 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2850 return -EOPNOTSUPP; 2851 2852 if (smu->ppt_funcs->get_dpm_clock_table) 2853 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2854 2855 return ret; 2856 } 2857 2858 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2859 { 2860 struct smu_context *smu = handle; 2861 2862 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2863 return -EOPNOTSUPP; 2864 2865 if (!smu->ppt_funcs->get_gpu_metrics) 2866 return -EOPNOTSUPP; 2867 2868 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2869 } 2870 2871 static int smu_enable_mgpu_fan_boost(void *handle) 2872 { 2873 struct smu_context *smu = handle; 2874 int ret = 0; 2875 2876 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2877 return -EOPNOTSUPP; 2878 2879 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2880 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2881 2882 return ret; 2883 } 2884 2885 static int smu_gfx_state_change_set(void *handle, 2886 uint32_t state) 2887 { 2888 struct smu_context *smu = handle; 2889 int ret = 0; 2890 2891 if (smu->ppt_funcs->gfx_state_change_set) 2892 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2893 2894 return ret; 2895 } 2896 2897 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2898 { 2899 int ret = 0; 2900 2901 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2902 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2903 2904 return ret; 2905 } 2906 2907 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2908 { 2909 int ret = -EOPNOTSUPP; 2910 2911 if (smu->ppt_funcs && 2912 smu->ppt_funcs->get_ecc_info) 2913 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2914 2915 return ret; 2916 2917 } 2918 2919 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2920 { 2921 struct smu_context *smu = handle; 2922 struct smu_table_context *smu_table = &smu->smu_table; 2923 struct smu_table *memory_pool = &smu_table->memory_pool; 2924 2925 if (!addr || !size) 2926 return -EINVAL; 2927 2928 *addr = NULL; 2929 *size = 0; 2930 if (memory_pool->bo) { 2931 *addr = memory_pool->cpu_addr; 2932 *size = memory_pool->size; 2933 } 2934 2935 return 0; 2936 } 2937 2938 static const struct amd_pm_funcs swsmu_pm_funcs = { 2939 /* export for sysfs */ 2940 .set_fan_control_mode = smu_set_fan_control_mode, 2941 .get_fan_control_mode = smu_get_fan_control_mode, 2942 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2943 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2944 .force_clock_level = smu_force_ppclk_levels, 2945 .print_clock_levels = smu_print_ppclk_levels, 2946 .emit_clock_levels = smu_emit_ppclk_levels, 2947 .force_performance_level = smu_force_performance_level, 2948 .read_sensor = smu_read_sensor, 2949 .get_performance_level = smu_get_performance_level, 2950 .get_current_power_state = smu_get_current_power_state, 2951 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2952 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2953 .get_pp_num_states = smu_get_power_num_states, 2954 .get_pp_table = smu_sys_get_pp_table, 2955 .set_pp_table = smu_sys_set_pp_table, 2956 .switch_power_profile = smu_switch_power_profile, 2957 /* export to amdgpu */ 2958 .dispatch_tasks = smu_handle_dpm_task, 2959 .load_firmware = smu_load_microcode, 2960 .set_powergating_by_smu = smu_dpm_set_power_gate, 2961 .set_power_limit = smu_set_power_limit, 2962 .get_power_limit = smu_get_power_limit, 2963 .get_power_profile_mode = smu_get_power_profile_mode, 2964 .set_power_profile_mode = smu_set_power_profile_mode, 2965 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2966 .set_mp1_state = smu_set_mp1_state, 2967 .gfx_state_change_set = smu_gfx_state_change_set, 2968 /* export to DC */ 2969 .get_sclk = smu_get_sclk, 2970 .get_mclk = smu_get_mclk, 2971 .display_configuration_change = smu_display_configuration_change, 2972 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2973 .display_clock_voltage_request = smu_display_clock_voltage_request, 2974 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2975 .set_active_display_count = smu_set_display_count, 2976 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2977 .get_asic_baco_capability = smu_get_baco_capability, 2978 .set_asic_baco_state = smu_baco_set_state, 2979 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2980 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2981 .asic_reset_mode_2 = smu_mode2_reset, 2982 .set_df_cstate = smu_set_df_cstate, 2983 .set_xgmi_pstate = smu_set_xgmi_pstate, 2984 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2985 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2986 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2987 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2988 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2989 .get_dpm_clock_table = smu_get_dpm_clock_table, 2990 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 2991 }; 2992 2993 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 2994 uint64_t event_arg) 2995 { 2996 int ret = -EINVAL; 2997 2998 if (smu->ppt_funcs->wait_for_event) 2999 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3000 3001 return ret; 3002 } 3003 3004 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3005 { 3006 3007 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3008 return -EOPNOTSUPP; 3009 3010 /* Confirm the buffer allocated is of correct size */ 3011 if (size != smu->stb_context.stb_buf_size) 3012 return -EINVAL; 3013 3014 /* 3015 * No need to lock smu mutex as we access STB directly through MMIO 3016 * and not going through SMU messaging route (for now at least). 3017 * For registers access rely on implementation internal locking. 3018 */ 3019 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3020 } 3021 3022 #if defined(CONFIG_DEBUG_FS) 3023 3024 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3025 { 3026 struct amdgpu_device *adev = filp->f_inode->i_private; 3027 struct smu_context *smu = adev->powerplay.pp_handle; 3028 unsigned char *buf; 3029 int r; 3030 3031 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3032 if (!buf) 3033 return -ENOMEM; 3034 3035 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3036 if (r) 3037 goto out; 3038 3039 filp->private_data = buf; 3040 3041 return 0; 3042 3043 out: 3044 kvfree(buf); 3045 return r; 3046 } 3047 3048 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3049 loff_t *pos) 3050 { 3051 struct amdgpu_device *adev = filp->f_inode->i_private; 3052 struct smu_context *smu = adev->powerplay.pp_handle; 3053 3054 3055 if (!filp->private_data) 3056 return -EINVAL; 3057 3058 return simple_read_from_buffer(buf, 3059 size, 3060 pos, filp->private_data, 3061 smu->stb_context.stb_buf_size); 3062 } 3063 3064 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3065 { 3066 kvfree(filp->private_data); 3067 filp->private_data = NULL; 3068 3069 return 0; 3070 } 3071 3072 /* 3073 * We have to define not only read method but also 3074 * open and release because .read takes up to PAGE_SIZE 3075 * data each time so and so is invoked multiple times. 3076 * We allocate the STB buffer in .open and release it 3077 * in .release 3078 */ 3079 static const struct file_operations smu_stb_debugfs_fops = { 3080 .owner = THIS_MODULE, 3081 .open = smu_stb_debugfs_open, 3082 .read = smu_stb_debugfs_read, 3083 .release = smu_stb_debugfs_release, 3084 .llseek = default_llseek, 3085 }; 3086 3087 #endif 3088 3089 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3090 { 3091 #if defined(CONFIG_DEBUG_FS) 3092 3093 struct smu_context *smu = adev->powerplay.pp_handle; 3094 3095 if (!smu || (!smu->stb_context.stb_buf_size)) 3096 return; 3097 3098 debugfs_create_file_size("amdgpu_smu_stb_dump", 3099 S_IRUSR, 3100 adev_to_drm(adev)->primary->debugfs_root, 3101 adev, 3102 &smu_stb_debugfs_fops, 3103 smu->stb_context.stb_buf_size); 3104 #endif 3105 } 3106 3107 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3108 { 3109 int ret = 0; 3110 3111 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3112 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3113 3114 return ret; 3115 } 3116 3117 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3118 { 3119 int ret = 0; 3120 3121 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3122 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3123 3124 return ret; 3125 } 3126