1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "amd_pcie.h" 37 38 /* 39 * DO NOT use these for err/warn/info/debug messages. 40 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 41 * They are more MGPU friendly. 42 */ 43 #undef pr_err 44 #undef pr_warn 45 #undef pr_info 46 #undef pr_debug 47 48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) 49 { 50 size_t size = 0; 51 52 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 53 return -EOPNOTSUPP; 54 55 mutex_lock(&smu->mutex); 56 57 size = smu_get_pp_feature_mask(smu, buf); 58 59 mutex_unlock(&smu->mutex); 60 61 return size; 62 } 63 64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) 65 { 66 int ret = 0; 67 68 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 69 return -EOPNOTSUPP; 70 71 mutex_lock(&smu->mutex); 72 73 ret = smu_set_pp_feature_mask(smu, new_mask); 74 75 mutex_unlock(&smu->mutex); 76 77 return ret; 78 } 79 80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 81 { 82 int ret = 0; 83 struct smu_context *smu = &adev->smu; 84 85 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 86 *value = smu_get_gfx_off_status(smu); 87 else 88 ret = -EINVAL; 89 90 return ret; 91 } 92 93 int smu_set_soft_freq_range(struct smu_context *smu, 94 enum smu_clk_type clk_type, 95 uint32_t min, 96 uint32_t max) 97 { 98 int ret = 0; 99 100 mutex_lock(&smu->mutex); 101 102 if (smu->ppt_funcs->set_soft_freq_limited_range) 103 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 104 clk_type, 105 min, 106 max); 107 108 mutex_unlock(&smu->mutex); 109 110 return ret; 111 } 112 113 int smu_get_dpm_freq_range(struct smu_context *smu, 114 enum smu_clk_type clk_type, 115 uint32_t *min, 116 uint32_t *max) 117 { 118 int ret = 0; 119 120 if (!min && !max) 121 return -EINVAL; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->get_dpm_ultimate_freq) 126 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 137 bool enable) 138 { 139 struct smu_power_context *smu_power = &smu->smu_power; 140 struct smu_power_gate *power_gate = &smu_power->power_gate; 141 int ret = 0; 142 143 if (!smu->ppt_funcs->dpm_set_vcn_enable) 144 return 0; 145 146 if (atomic_read(&power_gate->vcn_gated) ^ enable) 147 return 0; 148 149 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 150 if (!ret) 151 atomic_set(&power_gate->vcn_gated, !enable); 152 153 return ret; 154 } 155 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 157 bool enable) 158 { 159 struct smu_power_context *smu_power = &smu->smu_power; 160 struct smu_power_gate *power_gate = &smu_power->power_gate; 161 int ret = 0; 162 163 mutex_lock(&power_gate->vcn_gate_lock); 164 165 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 166 167 mutex_unlock(&power_gate->vcn_gate_lock); 168 169 return ret; 170 } 171 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 173 bool enable) 174 { 175 struct smu_power_context *smu_power = &smu->smu_power; 176 struct smu_power_gate *power_gate = &smu_power->power_gate; 177 int ret = 0; 178 179 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 180 return 0; 181 182 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 183 return 0; 184 185 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 186 if (!ret) 187 atomic_set(&power_gate->jpeg_gated, !enable); 188 189 return ret; 190 } 191 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 193 bool enable) 194 { 195 struct smu_power_context *smu_power = &smu->smu_power; 196 struct smu_power_gate *power_gate = &smu_power->power_gate; 197 int ret = 0; 198 199 mutex_lock(&power_gate->jpeg_gate_lock); 200 201 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 202 203 mutex_unlock(&power_gate->jpeg_gate_lock); 204 205 return ret; 206 } 207 208 /** 209 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 210 * 211 * @smu: smu_context pointer 212 * @block_type: the IP block to power gate/ungate 213 * @gate: to power gate if true, ungate otherwise 214 * 215 * This API uses no smu->mutex lock protection due to: 216 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 217 * This is guarded to be race condition free by the caller. 218 * 2. Or get called on user setting request of power_dpm_force_performance_level. 219 * Under this case, the smu->mutex lock protection is already enforced on 220 * the parent API smu_force_performance_level of the call path. 221 */ 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, 223 bool gate) 224 { 225 int ret = 0; 226 227 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 228 return -EOPNOTSUPP; 229 230 switch (block_type) { 231 /* 232 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 233 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 234 */ 235 case AMD_IP_BLOCK_TYPE_UVD: 236 case AMD_IP_BLOCK_TYPE_VCN: 237 ret = smu_dpm_set_vcn_enable(smu, !gate); 238 if (ret) 239 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 240 gate ? "gate" : "ungate"); 241 break; 242 case AMD_IP_BLOCK_TYPE_GFX: 243 ret = smu_gfx_off_control(smu, gate); 244 if (ret) 245 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 246 gate ? "enable" : "disable"); 247 break; 248 case AMD_IP_BLOCK_TYPE_SDMA: 249 ret = smu_powergate_sdma(smu, gate); 250 if (ret) 251 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 252 gate ? "gate" : "ungate"); 253 break; 254 case AMD_IP_BLOCK_TYPE_JPEG: 255 ret = smu_dpm_set_jpeg_enable(smu, !gate); 256 if (ret) 257 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 258 gate ? "gate" : "ungate"); 259 break; 260 default: 261 dev_err(smu->adev->dev, "Unsupported block type!\n"); 262 return -EINVAL; 263 } 264 265 return ret; 266 } 267 268 int smu_get_power_num_states(struct smu_context *smu, 269 struct pp_states_info *state_info) 270 { 271 if (!state_info) 272 return -EINVAL; 273 274 /* not support power state */ 275 memset(state_info, 0, sizeof(struct pp_states_info)); 276 state_info->nums = 1; 277 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 278 279 return 0; 280 } 281 282 bool is_support_sw_smu(struct amdgpu_device *adev) 283 { 284 if (adev->asic_type >= CHIP_ARCTURUS) 285 return true; 286 287 return false; 288 } 289 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table) 291 { 292 struct smu_table_context *smu_table = &smu->smu_table; 293 uint32_t powerplay_table_size; 294 295 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 296 return -EOPNOTSUPP; 297 298 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 299 return -EINVAL; 300 301 mutex_lock(&smu->mutex); 302 303 if (smu_table->hardcode_pptable) 304 *table = smu_table->hardcode_pptable; 305 else 306 *table = smu_table->power_play_table; 307 308 powerplay_table_size = smu_table->power_play_table_size; 309 310 mutex_unlock(&smu->mutex); 311 312 return powerplay_table_size; 313 } 314 315 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size) 316 { 317 struct smu_table_context *smu_table = &smu->smu_table; 318 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 319 int ret = 0; 320 321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 322 return -EOPNOTSUPP; 323 324 if (header->usStructureSize != size) { 325 dev_err(smu->adev->dev, "pp table size not matched !\n"); 326 return -EIO; 327 } 328 329 mutex_lock(&smu->mutex); 330 if (!smu_table->hardcode_pptable) 331 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 332 if (!smu_table->hardcode_pptable) { 333 ret = -ENOMEM; 334 goto failed; 335 } 336 337 memcpy(smu_table->hardcode_pptable, buf, size); 338 smu_table->power_play_table = smu_table->hardcode_pptable; 339 smu_table->power_play_table_size = size; 340 341 /* 342 * Special hw_fini action(for Navi1x, the DPMs disablement will be 343 * skipped) may be needed for custom pptable uploading. 344 */ 345 smu->uploading_custom_pp_table = true; 346 347 ret = smu_reset(smu); 348 if (ret) 349 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 350 351 smu->uploading_custom_pp_table = false; 352 353 failed: 354 mutex_unlock(&smu->mutex); 355 return ret; 356 } 357 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 359 { 360 struct smu_feature *feature = &smu->smu_feature; 361 int ret = 0; 362 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 363 364 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 365 366 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 367 SMU_FEATURE_MAX/32); 368 if (ret) 369 return ret; 370 371 bitmap_or(feature->allowed, feature->allowed, 372 (unsigned long *)allowed_feature_mask, 373 feature->feature_num); 374 375 return ret; 376 } 377 378 static int smu_set_funcs(struct amdgpu_device *adev) 379 { 380 struct smu_context *smu = &adev->smu; 381 382 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 383 smu->od_enabled = true; 384 385 switch (adev->asic_type) { 386 case CHIP_NAVI10: 387 case CHIP_NAVI14: 388 case CHIP_NAVI12: 389 navi10_set_ppt_funcs(smu); 390 break; 391 case CHIP_ARCTURUS: 392 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 393 arcturus_set_ppt_funcs(smu); 394 /* OD is not supported on Arcturus */ 395 smu->od_enabled =false; 396 break; 397 case CHIP_SIENNA_CICHLID: 398 case CHIP_NAVY_FLOUNDER: 399 sienna_cichlid_set_ppt_funcs(smu); 400 break; 401 case CHIP_RENOIR: 402 renoir_set_ppt_funcs(smu); 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 return 0; 409 } 410 411 static int smu_early_init(void *handle) 412 { 413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 414 struct smu_context *smu = &adev->smu; 415 416 smu->adev = adev; 417 smu->pm_enabled = !!amdgpu_dpm; 418 smu->is_apu = false; 419 mutex_init(&smu->mutex); 420 421 return smu_set_funcs(adev); 422 } 423 424 static int smu_set_default_dpm_table(struct smu_context *smu) 425 { 426 struct smu_power_context *smu_power = &smu->smu_power; 427 struct smu_power_gate *power_gate = &smu_power->power_gate; 428 int vcn_gate, jpeg_gate; 429 int ret = 0; 430 431 if (!smu->ppt_funcs->set_default_dpm_table) 432 return 0; 433 434 mutex_lock(&power_gate->vcn_gate_lock); 435 mutex_lock(&power_gate->jpeg_gate_lock); 436 437 vcn_gate = atomic_read(&power_gate->vcn_gated); 438 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 439 440 ret = smu_dpm_set_vcn_enable_locked(smu, true); 441 if (ret) 442 goto err0_out; 443 444 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 445 if (ret) 446 goto err1_out; 447 448 ret = smu->ppt_funcs->set_default_dpm_table(smu); 449 if (ret) 450 dev_err(smu->adev->dev, 451 "Failed to setup default dpm clock tables!\n"); 452 453 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 454 err1_out: 455 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 456 err0_out: 457 mutex_unlock(&power_gate->jpeg_gate_lock); 458 mutex_unlock(&power_gate->vcn_gate_lock); 459 460 return ret; 461 } 462 463 static int smu_late_init(void *handle) 464 { 465 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 466 struct smu_context *smu = &adev->smu; 467 int ret = 0; 468 469 if (!smu->pm_enabled) 470 return 0; 471 472 ret = smu_post_init(smu); 473 if (ret) { 474 dev_err(adev->dev, "Failed to post smu init!\n"); 475 return ret; 476 } 477 478 ret = smu_set_default_od_settings(smu); 479 if (ret) { 480 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 481 return ret; 482 } 483 484 ret = smu_populate_umd_state_clk(smu); 485 if (ret) { 486 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 487 return ret; 488 } 489 490 ret = smu_get_asic_power_limits(smu); 491 if (ret) { 492 dev_err(adev->dev, "Failed to get asic power limits!\n"); 493 return ret; 494 } 495 496 smu_get_unique_id(smu); 497 498 smu_get_fan_parameters(smu); 499 500 smu_handle_task(&adev->smu, 501 smu->smu_dpm.dpm_level, 502 AMD_PP_TASK_COMPLETE_INIT, 503 false); 504 505 return 0; 506 } 507 508 static int smu_init_fb_allocations(struct smu_context *smu) 509 { 510 struct amdgpu_device *adev = smu->adev; 511 struct smu_table_context *smu_table = &smu->smu_table; 512 struct smu_table *tables = smu_table->tables; 513 struct smu_table *driver_table = &(smu_table->driver_table); 514 uint32_t max_table_size = 0; 515 int ret, i; 516 517 /* VRAM allocation for tool table */ 518 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 519 ret = amdgpu_bo_create_kernel(adev, 520 tables[SMU_TABLE_PMSTATUSLOG].size, 521 tables[SMU_TABLE_PMSTATUSLOG].align, 522 tables[SMU_TABLE_PMSTATUSLOG].domain, 523 &tables[SMU_TABLE_PMSTATUSLOG].bo, 524 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 525 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 526 if (ret) { 527 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 528 return ret; 529 } 530 } 531 532 /* VRAM allocation for driver table */ 533 for (i = 0; i < SMU_TABLE_COUNT; i++) { 534 if (tables[i].size == 0) 535 continue; 536 537 if (i == SMU_TABLE_PMSTATUSLOG) 538 continue; 539 540 if (max_table_size < tables[i].size) 541 max_table_size = tables[i].size; 542 } 543 544 driver_table->size = max_table_size; 545 driver_table->align = PAGE_SIZE; 546 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 547 548 ret = amdgpu_bo_create_kernel(adev, 549 driver_table->size, 550 driver_table->align, 551 driver_table->domain, 552 &driver_table->bo, 553 &driver_table->mc_address, 554 &driver_table->cpu_addr); 555 if (ret) { 556 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 557 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 558 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 559 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 560 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 561 } 562 563 return ret; 564 } 565 566 static int smu_fini_fb_allocations(struct smu_context *smu) 567 { 568 struct smu_table_context *smu_table = &smu->smu_table; 569 struct smu_table *tables = smu_table->tables; 570 struct smu_table *driver_table = &(smu_table->driver_table); 571 572 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 573 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 574 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 575 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 576 577 amdgpu_bo_free_kernel(&driver_table->bo, 578 &driver_table->mc_address, 579 &driver_table->cpu_addr); 580 581 return 0; 582 } 583 584 /** 585 * smu_alloc_memory_pool - allocate memory pool in the system memory 586 * 587 * @smu: amdgpu_device pointer 588 * 589 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 590 * and DramLogSetDramAddr can notify it changed. 591 * 592 * Returns 0 on success, error on failure. 593 */ 594 static int smu_alloc_memory_pool(struct smu_context *smu) 595 { 596 struct amdgpu_device *adev = smu->adev; 597 struct smu_table_context *smu_table = &smu->smu_table; 598 struct smu_table *memory_pool = &smu_table->memory_pool; 599 uint64_t pool_size = smu->pool_size; 600 int ret = 0; 601 602 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 603 return ret; 604 605 memory_pool->size = pool_size; 606 memory_pool->align = PAGE_SIZE; 607 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 608 609 switch (pool_size) { 610 case SMU_MEMORY_POOL_SIZE_256_MB: 611 case SMU_MEMORY_POOL_SIZE_512_MB: 612 case SMU_MEMORY_POOL_SIZE_1_GB: 613 case SMU_MEMORY_POOL_SIZE_2_GB: 614 ret = amdgpu_bo_create_kernel(adev, 615 memory_pool->size, 616 memory_pool->align, 617 memory_pool->domain, 618 &memory_pool->bo, 619 &memory_pool->mc_address, 620 &memory_pool->cpu_addr); 621 if (ret) 622 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 623 break; 624 default: 625 break; 626 } 627 628 return ret; 629 } 630 631 static int smu_free_memory_pool(struct smu_context *smu) 632 { 633 struct smu_table_context *smu_table = &smu->smu_table; 634 struct smu_table *memory_pool = &smu_table->memory_pool; 635 636 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 637 return 0; 638 639 amdgpu_bo_free_kernel(&memory_pool->bo, 640 &memory_pool->mc_address, 641 &memory_pool->cpu_addr); 642 643 memset(memory_pool, 0, sizeof(struct smu_table)); 644 645 return 0; 646 } 647 648 static int smu_alloc_dummy_read_table(struct smu_context *smu) 649 { 650 struct smu_table_context *smu_table = &smu->smu_table; 651 struct smu_table *dummy_read_1_table = 652 &smu_table->dummy_read_1_table; 653 struct amdgpu_device *adev = smu->adev; 654 int ret = 0; 655 656 dummy_read_1_table->size = 0x40000; 657 dummy_read_1_table->align = PAGE_SIZE; 658 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 659 660 ret = amdgpu_bo_create_kernel(adev, 661 dummy_read_1_table->size, 662 dummy_read_1_table->align, 663 dummy_read_1_table->domain, 664 &dummy_read_1_table->bo, 665 &dummy_read_1_table->mc_address, 666 &dummy_read_1_table->cpu_addr); 667 if (ret) 668 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 669 670 return ret; 671 } 672 673 static void smu_free_dummy_read_table(struct smu_context *smu) 674 { 675 struct smu_table_context *smu_table = &smu->smu_table; 676 struct smu_table *dummy_read_1_table = 677 &smu_table->dummy_read_1_table; 678 679 680 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 681 &dummy_read_1_table->mc_address, 682 &dummy_read_1_table->cpu_addr); 683 684 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 685 } 686 687 static int smu_smc_table_sw_init(struct smu_context *smu) 688 { 689 int ret; 690 691 /** 692 * Create smu_table structure, and init smc tables such as 693 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 694 */ 695 ret = smu_init_smc_tables(smu); 696 if (ret) { 697 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 698 return ret; 699 } 700 701 /** 702 * Create smu_power_context structure, and allocate smu_dpm_context and 703 * context size to fill the smu_power_context data. 704 */ 705 ret = smu_init_power(smu); 706 if (ret) { 707 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 708 return ret; 709 } 710 711 /* 712 * allocate vram bos to store smc table contents. 713 */ 714 ret = smu_init_fb_allocations(smu); 715 if (ret) 716 return ret; 717 718 ret = smu_alloc_memory_pool(smu); 719 if (ret) 720 return ret; 721 722 ret = smu_alloc_dummy_read_table(smu); 723 if (ret) 724 return ret; 725 726 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 727 if (ret) 728 return ret; 729 730 return 0; 731 } 732 733 static int smu_smc_table_sw_fini(struct smu_context *smu) 734 { 735 int ret; 736 737 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 738 739 smu_free_dummy_read_table(smu); 740 741 ret = smu_free_memory_pool(smu); 742 if (ret) 743 return ret; 744 745 ret = smu_fini_fb_allocations(smu); 746 if (ret) 747 return ret; 748 749 ret = smu_fini_power(smu); 750 if (ret) { 751 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 752 return ret; 753 } 754 755 ret = smu_fini_smc_tables(smu); 756 if (ret) { 757 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 758 return ret; 759 } 760 761 return 0; 762 } 763 764 static void smu_throttling_logging_work_fn(struct work_struct *work) 765 { 766 struct smu_context *smu = container_of(work, struct smu_context, 767 throttling_logging_work); 768 769 smu_log_thermal_throttling(smu); 770 } 771 772 static void smu_interrupt_work_fn(struct work_struct *work) 773 { 774 struct smu_context *smu = container_of(work, struct smu_context, 775 interrupt_work); 776 777 mutex_lock(&smu->mutex); 778 779 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 780 smu->ppt_funcs->interrupt_work(smu); 781 782 mutex_unlock(&smu->mutex); 783 } 784 785 static int smu_sw_init(void *handle) 786 { 787 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 788 struct smu_context *smu = &adev->smu; 789 int ret; 790 791 smu->pool_size = adev->pm.smu_prv_buffer_size; 792 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 793 mutex_init(&smu->smu_feature.mutex); 794 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 795 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 796 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 797 798 mutex_init(&smu->smu_baco.mutex); 799 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 800 smu->smu_baco.platform_support = false; 801 802 mutex_init(&smu->sensor_lock); 803 mutex_init(&smu->metrics_lock); 804 mutex_init(&smu->message_lock); 805 806 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 807 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 808 atomic64_set(&smu->throttle_int_counter, 0); 809 smu->watermarks_bitmap = 0; 810 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 811 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 812 813 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 814 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 815 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 816 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 817 818 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 819 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 820 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 821 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 822 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 823 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 824 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 825 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 826 827 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 828 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 829 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 830 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 831 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 832 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 833 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 834 smu->display_config = &adev->pm.pm_display_cfg; 835 836 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 837 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 838 839 if (!amdgpu_sriov_vf(adev)) { 840 ret = smu_init_microcode(smu); 841 if (ret) { 842 dev_err(adev->dev, "Failed to load smu firmware!\n"); 843 return ret; 844 } 845 } 846 847 ret = smu_smc_table_sw_init(smu); 848 if (ret) { 849 dev_err(adev->dev, "Failed to sw init smc table!\n"); 850 return ret; 851 } 852 853 ret = smu_register_irq_handler(smu); 854 if (ret) { 855 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 856 return ret; 857 } 858 859 return 0; 860 } 861 862 static int smu_sw_fini(void *handle) 863 { 864 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 865 struct smu_context *smu = &adev->smu; 866 int ret; 867 868 ret = smu_smc_table_sw_fini(smu); 869 if (ret) { 870 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 871 return ret; 872 } 873 874 smu_fini_microcode(smu); 875 876 return 0; 877 } 878 879 static int smu_get_thermal_temperature_range(struct smu_context *smu) 880 { 881 struct amdgpu_device *adev = smu->adev; 882 struct smu_temperature_range *range = 883 &smu->thermal_range; 884 int ret = 0; 885 886 if (!smu->ppt_funcs->get_thermal_temperature_range) 887 return 0; 888 889 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 890 if (ret) 891 return ret; 892 893 adev->pm.dpm.thermal.min_temp = range->min; 894 adev->pm.dpm.thermal.max_temp = range->max; 895 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 896 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 897 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 898 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 899 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 900 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 901 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 902 903 return ret; 904 } 905 906 static int smu_smc_hw_setup(struct smu_context *smu) 907 { 908 struct amdgpu_device *adev = smu->adev; 909 uint32_t pcie_gen = 0, pcie_width = 0; 910 int ret; 911 912 if (adev->in_suspend && smu_is_dpm_running(smu)) { 913 dev_info(adev->dev, "dpm has been enabled\n"); 914 return 0; 915 } 916 917 ret = smu_init_display_count(smu, 0); 918 if (ret) { 919 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 920 return ret; 921 } 922 923 ret = smu_set_driver_table_location(smu); 924 if (ret) { 925 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 926 return ret; 927 } 928 929 /* 930 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 931 */ 932 ret = smu_set_tool_table_location(smu); 933 if (ret) { 934 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 935 return ret; 936 } 937 938 /* 939 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 940 * pool location. 941 */ 942 ret = smu_notify_memory_pool_location(smu); 943 if (ret) { 944 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 945 return ret; 946 } 947 948 /* smu_dump_pptable(smu); */ 949 /* 950 * Copy pptable bo in the vram to smc with SMU MSGs such as 951 * SetDriverDramAddr and TransferTableDram2Smu. 952 */ 953 ret = smu_write_pptable(smu); 954 if (ret) { 955 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 956 return ret; 957 } 958 959 /* issue Run*Btc msg */ 960 ret = smu_run_btc(smu); 961 if (ret) 962 return ret; 963 964 ret = smu_feature_set_allowed_mask(smu); 965 if (ret) { 966 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 967 return ret; 968 } 969 970 ret = smu_system_features_control(smu, true); 971 if (ret) { 972 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 973 return ret; 974 } 975 976 if (!smu_is_dpm_running(smu)) 977 dev_info(adev->dev, "dpm has been disabled\n"); 978 979 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 980 pcie_gen = 3; 981 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 982 pcie_gen = 2; 983 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 984 pcie_gen = 1; 985 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 986 pcie_gen = 0; 987 988 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 989 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 990 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 991 */ 992 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 993 pcie_width = 6; 994 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 995 pcie_width = 5; 996 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 997 pcie_width = 4; 998 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 999 pcie_width = 3; 1000 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1001 pcie_width = 2; 1002 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1003 pcie_width = 1; 1004 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1005 if (ret) { 1006 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1007 return ret; 1008 } 1009 1010 ret = smu_get_thermal_temperature_range(smu); 1011 if (ret) { 1012 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1013 return ret; 1014 } 1015 1016 ret = smu_enable_thermal_alert(smu); 1017 if (ret) { 1018 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1019 return ret; 1020 } 1021 1022 /* 1023 * Set initialized values (get from vbios) to dpm tables context such as 1024 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1025 * type of clks. 1026 */ 1027 ret = smu_set_default_dpm_table(smu); 1028 if (ret) { 1029 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1030 return ret; 1031 } 1032 1033 /* 1034 * Set initialized values (get from vbios) to dpm tables context such as 1035 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1036 * type of clks. 1037 */ 1038 ret = smu_set_default_dpm_table(smu); 1039 if (ret) { 1040 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1041 return ret; 1042 } 1043 1044 ret = smu_notify_display_change(smu); 1045 if (ret) 1046 return ret; 1047 1048 /* 1049 * Set min deep sleep dce fclk with bootup value from vbios via 1050 * SetMinDeepSleepDcefclk MSG. 1051 */ 1052 ret = smu_set_min_dcef_deep_sleep(smu, 1053 smu->smu_table.boot_values.dcefclk / 100); 1054 if (ret) 1055 return ret; 1056 1057 return ret; 1058 } 1059 1060 static int smu_start_smc_engine(struct smu_context *smu) 1061 { 1062 struct amdgpu_device *adev = smu->adev; 1063 int ret = 0; 1064 1065 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1066 if (adev->asic_type < CHIP_NAVI10) { 1067 if (smu->ppt_funcs->load_microcode) { 1068 ret = smu->ppt_funcs->load_microcode(smu); 1069 if (ret) 1070 return ret; 1071 } 1072 } 1073 } 1074 1075 if (smu->ppt_funcs->check_fw_status) { 1076 ret = smu->ppt_funcs->check_fw_status(smu); 1077 if (ret) { 1078 dev_err(adev->dev, "SMC is not ready\n"); 1079 return ret; 1080 } 1081 } 1082 1083 /* 1084 * Send msg GetDriverIfVersion to check if the return value is equal 1085 * with DRIVER_IF_VERSION of smc header. 1086 */ 1087 ret = smu_check_fw_version(smu); 1088 if (ret) 1089 return ret; 1090 1091 return ret; 1092 } 1093 1094 static int smu_hw_init(void *handle) 1095 { 1096 int ret; 1097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1098 struct smu_context *smu = &adev->smu; 1099 1100 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1101 smu->pm_enabled = false; 1102 return 0; 1103 } 1104 1105 ret = smu_start_smc_engine(smu); 1106 if (ret) { 1107 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1108 return ret; 1109 } 1110 1111 if (smu->is_apu) { 1112 smu_powergate_sdma(&adev->smu, false); 1113 smu_dpm_set_vcn_enable(smu, true); 1114 smu_dpm_set_jpeg_enable(smu, true); 1115 smu_set_gfx_cgpg(&adev->smu, true); 1116 } 1117 1118 if (!smu->pm_enabled) 1119 return 0; 1120 1121 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1122 ret = smu_get_vbios_bootup_values(smu); 1123 if (ret) { 1124 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1125 return ret; 1126 } 1127 1128 ret = smu_setup_pptable(smu); 1129 if (ret) { 1130 dev_err(adev->dev, "Failed to setup pptable!\n"); 1131 return ret; 1132 } 1133 1134 ret = smu_get_driver_allowed_feature_mask(smu); 1135 if (ret) 1136 return ret; 1137 1138 ret = smu_smc_hw_setup(smu); 1139 if (ret) { 1140 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1141 return ret; 1142 } 1143 1144 /* 1145 * Move maximum sustainable clock retrieving here considering 1146 * 1. It is not needed on resume(from S3). 1147 * 2. DAL settings come between .hw_init and .late_init of SMU. 1148 * And DAL needs to know the maximum sustainable clocks. Thus 1149 * it cannot be put in .late_init(). 1150 */ 1151 ret = smu_init_max_sustainable_clocks(smu); 1152 if (ret) { 1153 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1154 return ret; 1155 } 1156 1157 adev->pm.dpm_enabled = true; 1158 1159 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1160 1161 return 0; 1162 } 1163 1164 static int smu_disable_dpms(struct smu_context *smu) 1165 { 1166 struct amdgpu_device *adev = smu->adev; 1167 int ret = 0; 1168 bool use_baco = !smu->is_apu && 1169 ((amdgpu_in_reset(adev) && 1170 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1171 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev))); 1172 1173 /* 1174 * For custom pptable uploading, skip the DPM features 1175 * disable process on Navi1x ASICs. 1176 * - As the gfx related features are under control of 1177 * RLC on those ASICs. RLC reinitialization will be 1178 * needed to reenable them. That will cost much more 1179 * efforts. 1180 * 1181 * - SMU firmware can handle the DPM reenablement 1182 * properly. 1183 */ 1184 if (smu->uploading_custom_pp_table && 1185 (adev->asic_type >= CHIP_NAVI10) && 1186 (adev->asic_type <= CHIP_NAVY_FLOUNDER)) 1187 return 0; 1188 1189 /* 1190 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1191 * on BACO in. Driver involvement is unnecessary. 1192 */ 1193 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1194 use_baco) 1195 return 0; 1196 1197 /* 1198 * For gpu reset, runpm and hibernation through BACO, 1199 * BACO feature has to be kept enabled. 1200 */ 1201 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1202 ret = smu_disable_all_features_with_exception(smu, 1203 SMU_FEATURE_BACO_BIT); 1204 if (ret) 1205 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1206 } else { 1207 ret = smu_system_features_control(smu, false); 1208 if (ret) 1209 dev_err(adev->dev, "Failed to disable smu features.\n"); 1210 } 1211 1212 if (adev->asic_type >= CHIP_NAVI10 && 1213 adev->gfx.rlc.funcs->stop) 1214 adev->gfx.rlc.funcs->stop(adev); 1215 1216 return ret; 1217 } 1218 1219 static int smu_smc_hw_cleanup(struct smu_context *smu) 1220 { 1221 struct amdgpu_device *adev = smu->adev; 1222 int ret = 0; 1223 1224 cancel_work_sync(&smu->throttling_logging_work); 1225 cancel_work_sync(&smu->interrupt_work); 1226 1227 ret = smu_disable_thermal_alert(smu); 1228 if (ret) { 1229 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1230 return ret; 1231 } 1232 1233 ret = smu_disable_dpms(smu); 1234 if (ret) { 1235 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1236 return ret; 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int smu_hw_fini(void *handle) 1243 { 1244 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1245 struct smu_context *smu = &adev->smu; 1246 1247 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1248 return 0; 1249 1250 if (smu->is_apu) { 1251 smu_powergate_sdma(&adev->smu, true); 1252 smu_dpm_set_vcn_enable(smu, false); 1253 smu_dpm_set_jpeg_enable(smu, false); 1254 } 1255 1256 if (!smu->pm_enabled) 1257 return 0; 1258 1259 adev->pm.dpm_enabled = false; 1260 1261 return smu_smc_hw_cleanup(smu); 1262 } 1263 1264 int smu_reset(struct smu_context *smu) 1265 { 1266 struct amdgpu_device *adev = smu->adev; 1267 int ret; 1268 1269 amdgpu_gfx_off_ctrl(smu->adev, false); 1270 1271 ret = smu_hw_fini(adev); 1272 if (ret) 1273 return ret; 1274 1275 ret = smu_hw_init(adev); 1276 if (ret) 1277 return ret; 1278 1279 ret = smu_late_init(adev); 1280 if (ret) 1281 return ret; 1282 1283 amdgpu_gfx_off_ctrl(smu->adev, true); 1284 1285 return 0; 1286 } 1287 1288 static int smu_suspend(void *handle) 1289 { 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 struct smu_context *smu = &adev->smu; 1292 int ret; 1293 1294 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1295 return 0; 1296 1297 if (!smu->pm_enabled) 1298 return 0; 1299 1300 adev->pm.dpm_enabled = false; 1301 1302 ret = smu_smc_hw_cleanup(smu); 1303 if (ret) 1304 return ret; 1305 1306 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1307 1308 if (smu->is_apu) 1309 smu_set_gfx_cgpg(&adev->smu, false); 1310 1311 return 0; 1312 } 1313 1314 static int smu_resume(void *handle) 1315 { 1316 int ret; 1317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1318 struct smu_context *smu = &adev->smu; 1319 1320 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1321 return 0; 1322 1323 if (!smu->pm_enabled) 1324 return 0; 1325 1326 dev_info(adev->dev, "SMU is resuming...\n"); 1327 1328 ret = smu_start_smc_engine(smu); 1329 if (ret) { 1330 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1331 return ret; 1332 } 1333 1334 ret = smu_smc_hw_setup(smu); 1335 if (ret) { 1336 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1337 return ret; 1338 } 1339 1340 if (smu->is_apu) 1341 smu_set_gfx_cgpg(&adev->smu, true); 1342 1343 smu->disable_uclk_switch = 0; 1344 1345 adev->pm.dpm_enabled = true; 1346 1347 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1348 1349 return 0; 1350 } 1351 1352 int smu_display_configuration_change(struct smu_context *smu, 1353 const struct amd_pp_display_configuration *display_config) 1354 { 1355 int index = 0; 1356 int num_of_active_display = 0; 1357 1358 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1359 return -EOPNOTSUPP; 1360 1361 if (!display_config) 1362 return -EINVAL; 1363 1364 mutex_lock(&smu->mutex); 1365 1366 smu_set_min_dcef_deep_sleep(smu, 1367 display_config->min_dcef_deep_sleep_set_clk / 100); 1368 1369 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1370 if (display_config->displays[index].controller_id != 0) 1371 num_of_active_display++; 1372 } 1373 1374 smu_set_active_display_count(smu, num_of_active_display); 1375 1376 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time, 1377 display_config->cpu_cc6_disable, 1378 display_config->cpu_pstate_disable, 1379 display_config->nb_pstate_switch_disable); 1380 1381 mutex_unlock(&smu->mutex); 1382 1383 return 0; 1384 } 1385 1386 static int smu_get_clock_info(struct smu_context *smu, 1387 struct smu_clock_info *clk_info, 1388 enum smu_perf_level_designation designation) 1389 { 1390 int ret; 1391 struct smu_performance_level level = {0}; 1392 1393 if (!clk_info) 1394 return -EINVAL; 1395 1396 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level); 1397 if (ret) 1398 return -EINVAL; 1399 1400 clk_info->min_mem_clk = level.memory_clock; 1401 clk_info->min_eng_clk = level.core_clock; 1402 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width; 1403 1404 ret = smu_get_perf_level(smu, designation, &level); 1405 if (ret) 1406 return -EINVAL; 1407 1408 clk_info->min_mem_clk = level.memory_clock; 1409 clk_info->min_eng_clk = level.core_clock; 1410 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width; 1411 1412 return 0; 1413 } 1414 1415 int smu_get_current_clocks(struct smu_context *smu, 1416 struct amd_pp_clock_info *clocks) 1417 { 1418 struct amd_pp_simple_clock_info simple_clocks = {0}; 1419 struct smu_clock_info hw_clocks; 1420 int ret = 0; 1421 1422 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1423 return -EOPNOTSUPP; 1424 1425 mutex_lock(&smu->mutex); 1426 1427 smu_get_dal_power_level(smu, &simple_clocks); 1428 1429 if (smu->support_power_containment) 1430 ret = smu_get_clock_info(smu, &hw_clocks, 1431 PERF_LEVEL_POWER_CONTAINMENT); 1432 else 1433 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY); 1434 1435 if (ret) { 1436 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n"); 1437 goto failed; 1438 } 1439 1440 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1441 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1442 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1443 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1444 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1445 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1446 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1447 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1448 1449 if (simple_clocks.level == 0) 1450 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; 1451 else 1452 clocks->max_clocks_state = simple_clocks.level; 1453 1454 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) { 1455 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1456 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1457 } 1458 1459 failed: 1460 mutex_unlock(&smu->mutex); 1461 return ret; 1462 } 1463 1464 static int smu_set_clockgating_state(void *handle, 1465 enum amd_clockgating_state state) 1466 { 1467 return 0; 1468 } 1469 1470 static int smu_set_powergating_state(void *handle, 1471 enum amd_powergating_state state) 1472 { 1473 return 0; 1474 } 1475 1476 static int smu_enable_umd_pstate(void *handle, 1477 enum amd_dpm_forced_level *level) 1478 { 1479 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1480 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1481 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1482 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1483 1484 struct smu_context *smu = (struct smu_context*)(handle); 1485 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1486 1487 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1488 return -EINVAL; 1489 1490 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1491 /* enter umd pstate, save current level, disable gfx cg*/ 1492 if (*level & profile_mode_mask) { 1493 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1494 smu_dpm_ctx->enable_umd_pstate = true; 1495 amdgpu_device_ip_set_powergating_state(smu->adev, 1496 AMD_IP_BLOCK_TYPE_GFX, 1497 AMD_PG_STATE_UNGATE); 1498 amdgpu_device_ip_set_clockgating_state(smu->adev, 1499 AMD_IP_BLOCK_TYPE_GFX, 1500 AMD_CG_STATE_UNGATE); 1501 smu_gfx_ulv_control(smu, false); 1502 smu_deep_sleep_control(smu, false); 1503 } 1504 } else { 1505 /* exit umd pstate, restore level, enable gfx cg*/ 1506 if (!(*level & profile_mode_mask)) { 1507 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1508 *level = smu_dpm_ctx->saved_dpm_level; 1509 smu_dpm_ctx->enable_umd_pstate = false; 1510 smu_deep_sleep_control(smu, true); 1511 smu_gfx_ulv_control(smu, true); 1512 amdgpu_device_ip_set_clockgating_state(smu->adev, 1513 AMD_IP_BLOCK_TYPE_GFX, 1514 AMD_CG_STATE_GATE); 1515 amdgpu_device_ip_set_powergating_state(smu->adev, 1516 AMD_IP_BLOCK_TYPE_GFX, 1517 AMD_PG_STATE_GATE); 1518 } 1519 } 1520 1521 return 0; 1522 } 1523 1524 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1525 enum amd_dpm_forced_level level, 1526 bool skip_display_settings) 1527 { 1528 int ret = 0; 1529 int index = 0; 1530 long workload; 1531 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1532 1533 if (!skip_display_settings) { 1534 ret = smu_display_config_changed(smu); 1535 if (ret) { 1536 dev_err(smu->adev->dev, "Failed to change display config!"); 1537 return ret; 1538 } 1539 } 1540 1541 ret = smu_apply_clocks_adjust_rules(smu); 1542 if (ret) { 1543 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1544 return ret; 1545 } 1546 1547 if (!skip_display_settings) { 1548 ret = smu_notify_smc_display_config(smu); 1549 if (ret) { 1550 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1551 return ret; 1552 } 1553 } 1554 1555 if (smu_dpm_ctx->dpm_level != level) { 1556 ret = smu_asic_set_performance_level(smu, level); 1557 if (ret) { 1558 dev_err(smu->adev->dev, "Failed to set performance level!"); 1559 return ret; 1560 } 1561 1562 /* update the saved copy */ 1563 smu_dpm_ctx->dpm_level = level; 1564 } 1565 1566 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1567 index = fls(smu->workload_mask); 1568 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1569 workload = smu->workload_setting[index]; 1570 1571 if (smu->power_profile_mode != workload) 1572 smu_set_power_profile_mode(smu, &workload, 0, false); 1573 } 1574 1575 return ret; 1576 } 1577 1578 int smu_handle_task(struct smu_context *smu, 1579 enum amd_dpm_forced_level level, 1580 enum amd_pp_task task_id, 1581 bool lock_needed) 1582 { 1583 int ret = 0; 1584 1585 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1586 return -EOPNOTSUPP; 1587 1588 if (lock_needed) 1589 mutex_lock(&smu->mutex); 1590 1591 switch (task_id) { 1592 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1593 ret = smu_pre_display_config_changed(smu); 1594 if (ret) 1595 goto out; 1596 ret = smu_set_cpu_power_state(smu); 1597 if (ret) 1598 goto out; 1599 ret = smu_adjust_power_state_dynamic(smu, level, false); 1600 break; 1601 case AMD_PP_TASK_COMPLETE_INIT: 1602 case AMD_PP_TASK_READJUST_POWER_STATE: 1603 ret = smu_adjust_power_state_dynamic(smu, level, true); 1604 break; 1605 default: 1606 break; 1607 } 1608 1609 out: 1610 if (lock_needed) 1611 mutex_unlock(&smu->mutex); 1612 1613 return ret; 1614 } 1615 1616 int smu_switch_power_profile(struct smu_context *smu, 1617 enum PP_SMC_POWER_PROFILE type, 1618 bool en) 1619 { 1620 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1621 long workload; 1622 uint32_t index; 1623 1624 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1625 return -EOPNOTSUPP; 1626 1627 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1628 return -EINVAL; 1629 1630 mutex_lock(&smu->mutex); 1631 1632 if (!en) { 1633 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1634 index = fls(smu->workload_mask); 1635 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1636 workload = smu->workload_setting[index]; 1637 } else { 1638 smu->workload_mask |= (1 << smu->workload_prority[type]); 1639 index = fls(smu->workload_mask); 1640 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1641 workload = smu->workload_setting[index]; 1642 } 1643 1644 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1645 smu_set_power_profile_mode(smu, &workload, 0, false); 1646 1647 mutex_unlock(&smu->mutex); 1648 1649 return 0; 1650 } 1651 1652 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) 1653 { 1654 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1655 enum amd_dpm_forced_level level; 1656 1657 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1658 return -EOPNOTSUPP; 1659 1660 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1661 return -EINVAL; 1662 1663 mutex_lock(&(smu->mutex)); 1664 level = smu_dpm_ctx->dpm_level; 1665 mutex_unlock(&(smu->mutex)); 1666 1667 return level; 1668 } 1669 1670 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) 1671 { 1672 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1673 int ret = 0; 1674 1675 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1676 return -EOPNOTSUPP; 1677 1678 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1679 return -EINVAL; 1680 1681 mutex_lock(&smu->mutex); 1682 1683 ret = smu_enable_umd_pstate(smu, &level); 1684 if (ret) { 1685 mutex_unlock(&smu->mutex); 1686 return ret; 1687 } 1688 1689 ret = smu_handle_task(smu, level, 1690 AMD_PP_TASK_READJUST_POWER_STATE, 1691 false); 1692 1693 mutex_unlock(&smu->mutex); 1694 1695 return ret; 1696 } 1697 1698 int smu_set_display_count(struct smu_context *smu, uint32_t count) 1699 { 1700 int ret = 0; 1701 1702 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1703 return -EOPNOTSUPP; 1704 1705 mutex_lock(&smu->mutex); 1706 ret = smu_init_display_count(smu, count); 1707 mutex_unlock(&smu->mutex); 1708 1709 return ret; 1710 } 1711 1712 int smu_force_clk_levels(struct smu_context *smu, 1713 enum smu_clk_type clk_type, 1714 uint32_t mask) 1715 { 1716 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1717 int ret = 0; 1718 1719 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1720 return -EOPNOTSUPP; 1721 1722 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1723 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1724 return -EINVAL; 1725 } 1726 1727 mutex_lock(&smu->mutex); 1728 1729 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) 1730 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1731 1732 mutex_unlock(&smu->mutex); 1733 1734 return ret; 1735 } 1736 1737 /* 1738 * On system suspending or resetting, the dpm_enabled 1739 * flag will be cleared. So that those SMU services which 1740 * are not supported will be gated. 1741 * However, the mp1 state setting should still be granted 1742 * even if the dpm_enabled cleared. 1743 */ 1744 int smu_set_mp1_state(struct smu_context *smu, 1745 enum pp_mp1_state mp1_state) 1746 { 1747 uint16_t msg; 1748 int ret; 1749 1750 if (!smu->pm_enabled) 1751 return -EOPNOTSUPP; 1752 1753 mutex_lock(&smu->mutex); 1754 1755 switch (mp1_state) { 1756 case PP_MP1_STATE_SHUTDOWN: 1757 msg = SMU_MSG_PrepareMp1ForShutdown; 1758 break; 1759 case PP_MP1_STATE_UNLOAD: 1760 msg = SMU_MSG_PrepareMp1ForUnload; 1761 break; 1762 case PP_MP1_STATE_RESET: 1763 msg = SMU_MSG_PrepareMp1ForReset; 1764 break; 1765 case PP_MP1_STATE_NONE: 1766 default: 1767 mutex_unlock(&smu->mutex); 1768 return 0; 1769 } 1770 1771 ret = smu_send_smc_msg(smu, msg, NULL); 1772 /* some asics may not support those messages */ 1773 if (ret == -EINVAL) 1774 ret = 0; 1775 if (ret) 1776 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); 1777 1778 mutex_unlock(&smu->mutex); 1779 1780 return ret; 1781 } 1782 1783 int smu_set_df_cstate(struct smu_context *smu, 1784 enum pp_df_cstate state) 1785 { 1786 int ret = 0; 1787 1788 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1789 return -EOPNOTSUPP; 1790 1791 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1792 return 0; 1793 1794 mutex_lock(&smu->mutex); 1795 1796 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1797 if (ret) 1798 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1799 1800 mutex_unlock(&smu->mutex); 1801 1802 return ret; 1803 } 1804 1805 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1806 { 1807 int ret = 0; 1808 1809 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1810 return -EOPNOTSUPP; 1811 1812 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1813 return 0; 1814 1815 mutex_lock(&smu->mutex); 1816 1817 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1818 if (ret) 1819 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1820 1821 mutex_unlock(&smu->mutex); 1822 1823 return ret; 1824 } 1825 1826 int smu_write_watermarks_table(struct smu_context *smu) 1827 { 1828 int ret = 0; 1829 1830 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1831 return -EOPNOTSUPP; 1832 1833 mutex_lock(&smu->mutex); 1834 1835 ret = smu_set_watermarks_table(smu, NULL); 1836 1837 mutex_unlock(&smu->mutex); 1838 1839 return ret; 1840 } 1841 1842 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 1843 struct pp_smu_wm_range_sets *clock_ranges) 1844 { 1845 int ret = 0; 1846 1847 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1848 return -EOPNOTSUPP; 1849 1850 if (smu->disable_watermark) 1851 return 0; 1852 1853 mutex_lock(&smu->mutex); 1854 1855 ret = smu_set_watermarks_table(smu, clock_ranges); 1856 1857 mutex_unlock(&smu->mutex); 1858 1859 return ret; 1860 } 1861 1862 int smu_set_ac_dc(struct smu_context *smu) 1863 { 1864 int ret = 0; 1865 1866 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1867 return -EOPNOTSUPP; 1868 1869 /* controlled by firmware */ 1870 if (smu->dc_controlled_by_gpio) 1871 return 0; 1872 1873 mutex_lock(&smu->mutex); 1874 ret = smu_set_power_source(smu, 1875 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 1876 SMU_POWER_SOURCE_DC); 1877 if (ret) 1878 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 1879 smu->adev->pm.ac_power ? "AC" : "DC"); 1880 mutex_unlock(&smu->mutex); 1881 1882 return ret; 1883 } 1884 1885 const struct amd_ip_funcs smu_ip_funcs = { 1886 .name = "smu", 1887 .early_init = smu_early_init, 1888 .late_init = smu_late_init, 1889 .sw_init = smu_sw_init, 1890 .sw_fini = smu_sw_fini, 1891 .hw_init = smu_hw_init, 1892 .hw_fini = smu_hw_fini, 1893 .suspend = smu_suspend, 1894 .resume = smu_resume, 1895 .is_idle = NULL, 1896 .check_soft_reset = NULL, 1897 .wait_for_idle = NULL, 1898 .soft_reset = NULL, 1899 .set_clockgating_state = smu_set_clockgating_state, 1900 .set_powergating_state = smu_set_powergating_state, 1901 .enable_umd_pstate = smu_enable_umd_pstate, 1902 }; 1903 1904 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 1905 { 1906 .type = AMD_IP_BLOCK_TYPE_SMC, 1907 .major = 11, 1908 .minor = 0, 1909 .rev = 0, 1910 .funcs = &smu_ip_funcs, 1911 }; 1912 1913 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 1914 { 1915 .type = AMD_IP_BLOCK_TYPE_SMC, 1916 .major = 12, 1917 .minor = 0, 1918 .rev = 0, 1919 .funcs = &smu_ip_funcs, 1920 }; 1921 1922 int smu_load_microcode(struct smu_context *smu) 1923 { 1924 int ret = 0; 1925 1926 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1927 return -EOPNOTSUPP; 1928 1929 mutex_lock(&smu->mutex); 1930 1931 if (smu->ppt_funcs->load_microcode) 1932 ret = smu->ppt_funcs->load_microcode(smu); 1933 1934 mutex_unlock(&smu->mutex); 1935 1936 return ret; 1937 } 1938 1939 int smu_check_fw_status(struct smu_context *smu) 1940 { 1941 int ret = 0; 1942 1943 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1944 return -EOPNOTSUPP; 1945 1946 mutex_lock(&smu->mutex); 1947 1948 if (smu->ppt_funcs->check_fw_status) 1949 ret = smu->ppt_funcs->check_fw_status(smu); 1950 1951 mutex_unlock(&smu->mutex); 1952 1953 return ret; 1954 } 1955 1956 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 1957 { 1958 int ret = 0; 1959 1960 mutex_lock(&smu->mutex); 1961 1962 if (smu->ppt_funcs->set_gfx_cgpg) 1963 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 1964 1965 mutex_unlock(&smu->mutex); 1966 1967 return ret; 1968 } 1969 1970 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) 1971 { 1972 int ret = 0; 1973 1974 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1975 return -EOPNOTSUPP; 1976 1977 mutex_lock(&smu->mutex); 1978 1979 if (smu->ppt_funcs->set_fan_speed_rpm) 1980 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 1981 1982 mutex_unlock(&smu->mutex); 1983 1984 return ret; 1985 } 1986 1987 int smu_get_power_limit(struct smu_context *smu, 1988 uint32_t *limit, 1989 bool max_setting) 1990 { 1991 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1992 return -EOPNOTSUPP; 1993 1994 mutex_lock(&smu->mutex); 1995 1996 *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit); 1997 1998 mutex_unlock(&smu->mutex); 1999 2000 return 0; 2001 } 2002 2003 int smu_set_power_limit(struct smu_context *smu, uint32_t limit) 2004 { 2005 int ret = 0; 2006 2007 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2008 return -EOPNOTSUPP; 2009 2010 mutex_lock(&smu->mutex); 2011 2012 if (limit > smu->max_power_limit) { 2013 dev_err(smu->adev->dev, 2014 "New power limit (%d) is over the max allowed %d\n", 2015 limit, smu->max_power_limit); 2016 goto out; 2017 } 2018 2019 if (!limit) 2020 limit = smu->current_power_limit; 2021 2022 if (smu->ppt_funcs->set_power_limit) 2023 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2024 2025 out: 2026 mutex_unlock(&smu->mutex); 2027 2028 return ret; 2029 } 2030 2031 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2032 { 2033 int ret = 0; 2034 2035 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2036 return -EOPNOTSUPP; 2037 2038 mutex_lock(&smu->mutex); 2039 2040 if (smu->ppt_funcs->print_clk_levels) 2041 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2042 2043 mutex_unlock(&smu->mutex); 2044 2045 return ret; 2046 } 2047 2048 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type) 2049 { 2050 int ret = 0; 2051 2052 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2053 return -EOPNOTSUPP; 2054 2055 mutex_lock(&smu->mutex); 2056 2057 if (smu->ppt_funcs->get_od_percentage) 2058 ret = smu->ppt_funcs->get_od_percentage(smu, type); 2059 2060 mutex_unlock(&smu->mutex); 2061 2062 return ret; 2063 } 2064 2065 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value) 2066 { 2067 int ret = 0; 2068 2069 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2070 return -EOPNOTSUPP; 2071 2072 mutex_lock(&smu->mutex); 2073 2074 if (smu->ppt_funcs->set_od_percentage) 2075 ret = smu->ppt_funcs->set_od_percentage(smu, type, value); 2076 2077 mutex_unlock(&smu->mutex); 2078 2079 return ret; 2080 } 2081 2082 int smu_od_edit_dpm_table(struct smu_context *smu, 2083 enum PP_OD_DPM_TABLE_COMMAND type, 2084 long *input, uint32_t size) 2085 { 2086 int ret = 0; 2087 2088 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2089 return -EOPNOTSUPP; 2090 2091 mutex_lock(&smu->mutex); 2092 2093 if (smu->ppt_funcs->od_edit_dpm_table) { 2094 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2095 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE)) 2096 ret = smu_handle_task(smu, 2097 smu->smu_dpm.dpm_level, 2098 AMD_PP_TASK_READJUST_POWER_STATE, 2099 false); 2100 } 2101 2102 mutex_unlock(&smu->mutex); 2103 2104 return ret; 2105 } 2106 2107 int smu_read_sensor(struct smu_context *smu, 2108 enum amd_pp_sensors sensor, 2109 void *data, uint32_t *size) 2110 { 2111 struct smu_umd_pstate_table *pstate_table = 2112 &smu->pstate_table; 2113 int ret = 0; 2114 2115 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2116 return -EOPNOTSUPP; 2117 2118 if (!data || !size) 2119 return -EINVAL; 2120 2121 mutex_lock(&smu->mutex); 2122 2123 if (smu->ppt_funcs->read_sensor) 2124 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2125 goto unlock; 2126 2127 switch (sensor) { 2128 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2129 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2130 *size = 4; 2131 break; 2132 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2133 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2134 *size = 4; 2135 break; 2136 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2137 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2138 *size = 8; 2139 break; 2140 case AMDGPU_PP_SENSOR_UVD_POWER: 2141 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2142 *size = 4; 2143 break; 2144 case AMDGPU_PP_SENSOR_VCE_POWER: 2145 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2146 *size = 4; 2147 break; 2148 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2149 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2150 *size = 4; 2151 break; 2152 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2153 *(uint32_t *)data = 0; 2154 *size = 4; 2155 break; 2156 default: 2157 *size = 0; 2158 ret = -EOPNOTSUPP; 2159 break; 2160 } 2161 2162 unlock: 2163 mutex_unlock(&smu->mutex); 2164 2165 return ret; 2166 } 2167 2168 int smu_get_power_profile_mode(struct smu_context *smu, char *buf) 2169 { 2170 int ret = 0; 2171 2172 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2173 return -EOPNOTSUPP; 2174 2175 mutex_lock(&smu->mutex); 2176 2177 if (smu->ppt_funcs->get_power_profile_mode) 2178 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2179 2180 mutex_unlock(&smu->mutex); 2181 2182 return ret; 2183 } 2184 2185 int smu_set_power_profile_mode(struct smu_context *smu, 2186 long *param, 2187 uint32_t param_size, 2188 bool lock_needed) 2189 { 2190 int ret = 0; 2191 2192 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2193 return -EOPNOTSUPP; 2194 2195 if (lock_needed) 2196 mutex_lock(&smu->mutex); 2197 2198 if (smu->ppt_funcs->set_power_profile_mode) 2199 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2200 2201 if (lock_needed) 2202 mutex_unlock(&smu->mutex); 2203 2204 return ret; 2205 } 2206 2207 2208 int smu_get_fan_control_mode(struct smu_context *smu) 2209 { 2210 int ret = 0; 2211 2212 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2213 return -EOPNOTSUPP; 2214 2215 mutex_lock(&smu->mutex); 2216 2217 if (smu->ppt_funcs->get_fan_control_mode) 2218 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2219 2220 mutex_unlock(&smu->mutex); 2221 2222 return ret; 2223 } 2224 2225 int smu_set_fan_control_mode(struct smu_context *smu, int value) 2226 { 2227 int ret = 0; 2228 2229 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2230 return -EOPNOTSUPP; 2231 2232 mutex_lock(&smu->mutex); 2233 2234 if (smu->ppt_funcs->set_fan_control_mode) 2235 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2236 2237 mutex_unlock(&smu->mutex); 2238 2239 return ret; 2240 } 2241 2242 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed) 2243 { 2244 int ret = 0; 2245 uint32_t percent; 2246 uint32_t current_rpm; 2247 2248 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2249 return -EOPNOTSUPP; 2250 2251 mutex_lock(&smu->mutex); 2252 2253 if (smu->ppt_funcs->get_fan_speed_rpm) { 2254 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, ¤t_rpm); 2255 if (!ret) { 2256 percent = current_rpm * 100 / smu->fan_max_rpm; 2257 *speed = percent > 100 ? 100 : percent; 2258 } 2259 } 2260 2261 mutex_unlock(&smu->mutex); 2262 2263 2264 return ret; 2265 } 2266 2267 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) 2268 { 2269 int ret = 0; 2270 uint32_t rpm; 2271 2272 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2273 return -EOPNOTSUPP; 2274 2275 mutex_lock(&smu->mutex); 2276 2277 if (smu->ppt_funcs->set_fan_speed_rpm) { 2278 if (speed > 100) 2279 speed = 100; 2280 rpm = speed * smu->fan_max_rpm / 100; 2281 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm); 2282 } 2283 2284 mutex_unlock(&smu->mutex); 2285 2286 return ret; 2287 } 2288 2289 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed) 2290 { 2291 int ret = 0; 2292 2293 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2294 return -EOPNOTSUPP; 2295 2296 mutex_lock(&smu->mutex); 2297 2298 if (smu->ppt_funcs->get_fan_speed_rpm) 2299 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2300 2301 mutex_unlock(&smu->mutex); 2302 2303 return ret; 2304 } 2305 2306 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk) 2307 { 2308 int ret = 0; 2309 2310 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2311 return -EOPNOTSUPP; 2312 2313 mutex_lock(&smu->mutex); 2314 2315 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2316 2317 mutex_unlock(&smu->mutex); 2318 2319 return ret; 2320 } 2321 2322 int smu_get_clock_by_type(struct smu_context *smu, 2323 enum amd_pp_clock_type type, 2324 struct amd_pp_clocks *clocks) 2325 { 2326 int ret = 0; 2327 2328 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2329 return -EOPNOTSUPP; 2330 2331 mutex_lock(&smu->mutex); 2332 2333 if (smu->ppt_funcs->get_clock_by_type) 2334 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks); 2335 2336 mutex_unlock(&smu->mutex); 2337 2338 return ret; 2339 } 2340 2341 int smu_get_max_high_clocks(struct smu_context *smu, 2342 struct amd_pp_simple_clock_info *clocks) 2343 { 2344 int ret = 0; 2345 2346 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2347 return -EOPNOTSUPP; 2348 2349 mutex_lock(&smu->mutex); 2350 2351 if (smu->ppt_funcs->get_max_high_clocks) 2352 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks); 2353 2354 mutex_unlock(&smu->mutex); 2355 2356 return ret; 2357 } 2358 2359 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 2360 enum smu_clk_type clk_type, 2361 struct pp_clock_levels_with_latency *clocks) 2362 { 2363 int ret = 0; 2364 2365 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2366 return -EOPNOTSUPP; 2367 2368 mutex_lock(&smu->mutex); 2369 2370 if (smu->ppt_funcs->get_clock_by_type_with_latency) 2371 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2372 2373 mutex_unlock(&smu->mutex); 2374 2375 return ret; 2376 } 2377 2378 int smu_get_clock_by_type_with_voltage(struct smu_context *smu, 2379 enum amd_pp_clock_type type, 2380 struct pp_clock_levels_with_voltage *clocks) 2381 { 2382 int ret = 0; 2383 2384 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2385 return -EOPNOTSUPP; 2386 2387 mutex_lock(&smu->mutex); 2388 2389 if (smu->ppt_funcs->get_clock_by_type_with_voltage) 2390 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks); 2391 2392 mutex_unlock(&smu->mutex); 2393 2394 return ret; 2395 } 2396 2397 2398 int smu_display_clock_voltage_request(struct smu_context *smu, 2399 struct pp_display_clock_request *clock_req) 2400 { 2401 int ret = 0; 2402 2403 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2404 return -EOPNOTSUPP; 2405 2406 mutex_lock(&smu->mutex); 2407 2408 if (smu->ppt_funcs->display_clock_voltage_request) 2409 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2410 2411 mutex_unlock(&smu->mutex); 2412 2413 return ret; 2414 } 2415 2416 2417 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch) 2418 { 2419 int ret = -EINVAL; 2420 2421 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2422 return -EOPNOTSUPP; 2423 2424 mutex_lock(&smu->mutex); 2425 2426 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2427 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2428 2429 mutex_unlock(&smu->mutex); 2430 2431 return ret; 2432 } 2433 2434 int smu_notify_smu_enable_pwe(struct smu_context *smu) 2435 { 2436 int ret = 0; 2437 2438 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2439 return -EOPNOTSUPP; 2440 2441 mutex_lock(&smu->mutex); 2442 2443 if (smu->ppt_funcs->notify_smu_enable_pwe) 2444 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu); 2445 2446 mutex_unlock(&smu->mutex); 2447 2448 return ret; 2449 } 2450 2451 int smu_set_xgmi_pstate(struct smu_context *smu, 2452 uint32_t pstate) 2453 { 2454 int ret = 0; 2455 2456 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2457 return -EOPNOTSUPP; 2458 2459 mutex_lock(&smu->mutex); 2460 2461 if (smu->ppt_funcs->set_xgmi_pstate) 2462 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2463 2464 mutex_unlock(&smu->mutex); 2465 2466 if(ret) 2467 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2468 2469 return ret; 2470 } 2471 2472 int smu_set_azalia_d3_pme(struct smu_context *smu) 2473 { 2474 int ret = 0; 2475 2476 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2477 return -EOPNOTSUPP; 2478 2479 mutex_lock(&smu->mutex); 2480 2481 if (smu->ppt_funcs->set_azalia_d3_pme) 2482 ret = smu->ppt_funcs->set_azalia_d3_pme(smu); 2483 2484 mutex_unlock(&smu->mutex); 2485 2486 return ret; 2487 } 2488 2489 /* 2490 * On system suspending or resetting, the dpm_enabled 2491 * flag will be cleared. So that those SMU services which 2492 * are not supported will be gated. 2493 * 2494 * However, the baco/mode1 reset should still be granted 2495 * as they are still supported and necessary. 2496 */ 2497 bool smu_baco_is_support(struct smu_context *smu) 2498 { 2499 bool ret = false; 2500 2501 if (!smu->pm_enabled) 2502 return false; 2503 2504 mutex_lock(&smu->mutex); 2505 2506 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2507 ret = smu->ppt_funcs->baco_is_support(smu); 2508 2509 mutex_unlock(&smu->mutex); 2510 2511 return ret; 2512 } 2513 2514 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state) 2515 { 2516 if (smu->ppt_funcs->baco_get_state) 2517 return -EINVAL; 2518 2519 mutex_lock(&smu->mutex); 2520 *state = smu->ppt_funcs->baco_get_state(smu); 2521 mutex_unlock(&smu->mutex); 2522 2523 return 0; 2524 } 2525 2526 int smu_baco_enter(struct smu_context *smu) 2527 { 2528 int ret = 0; 2529 2530 if (!smu->pm_enabled) 2531 return -EOPNOTSUPP; 2532 2533 mutex_lock(&smu->mutex); 2534 2535 if (smu->ppt_funcs->baco_enter) 2536 ret = smu->ppt_funcs->baco_enter(smu); 2537 2538 mutex_unlock(&smu->mutex); 2539 2540 if (ret) 2541 dev_err(smu->adev->dev, "Failed to enter BACO state!\n"); 2542 2543 return ret; 2544 } 2545 2546 int smu_baco_exit(struct smu_context *smu) 2547 { 2548 int ret = 0; 2549 2550 if (!smu->pm_enabled) 2551 return -EOPNOTSUPP; 2552 2553 mutex_lock(&smu->mutex); 2554 2555 if (smu->ppt_funcs->baco_exit) 2556 ret = smu->ppt_funcs->baco_exit(smu); 2557 2558 mutex_unlock(&smu->mutex); 2559 2560 if (ret) 2561 dev_err(smu->adev->dev, "Failed to exit BACO state!\n"); 2562 2563 return ret; 2564 } 2565 2566 bool smu_mode1_reset_is_support(struct smu_context *smu) 2567 { 2568 bool ret = false; 2569 2570 if (!smu->pm_enabled) 2571 return false; 2572 2573 mutex_lock(&smu->mutex); 2574 2575 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2576 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2577 2578 mutex_unlock(&smu->mutex); 2579 2580 return ret; 2581 } 2582 2583 int smu_mode1_reset(struct smu_context *smu) 2584 { 2585 int ret = 0; 2586 2587 if (!smu->pm_enabled) 2588 return -EOPNOTSUPP; 2589 2590 mutex_lock(&smu->mutex); 2591 2592 if (smu->ppt_funcs->mode1_reset) 2593 ret = smu->ppt_funcs->mode1_reset(smu); 2594 2595 mutex_unlock(&smu->mutex); 2596 2597 return ret; 2598 } 2599 2600 int smu_mode2_reset(struct smu_context *smu) 2601 { 2602 int ret = 0; 2603 2604 if (!smu->pm_enabled) 2605 return -EOPNOTSUPP; 2606 2607 mutex_lock(&smu->mutex); 2608 2609 if (smu->ppt_funcs->mode2_reset) 2610 ret = smu->ppt_funcs->mode2_reset(smu); 2611 2612 mutex_unlock(&smu->mutex); 2613 2614 if (ret) 2615 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2616 2617 return ret; 2618 } 2619 2620 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 2621 struct pp_smu_nv_clock_table *max_clocks) 2622 { 2623 int ret = 0; 2624 2625 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2626 return -EOPNOTSUPP; 2627 2628 mutex_lock(&smu->mutex); 2629 2630 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2631 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2632 2633 mutex_unlock(&smu->mutex); 2634 2635 return ret; 2636 } 2637 2638 int smu_get_uclk_dpm_states(struct smu_context *smu, 2639 unsigned int *clock_values_in_khz, 2640 unsigned int *num_states) 2641 { 2642 int ret = 0; 2643 2644 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2645 return -EOPNOTSUPP; 2646 2647 mutex_lock(&smu->mutex); 2648 2649 if (smu->ppt_funcs->get_uclk_dpm_states) 2650 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2651 2652 mutex_unlock(&smu->mutex); 2653 2654 return ret; 2655 } 2656 2657 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu) 2658 { 2659 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2660 2661 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2662 return -EOPNOTSUPP; 2663 2664 mutex_lock(&smu->mutex); 2665 2666 if (smu->ppt_funcs->get_current_power_state) 2667 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2668 2669 mutex_unlock(&smu->mutex); 2670 2671 return pm_state; 2672 } 2673 2674 int smu_get_dpm_clock_table(struct smu_context *smu, 2675 struct dpm_clocks *clock_table) 2676 { 2677 int ret = 0; 2678 2679 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2680 return -EOPNOTSUPP; 2681 2682 mutex_lock(&smu->mutex); 2683 2684 if (smu->ppt_funcs->get_dpm_clock_table) 2685 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2686 2687 mutex_unlock(&smu->mutex); 2688 2689 return ret; 2690 } 2691 2692 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, 2693 void **table) 2694 { 2695 ssize_t size; 2696 2697 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2698 return -EOPNOTSUPP; 2699 2700 if (!smu->ppt_funcs->get_gpu_metrics) 2701 return -EOPNOTSUPP; 2702 2703 mutex_lock(&smu->mutex); 2704 2705 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2706 2707 mutex_unlock(&smu->mutex); 2708 2709 return size; 2710 } 2711 2712 int smu_enable_mgpu_fan_boost(struct smu_context *smu) 2713 { 2714 int ret = 0; 2715 2716 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2717 return -EOPNOTSUPP; 2718 2719 mutex_lock(&smu->mutex); 2720 2721 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2722 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2723 2724 mutex_unlock(&smu->mutex); 2725 2726 return ret; 2727 } 2728