1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "amd_pcie.h" 39 40 /* 41 * DO NOT use these for err/warn/info/debug messages. 42 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 43 * They are more MGPU friendly. 44 */ 45 #undef pr_err 46 #undef pr_warn 47 #undef pr_info 48 #undef pr_debug 49 50 static const struct amd_pm_funcs swsmu_pm_funcs; 51 static int smu_force_smuclk_levels(struct smu_context *smu, 52 enum smu_clk_type clk_type, 53 uint32_t mask); 54 static int smu_handle_task(struct smu_context *smu, 55 enum amd_dpm_forced_level level, 56 enum amd_pp_task task_id, 57 bool lock_needed); 58 static int smu_reset(struct smu_context *smu); 59 static int smu_set_fan_speed_percent(void *handle, u32 speed); 60 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 61 static int smu_set_power_limit(void *handle, uint32_t limit); 62 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 63 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 64 65 static int smu_sys_get_pp_feature_mask(void *handle, 66 char *buf) 67 { 68 struct smu_context *smu = handle; 69 int size = 0; 70 71 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 72 return -EOPNOTSUPP; 73 74 mutex_lock(&smu->mutex); 75 76 size = smu_get_pp_feature_mask(smu, buf); 77 78 mutex_unlock(&smu->mutex); 79 80 return size; 81 } 82 83 static int smu_sys_set_pp_feature_mask(void *handle, 84 uint64_t new_mask) 85 { 86 struct smu_context *smu = handle; 87 int ret = 0; 88 89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 90 return -EOPNOTSUPP; 91 92 mutex_lock(&smu->mutex); 93 94 ret = smu_set_pp_feature_mask(smu, new_mask); 95 96 mutex_unlock(&smu->mutex); 97 98 return ret; 99 } 100 101 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 102 { 103 int ret = 0; 104 struct smu_context *smu = &adev->smu; 105 106 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 107 *value = smu_get_gfx_off_status(smu); 108 else 109 ret = -EINVAL; 110 111 return ret; 112 } 113 114 int smu_set_soft_freq_range(struct smu_context *smu, 115 enum smu_clk_type clk_type, 116 uint32_t min, 117 uint32_t max) 118 { 119 int ret = 0; 120 121 mutex_lock(&smu->mutex); 122 123 if (smu->ppt_funcs->set_soft_freq_limited_range) 124 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 125 clk_type, 126 min, 127 max); 128 129 mutex_unlock(&smu->mutex); 130 131 return ret; 132 } 133 134 int smu_get_dpm_freq_range(struct smu_context *smu, 135 enum smu_clk_type clk_type, 136 uint32_t *min, 137 uint32_t *max) 138 { 139 int ret = 0; 140 141 if (!min && !max) 142 return -EINVAL; 143 144 mutex_lock(&smu->mutex); 145 146 if (smu->ppt_funcs->get_dpm_ultimate_freq) 147 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 148 clk_type, 149 min, 150 max); 151 152 mutex_unlock(&smu->mutex); 153 154 return ret; 155 } 156 157 static u32 smu_get_mclk(void *handle, bool low) 158 { 159 struct smu_context *smu = handle; 160 uint32_t clk_freq; 161 int ret = 0; 162 163 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 164 low ? &clk_freq : NULL, 165 !low ? &clk_freq : NULL); 166 if (ret) 167 return 0; 168 return clk_freq * 100; 169 } 170 171 static u32 smu_get_sclk(void *handle, bool low) 172 { 173 struct smu_context *smu = handle; 174 uint32_t clk_freq; 175 int ret = 0; 176 177 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 178 low ? &clk_freq : NULL, 179 !low ? &clk_freq : NULL); 180 if (ret) 181 return 0; 182 return clk_freq * 100; 183 } 184 185 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 186 bool enable) 187 { 188 struct smu_power_context *smu_power = &smu->smu_power; 189 struct smu_power_gate *power_gate = &smu_power->power_gate; 190 int ret = 0; 191 192 if (!smu->ppt_funcs->dpm_set_vcn_enable) 193 return 0; 194 195 if (atomic_read(&power_gate->vcn_gated) ^ enable) 196 return 0; 197 198 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 199 if (!ret) 200 atomic_set(&power_gate->vcn_gated, !enable); 201 202 return ret; 203 } 204 205 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 206 bool enable) 207 { 208 struct smu_power_context *smu_power = &smu->smu_power; 209 struct smu_power_gate *power_gate = &smu_power->power_gate; 210 int ret = 0; 211 212 mutex_lock(&power_gate->vcn_gate_lock); 213 214 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 215 216 mutex_unlock(&power_gate->vcn_gate_lock); 217 218 return ret; 219 } 220 221 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 222 bool enable) 223 { 224 struct smu_power_context *smu_power = &smu->smu_power; 225 struct smu_power_gate *power_gate = &smu_power->power_gate; 226 int ret = 0; 227 228 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 229 return 0; 230 231 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 232 return 0; 233 234 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 235 if (!ret) 236 atomic_set(&power_gate->jpeg_gated, !enable); 237 238 return ret; 239 } 240 241 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 242 bool enable) 243 { 244 struct smu_power_context *smu_power = &smu->smu_power; 245 struct smu_power_gate *power_gate = &smu_power->power_gate; 246 int ret = 0; 247 248 mutex_lock(&power_gate->jpeg_gate_lock); 249 250 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 251 252 mutex_unlock(&power_gate->jpeg_gate_lock); 253 254 return ret; 255 } 256 257 /** 258 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 259 * 260 * @handle: smu_context pointer 261 * @block_type: the IP block to power gate/ungate 262 * @gate: to power gate if true, ungate otherwise 263 * 264 * This API uses no smu->mutex lock protection due to: 265 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 266 * This is guarded to be race condition free by the caller. 267 * 2. Or get called on user setting request of power_dpm_force_performance_level. 268 * Under this case, the smu->mutex lock protection is already enforced on 269 * the parent API smu_force_performance_level of the call path. 270 */ 271 static int smu_dpm_set_power_gate(void *handle, 272 uint32_t block_type, 273 bool gate) 274 { 275 struct smu_context *smu = handle; 276 int ret = 0; 277 278 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 279 return -EOPNOTSUPP; 280 281 switch (block_type) { 282 /* 283 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 284 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 285 */ 286 case AMD_IP_BLOCK_TYPE_UVD: 287 case AMD_IP_BLOCK_TYPE_VCN: 288 ret = smu_dpm_set_vcn_enable(smu, !gate); 289 if (ret) 290 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 291 gate ? "gate" : "ungate"); 292 break; 293 case AMD_IP_BLOCK_TYPE_GFX: 294 ret = smu_gfx_off_control(smu, gate); 295 if (ret) 296 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 297 gate ? "enable" : "disable"); 298 break; 299 case AMD_IP_BLOCK_TYPE_SDMA: 300 ret = smu_powergate_sdma(smu, gate); 301 if (ret) 302 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 303 gate ? "gate" : "ungate"); 304 break; 305 case AMD_IP_BLOCK_TYPE_JPEG: 306 ret = smu_dpm_set_jpeg_enable(smu, !gate); 307 if (ret) 308 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 309 gate ? "gate" : "ungate"); 310 break; 311 default: 312 dev_err(smu->adev->dev, "Unsupported block type!\n"); 313 return -EINVAL; 314 } 315 316 return ret; 317 } 318 319 /** 320 * smu_set_user_clk_dependencies - set user profile clock dependencies 321 * 322 * @smu: smu_context pointer 323 * @clk: enum smu_clk_type type 324 * 325 * Enable/Disable the clock dependency for the @clk type. 326 */ 327 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 328 { 329 if (smu->adev->in_suspend) 330 return; 331 332 if (clk == SMU_MCLK) { 333 smu->user_dpm_profile.clk_dependency = 0; 334 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 335 } else if (clk == SMU_FCLK) { 336 /* MCLK takes precedence over FCLK */ 337 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 338 return; 339 340 smu->user_dpm_profile.clk_dependency = 0; 341 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 342 } else if (clk == SMU_SOCCLK) { 343 /* MCLK takes precedence over SOCCLK */ 344 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 345 return; 346 347 smu->user_dpm_profile.clk_dependency = 0; 348 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 349 } else 350 /* Add clk dependencies here, if any */ 351 return; 352 } 353 354 /** 355 * smu_restore_dpm_user_profile - reinstate user dpm profile 356 * 357 * @smu: smu_context pointer 358 * 359 * Restore the saved user power configurations include power limit, 360 * clock frequencies, fan control mode and fan speed. 361 */ 362 static void smu_restore_dpm_user_profile(struct smu_context *smu) 363 { 364 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 365 int ret = 0; 366 367 if (!smu->adev->in_suspend) 368 return; 369 370 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 371 return; 372 373 /* Enable restore flag */ 374 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 375 376 /* set the user dpm power limit */ 377 if (smu->user_dpm_profile.power_limit) { 378 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 379 if (ret) 380 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 381 } 382 383 /* set the user dpm clock configurations */ 384 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 385 enum smu_clk_type clk_type; 386 387 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 388 /* 389 * Iterate over smu clk type and force the saved user clk 390 * configs, skip if clock dependency is enabled 391 */ 392 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 393 smu->user_dpm_profile.clk_mask[clk_type]) { 394 ret = smu_force_smuclk_levels(smu, clk_type, 395 smu->user_dpm_profile.clk_mask[clk_type]); 396 if (ret) 397 dev_err(smu->adev->dev, 398 "Failed to set clock type = %d\n", clk_type); 399 } 400 } 401 } 402 403 /* set the user dpm fan configurations */ 404 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) { 405 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 406 if (ret) { 407 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 408 return; 409 } 410 411 if (!ret && smu->user_dpm_profile.fan_speed_percent) { 412 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent); 413 if (ret) 414 dev_err(smu->adev->dev, "Failed to set manual fan speed\n"); 415 } 416 } 417 418 /* Disable restore flag */ 419 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 420 } 421 422 static int smu_get_power_num_states(void *handle, 423 struct pp_states_info *state_info) 424 { 425 if (!state_info) 426 return -EINVAL; 427 428 /* not support power state */ 429 memset(state_info, 0, sizeof(struct pp_states_info)); 430 state_info->nums = 1; 431 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 432 433 return 0; 434 } 435 436 bool is_support_sw_smu(struct amdgpu_device *adev) 437 { 438 if (adev->asic_type >= CHIP_ARCTURUS) 439 return true; 440 441 return false; 442 } 443 444 bool is_support_cclk_dpm(struct amdgpu_device *adev) 445 { 446 struct smu_context *smu = &adev->smu; 447 448 if (!is_support_sw_smu(adev)) 449 return false; 450 451 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 452 return false; 453 454 return true; 455 } 456 457 458 static int smu_sys_get_pp_table(void *handle, 459 char **table) 460 { 461 struct smu_context *smu = handle; 462 struct smu_table_context *smu_table = &smu->smu_table; 463 uint32_t powerplay_table_size; 464 465 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 466 return -EOPNOTSUPP; 467 468 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 469 return -EINVAL; 470 471 mutex_lock(&smu->mutex); 472 473 if (smu_table->hardcode_pptable) 474 *table = smu_table->hardcode_pptable; 475 else 476 *table = smu_table->power_play_table; 477 478 powerplay_table_size = smu_table->power_play_table_size; 479 480 mutex_unlock(&smu->mutex); 481 482 return powerplay_table_size; 483 } 484 485 static int smu_sys_set_pp_table(void *handle, 486 const char *buf, 487 size_t size) 488 { 489 struct smu_context *smu = handle; 490 struct smu_table_context *smu_table = &smu->smu_table; 491 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 492 int ret = 0; 493 494 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 495 return -EOPNOTSUPP; 496 497 if (header->usStructureSize != size) { 498 dev_err(smu->adev->dev, "pp table size not matched !\n"); 499 return -EIO; 500 } 501 502 mutex_lock(&smu->mutex); 503 if (!smu_table->hardcode_pptable) 504 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 505 if (!smu_table->hardcode_pptable) { 506 ret = -ENOMEM; 507 goto failed; 508 } 509 510 memcpy(smu_table->hardcode_pptable, buf, size); 511 smu_table->power_play_table = smu_table->hardcode_pptable; 512 smu_table->power_play_table_size = size; 513 514 /* 515 * Special hw_fini action(for Navi1x, the DPMs disablement will be 516 * skipped) may be needed for custom pptable uploading. 517 */ 518 smu->uploading_custom_pp_table = true; 519 520 ret = smu_reset(smu); 521 if (ret) 522 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 523 524 smu->uploading_custom_pp_table = false; 525 526 failed: 527 mutex_unlock(&smu->mutex); 528 return ret; 529 } 530 531 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 532 { 533 struct smu_feature *feature = &smu->smu_feature; 534 int ret = 0; 535 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 536 537 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 538 539 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 540 SMU_FEATURE_MAX/32); 541 if (ret) 542 return ret; 543 544 bitmap_or(feature->allowed, feature->allowed, 545 (unsigned long *)allowed_feature_mask, 546 feature->feature_num); 547 548 return ret; 549 } 550 551 static int smu_set_funcs(struct amdgpu_device *adev) 552 { 553 struct smu_context *smu = &adev->smu; 554 555 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 556 smu->od_enabled = true; 557 558 switch (adev->asic_type) { 559 case CHIP_NAVI10: 560 case CHIP_NAVI14: 561 case CHIP_NAVI12: 562 navi10_set_ppt_funcs(smu); 563 break; 564 case CHIP_ARCTURUS: 565 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 566 arcturus_set_ppt_funcs(smu); 567 /* OD is not supported on Arcturus */ 568 smu->od_enabled =false; 569 break; 570 case CHIP_SIENNA_CICHLID: 571 case CHIP_NAVY_FLOUNDER: 572 case CHIP_DIMGREY_CAVEFISH: 573 sienna_cichlid_set_ppt_funcs(smu); 574 break; 575 case CHIP_ALDEBARAN: 576 aldebaran_set_ppt_funcs(smu); 577 /* Enable pp_od_clk_voltage node */ 578 smu->od_enabled = true; 579 break; 580 case CHIP_RENOIR: 581 renoir_set_ppt_funcs(smu); 582 break; 583 case CHIP_VANGOGH: 584 vangogh_set_ppt_funcs(smu); 585 break; 586 default: 587 return -EINVAL; 588 } 589 590 return 0; 591 } 592 593 static int smu_early_init(void *handle) 594 { 595 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 596 struct smu_context *smu = &adev->smu; 597 598 smu->adev = adev; 599 smu->pm_enabled = !!amdgpu_dpm; 600 smu->is_apu = false; 601 mutex_init(&smu->mutex); 602 mutex_init(&smu->smu_baco.mutex); 603 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 604 smu->smu_baco.platform_support = false; 605 606 adev->powerplay.pp_handle = smu; 607 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 608 609 return smu_set_funcs(adev); 610 } 611 612 static int smu_set_default_dpm_table(struct smu_context *smu) 613 { 614 struct smu_power_context *smu_power = &smu->smu_power; 615 struct smu_power_gate *power_gate = &smu_power->power_gate; 616 int vcn_gate, jpeg_gate; 617 int ret = 0; 618 619 if (!smu->ppt_funcs->set_default_dpm_table) 620 return 0; 621 622 mutex_lock(&power_gate->vcn_gate_lock); 623 mutex_lock(&power_gate->jpeg_gate_lock); 624 625 vcn_gate = atomic_read(&power_gate->vcn_gated); 626 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 627 628 ret = smu_dpm_set_vcn_enable_locked(smu, true); 629 if (ret) 630 goto err0_out; 631 632 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 633 if (ret) 634 goto err1_out; 635 636 ret = smu->ppt_funcs->set_default_dpm_table(smu); 637 if (ret) 638 dev_err(smu->adev->dev, 639 "Failed to setup default dpm clock tables!\n"); 640 641 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 642 err1_out: 643 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 644 err0_out: 645 mutex_unlock(&power_gate->jpeg_gate_lock); 646 mutex_unlock(&power_gate->vcn_gate_lock); 647 648 return ret; 649 } 650 651 652 static int smu_late_init(void *handle) 653 { 654 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 655 struct smu_context *smu = &adev->smu; 656 int ret = 0; 657 658 smu_set_fine_grain_gfx_freq_parameters(smu); 659 660 if (!smu->pm_enabled) 661 return 0; 662 663 ret = smu_post_init(smu); 664 if (ret) { 665 dev_err(adev->dev, "Failed to post smu init!\n"); 666 return ret; 667 } 668 669 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 670 ret = smu_set_default_od_settings(smu); 671 if (ret) { 672 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 673 return ret; 674 } 675 } 676 677 ret = smu_populate_umd_state_clk(smu); 678 if (ret) { 679 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 680 return ret; 681 } 682 683 ret = smu_get_asic_power_limits(smu); 684 if (ret) { 685 dev_err(adev->dev, "Failed to get asic power limits!\n"); 686 return ret; 687 } 688 689 smu_get_unique_id(smu); 690 691 smu_get_fan_parameters(smu); 692 693 smu_handle_task(&adev->smu, 694 smu->smu_dpm.dpm_level, 695 AMD_PP_TASK_COMPLETE_INIT, 696 false); 697 698 smu_restore_dpm_user_profile(smu); 699 700 return 0; 701 } 702 703 static int smu_init_fb_allocations(struct smu_context *smu) 704 { 705 struct amdgpu_device *adev = smu->adev; 706 struct smu_table_context *smu_table = &smu->smu_table; 707 struct smu_table *tables = smu_table->tables; 708 struct smu_table *driver_table = &(smu_table->driver_table); 709 uint32_t max_table_size = 0; 710 int ret, i; 711 712 /* VRAM allocation for tool table */ 713 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 714 ret = amdgpu_bo_create_kernel(adev, 715 tables[SMU_TABLE_PMSTATUSLOG].size, 716 tables[SMU_TABLE_PMSTATUSLOG].align, 717 tables[SMU_TABLE_PMSTATUSLOG].domain, 718 &tables[SMU_TABLE_PMSTATUSLOG].bo, 719 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 720 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 721 if (ret) { 722 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 723 return ret; 724 } 725 } 726 727 /* VRAM allocation for driver table */ 728 for (i = 0; i < SMU_TABLE_COUNT; i++) { 729 if (tables[i].size == 0) 730 continue; 731 732 if (i == SMU_TABLE_PMSTATUSLOG) 733 continue; 734 735 if (max_table_size < tables[i].size) 736 max_table_size = tables[i].size; 737 } 738 739 driver_table->size = max_table_size; 740 driver_table->align = PAGE_SIZE; 741 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 742 743 ret = amdgpu_bo_create_kernel(adev, 744 driver_table->size, 745 driver_table->align, 746 driver_table->domain, 747 &driver_table->bo, 748 &driver_table->mc_address, 749 &driver_table->cpu_addr); 750 if (ret) { 751 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 752 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 753 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 754 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 755 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 756 } 757 758 return ret; 759 } 760 761 static int smu_fini_fb_allocations(struct smu_context *smu) 762 { 763 struct smu_table_context *smu_table = &smu->smu_table; 764 struct smu_table *tables = smu_table->tables; 765 struct smu_table *driver_table = &(smu_table->driver_table); 766 767 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 768 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 769 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 770 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 771 772 amdgpu_bo_free_kernel(&driver_table->bo, 773 &driver_table->mc_address, 774 &driver_table->cpu_addr); 775 776 return 0; 777 } 778 779 /** 780 * smu_alloc_memory_pool - allocate memory pool in the system memory 781 * 782 * @smu: amdgpu_device pointer 783 * 784 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 785 * and DramLogSetDramAddr can notify it changed. 786 * 787 * Returns 0 on success, error on failure. 788 */ 789 static int smu_alloc_memory_pool(struct smu_context *smu) 790 { 791 struct amdgpu_device *adev = smu->adev; 792 struct smu_table_context *smu_table = &smu->smu_table; 793 struct smu_table *memory_pool = &smu_table->memory_pool; 794 uint64_t pool_size = smu->pool_size; 795 int ret = 0; 796 797 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 798 return ret; 799 800 memory_pool->size = pool_size; 801 memory_pool->align = PAGE_SIZE; 802 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 803 804 switch (pool_size) { 805 case SMU_MEMORY_POOL_SIZE_256_MB: 806 case SMU_MEMORY_POOL_SIZE_512_MB: 807 case SMU_MEMORY_POOL_SIZE_1_GB: 808 case SMU_MEMORY_POOL_SIZE_2_GB: 809 ret = amdgpu_bo_create_kernel(adev, 810 memory_pool->size, 811 memory_pool->align, 812 memory_pool->domain, 813 &memory_pool->bo, 814 &memory_pool->mc_address, 815 &memory_pool->cpu_addr); 816 if (ret) 817 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 818 break; 819 default: 820 break; 821 } 822 823 return ret; 824 } 825 826 static int smu_free_memory_pool(struct smu_context *smu) 827 { 828 struct smu_table_context *smu_table = &smu->smu_table; 829 struct smu_table *memory_pool = &smu_table->memory_pool; 830 831 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 832 return 0; 833 834 amdgpu_bo_free_kernel(&memory_pool->bo, 835 &memory_pool->mc_address, 836 &memory_pool->cpu_addr); 837 838 memset(memory_pool, 0, sizeof(struct smu_table)); 839 840 return 0; 841 } 842 843 static int smu_alloc_dummy_read_table(struct smu_context *smu) 844 { 845 struct smu_table_context *smu_table = &smu->smu_table; 846 struct smu_table *dummy_read_1_table = 847 &smu_table->dummy_read_1_table; 848 struct amdgpu_device *adev = smu->adev; 849 int ret = 0; 850 851 dummy_read_1_table->size = 0x40000; 852 dummy_read_1_table->align = PAGE_SIZE; 853 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 854 855 ret = amdgpu_bo_create_kernel(adev, 856 dummy_read_1_table->size, 857 dummy_read_1_table->align, 858 dummy_read_1_table->domain, 859 &dummy_read_1_table->bo, 860 &dummy_read_1_table->mc_address, 861 &dummy_read_1_table->cpu_addr); 862 if (ret) 863 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 864 865 return ret; 866 } 867 868 static void smu_free_dummy_read_table(struct smu_context *smu) 869 { 870 struct smu_table_context *smu_table = &smu->smu_table; 871 struct smu_table *dummy_read_1_table = 872 &smu_table->dummy_read_1_table; 873 874 875 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 876 &dummy_read_1_table->mc_address, 877 &dummy_read_1_table->cpu_addr); 878 879 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 880 } 881 882 static int smu_smc_table_sw_init(struct smu_context *smu) 883 { 884 int ret; 885 886 /** 887 * Create smu_table structure, and init smc tables such as 888 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 889 */ 890 ret = smu_init_smc_tables(smu); 891 if (ret) { 892 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 893 return ret; 894 } 895 896 /** 897 * Create smu_power_context structure, and allocate smu_dpm_context and 898 * context size to fill the smu_power_context data. 899 */ 900 ret = smu_init_power(smu); 901 if (ret) { 902 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 903 return ret; 904 } 905 906 /* 907 * allocate vram bos to store smc table contents. 908 */ 909 ret = smu_init_fb_allocations(smu); 910 if (ret) 911 return ret; 912 913 ret = smu_alloc_memory_pool(smu); 914 if (ret) 915 return ret; 916 917 ret = smu_alloc_dummy_read_table(smu); 918 if (ret) 919 return ret; 920 921 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 922 if (ret) 923 return ret; 924 925 return 0; 926 } 927 928 static int smu_smc_table_sw_fini(struct smu_context *smu) 929 { 930 int ret; 931 932 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 933 934 smu_free_dummy_read_table(smu); 935 936 ret = smu_free_memory_pool(smu); 937 if (ret) 938 return ret; 939 940 ret = smu_fini_fb_allocations(smu); 941 if (ret) 942 return ret; 943 944 ret = smu_fini_power(smu); 945 if (ret) { 946 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 947 return ret; 948 } 949 950 ret = smu_fini_smc_tables(smu); 951 if (ret) { 952 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 953 return ret; 954 } 955 956 return 0; 957 } 958 959 static void smu_throttling_logging_work_fn(struct work_struct *work) 960 { 961 struct smu_context *smu = container_of(work, struct smu_context, 962 throttling_logging_work); 963 964 smu_log_thermal_throttling(smu); 965 } 966 967 static void smu_interrupt_work_fn(struct work_struct *work) 968 { 969 struct smu_context *smu = container_of(work, struct smu_context, 970 interrupt_work); 971 972 mutex_lock(&smu->mutex); 973 974 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 975 smu->ppt_funcs->interrupt_work(smu); 976 977 mutex_unlock(&smu->mutex); 978 } 979 980 static int smu_sw_init(void *handle) 981 { 982 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 983 struct smu_context *smu = &adev->smu; 984 int ret; 985 986 smu->pool_size = adev->pm.smu_prv_buffer_size; 987 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 988 mutex_init(&smu->smu_feature.mutex); 989 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 990 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 991 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 992 993 mutex_init(&smu->sensor_lock); 994 mutex_init(&smu->metrics_lock); 995 mutex_init(&smu->message_lock); 996 997 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 998 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 999 atomic64_set(&smu->throttle_int_counter, 0); 1000 smu->watermarks_bitmap = 0; 1001 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1002 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1003 1004 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1005 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1006 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1007 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1008 1009 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1010 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1011 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1012 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1013 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1014 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1015 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1016 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1017 1018 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1019 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1020 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1021 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1022 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1023 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1024 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1025 smu->display_config = &adev->pm.pm_display_cfg; 1026 1027 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1028 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1029 1030 ret = smu_init_microcode(smu); 1031 if (ret) { 1032 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1033 return ret; 1034 } 1035 1036 ret = smu_smc_table_sw_init(smu); 1037 if (ret) { 1038 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1039 return ret; 1040 } 1041 1042 ret = smu_register_irq_handler(smu); 1043 if (ret) { 1044 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1045 return ret; 1046 } 1047 1048 /* If there is no way to query fan control mode, fan control is not supported */ 1049 if (!smu->ppt_funcs->get_fan_control_mode) 1050 smu->adev->pm.no_fan = true; 1051 1052 return 0; 1053 } 1054 1055 static int smu_sw_fini(void *handle) 1056 { 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1058 struct smu_context *smu = &adev->smu; 1059 int ret; 1060 1061 ret = smu_smc_table_sw_fini(smu); 1062 if (ret) { 1063 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1064 return ret; 1065 } 1066 1067 smu_fini_microcode(smu); 1068 1069 return 0; 1070 } 1071 1072 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1073 { 1074 struct amdgpu_device *adev = smu->adev; 1075 struct smu_temperature_range *range = 1076 &smu->thermal_range; 1077 int ret = 0; 1078 1079 if (!smu->ppt_funcs->get_thermal_temperature_range) 1080 return 0; 1081 1082 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1083 if (ret) 1084 return ret; 1085 1086 adev->pm.dpm.thermal.min_temp = range->min; 1087 adev->pm.dpm.thermal.max_temp = range->max; 1088 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1089 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1090 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1091 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1092 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1093 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1094 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1095 1096 return ret; 1097 } 1098 1099 static int smu_smc_hw_setup(struct smu_context *smu) 1100 { 1101 struct amdgpu_device *adev = smu->adev; 1102 uint32_t pcie_gen = 0, pcie_width = 0; 1103 int ret = 0; 1104 1105 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1106 dev_info(adev->dev, "dpm has been enabled\n"); 1107 /* this is needed specifically */ 1108 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1109 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1110 ret = smu_system_features_control(smu, true); 1111 return ret; 1112 } 1113 1114 ret = smu_init_display_count(smu, 0); 1115 if (ret) { 1116 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1117 return ret; 1118 } 1119 1120 ret = smu_set_driver_table_location(smu); 1121 if (ret) { 1122 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1123 return ret; 1124 } 1125 1126 /* 1127 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1128 */ 1129 ret = smu_set_tool_table_location(smu); 1130 if (ret) { 1131 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1132 return ret; 1133 } 1134 1135 /* 1136 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1137 * pool location. 1138 */ 1139 ret = smu_notify_memory_pool_location(smu); 1140 if (ret) { 1141 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1142 return ret; 1143 } 1144 1145 /* smu_dump_pptable(smu); */ 1146 /* 1147 * Copy pptable bo in the vram to smc with SMU MSGs such as 1148 * SetDriverDramAddr and TransferTableDram2Smu. 1149 */ 1150 ret = smu_write_pptable(smu); 1151 if (ret) { 1152 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1153 return ret; 1154 } 1155 1156 /* issue Run*Btc msg */ 1157 ret = smu_run_btc(smu); 1158 if (ret) 1159 return ret; 1160 1161 ret = smu_feature_set_allowed_mask(smu); 1162 if (ret) { 1163 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1164 return ret; 1165 } 1166 1167 ret = smu_system_features_control(smu, true); 1168 if (ret) { 1169 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1170 return ret; 1171 } 1172 1173 if (!smu_is_dpm_running(smu)) 1174 dev_info(adev->dev, "dpm has been disabled\n"); 1175 1176 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1177 pcie_gen = 3; 1178 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1179 pcie_gen = 2; 1180 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1181 pcie_gen = 1; 1182 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1183 pcie_gen = 0; 1184 1185 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1186 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1187 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1188 */ 1189 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1190 pcie_width = 6; 1191 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1192 pcie_width = 5; 1193 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1194 pcie_width = 4; 1195 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1196 pcie_width = 3; 1197 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1198 pcie_width = 2; 1199 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1200 pcie_width = 1; 1201 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1202 if (ret) { 1203 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1204 return ret; 1205 } 1206 1207 ret = smu_get_thermal_temperature_range(smu); 1208 if (ret) { 1209 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1210 return ret; 1211 } 1212 1213 ret = smu_enable_thermal_alert(smu); 1214 if (ret) { 1215 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1216 return ret; 1217 } 1218 1219 /* 1220 * Set initialized values (get from vbios) to dpm tables context such as 1221 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1222 * type of clks. 1223 */ 1224 ret = smu_set_default_dpm_table(smu); 1225 if (ret) { 1226 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1227 return ret; 1228 } 1229 1230 ret = smu_notify_display_change(smu); 1231 if (ret) 1232 return ret; 1233 1234 /* 1235 * Set min deep sleep dce fclk with bootup value from vbios via 1236 * SetMinDeepSleepDcefclk MSG. 1237 */ 1238 ret = smu_set_min_dcef_deep_sleep(smu, 1239 smu->smu_table.boot_values.dcefclk / 100); 1240 if (ret) 1241 return ret; 1242 1243 return ret; 1244 } 1245 1246 static int smu_start_smc_engine(struct smu_context *smu) 1247 { 1248 struct amdgpu_device *adev = smu->adev; 1249 int ret = 0; 1250 1251 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1252 if (adev->asic_type < CHIP_NAVI10) { 1253 if (smu->ppt_funcs->load_microcode) { 1254 ret = smu->ppt_funcs->load_microcode(smu); 1255 if (ret) 1256 return ret; 1257 } 1258 } 1259 } 1260 1261 if (smu->ppt_funcs->check_fw_status) { 1262 ret = smu->ppt_funcs->check_fw_status(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "SMC is not ready\n"); 1265 return ret; 1266 } 1267 } 1268 1269 /* 1270 * Send msg GetDriverIfVersion to check if the return value is equal 1271 * with DRIVER_IF_VERSION of smc header. 1272 */ 1273 ret = smu_check_fw_version(smu); 1274 if (ret) 1275 return ret; 1276 1277 return ret; 1278 } 1279 1280 static int smu_hw_init(void *handle) 1281 { 1282 int ret; 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 struct smu_context *smu = &adev->smu; 1285 1286 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1287 smu->pm_enabled = false; 1288 return 0; 1289 } 1290 1291 ret = smu_start_smc_engine(smu); 1292 if (ret) { 1293 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1294 return ret; 1295 } 1296 1297 if (smu->is_apu) { 1298 smu_powergate_sdma(&adev->smu, false); 1299 smu_dpm_set_vcn_enable(smu, true); 1300 smu_dpm_set_jpeg_enable(smu, true); 1301 smu_set_gfx_cgpg(&adev->smu, true); 1302 } 1303 1304 if (!smu->pm_enabled) 1305 return 0; 1306 1307 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1308 ret = smu_get_vbios_bootup_values(smu); 1309 if (ret) { 1310 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1311 return ret; 1312 } 1313 1314 ret = smu_setup_pptable(smu); 1315 if (ret) { 1316 dev_err(adev->dev, "Failed to setup pptable!\n"); 1317 return ret; 1318 } 1319 1320 ret = smu_get_driver_allowed_feature_mask(smu); 1321 if (ret) 1322 return ret; 1323 1324 ret = smu_smc_hw_setup(smu); 1325 if (ret) { 1326 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1327 return ret; 1328 } 1329 1330 /* 1331 * Move maximum sustainable clock retrieving here considering 1332 * 1. It is not needed on resume(from S3). 1333 * 2. DAL settings come between .hw_init and .late_init of SMU. 1334 * And DAL needs to know the maximum sustainable clocks. Thus 1335 * it cannot be put in .late_init(). 1336 */ 1337 ret = smu_init_max_sustainable_clocks(smu); 1338 if (ret) { 1339 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1340 return ret; 1341 } 1342 1343 adev->pm.dpm_enabled = true; 1344 1345 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1346 1347 return 0; 1348 } 1349 1350 static int smu_disable_dpms(struct smu_context *smu) 1351 { 1352 struct amdgpu_device *adev = smu->adev; 1353 int ret = 0; 1354 bool use_baco = !smu->is_apu && 1355 ((amdgpu_in_reset(adev) && 1356 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1357 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1358 1359 /* 1360 * For custom pptable uploading, skip the DPM features 1361 * disable process on Navi1x ASICs. 1362 * - As the gfx related features are under control of 1363 * RLC on those ASICs. RLC reinitialization will be 1364 * needed to reenable them. That will cost much more 1365 * efforts. 1366 * 1367 * - SMU firmware can handle the DPM reenablement 1368 * properly. 1369 */ 1370 if (smu->uploading_custom_pp_table && 1371 (adev->asic_type >= CHIP_NAVI10) && 1372 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1373 return 0; 1374 1375 /* 1376 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1377 * on BACO in. Driver involvement is unnecessary. 1378 */ 1379 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1380 use_baco) 1381 return 0; 1382 1383 /* 1384 * For gpu reset, runpm and hibernation through BACO, 1385 * BACO feature has to be kept enabled. 1386 */ 1387 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1388 ret = smu_disable_all_features_with_exception(smu, 1389 SMU_FEATURE_BACO_BIT); 1390 if (ret) 1391 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1392 } else { 1393 ret = smu_system_features_control(smu, false); 1394 if (ret) 1395 dev_err(adev->dev, "Failed to disable smu features.\n"); 1396 } 1397 1398 if (adev->asic_type >= CHIP_NAVI10 && 1399 adev->gfx.rlc.funcs->stop) 1400 adev->gfx.rlc.funcs->stop(adev); 1401 1402 return ret; 1403 } 1404 1405 static int smu_smc_hw_cleanup(struct smu_context *smu) 1406 { 1407 struct amdgpu_device *adev = smu->adev; 1408 int ret = 0; 1409 1410 cancel_work_sync(&smu->throttling_logging_work); 1411 cancel_work_sync(&smu->interrupt_work); 1412 1413 ret = smu_disable_thermal_alert(smu); 1414 if (ret) { 1415 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1416 return ret; 1417 } 1418 1419 ret = smu_disable_dpms(smu); 1420 if (ret) { 1421 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1422 return ret; 1423 } 1424 1425 return 0; 1426 } 1427 1428 static int smu_hw_fini(void *handle) 1429 { 1430 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1431 struct smu_context *smu = &adev->smu; 1432 1433 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1434 return 0; 1435 1436 if (smu->is_apu) { 1437 smu_powergate_sdma(&adev->smu, true); 1438 smu_dpm_set_vcn_enable(smu, false); 1439 smu_dpm_set_jpeg_enable(smu, false); 1440 } 1441 1442 if (!smu->pm_enabled) 1443 return 0; 1444 1445 adev->pm.dpm_enabled = false; 1446 1447 return smu_smc_hw_cleanup(smu); 1448 } 1449 1450 static int smu_reset(struct smu_context *smu) 1451 { 1452 struct amdgpu_device *adev = smu->adev; 1453 int ret; 1454 1455 amdgpu_gfx_off_ctrl(smu->adev, false); 1456 1457 ret = smu_hw_fini(adev); 1458 if (ret) 1459 return ret; 1460 1461 ret = smu_hw_init(adev); 1462 if (ret) 1463 return ret; 1464 1465 ret = smu_late_init(adev); 1466 if (ret) 1467 return ret; 1468 1469 amdgpu_gfx_off_ctrl(smu->adev, true); 1470 1471 return 0; 1472 } 1473 1474 static int smu_suspend(void *handle) 1475 { 1476 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1477 struct smu_context *smu = &adev->smu; 1478 int ret; 1479 1480 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1481 return 0; 1482 1483 if (!smu->pm_enabled) 1484 return 0; 1485 1486 adev->pm.dpm_enabled = false; 1487 1488 ret = smu_smc_hw_cleanup(smu); 1489 if (ret) 1490 return ret; 1491 1492 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1493 1494 /* skip CGPG when in S0ix */ 1495 if (smu->is_apu && !adev->in_s0ix) 1496 smu_set_gfx_cgpg(&adev->smu, false); 1497 1498 return 0; 1499 } 1500 1501 static int smu_resume(void *handle) 1502 { 1503 int ret; 1504 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1505 struct smu_context *smu = &adev->smu; 1506 1507 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1508 return 0; 1509 1510 if (!smu->pm_enabled) 1511 return 0; 1512 1513 dev_info(adev->dev, "SMU is resuming...\n"); 1514 1515 ret = smu_start_smc_engine(smu); 1516 if (ret) { 1517 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1518 return ret; 1519 } 1520 1521 ret = smu_smc_hw_setup(smu); 1522 if (ret) { 1523 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1524 return ret; 1525 } 1526 1527 if (smu->is_apu) 1528 smu_set_gfx_cgpg(&adev->smu, true); 1529 1530 smu->disable_uclk_switch = 0; 1531 1532 adev->pm.dpm_enabled = true; 1533 1534 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1535 1536 return 0; 1537 } 1538 1539 static int smu_display_configuration_change(void *handle, 1540 const struct amd_pp_display_configuration *display_config) 1541 { 1542 struct smu_context *smu = handle; 1543 int index = 0; 1544 int num_of_active_display = 0; 1545 1546 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1547 return -EOPNOTSUPP; 1548 1549 if (!display_config) 1550 return -EINVAL; 1551 1552 mutex_lock(&smu->mutex); 1553 1554 smu_set_min_dcef_deep_sleep(smu, 1555 display_config->min_dcef_deep_sleep_set_clk / 100); 1556 1557 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1558 if (display_config->displays[index].controller_id != 0) 1559 num_of_active_display++; 1560 } 1561 1562 mutex_unlock(&smu->mutex); 1563 1564 return 0; 1565 } 1566 1567 static int smu_set_clockgating_state(void *handle, 1568 enum amd_clockgating_state state) 1569 { 1570 return 0; 1571 } 1572 1573 static int smu_set_powergating_state(void *handle, 1574 enum amd_powergating_state state) 1575 { 1576 return 0; 1577 } 1578 1579 static int smu_enable_umd_pstate(void *handle, 1580 enum amd_dpm_forced_level *level) 1581 { 1582 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1583 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1584 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1585 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1586 1587 struct smu_context *smu = (struct smu_context*)(handle); 1588 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1589 1590 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1591 return -EINVAL; 1592 1593 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1594 /* enter umd pstate, save current level, disable gfx cg*/ 1595 if (*level & profile_mode_mask) { 1596 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1597 smu_dpm_ctx->enable_umd_pstate = true; 1598 smu_gpo_control(smu, false); 1599 amdgpu_device_ip_set_powergating_state(smu->adev, 1600 AMD_IP_BLOCK_TYPE_GFX, 1601 AMD_PG_STATE_UNGATE); 1602 amdgpu_device_ip_set_clockgating_state(smu->adev, 1603 AMD_IP_BLOCK_TYPE_GFX, 1604 AMD_CG_STATE_UNGATE); 1605 smu_gfx_ulv_control(smu, false); 1606 smu_deep_sleep_control(smu, false); 1607 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1608 } 1609 } else { 1610 /* exit umd pstate, restore level, enable gfx cg*/ 1611 if (!(*level & profile_mode_mask)) { 1612 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1613 *level = smu_dpm_ctx->saved_dpm_level; 1614 smu_dpm_ctx->enable_umd_pstate = false; 1615 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1616 smu_deep_sleep_control(smu, true); 1617 smu_gfx_ulv_control(smu, true); 1618 amdgpu_device_ip_set_clockgating_state(smu->adev, 1619 AMD_IP_BLOCK_TYPE_GFX, 1620 AMD_CG_STATE_GATE); 1621 amdgpu_device_ip_set_powergating_state(smu->adev, 1622 AMD_IP_BLOCK_TYPE_GFX, 1623 AMD_PG_STATE_GATE); 1624 smu_gpo_control(smu, true); 1625 } 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int smu_bump_power_profile_mode(struct smu_context *smu, 1632 long *param, 1633 uint32_t param_size) 1634 { 1635 int ret = 0; 1636 1637 if (smu->ppt_funcs->set_power_profile_mode) 1638 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1639 1640 return ret; 1641 } 1642 1643 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1644 enum amd_dpm_forced_level level, 1645 bool skip_display_settings) 1646 { 1647 int ret = 0; 1648 int index = 0; 1649 long workload; 1650 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1651 1652 if (!skip_display_settings) { 1653 ret = smu_display_config_changed(smu); 1654 if (ret) { 1655 dev_err(smu->adev->dev, "Failed to change display config!"); 1656 return ret; 1657 } 1658 } 1659 1660 ret = smu_apply_clocks_adjust_rules(smu); 1661 if (ret) { 1662 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1663 return ret; 1664 } 1665 1666 if (!skip_display_settings) { 1667 ret = smu_notify_smc_display_config(smu); 1668 if (ret) { 1669 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1670 return ret; 1671 } 1672 } 1673 1674 if (smu_dpm_ctx->dpm_level != level) { 1675 ret = smu_asic_set_performance_level(smu, level); 1676 if (ret) { 1677 dev_err(smu->adev->dev, "Failed to set performance level!"); 1678 return ret; 1679 } 1680 1681 /* update the saved copy */ 1682 smu_dpm_ctx->dpm_level = level; 1683 } 1684 1685 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1686 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1687 index = fls(smu->workload_mask); 1688 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1689 workload = smu->workload_setting[index]; 1690 1691 if (smu->power_profile_mode != workload) 1692 smu_bump_power_profile_mode(smu, &workload, 0); 1693 } 1694 1695 return ret; 1696 } 1697 1698 static int smu_handle_task(struct smu_context *smu, 1699 enum amd_dpm_forced_level level, 1700 enum amd_pp_task task_id, 1701 bool lock_needed) 1702 { 1703 int ret = 0; 1704 1705 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1706 return -EOPNOTSUPP; 1707 1708 if (lock_needed) 1709 mutex_lock(&smu->mutex); 1710 1711 switch (task_id) { 1712 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1713 ret = smu_pre_display_config_changed(smu); 1714 if (ret) 1715 goto out; 1716 ret = smu_adjust_power_state_dynamic(smu, level, false); 1717 break; 1718 case AMD_PP_TASK_COMPLETE_INIT: 1719 case AMD_PP_TASK_READJUST_POWER_STATE: 1720 ret = smu_adjust_power_state_dynamic(smu, level, true); 1721 break; 1722 default: 1723 break; 1724 } 1725 1726 out: 1727 if (lock_needed) 1728 mutex_unlock(&smu->mutex); 1729 1730 return ret; 1731 } 1732 1733 static int smu_handle_dpm_task(void *handle, 1734 enum amd_pp_task task_id, 1735 enum amd_pm_state_type *user_state) 1736 { 1737 struct smu_context *smu = handle; 1738 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1739 1740 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1741 1742 } 1743 1744 static int smu_switch_power_profile(void *handle, 1745 enum PP_SMC_POWER_PROFILE type, 1746 bool en) 1747 { 1748 struct smu_context *smu = handle; 1749 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1750 long workload; 1751 uint32_t index; 1752 1753 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1754 return -EOPNOTSUPP; 1755 1756 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1757 return -EINVAL; 1758 1759 mutex_lock(&smu->mutex); 1760 1761 if (!en) { 1762 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1763 index = fls(smu->workload_mask); 1764 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1765 workload = smu->workload_setting[index]; 1766 } else { 1767 smu->workload_mask |= (1 << smu->workload_prority[type]); 1768 index = fls(smu->workload_mask); 1769 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1770 workload = smu->workload_setting[index]; 1771 } 1772 1773 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1774 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1775 smu_bump_power_profile_mode(smu, &workload, 0); 1776 1777 mutex_unlock(&smu->mutex); 1778 1779 return 0; 1780 } 1781 1782 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1783 { 1784 struct smu_context *smu = handle; 1785 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1786 enum amd_dpm_forced_level level; 1787 1788 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1789 return -EOPNOTSUPP; 1790 1791 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1792 return -EINVAL; 1793 1794 mutex_lock(&(smu->mutex)); 1795 level = smu_dpm_ctx->dpm_level; 1796 mutex_unlock(&(smu->mutex)); 1797 1798 return level; 1799 } 1800 1801 static int smu_force_performance_level(void *handle, 1802 enum amd_dpm_forced_level level) 1803 { 1804 struct smu_context *smu = handle; 1805 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1806 int ret = 0; 1807 1808 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1809 return -EOPNOTSUPP; 1810 1811 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1812 return -EINVAL; 1813 1814 mutex_lock(&smu->mutex); 1815 1816 ret = smu_enable_umd_pstate(smu, &level); 1817 if (ret) { 1818 mutex_unlock(&smu->mutex); 1819 return ret; 1820 } 1821 1822 ret = smu_handle_task(smu, level, 1823 AMD_PP_TASK_READJUST_POWER_STATE, 1824 false); 1825 1826 mutex_unlock(&smu->mutex); 1827 1828 /* reset user dpm clock state */ 1829 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1830 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1831 smu->user_dpm_profile.clk_dependency = 0; 1832 } 1833 1834 return ret; 1835 } 1836 1837 static int smu_set_display_count(void *handle, uint32_t count) 1838 { 1839 struct smu_context *smu = handle; 1840 int ret = 0; 1841 1842 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1843 return -EOPNOTSUPP; 1844 1845 mutex_lock(&smu->mutex); 1846 ret = smu_init_display_count(smu, count); 1847 mutex_unlock(&smu->mutex); 1848 1849 return ret; 1850 } 1851 1852 static int smu_force_smuclk_levels(struct smu_context *smu, 1853 enum smu_clk_type clk_type, 1854 uint32_t mask) 1855 { 1856 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1857 int ret = 0; 1858 1859 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1860 return -EOPNOTSUPP; 1861 1862 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1863 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1864 return -EINVAL; 1865 } 1866 1867 mutex_lock(&smu->mutex); 1868 1869 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1870 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1871 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1872 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1873 smu_set_user_clk_dependencies(smu, clk_type); 1874 } 1875 } 1876 1877 mutex_unlock(&smu->mutex); 1878 1879 return ret; 1880 } 1881 1882 static int smu_force_ppclk_levels(void *handle, 1883 enum pp_clock_type type, 1884 uint32_t mask) 1885 { 1886 struct smu_context *smu = handle; 1887 enum smu_clk_type clk_type; 1888 1889 switch (type) { 1890 case PP_SCLK: 1891 clk_type = SMU_SCLK; break; 1892 case PP_MCLK: 1893 clk_type = SMU_MCLK; break; 1894 case PP_PCIE: 1895 clk_type = SMU_PCIE; break; 1896 case PP_SOCCLK: 1897 clk_type = SMU_SOCCLK; break; 1898 case PP_FCLK: 1899 clk_type = SMU_FCLK; break; 1900 case PP_DCEFCLK: 1901 clk_type = SMU_DCEFCLK; break; 1902 case PP_VCLK: 1903 clk_type = SMU_VCLK; break; 1904 case PP_DCLK: 1905 clk_type = SMU_DCLK; break; 1906 case OD_SCLK: 1907 clk_type = SMU_OD_SCLK; break; 1908 case OD_MCLK: 1909 clk_type = SMU_OD_MCLK; break; 1910 case OD_VDDC_CURVE: 1911 clk_type = SMU_OD_VDDC_CURVE; break; 1912 case OD_RANGE: 1913 clk_type = SMU_OD_RANGE; break; 1914 default: 1915 return -EINVAL; 1916 } 1917 1918 return smu_force_smuclk_levels(smu, clk_type, mask); 1919 } 1920 1921 /* 1922 * On system suspending or resetting, the dpm_enabled 1923 * flag will be cleared. So that those SMU services which 1924 * are not supported will be gated. 1925 * However, the mp1 state setting should still be granted 1926 * even if the dpm_enabled cleared. 1927 */ 1928 static int smu_set_mp1_state(void *handle, 1929 enum pp_mp1_state mp1_state) 1930 { 1931 struct smu_context *smu = handle; 1932 int ret = 0; 1933 1934 if (!smu->pm_enabled) 1935 return -EOPNOTSUPP; 1936 1937 mutex_lock(&smu->mutex); 1938 1939 if (smu->ppt_funcs && 1940 smu->ppt_funcs->set_mp1_state) 1941 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1942 1943 mutex_unlock(&smu->mutex); 1944 1945 return ret; 1946 } 1947 1948 static int smu_set_df_cstate(void *handle, 1949 enum pp_df_cstate state) 1950 { 1951 struct smu_context *smu = handle; 1952 int ret = 0; 1953 1954 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1955 return -EOPNOTSUPP; 1956 1957 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1958 return 0; 1959 1960 mutex_lock(&smu->mutex); 1961 1962 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1963 if (ret) 1964 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1965 1966 mutex_unlock(&smu->mutex); 1967 1968 return ret; 1969 } 1970 1971 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1972 { 1973 int ret = 0; 1974 1975 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1976 return -EOPNOTSUPP; 1977 1978 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1979 return 0; 1980 1981 mutex_lock(&smu->mutex); 1982 1983 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1984 if (ret) 1985 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1986 1987 mutex_unlock(&smu->mutex); 1988 1989 return ret; 1990 } 1991 1992 int smu_write_watermarks_table(struct smu_context *smu) 1993 { 1994 int ret = 0; 1995 1996 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1997 return -EOPNOTSUPP; 1998 1999 mutex_lock(&smu->mutex); 2000 2001 ret = smu_set_watermarks_table(smu, NULL); 2002 2003 mutex_unlock(&smu->mutex); 2004 2005 return ret; 2006 } 2007 2008 static int smu_set_watermarks_for_clock_ranges(void *handle, 2009 struct pp_smu_wm_range_sets *clock_ranges) 2010 { 2011 struct smu_context *smu = handle; 2012 int ret = 0; 2013 2014 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2015 return -EOPNOTSUPP; 2016 2017 if (smu->disable_watermark) 2018 return 0; 2019 2020 mutex_lock(&smu->mutex); 2021 2022 ret = smu_set_watermarks_table(smu, clock_ranges); 2023 2024 mutex_unlock(&smu->mutex); 2025 2026 return ret; 2027 } 2028 2029 int smu_set_ac_dc(struct smu_context *smu) 2030 { 2031 int ret = 0; 2032 2033 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2034 return -EOPNOTSUPP; 2035 2036 /* controlled by firmware */ 2037 if (smu->dc_controlled_by_gpio) 2038 return 0; 2039 2040 mutex_lock(&smu->mutex); 2041 ret = smu_set_power_source(smu, 2042 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2043 SMU_POWER_SOURCE_DC); 2044 if (ret) 2045 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2046 smu->adev->pm.ac_power ? "AC" : "DC"); 2047 mutex_unlock(&smu->mutex); 2048 2049 return ret; 2050 } 2051 2052 const struct amd_ip_funcs smu_ip_funcs = { 2053 .name = "smu", 2054 .early_init = smu_early_init, 2055 .late_init = smu_late_init, 2056 .sw_init = smu_sw_init, 2057 .sw_fini = smu_sw_fini, 2058 .hw_init = smu_hw_init, 2059 .hw_fini = smu_hw_fini, 2060 .suspend = smu_suspend, 2061 .resume = smu_resume, 2062 .is_idle = NULL, 2063 .check_soft_reset = NULL, 2064 .wait_for_idle = NULL, 2065 .soft_reset = NULL, 2066 .set_clockgating_state = smu_set_clockgating_state, 2067 .set_powergating_state = smu_set_powergating_state, 2068 .enable_umd_pstate = smu_enable_umd_pstate, 2069 }; 2070 2071 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2072 { 2073 .type = AMD_IP_BLOCK_TYPE_SMC, 2074 .major = 11, 2075 .minor = 0, 2076 .rev = 0, 2077 .funcs = &smu_ip_funcs, 2078 }; 2079 2080 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2081 { 2082 .type = AMD_IP_BLOCK_TYPE_SMC, 2083 .major = 12, 2084 .minor = 0, 2085 .rev = 0, 2086 .funcs = &smu_ip_funcs, 2087 }; 2088 2089 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2090 { 2091 .type = AMD_IP_BLOCK_TYPE_SMC, 2092 .major = 13, 2093 .minor = 0, 2094 .rev = 0, 2095 .funcs = &smu_ip_funcs, 2096 }; 2097 2098 static int smu_load_microcode(void *handle) 2099 { 2100 struct smu_context *smu = handle; 2101 struct amdgpu_device *adev = smu->adev; 2102 int ret = 0; 2103 2104 if (!smu->pm_enabled) 2105 return -EOPNOTSUPP; 2106 2107 /* This should be used for non PSP loading */ 2108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2109 return 0; 2110 2111 if (smu->ppt_funcs->load_microcode) { 2112 ret = smu->ppt_funcs->load_microcode(smu); 2113 if (ret) { 2114 dev_err(adev->dev, "Load microcode failed\n"); 2115 return ret; 2116 } 2117 } 2118 2119 if (smu->ppt_funcs->check_fw_status) { 2120 ret = smu->ppt_funcs->check_fw_status(smu); 2121 if (ret) { 2122 dev_err(adev->dev, "SMC is not ready\n"); 2123 return ret; 2124 } 2125 } 2126 2127 return ret; 2128 } 2129 2130 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2131 { 2132 int ret = 0; 2133 2134 mutex_lock(&smu->mutex); 2135 2136 if (smu->ppt_funcs->set_gfx_cgpg) 2137 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2138 2139 mutex_unlock(&smu->mutex); 2140 2141 return ret; 2142 } 2143 2144 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2145 { 2146 struct smu_context *smu = handle; 2147 u32 percent; 2148 int ret = 0; 2149 2150 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2151 return -EOPNOTSUPP; 2152 2153 mutex_lock(&smu->mutex); 2154 2155 if (smu->ppt_funcs->set_fan_speed_percent) { 2156 percent = speed * 100 / smu->fan_max_rpm; 2157 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); 2158 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2159 smu->user_dpm_profile.fan_speed_percent = percent; 2160 } 2161 2162 mutex_unlock(&smu->mutex); 2163 2164 return ret; 2165 } 2166 2167 int smu_get_power_limit(struct smu_context *smu, 2168 uint32_t *limit, 2169 enum smu_ppt_limit_level limit_level) 2170 { 2171 uint32_t limit_type = *limit >> 24; 2172 int ret = 0; 2173 2174 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2175 return -EOPNOTSUPP; 2176 2177 mutex_lock(&smu->mutex); 2178 2179 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2180 if (smu->ppt_funcs->get_ppt_limit) 2181 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2182 } else { 2183 switch (limit_level) { 2184 case SMU_PPT_LIMIT_CURRENT: 2185 *limit = smu->current_power_limit; 2186 break; 2187 case SMU_PPT_LIMIT_DEFAULT: 2188 *limit = smu->default_power_limit; 2189 break; 2190 case SMU_PPT_LIMIT_MAX: 2191 *limit = smu->max_power_limit; 2192 break; 2193 default: 2194 break; 2195 } 2196 } 2197 2198 mutex_unlock(&smu->mutex); 2199 2200 return ret; 2201 } 2202 2203 static int smu_set_power_limit(void *handle, uint32_t limit) 2204 { 2205 struct smu_context *smu = handle; 2206 uint32_t limit_type = limit >> 24; 2207 int ret = 0; 2208 2209 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2210 return -EOPNOTSUPP; 2211 2212 mutex_lock(&smu->mutex); 2213 2214 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2215 if (smu->ppt_funcs->set_power_limit) { 2216 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2217 goto out; 2218 } 2219 2220 if (limit > smu->max_power_limit) { 2221 dev_err(smu->adev->dev, 2222 "New power limit (%d) is over the max allowed %d\n", 2223 limit, smu->max_power_limit); 2224 ret = -EINVAL; 2225 goto out; 2226 } 2227 2228 if (!limit) 2229 limit = smu->current_power_limit; 2230 2231 if (smu->ppt_funcs->set_power_limit) { 2232 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2233 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2234 smu->user_dpm_profile.power_limit = limit; 2235 } 2236 2237 out: 2238 mutex_unlock(&smu->mutex); 2239 2240 return ret; 2241 } 2242 2243 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2244 { 2245 int ret = 0; 2246 2247 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2248 return -EOPNOTSUPP; 2249 2250 mutex_lock(&smu->mutex); 2251 2252 if (smu->ppt_funcs->print_clk_levels) 2253 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2254 2255 mutex_unlock(&smu->mutex); 2256 2257 return ret; 2258 } 2259 2260 static int smu_print_ppclk_levels(void *handle, 2261 enum pp_clock_type type, 2262 char *buf) 2263 { 2264 struct smu_context *smu = handle; 2265 enum smu_clk_type clk_type; 2266 2267 switch (type) { 2268 case PP_SCLK: 2269 clk_type = SMU_SCLK; break; 2270 case PP_MCLK: 2271 clk_type = SMU_MCLK; break; 2272 case PP_PCIE: 2273 clk_type = SMU_PCIE; break; 2274 case PP_SOCCLK: 2275 clk_type = SMU_SOCCLK; break; 2276 case PP_FCLK: 2277 clk_type = SMU_FCLK; break; 2278 case PP_DCEFCLK: 2279 clk_type = SMU_DCEFCLK; break; 2280 case PP_VCLK: 2281 clk_type = SMU_VCLK; break; 2282 case PP_DCLK: 2283 clk_type = SMU_DCLK; break; 2284 case OD_SCLK: 2285 clk_type = SMU_OD_SCLK; break; 2286 case OD_MCLK: 2287 clk_type = SMU_OD_MCLK; break; 2288 case OD_VDDC_CURVE: 2289 clk_type = SMU_OD_VDDC_CURVE; break; 2290 case OD_RANGE: 2291 clk_type = SMU_OD_RANGE; break; 2292 case OD_VDDGFX_OFFSET: 2293 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2294 case OD_CCLK: 2295 clk_type = SMU_OD_CCLK; break; 2296 default: 2297 return -EINVAL; 2298 } 2299 2300 return smu_print_smuclk_levels(smu, clk_type, buf); 2301 } 2302 2303 static int smu_od_edit_dpm_table(void *handle, 2304 enum PP_OD_DPM_TABLE_COMMAND type, 2305 long *input, uint32_t size) 2306 { 2307 struct smu_context *smu = handle; 2308 int ret = 0; 2309 2310 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2311 return -EOPNOTSUPP; 2312 2313 mutex_lock(&smu->mutex); 2314 2315 if (smu->ppt_funcs->od_edit_dpm_table) { 2316 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2317 } 2318 2319 mutex_unlock(&smu->mutex); 2320 2321 return ret; 2322 } 2323 2324 static int smu_read_sensor(void *handle, 2325 int sensor, 2326 void *data, 2327 int *size_arg) 2328 { 2329 struct smu_context *smu = handle; 2330 struct smu_umd_pstate_table *pstate_table = 2331 &smu->pstate_table; 2332 int ret = 0; 2333 uint32_t *size, size_val; 2334 2335 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2336 return -EOPNOTSUPP; 2337 2338 if (!data || !size_arg) 2339 return -EINVAL; 2340 2341 size_val = *size_arg; 2342 size = &size_val; 2343 2344 mutex_lock(&smu->mutex); 2345 2346 if (smu->ppt_funcs->read_sensor) 2347 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2348 goto unlock; 2349 2350 switch (sensor) { 2351 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2352 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2353 *size = 4; 2354 break; 2355 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2356 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2357 *size = 4; 2358 break; 2359 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2360 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2361 *size = 8; 2362 break; 2363 case AMDGPU_PP_SENSOR_UVD_POWER: 2364 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2365 *size = 4; 2366 break; 2367 case AMDGPU_PP_SENSOR_VCE_POWER: 2368 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2369 *size = 4; 2370 break; 2371 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2372 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2373 *size = 4; 2374 break; 2375 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2376 *(uint32_t *)data = 0; 2377 *size = 4; 2378 break; 2379 default: 2380 *size = 0; 2381 ret = -EOPNOTSUPP; 2382 break; 2383 } 2384 2385 unlock: 2386 mutex_unlock(&smu->mutex); 2387 2388 // assign uint32_t to int 2389 *size_arg = size_val; 2390 2391 return ret; 2392 } 2393 2394 static int smu_get_power_profile_mode(void *handle, char *buf) 2395 { 2396 struct smu_context *smu = handle; 2397 int ret = 0; 2398 2399 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2400 return -EOPNOTSUPP; 2401 2402 mutex_lock(&smu->mutex); 2403 2404 if (smu->ppt_funcs->get_power_profile_mode) 2405 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2406 2407 mutex_unlock(&smu->mutex); 2408 2409 return ret; 2410 } 2411 2412 static int smu_set_power_profile_mode(void *handle, 2413 long *param, 2414 uint32_t param_size) 2415 { 2416 struct smu_context *smu = handle; 2417 int ret = 0; 2418 2419 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2420 return -EOPNOTSUPP; 2421 2422 mutex_lock(&smu->mutex); 2423 2424 smu_bump_power_profile_mode(smu, param, param_size); 2425 2426 mutex_unlock(&smu->mutex); 2427 2428 return ret; 2429 } 2430 2431 2432 static u32 smu_get_fan_control_mode(void *handle) 2433 { 2434 struct smu_context *smu = handle; 2435 u32 ret = 0; 2436 2437 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2438 return AMD_FAN_CTRL_NONE; 2439 2440 mutex_lock(&smu->mutex); 2441 2442 if (smu->ppt_funcs->get_fan_control_mode) 2443 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2444 2445 mutex_unlock(&smu->mutex); 2446 2447 return ret; 2448 } 2449 2450 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2451 { 2452 int ret = 0; 2453 2454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2455 return -EOPNOTSUPP; 2456 2457 mutex_lock(&smu->mutex); 2458 2459 if (smu->ppt_funcs->set_fan_control_mode) { 2460 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2461 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2462 smu->user_dpm_profile.fan_mode = value; 2463 } 2464 2465 mutex_unlock(&smu->mutex); 2466 2467 /* reset user dpm fan speed */ 2468 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2469 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2470 smu->user_dpm_profile.fan_speed_percent = 0; 2471 2472 return ret; 2473 } 2474 2475 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2476 { 2477 struct smu_context *smu = handle; 2478 2479 smu_set_fan_control_mode(smu, value); 2480 } 2481 2482 2483 static int smu_get_fan_speed_percent(void *handle, u32 *speed) 2484 { 2485 struct smu_context *smu = handle; 2486 int ret = 0; 2487 uint32_t percent; 2488 2489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2490 return -EOPNOTSUPP; 2491 2492 mutex_lock(&smu->mutex); 2493 2494 if (smu->ppt_funcs->get_fan_speed_percent) { 2495 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2496 if (!ret) { 2497 *speed = percent > 100 ? 100 : percent; 2498 } 2499 } 2500 2501 mutex_unlock(&smu->mutex); 2502 2503 2504 return ret; 2505 } 2506 2507 static int smu_set_fan_speed_percent(void *handle, u32 speed) 2508 { 2509 struct smu_context *smu = handle; 2510 int ret = 0; 2511 2512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2513 return -EOPNOTSUPP; 2514 2515 mutex_lock(&smu->mutex); 2516 2517 if (smu->ppt_funcs->set_fan_speed_percent) { 2518 if (speed > 100) 2519 speed = 100; 2520 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); 2521 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2522 smu->user_dpm_profile.fan_speed_percent = speed; 2523 } 2524 2525 mutex_unlock(&smu->mutex); 2526 2527 return ret; 2528 } 2529 2530 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2531 { 2532 struct smu_context *smu = handle; 2533 int ret = 0; 2534 u32 percent; 2535 2536 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2537 return -EOPNOTSUPP; 2538 2539 mutex_lock(&smu->mutex); 2540 2541 if (smu->ppt_funcs->get_fan_speed_percent) { 2542 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2543 *speed = percent * smu->fan_max_rpm / 100; 2544 } 2545 2546 mutex_unlock(&smu->mutex); 2547 2548 return ret; 2549 } 2550 2551 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2552 { 2553 struct smu_context *smu = handle; 2554 int ret = 0; 2555 2556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2557 return -EOPNOTSUPP; 2558 2559 mutex_lock(&smu->mutex); 2560 2561 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2562 2563 mutex_unlock(&smu->mutex); 2564 2565 return ret; 2566 } 2567 2568 static int smu_get_clock_by_type_with_latency(void *handle, 2569 enum amd_pp_clock_type type, 2570 struct pp_clock_levels_with_latency *clocks) 2571 { 2572 struct smu_context *smu = handle; 2573 enum smu_clk_type clk_type; 2574 int ret = 0; 2575 2576 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2577 return -EOPNOTSUPP; 2578 2579 mutex_lock(&smu->mutex); 2580 2581 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2582 switch (type) { 2583 case amd_pp_sys_clock: 2584 clk_type = SMU_GFXCLK; 2585 break; 2586 case amd_pp_mem_clock: 2587 clk_type = SMU_MCLK; 2588 break; 2589 case amd_pp_dcef_clock: 2590 clk_type = SMU_DCEFCLK; 2591 break; 2592 case amd_pp_disp_clock: 2593 clk_type = SMU_DISPCLK; 2594 break; 2595 default: 2596 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2597 mutex_unlock(&smu->mutex); 2598 return -EINVAL; 2599 } 2600 2601 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2602 } 2603 2604 mutex_unlock(&smu->mutex); 2605 2606 return ret; 2607 } 2608 2609 static int smu_display_clock_voltage_request(void *handle, 2610 struct pp_display_clock_request *clock_req) 2611 { 2612 struct smu_context *smu = handle; 2613 int ret = 0; 2614 2615 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2616 return -EOPNOTSUPP; 2617 2618 mutex_lock(&smu->mutex); 2619 2620 if (smu->ppt_funcs->display_clock_voltage_request) 2621 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2622 2623 mutex_unlock(&smu->mutex); 2624 2625 return ret; 2626 } 2627 2628 2629 static int smu_display_disable_memory_clock_switch(void *handle, 2630 bool disable_memory_clock_switch) 2631 { 2632 struct smu_context *smu = handle; 2633 int ret = -EINVAL; 2634 2635 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2636 return -EOPNOTSUPP; 2637 2638 mutex_lock(&smu->mutex); 2639 2640 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2641 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2642 2643 mutex_unlock(&smu->mutex); 2644 2645 return ret; 2646 } 2647 2648 static int smu_set_xgmi_pstate(void *handle, 2649 uint32_t pstate) 2650 { 2651 struct smu_context *smu = handle; 2652 int ret = 0; 2653 2654 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2655 return -EOPNOTSUPP; 2656 2657 mutex_lock(&smu->mutex); 2658 2659 if (smu->ppt_funcs->set_xgmi_pstate) 2660 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2661 2662 mutex_unlock(&smu->mutex); 2663 2664 if(ret) 2665 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2666 2667 return ret; 2668 } 2669 2670 static int smu_get_baco_capability(void *handle, bool *cap) 2671 { 2672 struct smu_context *smu = handle; 2673 int ret = 0; 2674 2675 *cap = false; 2676 2677 if (!smu->pm_enabled) 2678 return 0; 2679 2680 mutex_lock(&smu->mutex); 2681 2682 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2683 *cap = smu->ppt_funcs->baco_is_support(smu); 2684 2685 mutex_unlock(&smu->mutex); 2686 2687 return ret; 2688 } 2689 2690 static int smu_baco_set_state(void *handle, int state) 2691 { 2692 struct smu_context *smu = handle; 2693 int ret = 0; 2694 2695 if (!smu->pm_enabled) 2696 return -EOPNOTSUPP; 2697 2698 if (state == 0) { 2699 mutex_lock(&smu->mutex); 2700 2701 if (smu->ppt_funcs->baco_exit) 2702 ret = smu->ppt_funcs->baco_exit(smu); 2703 2704 mutex_unlock(&smu->mutex); 2705 } else if (state == 1) { 2706 mutex_lock(&smu->mutex); 2707 2708 if (smu->ppt_funcs->baco_enter) 2709 ret = smu->ppt_funcs->baco_enter(smu); 2710 2711 mutex_unlock(&smu->mutex); 2712 2713 } else { 2714 return -EINVAL; 2715 } 2716 2717 if (ret) 2718 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2719 (state)?"enter":"exit"); 2720 2721 return ret; 2722 } 2723 2724 bool smu_mode1_reset_is_support(struct smu_context *smu) 2725 { 2726 bool ret = false; 2727 2728 if (!smu->pm_enabled) 2729 return false; 2730 2731 mutex_lock(&smu->mutex); 2732 2733 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2734 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2735 2736 mutex_unlock(&smu->mutex); 2737 2738 return ret; 2739 } 2740 2741 bool smu_mode2_reset_is_support(struct smu_context *smu) 2742 { 2743 bool ret = false; 2744 2745 if (!smu->pm_enabled) 2746 return false; 2747 2748 mutex_lock(&smu->mutex); 2749 2750 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2751 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2752 2753 mutex_unlock(&smu->mutex); 2754 2755 return ret; 2756 } 2757 2758 int smu_mode1_reset(struct smu_context *smu) 2759 { 2760 int ret = 0; 2761 2762 if (!smu->pm_enabled) 2763 return -EOPNOTSUPP; 2764 2765 mutex_lock(&smu->mutex); 2766 2767 if (smu->ppt_funcs->mode1_reset) 2768 ret = smu->ppt_funcs->mode1_reset(smu); 2769 2770 mutex_unlock(&smu->mutex); 2771 2772 return ret; 2773 } 2774 2775 static int smu_mode2_reset(void *handle) 2776 { 2777 struct smu_context *smu = handle; 2778 int ret = 0; 2779 2780 if (!smu->pm_enabled) 2781 return -EOPNOTSUPP; 2782 2783 mutex_lock(&smu->mutex); 2784 2785 if (smu->ppt_funcs->mode2_reset) 2786 ret = smu->ppt_funcs->mode2_reset(smu); 2787 2788 mutex_unlock(&smu->mutex); 2789 2790 if (ret) 2791 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2792 2793 return ret; 2794 } 2795 2796 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2797 struct pp_smu_nv_clock_table *max_clocks) 2798 { 2799 struct smu_context *smu = handle; 2800 int ret = 0; 2801 2802 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2803 return -EOPNOTSUPP; 2804 2805 mutex_lock(&smu->mutex); 2806 2807 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2808 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2809 2810 mutex_unlock(&smu->mutex); 2811 2812 return ret; 2813 } 2814 2815 static int smu_get_uclk_dpm_states(void *handle, 2816 unsigned int *clock_values_in_khz, 2817 unsigned int *num_states) 2818 { 2819 struct smu_context *smu = handle; 2820 int ret = 0; 2821 2822 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2823 return -EOPNOTSUPP; 2824 2825 mutex_lock(&smu->mutex); 2826 2827 if (smu->ppt_funcs->get_uclk_dpm_states) 2828 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2829 2830 mutex_unlock(&smu->mutex); 2831 2832 return ret; 2833 } 2834 2835 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2836 { 2837 struct smu_context *smu = handle; 2838 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2839 2840 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2841 return -EOPNOTSUPP; 2842 2843 mutex_lock(&smu->mutex); 2844 2845 if (smu->ppt_funcs->get_current_power_state) 2846 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2847 2848 mutex_unlock(&smu->mutex); 2849 2850 return pm_state; 2851 } 2852 2853 static int smu_get_dpm_clock_table(void *handle, 2854 struct dpm_clocks *clock_table) 2855 { 2856 struct smu_context *smu = handle; 2857 int ret = 0; 2858 2859 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2860 return -EOPNOTSUPP; 2861 2862 mutex_lock(&smu->mutex); 2863 2864 if (smu->ppt_funcs->get_dpm_clock_table) 2865 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2866 2867 mutex_unlock(&smu->mutex); 2868 2869 return ret; 2870 } 2871 2872 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2873 { 2874 struct smu_context *smu = handle; 2875 ssize_t size; 2876 2877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2878 return -EOPNOTSUPP; 2879 2880 if (!smu->ppt_funcs->get_gpu_metrics) 2881 return -EOPNOTSUPP; 2882 2883 mutex_lock(&smu->mutex); 2884 2885 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2886 2887 mutex_unlock(&smu->mutex); 2888 2889 return size; 2890 } 2891 2892 static int smu_enable_mgpu_fan_boost(void *handle) 2893 { 2894 struct smu_context *smu = handle; 2895 int ret = 0; 2896 2897 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2898 return -EOPNOTSUPP; 2899 2900 mutex_lock(&smu->mutex); 2901 2902 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2903 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2904 2905 mutex_unlock(&smu->mutex); 2906 2907 return ret; 2908 } 2909 2910 static int smu_gfx_state_change_set(void *handle, 2911 uint32_t state) 2912 { 2913 struct smu_context *smu = handle; 2914 int ret = 0; 2915 2916 mutex_lock(&smu->mutex); 2917 if (smu->ppt_funcs->gfx_state_change_set) 2918 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2919 mutex_unlock(&smu->mutex); 2920 2921 return ret; 2922 } 2923 2924 int smu_set_light_sbr(struct smu_context *smu, bool enable) 2925 { 2926 int ret = 0; 2927 2928 mutex_lock(&smu->mutex); 2929 if (smu->ppt_funcs->set_light_sbr) 2930 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 2931 mutex_unlock(&smu->mutex); 2932 2933 return ret; 2934 } 2935 2936 2937 static const struct amd_pm_funcs swsmu_pm_funcs = { 2938 /* export for sysfs */ 2939 .set_fan_control_mode = smu_pp_set_fan_control_mode, 2940 .get_fan_control_mode = smu_get_fan_control_mode, 2941 .set_fan_speed_percent = smu_set_fan_speed_percent, 2942 .get_fan_speed_percent = smu_get_fan_speed_percent, 2943 .force_performance_level = smu_force_performance_level, 2944 .read_sensor = smu_read_sensor, 2945 .get_performance_level = smu_get_performance_level, 2946 .get_current_power_state = smu_get_current_power_state, 2947 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2948 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2949 .get_pp_num_states = smu_get_power_num_states, 2950 .get_pp_table = smu_sys_get_pp_table, 2951 .set_pp_table = smu_sys_set_pp_table, 2952 .switch_power_profile = smu_switch_power_profile, 2953 /* export to amdgpu */ 2954 .dispatch_tasks = smu_handle_dpm_task, 2955 .set_powergating_by_smu = smu_dpm_set_power_gate, 2956 .set_power_limit = smu_set_power_limit, 2957 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2958 .set_mp1_state = smu_set_mp1_state, 2959 /* export to DC */ 2960 .get_sclk = smu_get_sclk, 2961 .get_mclk = smu_get_mclk, 2962 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2963 .get_asic_baco_capability = smu_get_baco_capability, 2964 .set_asic_baco_state = smu_baco_set_state, 2965 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2966 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2967 .asic_reset_mode_2 = smu_mode2_reset, 2968 .set_df_cstate = smu_set_df_cstate, 2969 .set_xgmi_pstate = smu_set_xgmi_pstate, 2970 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2971 .set_power_profile_mode = smu_set_power_profile_mode, 2972 .get_power_profile_mode = smu_get_power_profile_mode, 2973 .force_clock_level = smu_force_ppclk_levels, 2974 .print_clock_levels = smu_print_ppclk_levels, 2975 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2976 .get_dpm_clock_table = smu_get_dpm_clock_table, 2977 .display_configuration_change = smu_display_configuration_change, 2978 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2979 .display_clock_voltage_request = smu_display_clock_voltage_request, 2980 .set_active_display_count = smu_set_display_count, 2981 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2982 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2983 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2984 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2985 .load_firmware = smu_load_microcode, 2986 .gfx_state_change_set = smu_gfx_state_change_set, 2987 }; 2988 2989 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 2990 uint64_t event_arg) 2991 { 2992 int ret = -EINVAL; 2993 struct smu_context *smu = &adev->smu; 2994 2995 if (smu->ppt_funcs->wait_for_event) { 2996 mutex_lock(&smu->mutex); 2997 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 2998 mutex_unlock(&smu->mutex); 2999 } 3000 3001 return ret; 3002 } 3003