1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id); 59 static int smu_reset(struct smu_context *smu); 60 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 61 static int smu_set_fan_control_mode(void *handle, u32 value); 62 static int smu_set_power_limit(void *handle, uint32_t limit); 63 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 64 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 65 66 static int smu_sys_get_pp_feature_mask(void *handle, 67 char *buf) 68 { 69 struct smu_context *smu = handle; 70 71 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 72 return -EOPNOTSUPP; 73 74 return smu_get_pp_feature_mask(smu, buf); 75 } 76 77 static int smu_sys_set_pp_feature_mask(void *handle, 78 uint64_t new_mask) 79 { 80 struct smu_context *smu = handle; 81 82 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 83 return -EOPNOTSUPP; 84 85 return smu_set_pp_feature_mask(smu, new_mask); 86 } 87 88 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 89 { 90 if (!smu->ppt_funcs->get_gfx_off_status) 91 return -EINVAL; 92 93 *value = smu_get_gfx_off_status(smu); 94 95 return 0; 96 } 97 98 int smu_set_soft_freq_range(struct smu_context *smu, 99 enum smu_clk_type clk_type, 100 uint32_t min, 101 uint32_t max) 102 { 103 int ret = 0; 104 105 if (smu->ppt_funcs->set_soft_freq_limited_range) 106 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 107 clk_type, 108 min, 109 max); 110 111 return ret; 112 } 113 114 int smu_get_dpm_freq_range(struct smu_context *smu, 115 enum smu_clk_type clk_type, 116 uint32_t *min, 117 uint32_t *max) 118 { 119 int ret = -ENOTSUPP; 120 121 if (!min && !max) 122 return -EINVAL; 123 124 if (smu->ppt_funcs->get_dpm_ultimate_freq) 125 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 126 clk_type, 127 min, 128 max); 129 130 return ret; 131 } 132 133 static u32 smu_get_mclk(void *handle, bool low) 134 { 135 struct smu_context *smu = handle; 136 uint32_t clk_freq; 137 int ret = 0; 138 139 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 140 low ? &clk_freq : NULL, 141 !low ? &clk_freq : NULL); 142 if (ret) 143 return 0; 144 return clk_freq * 100; 145 } 146 147 static u32 smu_get_sclk(void *handle, bool low) 148 { 149 struct smu_context *smu = handle; 150 uint32_t clk_freq; 151 int ret = 0; 152 153 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 154 low ? &clk_freq : NULL, 155 !low ? &clk_freq : NULL); 156 if (ret) 157 return 0; 158 return clk_freq * 100; 159 } 160 161 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 162 bool enable) 163 { 164 struct smu_power_context *smu_power = &smu->smu_power; 165 struct smu_power_gate *power_gate = &smu_power->power_gate; 166 int ret = 0; 167 168 if (!smu->ppt_funcs->dpm_set_vcn_enable) 169 return 0; 170 171 if (atomic_read(&power_gate->vcn_gated) ^ enable) 172 return 0; 173 174 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 175 if (!ret) 176 atomic_set(&power_gate->vcn_gated, !enable); 177 178 return ret; 179 } 180 181 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 182 bool enable) 183 { 184 struct smu_power_context *smu_power = &smu->smu_power; 185 struct smu_power_gate *power_gate = &smu_power->power_gate; 186 int ret = 0; 187 188 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 189 return 0; 190 191 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 192 return 0; 193 194 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 195 if (!ret) 196 atomic_set(&power_gate->jpeg_gated, !enable); 197 198 return ret; 199 } 200 201 /** 202 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 203 * 204 * @handle: smu_context pointer 205 * @block_type: the IP block to power gate/ungate 206 * @gate: to power gate if true, ungate otherwise 207 * 208 * This API uses no smu->mutex lock protection due to: 209 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 210 * This is guarded to be race condition free by the caller. 211 * 2. Or get called on user setting request of power_dpm_force_performance_level. 212 * Under this case, the smu->mutex lock protection is already enforced on 213 * the parent API smu_force_performance_level of the call path. 214 */ 215 static int smu_dpm_set_power_gate(void *handle, 216 uint32_t block_type, 217 bool gate) 218 { 219 struct smu_context *smu = handle; 220 int ret = 0; 221 222 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 223 dev_WARN(smu->adev->dev, 224 "SMU uninitialized but power %s requested for %u!\n", 225 gate ? "gate" : "ungate", block_type); 226 return -EOPNOTSUPP; 227 } 228 229 switch (block_type) { 230 /* 231 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 232 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 233 */ 234 case AMD_IP_BLOCK_TYPE_UVD: 235 case AMD_IP_BLOCK_TYPE_VCN: 236 ret = smu_dpm_set_vcn_enable(smu, !gate); 237 if (ret) 238 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 239 gate ? "gate" : "ungate"); 240 break; 241 case AMD_IP_BLOCK_TYPE_GFX: 242 ret = smu_gfx_off_control(smu, gate); 243 if (ret) 244 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 245 gate ? "enable" : "disable"); 246 break; 247 case AMD_IP_BLOCK_TYPE_SDMA: 248 ret = smu_powergate_sdma(smu, gate); 249 if (ret) 250 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 251 gate ? "gate" : "ungate"); 252 break; 253 case AMD_IP_BLOCK_TYPE_JPEG: 254 ret = smu_dpm_set_jpeg_enable(smu, !gate); 255 if (ret) 256 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 257 gate ? "gate" : "ungate"); 258 break; 259 default: 260 dev_err(smu->adev->dev, "Unsupported block type!\n"); 261 return -EINVAL; 262 } 263 264 return ret; 265 } 266 267 /** 268 * smu_set_user_clk_dependencies - set user profile clock dependencies 269 * 270 * @smu: smu_context pointer 271 * @clk: enum smu_clk_type type 272 * 273 * Enable/Disable the clock dependency for the @clk type. 274 */ 275 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 276 { 277 if (smu->adev->in_suspend) 278 return; 279 280 if (clk == SMU_MCLK) { 281 smu->user_dpm_profile.clk_dependency = 0; 282 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 283 } else if (clk == SMU_FCLK) { 284 /* MCLK takes precedence over FCLK */ 285 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 286 return; 287 288 smu->user_dpm_profile.clk_dependency = 0; 289 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 290 } else if (clk == SMU_SOCCLK) { 291 /* MCLK takes precedence over SOCCLK */ 292 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 293 return; 294 295 smu->user_dpm_profile.clk_dependency = 0; 296 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 297 } else 298 /* Add clk dependencies here, if any */ 299 return; 300 } 301 302 /** 303 * smu_restore_dpm_user_profile - reinstate user dpm profile 304 * 305 * @smu: smu_context pointer 306 * 307 * Restore the saved user power configurations include power limit, 308 * clock frequencies, fan control mode and fan speed. 309 */ 310 static void smu_restore_dpm_user_profile(struct smu_context *smu) 311 { 312 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 313 int ret = 0; 314 315 if (!smu->adev->in_suspend) 316 return; 317 318 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 319 return; 320 321 /* Enable restore flag */ 322 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 323 324 /* set the user dpm power limit */ 325 if (smu->user_dpm_profile.power_limit) { 326 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 327 if (ret) 328 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 329 } 330 331 /* set the user dpm clock configurations */ 332 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 333 enum smu_clk_type clk_type; 334 335 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 336 /* 337 * Iterate over smu clk type and force the saved user clk 338 * configs, skip if clock dependency is enabled 339 */ 340 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 341 smu->user_dpm_profile.clk_mask[clk_type]) { 342 ret = smu_force_smuclk_levels(smu, clk_type, 343 smu->user_dpm_profile.clk_mask[clk_type]); 344 if (ret) 345 dev_err(smu->adev->dev, 346 "Failed to set clock type = %d\n", clk_type); 347 } 348 } 349 } 350 351 /* set the user dpm fan configurations */ 352 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 353 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 354 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 355 if (ret != -EOPNOTSUPP) { 356 smu->user_dpm_profile.fan_speed_pwm = 0; 357 smu->user_dpm_profile.fan_speed_rpm = 0; 358 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 359 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 360 } 361 362 if (smu->user_dpm_profile.fan_speed_pwm) { 363 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 364 if (ret != -EOPNOTSUPP) 365 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 366 } 367 368 if (smu->user_dpm_profile.fan_speed_rpm) { 369 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 370 if (ret != -EOPNOTSUPP) 371 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 372 } 373 } 374 375 /* Restore user customized OD settings */ 376 if (smu->user_dpm_profile.user_od) { 377 if (smu->ppt_funcs->restore_user_od_settings) { 378 ret = smu->ppt_funcs->restore_user_od_settings(smu); 379 if (ret) 380 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 381 } 382 } 383 384 /* Disable restore flag */ 385 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 386 } 387 388 static int smu_get_power_num_states(void *handle, 389 struct pp_states_info *state_info) 390 { 391 if (!state_info) 392 return -EINVAL; 393 394 /* not support power state */ 395 memset(state_info, 0, sizeof(struct pp_states_info)); 396 state_info->nums = 1; 397 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 398 399 return 0; 400 } 401 402 bool is_support_sw_smu(struct amdgpu_device *adev) 403 { 404 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 405 if (adev->asic_type == CHIP_VEGA20) 406 return false; 407 408 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 409 return true; 410 411 return false; 412 } 413 414 bool is_support_cclk_dpm(struct amdgpu_device *adev) 415 { 416 struct smu_context *smu = adev->powerplay.pp_handle; 417 418 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 419 return false; 420 421 return true; 422 } 423 424 425 static int smu_sys_get_pp_table(void *handle, 426 char **table) 427 { 428 struct smu_context *smu = handle; 429 struct smu_table_context *smu_table = &smu->smu_table; 430 431 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 432 return -EOPNOTSUPP; 433 434 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 435 return -EINVAL; 436 437 if (smu_table->hardcode_pptable) 438 *table = smu_table->hardcode_pptable; 439 else 440 *table = smu_table->power_play_table; 441 442 return smu_table->power_play_table_size; 443 } 444 445 static int smu_sys_set_pp_table(void *handle, 446 const char *buf, 447 size_t size) 448 { 449 struct smu_context *smu = handle; 450 struct smu_table_context *smu_table = &smu->smu_table; 451 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 452 int ret = 0; 453 454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 455 return -EOPNOTSUPP; 456 457 if (header->usStructureSize != size) { 458 dev_err(smu->adev->dev, "pp table size not matched !\n"); 459 return -EIO; 460 } 461 462 if (!smu_table->hardcode_pptable) { 463 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 464 if (!smu_table->hardcode_pptable) 465 return -ENOMEM; 466 } 467 468 memcpy(smu_table->hardcode_pptable, buf, size); 469 smu_table->power_play_table = smu_table->hardcode_pptable; 470 smu_table->power_play_table_size = size; 471 472 /* 473 * Special hw_fini action(for Navi1x, the DPMs disablement will be 474 * skipped) may be needed for custom pptable uploading. 475 */ 476 smu->uploading_custom_pp_table = true; 477 478 ret = smu_reset(smu); 479 if (ret) 480 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 481 482 smu->uploading_custom_pp_table = false; 483 484 return ret; 485 } 486 487 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 488 { 489 struct smu_feature *feature = &smu->smu_feature; 490 int ret = 0; 491 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 492 493 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 494 495 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 496 SMU_FEATURE_MAX/32); 497 if (ret) 498 return ret; 499 500 bitmap_or(feature->allowed, feature->allowed, 501 (unsigned long *)allowed_feature_mask, 502 feature->feature_num); 503 504 return ret; 505 } 506 507 static int smu_set_funcs(struct amdgpu_device *adev) 508 { 509 struct smu_context *smu = adev->powerplay.pp_handle; 510 511 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 512 smu->od_enabled = true; 513 514 switch (adev->ip_versions[MP1_HWIP][0]) { 515 case IP_VERSION(11, 0, 0): 516 case IP_VERSION(11, 0, 5): 517 case IP_VERSION(11, 0, 9): 518 navi10_set_ppt_funcs(smu); 519 break; 520 case IP_VERSION(11, 0, 7): 521 case IP_VERSION(11, 0, 11): 522 case IP_VERSION(11, 0, 12): 523 case IP_VERSION(11, 0, 13): 524 sienna_cichlid_set_ppt_funcs(smu); 525 break; 526 case IP_VERSION(12, 0, 0): 527 case IP_VERSION(12, 0, 1): 528 renoir_set_ppt_funcs(smu); 529 break; 530 case IP_VERSION(11, 5, 0): 531 vangogh_set_ppt_funcs(smu); 532 break; 533 case IP_VERSION(13, 0, 1): 534 case IP_VERSION(13, 0, 3): 535 yellow_carp_set_ppt_funcs(smu); 536 break; 537 case IP_VERSION(11, 0, 8): 538 cyan_skillfish_set_ppt_funcs(smu); 539 break; 540 case IP_VERSION(11, 0, 2): 541 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 542 arcturus_set_ppt_funcs(smu); 543 /* OD is not supported on Arcturus */ 544 smu->od_enabled =false; 545 break; 546 case IP_VERSION(13, 0, 2): 547 aldebaran_set_ppt_funcs(smu); 548 /* Enable pp_od_clk_voltage node */ 549 smu->od_enabled = true; 550 break; 551 default: 552 return -EINVAL; 553 } 554 555 return 0; 556 } 557 558 static int smu_early_init(void *handle) 559 { 560 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 561 struct smu_context *smu; 562 563 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 564 if (!smu) 565 return -ENOMEM; 566 567 smu->adev = adev; 568 smu->pm_enabled = !!amdgpu_dpm; 569 smu->is_apu = false; 570 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 571 smu->smu_baco.platform_support = false; 572 smu->user_dpm_profile.fan_mode = -1; 573 574 adev->powerplay.pp_handle = smu; 575 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 576 577 return smu_set_funcs(adev); 578 } 579 580 static int smu_set_default_dpm_table(struct smu_context *smu) 581 { 582 struct smu_power_context *smu_power = &smu->smu_power; 583 struct smu_power_gate *power_gate = &smu_power->power_gate; 584 int vcn_gate, jpeg_gate; 585 int ret = 0; 586 587 if (!smu->ppt_funcs->set_default_dpm_table) 588 return 0; 589 590 vcn_gate = atomic_read(&power_gate->vcn_gated); 591 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 592 593 ret = smu_dpm_set_vcn_enable(smu, true); 594 if (ret) 595 return ret; 596 597 ret = smu_dpm_set_jpeg_enable(smu, true); 598 if (ret) 599 goto err_out; 600 601 ret = smu->ppt_funcs->set_default_dpm_table(smu); 602 if (ret) 603 dev_err(smu->adev->dev, 604 "Failed to setup default dpm clock tables!\n"); 605 606 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 607 err_out: 608 smu_dpm_set_vcn_enable(smu, !vcn_gate); 609 return ret; 610 } 611 612 613 static int smu_late_init(void *handle) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 616 struct smu_context *smu = adev->powerplay.pp_handle; 617 int ret = 0; 618 619 smu_set_fine_grain_gfx_freq_parameters(smu); 620 621 if (!smu->pm_enabled) 622 return 0; 623 624 ret = smu_post_init(smu); 625 if (ret) { 626 dev_err(adev->dev, "Failed to post smu init!\n"); 627 return ret; 628 } 629 630 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 631 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 632 return 0; 633 634 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 635 ret = smu_set_default_od_settings(smu); 636 if (ret) { 637 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 638 return ret; 639 } 640 } 641 642 ret = smu_populate_umd_state_clk(smu); 643 if (ret) { 644 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 645 return ret; 646 } 647 648 ret = smu_get_asic_power_limits(smu, 649 &smu->current_power_limit, 650 &smu->default_power_limit, 651 &smu->max_power_limit); 652 if (ret) { 653 dev_err(adev->dev, "Failed to get asic power limits!\n"); 654 return ret; 655 } 656 657 if (!amdgpu_sriov_vf(adev)) 658 smu_get_unique_id(smu); 659 660 smu_get_fan_parameters(smu); 661 662 smu_handle_task(smu, 663 smu->smu_dpm.dpm_level, 664 AMD_PP_TASK_COMPLETE_INIT); 665 666 smu_restore_dpm_user_profile(smu); 667 668 return 0; 669 } 670 671 static int smu_init_fb_allocations(struct smu_context *smu) 672 { 673 struct amdgpu_device *adev = smu->adev; 674 struct smu_table_context *smu_table = &smu->smu_table; 675 struct smu_table *tables = smu_table->tables; 676 struct smu_table *driver_table = &(smu_table->driver_table); 677 uint32_t max_table_size = 0; 678 int ret, i; 679 680 /* VRAM allocation for tool table */ 681 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 682 ret = amdgpu_bo_create_kernel(adev, 683 tables[SMU_TABLE_PMSTATUSLOG].size, 684 tables[SMU_TABLE_PMSTATUSLOG].align, 685 tables[SMU_TABLE_PMSTATUSLOG].domain, 686 &tables[SMU_TABLE_PMSTATUSLOG].bo, 687 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 688 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 689 if (ret) { 690 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 691 return ret; 692 } 693 } 694 695 /* VRAM allocation for driver table */ 696 for (i = 0; i < SMU_TABLE_COUNT; i++) { 697 if (tables[i].size == 0) 698 continue; 699 700 if (i == SMU_TABLE_PMSTATUSLOG) 701 continue; 702 703 if (max_table_size < tables[i].size) 704 max_table_size = tables[i].size; 705 } 706 707 driver_table->size = max_table_size; 708 driver_table->align = PAGE_SIZE; 709 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 710 711 ret = amdgpu_bo_create_kernel(adev, 712 driver_table->size, 713 driver_table->align, 714 driver_table->domain, 715 &driver_table->bo, 716 &driver_table->mc_address, 717 &driver_table->cpu_addr); 718 if (ret) { 719 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 720 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 721 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 722 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 723 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 724 } 725 726 return ret; 727 } 728 729 static int smu_fini_fb_allocations(struct smu_context *smu) 730 { 731 struct smu_table_context *smu_table = &smu->smu_table; 732 struct smu_table *tables = smu_table->tables; 733 struct smu_table *driver_table = &(smu_table->driver_table); 734 735 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 736 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 737 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 738 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 739 740 amdgpu_bo_free_kernel(&driver_table->bo, 741 &driver_table->mc_address, 742 &driver_table->cpu_addr); 743 744 return 0; 745 } 746 747 /** 748 * smu_alloc_memory_pool - allocate memory pool in the system memory 749 * 750 * @smu: amdgpu_device pointer 751 * 752 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 753 * and DramLogSetDramAddr can notify it changed. 754 * 755 * Returns 0 on success, error on failure. 756 */ 757 static int smu_alloc_memory_pool(struct smu_context *smu) 758 { 759 struct amdgpu_device *adev = smu->adev; 760 struct smu_table_context *smu_table = &smu->smu_table; 761 struct smu_table *memory_pool = &smu_table->memory_pool; 762 uint64_t pool_size = smu->pool_size; 763 int ret = 0; 764 765 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 766 return ret; 767 768 memory_pool->size = pool_size; 769 memory_pool->align = PAGE_SIZE; 770 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 771 772 switch (pool_size) { 773 case SMU_MEMORY_POOL_SIZE_256_MB: 774 case SMU_MEMORY_POOL_SIZE_512_MB: 775 case SMU_MEMORY_POOL_SIZE_1_GB: 776 case SMU_MEMORY_POOL_SIZE_2_GB: 777 ret = amdgpu_bo_create_kernel(adev, 778 memory_pool->size, 779 memory_pool->align, 780 memory_pool->domain, 781 &memory_pool->bo, 782 &memory_pool->mc_address, 783 &memory_pool->cpu_addr); 784 if (ret) 785 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 786 break; 787 default: 788 break; 789 } 790 791 return ret; 792 } 793 794 static int smu_free_memory_pool(struct smu_context *smu) 795 { 796 struct smu_table_context *smu_table = &smu->smu_table; 797 struct smu_table *memory_pool = &smu_table->memory_pool; 798 799 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 800 return 0; 801 802 amdgpu_bo_free_kernel(&memory_pool->bo, 803 &memory_pool->mc_address, 804 &memory_pool->cpu_addr); 805 806 memset(memory_pool, 0, sizeof(struct smu_table)); 807 808 return 0; 809 } 810 811 static int smu_alloc_dummy_read_table(struct smu_context *smu) 812 { 813 struct smu_table_context *smu_table = &smu->smu_table; 814 struct smu_table *dummy_read_1_table = 815 &smu_table->dummy_read_1_table; 816 struct amdgpu_device *adev = smu->adev; 817 int ret = 0; 818 819 dummy_read_1_table->size = 0x40000; 820 dummy_read_1_table->align = PAGE_SIZE; 821 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 822 823 ret = amdgpu_bo_create_kernel(adev, 824 dummy_read_1_table->size, 825 dummy_read_1_table->align, 826 dummy_read_1_table->domain, 827 &dummy_read_1_table->bo, 828 &dummy_read_1_table->mc_address, 829 &dummy_read_1_table->cpu_addr); 830 if (ret) 831 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 832 833 return ret; 834 } 835 836 static void smu_free_dummy_read_table(struct smu_context *smu) 837 { 838 struct smu_table_context *smu_table = &smu->smu_table; 839 struct smu_table *dummy_read_1_table = 840 &smu_table->dummy_read_1_table; 841 842 843 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 844 &dummy_read_1_table->mc_address, 845 &dummy_read_1_table->cpu_addr); 846 847 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 848 } 849 850 static int smu_smc_table_sw_init(struct smu_context *smu) 851 { 852 int ret; 853 854 /** 855 * Create smu_table structure, and init smc tables such as 856 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 857 */ 858 ret = smu_init_smc_tables(smu); 859 if (ret) { 860 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 861 return ret; 862 } 863 864 /** 865 * Create smu_power_context structure, and allocate smu_dpm_context and 866 * context size to fill the smu_power_context data. 867 */ 868 ret = smu_init_power(smu); 869 if (ret) { 870 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 871 return ret; 872 } 873 874 /* 875 * allocate vram bos to store smc table contents. 876 */ 877 ret = smu_init_fb_allocations(smu); 878 if (ret) 879 return ret; 880 881 ret = smu_alloc_memory_pool(smu); 882 if (ret) 883 return ret; 884 885 ret = smu_alloc_dummy_read_table(smu); 886 if (ret) 887 return ret; 888 889 ret = smu_i2c_init(smu); 890 if (ret) 891 return ret; 892 893 return 0; 894 } 895 896 static int smu_smc_table_sw_fini(struct smu_context *smu) 897 { 898 int ret; 899 900 smu_i2c_fini(smu); 901 902 smu_free_dummy_read_table(smu); 903 904 ret = smu_free_memory_pool(smu); 905 if (ret) 906 return ret; 907 908 ret = smu_fini_fb_allocations(smu); 909 if (ret) 910 return ret; 911 912 ret = smu_fini_power(smu); 913 if (ret) { 914 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 915 return ret; 916 } 917 918 ret = smu_fini_smc_tables(smu); 919 if (ret) { 920 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 921 return ret; 922 } 923 924 return 0; 925 } 926 927 static void smu_throttling_logging_work_fn(struct work_struct *work) 928 { 929 struct smu_context *smu = container_of(work, struct smu_context, 930 throttling_logging_work); 931 932 smu_log_thermal_throttling(smu); 933 } 934 935 static void smu_interrupt_work_fn(struct work_struct *work) 936 { 937 struct smu_context *smu = container_of(work, struct smu_context, 938 interrupt_work); 939 940 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 941 smu->ppt_funcs->interrupt_work(smu); 942 } 943 944 static int smu_sw_init(void *handle) 945 { 946 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 947 struct smu_context *smu = adev->powerplay.pp_handle; 948 int ret; 949 950 smu->pool_size = adev->pm.smu_prv_buffer_size; 951 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 952 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 953 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 954 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 955 956 mutex_init(&smu->message_lock); 957 958 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 959 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 960 atomic64_set(&smu->throttle_int_counter, 0); 961 smu->watermarks_bitmap = 0; 962 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 963 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 964 965 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 966 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 967 968 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 969 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 970 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 971 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 972 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 973 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 974 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 975 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 976 977 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 978 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 979 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 980 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 981 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 982 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 983 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 984 smu->display_config = &adev->pm.pm_display_cfg; 985 986 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 987 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 988 989 ret = smu_init_microcode(smu); 990 if (ret) { 991 dev_err(adev->dev, "Failed to load smu firmware!\n"); 992 return ret; 993 } 994 995 ret = smu_smc_table_sw_init(smu); 996 if (ret) { 997 dev_err(adev->dev, "Failed to sw init smc table!\n"); 998 return ret; 999 } 1000 1001 ret = smu_register_irq_handler(smu); 1002 if (ret) { 1003 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1004 return ret; 1005 } 1006 1007 /* If there is no way to query fan control mode, fan control is not supported */ 1008 if (!smu->ppt_funcs->get_fan_control_mode) 1009 smu->adev->pm.no_fan = true; 1010 1011 return 0; 1012 } 1013 1014 static int smu_sw_fini(void *handle) 1015 { 1016 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1017 struct smu_context *smu = adev->powerplay.pp_handle; 1018 int ret; 1019 1020 ret = smu_smc_table_sw_fini(smu); 1021 if (ret) { 1022 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1023 return ret; 1024 } 1025 1026 smu_fini_microcode(smu); 1027 1028 return 0; 1029 } 1030 1031 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1032 { 1033 struct amdgpu_device *adev = smu->adev; 1034 struct smu_temperature_range *range = 1035 &smu->thermal_range; 1036 int ret = 0; 1037 1038 if (!smu->ppt_funcs->get_thermal_temperature_range) 1039 return 0; 1040 1041 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1042 if (ret) 1043 return ret; 1044 1045 adev->pm.dpm.thermal.min_temp = range->min; 1046 adev->pm.dpm.thermal.max_temp = range->max; 1047 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1048 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1049 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1050 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1051 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1052 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1053 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1054 1055 return ret; 1056 } 1057 1058 static int smu_smc_hw_setup(struct smu_context *smu) 1059 { 1060 struct amdgpu_device *adev = smu->adev; 1061 uint32_t pcie_gen = 0, pcie_width = 0; 1062 int ret = 0; 1063 1064 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1065 dev_info(adev->dev, "dpm has been enabled\n"); 1066 /* this is needed specifically */ 1067 switch (adev->ip_versions[MP1_HWIP][0]) { 1068 case IP_VERSION(11, 0, 7): 1069 case IP_VERSION(11, 0, 11): 1070 case IP_VERSION(11, 5, 0): 1071 case IP_VERSION(11, 0, 12): 1072 ret = smu_system_features_control(smu, true); 1073 if (ret) 1074 dev_err(adev->dev, "Failed system features control!\n"); 1075 break; 1076 default: 1077 break; 1078 } 1079 return ret; 1080 } 1081 1082 ret = smu_init_display_count(smu, 0); 1083 if (ret) { 1084 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1085 return ret; 1086 } 1087 1088 ret = smu_set_driver_table_location(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1091 return ret; 1092 } 1093 1094 /* 1095 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1096 */ 1097 ret = smu_set_tool_table_location(smu); 1098 if (ret) { 1099 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1100 return ret; 1101 } 1102 1103 /* 1104 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1105 * pool location. 1106 */ 1107 ret = smu_notify_memory_pool_location(smu); 1108 if (ret) { 1109 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1110 return ret; 1111 } 1112 1113 /* smu_dump_pptable(smu); */ 1114 /* 1115 * Copy pptable bo in the vram to smc with SMU MSGs such as 1116 * SetDriverDramAddr and TransferTableDram2Smu. 1117 */ 1118 ret = smu_write_pptable(smu); 1119 if (ret) { 1120 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1121 return ret; 1122 } 1123 1124 /* issue Run*Btc msg */ 1125 ret = smu_run_btc(smu); 1126 if (ret) 1127 return ret; 1128 1129 ret = smu_feature_set_allowed_mask(smu); 1130 if (ret) { 1131 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1132 return ret; 1133 } 1134 1135 ret = smu_system_features_control(smu, true); 1136 if (ret) { 1137 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1138 return ret; 1139 } 1140 1141 if (!smu_is_dpm_running(smu)) 1142 dev_info(adev->dev, "dpm has been disabled\n"); 1143 1144 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1145 pcie_gen = 3; 1146 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1147 pcie_gen = 2; 1148 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1149 pcie_gen = 1; 1150 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1151 pcie_gen = 0; 1152 1153 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1154 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1155 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1156 */ 1157 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1158 pcie_width = 6; 1159 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1160 pcie_width = 5; 1161 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1162 pcie_width = 4; 1163 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1164 pcie_width = 3; 1165 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1166 pcie_width = 2; 1167 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1168 pcie_width = 1; 1169 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1170 if (ret) { 1171 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1172 return ret; 1173 } 1174 1175 ret = smu_get_thermal_temperature_range(smu); 1176 if (ret) { 1177 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1178 return ret; 1179 } 1180 1181 ret = smu_enable_thermal_alert(smu); 1182 if (ret) { 1183 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1184 return ret; 1185 } 1186 1187 /* 1188 * Set initialized values (get from vbios) to dpm tables context such as 1189 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1190 * type of clks. 1191 */ 1192 ret = smu_set_default_dpm_table(smu); 1193 if (ret) { 1194 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1195 return ret; 1196 } 1197 1198 ret = smu_notify_display_change(smu); 1199 if (ret) { 1200 dev_err(adev->dev, "Failed to notify display change!\n"); 1201 return ret; 1202 } 1203 1204 /* 1205 * Set min deep sleep dce fclk with bootup value from vbios via 1206 * SetMinDeepSleepDcefclk MSG. 1207 */ 1208 ret = smu_set_min_dcef_deep_sleep(smu, 1209 smu->smu_table.boot_values.dcefclk / 100); 1210 1211 return ret; 1212 } 1213 1214 static int smu_start_smc_engine(struct smu_context *smu) 1215 { 1216 struct amdgpu_device *adev = smu->adev; 1217 int ret = 0; 1218 1219 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1220 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1221 if (smu->ppt_funcs->load_microcode) { 1222 ret = smu->ppt_funcs->load_microcode(smu); 1223 if (ret) 1224 return ret; 1225 } 1226 } 1227 } 1228 1229 if (smu->ppt_funcs->check_fw_status) { 1230 ret = smu->ppt_funcs->check_fw_status(smu); 1231 if (ret) { 1232 dev_err(adev->dev, "SMC is not ready\n"); 1233 return ret; 1234 } 1235 } 1236 1237 /* 1238 * Send msg GetDriverIfVersion to check if the return value is equal 1239 * with DRIVER_IF_VERSION of smc header. 1240 */ 1241 ret = smu_check_fw_version(smu); 1242 if (ret) 1243 return ret; 1244 1245 return ret; 1246 } 1247 1248 static int smu_hw_init(void *handle) 1249 { 1250 int ret; 1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1252 struct smu_context *smu = adev->powerplay.pp_handle; 1253 1254 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1255 smu->pm_enabled = false; 1256 return 0; 1257 } 1258 1259 ret = smu_start_smc_engine(smu); 1260 if (ret) { 1261 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1262 return ret; 1263 } 1264 1265 if (smu->is_apu) { 1266 smu_dpm_set_vcn_enable(smu, true); 1267 smu_dpm_set_jpeg_enable(smu, true); 1268 smu_set_gfx_cgpg(smu, true); 1269 } 1270 1271 if (!smu->pm_enabled) 1272 return 0; 1273 1274 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1275 ret = smu_get_vbios_bootup_values(smu); 1276 if (ret) { 1277 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1278 return ret; 1279 } 1280 1281 ret = smu_setup_pptable(smu); 1282 if (ret) { 1283 dev_err(adev->dev, "Failed to setup pptable!\n"); 1284 return ret; 1285 } 1286 1287 ret = smu_get_driver_allowed_feature_mask(smu); 1288 if (ret) 1289 return ret; 1290 1291 ret = smu_smc_hw_setup(smu); 1292 if (ret) { 1293 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1294 return ret; 1295 } 1296 1297 /* 1298 * Move maximum sustainable clock retrieving here considering 1299 * 1. It is not needed on resume(from S3). 1300 * 2. DAL settings come between .hw_init and .late_init of SMU. 1301 * And DAL needs to know the maximum sustainable clocks. Thus 1302 * it cannot be put in .late_init(). 1303 */ 1304 ret = smu_init_max_sustainable_clocks(smu); 1305 if (ret) { 1306 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1307 return ret; 1308 } 1309 1310 adev->pm.dpm_enabled = true; 1311 1312 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1313 1314 return 0; 1315 } 1316 1317 static int smu_disable_dpms(struct smu_context *smu) 1318 { 1319 struct amdgpu_device *adev = smu->adev; 1320 int ret = 0; 1321 /* 1322 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair 1323 * the workaround which always reset the asic in suspend. 1324 * It's likely that workaround will be dropped in the future. 1325 * Then the change here should be dropped together. 1326 */ 1327 bool use_baco = !smu->is_apu && 1328 (((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) && 1329 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1330 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1331 1332 /* 1333 * For custom pptable uploading, skip the DPM features 1334 * disable process on Navi1x ASICs. 1335 * - As the gfx related features are under control of 1336 * RLC on those ASICs. RLC reinitialization will be 1337 * needed to reenable them. That will cost much more 1338 * efforts. 1339 * 1340 * - SMU firmware can handle the DPM reenablement 1341 * properly. 1342 */ 1343 if (smu->uploading_custom_pp_table) { 1344 switch (adev->ip_versions[MP1_HWIP][0]) { 1345 case IP_VERSION(11, 0, 0): 1346 case IP_VERSION(11, 0, 5): 1347 case IP_VERSION(11, 0, 9): 1348 case IP_VERSION(11, 0, 7): 1349 case IP_VERSION(11, 0, 11): 1350 case IP_VERSION(11, 5, 0): 1351 case IP_VERSION(11, 0, 12): 1352 case IP_VERSION(11, 0, 13): 1353 return smu_disable_all_features_with_exception(smu, 1354 true, 1355 SMU_FEATURE_COUNT); 1356 default: 1357 break; 1358 } 1359 } 1360 1361 /* 1362 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1363 * on BACO in. Driver involvement is unnecessary. 1364 */ 1365 if (use_baco) { 1366 switch (adev->ip_versions[MP1_HWIP][0]) { 1367 case IP_VERSION(11, 0, 7): 1368 case IP_VERSION(11, 0, 0): 1369 case IP_VERSION(11, 0, 5): 1370 case IP_VERSION(11, 0, 9): 1371 return smu_disable_all_features_with_exception(smu, 1372 true, 1373 SMU_FEATURE_BACO_BIT); 1374 default: 1375 break; 1376 } 1377 } 1378 1379 /* 1380 * For gpu reset, runpm and hibernation through BACO, 1381 * BACO feature has to be kept enabled. 1382 */ 1383 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1384 ret = smu_disable_all_features_with_exception(smu, 1385 false, 1386 SMU_FEATURE_BACO_BIT); 1387 if (ret) 1388 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1389 } else { 1390 ret = smu_system_features_control(smu, false); 1391 if (ret) 1392 dev_err(adev->dev, "Failed to disable smu features.\n"); 1393 } 1394 1395 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1396 adev->gfx.rlc.funcs->stop) 1397 adev->gfx.rlc.funcs->stop(adev); 1398 1399 return ret; 1400 } 1401 1402 static int smu_smc_hw_cleanup(struct smu_context *smu) 1403 { 1404 struct amdgpu_device *adev = smu->adev; 1405 int ret = 0; 1406 1407 cancel_work_sync(&smu->throttling_logging_work); 1408 cancel_work_sync(&smu->interrupt_work); 1409 1410 ret = smu_disable_thermal_alert(smu); 1411 if (ret) { 1412 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1413 return ret; 1414 } 1415 1416 ret = smu_disable_dpms(smu); 1417 if (ret) { 1418 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1419 return ret; 1420 } 1421 1422 return 0; 1423 } 1424 1425 static int smu_hw_fini(void *handle) 1426 { 1427 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1428 struct smu_context *smu = adev->powerplay.pp_handle; 1429 1430 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1431 return 0; 1432 1433 smu_dpm_set_vcn_enable(smu, false); 1434 smu_dpm_set_jpeg_enable(smu, false); 1435 1436 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1437 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1438 1439 if (!smu->pm_enabled) 1440 return 0; 1441 1442 adev->pm.dpm_enabled = false; 1443 1444 return smu_smc_hw_cleanup(smu); 1445 } 1446 1447 static void smu_late_fini(void *handle) 1448 { 1449 struct amdgpu_device *adev = handle; 1450 struct smu_context *smu = adev->powerplay.pp_handle; 1451 1452 kfree(smu); 1453 } 1454 1455 static int smu_reset(struct smu_context *smu) 1456 { 1457 struct amdgpu_device *adev = smu->adev; 1458 int ret; 1459 1460 ret = smu_hw_fini(adev); 1461 if (ret) 1462 return ret; 1463 1464 ret = smu_hw_init(adev); 1465 if (ret) 1466 return ret; 1467 1468 ret = smu_late_init(adev); 1469 if (ret) 1470 return ret; 1471 1472 return 0; 1473 } 1474 1475 static int smu_suspend(void *handle) 1476 { 1477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1478 struct smu_context *smu = adev->powerplay.pp_handle; 1479 int ret; 1480 1481 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1482 return 0; 1483 1484 if (!smu->pm_enabled) 1485 return 0; 1486 1487 adev->pm.dpm_enabled = false; 1488 1489 ret = smu_smc_hw_cleanup(smu); 1490 if (ret) 1491 return ret; 1492 1493 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1494 1495 smu_set_gfx_cgpg(smu, false); 1496 1497 return 0; 1498 } 1499 1500 static int smu_resume(void *handle) 1501 { 1502 int ret; 1503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1504 struct smu_context *smu = adev->powerplay.pp_handle; 1505 1506 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1507 return 0; 1508 1509 if (!smu->pm_enabled) 1510 return 0; 1511 1512 dev_info(adev->dev, "SMU is resuming...\n"); 1513 1514 ret = smu_start_smc_engine(smu); 1515 if (ret) { 1516 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1517 return ret; 1518 } 1519 1520 ret = smu_smc_hw_setup(smu); 1521 if (ret) { 1522 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1523 return ret; 1524 } 1525 1526 smu_set_gfx_cgpg(smu, true); 1527 1528 smu->disable_uclk_switch = 0; 1529 1530 adev->pm.dpm_enabled = true; 1531 1532 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1533 1534 return 0; 1535 } 1536 1537 static int smu_display_configuration_change(void *handle, 1538 const struct amd_pp_display_configuration *display_config) 1539 { 1540 struct smu_context *smu = handle; 1541 int index = 0; 1542 int num_of_active_display = 0; 1543 1544 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1545 return -EOPNOTSUPP; 1546 1547 if (!display_config) 1548 return -EINVAL; 1549 1550 smu_set_min_dcef_deep_sleep(smu, 1551 display_config->min_dcef_deep_sleep_set_clk / 100); 1552 1553 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1554 if (display_config->displays[index].controller_id != 0) 1555 num_of_active_display++; 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int smu_set_clockgating_state(void *handle, 1562 enum amd_clockgating_state state) 1563 { 1564 return 0; 1565 } 1566 1567 static int smu_set_powergating_state(void *handle, 1568 enum amd_powergating_state state) 1569 { 1570 return 0; 1571 } 1572 1573 static int smu_enable_umd_pstate(void *handle, 1574 enum amd_dpm_forced_level *level) 1575 { 1576 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1577 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1578 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1579 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1580 1581 struct smu_context *smu = (struct smu_context*)(handle); 1582 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1583 1584 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1585 return -EINVAL; 1586 1587 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1588 /* enter umd pstate, save current level, disable gfx cg*/ 1589 if (*level & profile_mode_mask) { 1590 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1591 smu_gpo_control(smu, false); 1592 smu_gfx_ulv_control(smu, false); 1593 smu_deep_sleep_control(smu, false); 1594 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1595 } 1596 } else { 1597 /* exit umd pstate, restore level, enable gfx cg*/ 1598 if (!(*level & profile_mode_mask)) { 1599 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1600 *level = smu_dpm_ctx->saved_dpm_level; 1601 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1602 smu_deep_sleep_control(smu, true); 1603 smu_gfx_ulv_control(smu, true); 1604 smu_gpo_control(smu, true); 1605 } 1606 } 1607 1608 return 0; 1609 } 1610 1611 static int smu_bump_power_profile_mode(struct smu_context *smu, 1612 long *param, 1613 uint32_t param_size) 1614 { 1615 int ret = 0; 1616 1617 if (smu->ppt_funcs->set_power_profile_mode) 1618 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1619 1620 return ret; 1621 } 1622 1623 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1624 enum amd_dpm_forced_level level, 1625 bool skip_display_settings) 1626 { 1627 int ret = 0; 1628 int index = 0; 1629 long workload; 1630 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1631 1632 if (!skip_display_settings) { 1633 ret = smu_display_config_changed(smu); 1634 if (ret) { 1635 dev_err(smu->adev->dev, "Failed to change display config!"); 1636 return ret; 1637 } 1638 } 1639 1640 ret = smu_apply_clocks_adjust_rules(smu); 1641 if (ret) { 1642 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1643 return ret; 1644 } 1645 1646 if (!skip_display_settings) { 1647 ret = smu_notify_smc_display_config(smu); 1648 if (ret) { 1649 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1650 return ret; 1651 } 1652 } 1653 1654 if (smu_dpm_ctx->dpm_level != level) { 1655 ret = smu_asic_set_performance_level(smu, level); 1656 if (ret) { 1657 dev_err(smu->adev->dev, "Failed to set performance level!"); 1658 return ret; 1659 } 1660 1661 /* update the saved copy */ 1662 smu_dpm_ctx->dpm_level = level; 1663 } 1664 1665 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1666 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1667 index = fls(smu->workload_mask); 1668 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1669 workload = smu->workload_setting[index]; 1670 1671 if (smu->power_profile_mode != workload) 1672 smu_bump_power_profile_mode(smu, &workload, 0); 1673 } 1674 1675 return ret; 1676 } 1677 1678 static int smu_handle_task(struct smu_context *smu, 1679 enum amd_dpm_forced_level level, 1680 enum amd_pp_task task_id) 1681 { 1682 int ret = 0; 1683 1684 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1685 return -EOPNOTSUPP; 1686 1687 switch (task_id) { 1688 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1689 ret = smu_pre_display_config_changed(smu); 1690 if (ret) 1691 return ret; 1692 ret = smu_adjust_power_state_dynamic(smu, level, false); 1693 break; 1694 case AMD_PP_TASK_COMPLETE_INIT: 1695 case AMD_PP_TASK_READJUST_POWER_STATE: 1696 ret = smu_adjust_power_state_dynamic(smu, level, true); 1697 break; 1698 default: 1699 break; 1700 } 1701 1702 return ret; 1703 } 1704 1705 static int smu_handle_dpm_task(void *handle, 1706 enum amd_pp_task task_id, 1707 enum amd_pm_state_type *user_state) 1708 { 1709 struct smu_context *smu = handle; 1710 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1711 1712 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1713 1714 } 1715 1716 static int smu_switch_power_profile(void *handle, 1717 enum PP_SMC_POWER_PROFILE type, 1718 bool en) 1719 { 1720 struct smu_context *smu = handle; 1721 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1722 long workload; 1723 uint32_t index; 1724 1725 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1726 return -EOPNOTSUPP; 1727 1728 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1729 return -EINVAL; 1730 1731 if (!en) { 1732 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1733 index = fls(smu->workload_mask); 1734 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1735 workload = smu->workload_setting[index]; 1736 } else { 1737 smu->workload_mask |= (1 << smu->workload_prority[type]); 1738 index = fls(smu->workload_mask); 1739 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1740 workload = smu->workload_setting[index]; 1741 } 1742 1743 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1744 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1745 smu_bump_power_profile_mode(smu, &workload, 0); 1746 1747 return 0; 1748 } 1749 1750 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1751 { 1752 struct smu_context *smu = handle; 1753 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1754 1755 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1756 return -EOPNOTSUPP; 1757 1758 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1759 return -EINVAL; 1760 1761 return smu_dpm_ctx->dpm_level; 1762 } 1763 1764 static int smu_force_performance_level(void *handle, 1765 enum amd_dpm_forced_level level) 1766 { 1767 struct smu_context *smu = handle; 1768 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1769 int ret = 0; 1770 1771 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1772 return -EOPNOTSUPP; 1773 1774 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1775 return -EINVAL; 1776 1777 ret = smu_enable_umd_pstate(smu, &level); 1778 if (ret) 1779 return ret; 1780 1781 ret = smu_handle_task(smu, level, 1782 AMD_PP_TASK_READJUST_POWER_STATE); 1783 1784 /* reset user dpm clock state */ 1785 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1786 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1787 smu->user_dpm_profile.clk_dependency = 0; 1788 } 1789 1790 return ret; 1791 } 1792 1793 static int smu_set_display_count(void *handle, uint32_t count) 1794 { 1795 struct smu_context *smu = handle; 1796 1797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1798 return -EOPNOTSUPP; 1799 1800 return smu_init_display_count(smu, count); 1801 } 1802 1803 static int smu_force_smuclk_levels(struct smu_context *smu, 1804 enum smu_clk_type clk_type, 1805 uint32_t mask) 1806 { 1807 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1808 int ret = 0; 1809 1810 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1811 return -EOPNOTSUPP; 1812 1813 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1814 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1815 return -EINVAL; 1816 } 1817 1818 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1819 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1820 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1821 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1822 smu_set_user_clk_dependencies(smu, clk_type); 1823 } 1824 } 1825 1826 return ret; 1827 } 1828 1829 static int smu_force_ppclk_levels(void *handle, 1830 enum pp_clock_type type, 1831 uint32_t mask) 1832 { 1833 struct smu_context *smu = handle; 1834 enum smu_clk_type clk_type; 1835 1836 switch (type) { 1837 case PP_SCLK: 1838 clk_type = SMU_SCLK; break; 1839 case PP_MCLK: 1840 clk_type = SMU_MCLK; break; 1841 case PP_PCIE: 1842 clk_type = SMU_PCIE; break; 1843 case PP_SOCCLK: 1844 clk_type = SMU_SOCCLK; break; 1845 case PP_FCLK: 1846 clk_type = SMU_FCLK; break; 1847 case PP_DCEFCLK: 1848 clk_type = SMU_DCEFCLK; break; 1849 case PP_VCLK: 1850 clk_type = SMU_VCLK; break; 1851 case PP_DCLK: 1852 clk_type = SMU_DCLK; break; 1853 case OD_SCLK: 1854 clk_type = SMU_OD_SCLK; break; 1855 case OD_MCLK: 1856 clk_type = SMU_OD_MCLK; break; 1857 case OD_VDDC_CURVE: 1858 clk_type = SMU_OD_VDDC_CURVE; break; 1859 case OD_RANGE: 1860 clk_type = SMU_OD_RANGE; break; 1861 default: 1862 return -EINVAL; 1863 } 1864 1865 return smu_force_smuclk_levels(smu, clk_type, mask); 1866 } 1867 1868 /* 1869 * On system suspending or resetting, the dpm_enabled 1870 * flag will be cleared. So that those SMU services which 1871 * are not supported will be gated. 1872 * However, the mp1 state setting should still be granted 1873 * even if the dpm_enabled cleared. 1874 */ 1875 static int smu_set_mp1_state(void *handle, 1876 enum pp_mp1_state mp1_state) 1877 { 1878 struct smu_context *smu = handle; 1879 int ret = 0; 1880 1881 if (!smu->pm_enabled) 1882 return -EOPNOTSUPP; 1883 1884 if (smu->ppt_funcs && 1885 smu->ppt_funcs->set_mp1_state) 1886 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1887 1888 return ret; 1889 } 1890 1891 static int smu_set_df_cstate(void *handle, 1892 enum pp_df_cstate state) 1893 { 1894 struct smu_context *smu = handle; 1895 int ret = 0; 1896 1897 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1898 return -EOPNOTSUPP; 1899 1900 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1901 return 0; 1902 1903 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1904 if (ret) 1905 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1906 1907 return ret; 1908 } 1909 1910 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1911 { 1912 int ret = 0; 1913 1914 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1915 return -EOPNOTSUPP; 1916 1917 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1918 return 0; 1919 1920 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1921 if (ret) 1922 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1923 1924 return ret; 1925 } 1926 1927 int smu_write_watermarks_table(struct smu_context *smu) 1928 { 1929 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1930 return -EOPNOTSUPP; 1931 1932 return smu_set_watermarks_table(smu, NULL); 1933 } 1934 1935 static int smu_set_watermarks_for_clock_ranges(void *handle, 1936 struct pp_smu_wm_range_sets *clock_ranges) 1937 { 1938 struct smu_context *smu = handle; 1939 1940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1941 return -EOPNOTSUPP; 1942 1943 if (smu->disable_watermark) 1944 return 0; 1945 1946 return smu_set_watermarks_table(smu, clock_ranges); 1947 } 1948 1949 int smu_set_ac_dc(struct smu_context *smu) 1950 { 1951 int ret = 0; 1952 1953 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1954 return -EOPNOTSUPP; 1955 1956 /* controlled by firmware */ 1957 if (smu->dc_controlled_by_gpio) 1958 return 0; 1959 1960 ret = smu_set_power_source(smu, 1961 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 1962 SMU_POWER_SOURCE_DC); 1963 if (ret) 1964 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 1965 smu->adev->pm.ac_power ? "AC" : "DC"); 1966 1967 return ret; 1968 } 1969 1970 const struct amd_ip_funcs smu_ip_funcs = { 1971 .name = "smu", 1972 .early_init = smu_early_init, 1973 .late_init = smu_late_init, 1974 .sw_init = smu_sw_init, 1975 .sw_fini = smu_sw_fini, 1976 .hw_init = smu_hw_init, 1977 .hw_fini = smu_hw_fini, 1978 .late_fini = smu_late_fini, 1979 .suspend = smu_suspend, 1980 .resume = smu_resume, 1981 .is_idle = NULL, 1982 .check_soft_reset = NULL, 1983 .wait_for_idle = NULL, 1984 .soft_reset = NULL, 1985 .set_clockgating_state = smu_set_clockgating_state, 1986 .set_powergating_state = smu_set_powergating_state, 1987 }; 1988 1989 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 1990 { 1991 .type = AMD_IP_BLOCK_TYPE_SMC, 1992 .major = 11, 1993 .minor = 0, 1994 .rev = 0, 1995 .funcs = &smu_ip_funcs, 1996 }; 1997 1998 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 1999 { 2000 .type = AMD_IP_BLOCK_TYPE_SMC, 2001 .major = 12, 2002 .minor = 0, 2003 .rev = 0, 2004 .funcs = &smu_ip_funcs, 2005 }; 2006 2007 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2008 { 2009 .type = AMD_IP_BLOCK_TYPE_SMC, 2010 .major = 13, 2011 .minor = 0, 2012 .rev = 0, 2013 .funcs = &smu_ip_funcs, 2014 }; 2015 2016 static int smu_load_microcode(void *handle) 2017 { 2018 struct smu_context *smu = handle; 2019 struct amdgpu_device *adev = smu->adev; 2020 int ret = 0; 2021 2022 if (!smu->pm_enabled) 2023 return -EOPNOTSUPP; 2024 2025 /* This should be used for non PSP loading */ 2026 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2027 return 0; 2028 2029 if (smu->ppt_funcs->load_microcode) { 2030 ret = smu->ppt_funcs->load_microcode(smu); 2031 if (ret) { 2032 dev_err(adev->dev, "Load microcode failed\n"); 2033 return ret; 2034 } 2035 } 2036 2037 if (smu->ppt_funcs->check_fw_status) { 2038 ret = smu->ppt_funcs->check_fw_status(smu); 2039 if (ret) { 2040 dev_err(adev->dev, "SMC is not ready\n"); 2041 return ret; 2042 } 2043 } 2044 2045 return ret; 2046 } 2047 2048 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2049 { 2050 int ret = 0; 2051 2052 if (smu->ppt_funcs->set_gfx_cgpg) 2053 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2054 2055 return ret; 2056 } 2057 2058 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2059 { 2060 struct smu_context *smu = handle; 2061 int ret = 0; 2062 2063 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2064 return -EOPNOTSUPP; 2065 2066 if (!smu->ppt_funcs->set_fan_speed_rpm) 2067 return -EOPNOTSUPP; 2068 2069 if (speed == U32_MAX) 2070 return -EINVAL; 2071 2072 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2073 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2074 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2075 smu->user_dpm_profile.fan_speed_rpm = speed; 2076 2077 /* Override custom PWM setting as they cannot co-exist */ 2078 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2079 smu->user_dpm_profile.fan_speed_pwm = 0; 2080 } 2081 2082 return ret; 2083 } 2084 2085 /** 2086 * smu_get_power_limit - Request one of the SMU Power Limits 2087 * 2088 * @handle: pointer to smu context 2089 * @limit: requested limit is written back to this variable 2090 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2091 * @pp_power_type: &pp_power_type type of power 2092 * Return: 0 on success, <0 on error 2093 * 2094 */ 2095 int smu_get_power_limit(void *handle, 2096 uint32_t *limit, 2097 enum pp_power_limit_level pp_limit_level, 2098 enum pp_power_type pp_power_type) 2099 { 2100 struct smu_context *smu = handle; 2101 struct amdgpu_device *adev = smu->adev; 2102 enum smu_ppt_limit_level limit_level; 2103 uint32_t limit_type; 2104 int ret = 0; 2105 2106 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2107 return -EOPNOTSUPP; 2108 2109 switch(pp_power_type) { 2110 case PP_PWR_TYPE_SUSTAINED: 2111 limit_type = SMU_DEFAULT_PPT_LIMIT; 2112 break; 2113 case PP_PWR_TYPE_FAST: 2114 limit_type = SMU_FAST_PPT_LIMIT; 2115 break; 2116 default: 2117 return -EOPNOTSUPP; 2118 break; 2119 } 2120 2121 switch(pp_limit_level){ 2122 case PP_PWR_LIMIT_CURRENT: 2123 limit_level = SMU_PPT_LIMIT_CURRENT; 2124 break; 2125 case PP_PWR_LIMIT_DEFAULT: 2126 limit_level = SMU_PPT_LIMIT_DEFAULT; 2127 break; 2128 case PP_PWR_LIMIT_MAX: 2129 limit_level = SMU_PPT_LIMIT_MAX; 2130 break; 2131 case PP_PWR_LIMIT_MIN: 2132 default: 2133 return -EOPNOTSUPP; 2134 break; 2135 } 2136 2137 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2138 if (smu->ppt_funcs->get_ppt_limit) 2139 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2140 } else { 2141 switch (limit_level) { 2142 case SMU_PPT_LIMIT_CURRENT: 2143 switch (adev->ip_versions[MP1_HWIP][0]) { 2144 case IP_VERSION(13, 0, 2): 2145 case IP_VERSION(11, 0, 7): 2146 case IP_VERSION(11, 0, 11): 2147 case IP_VERSION(11, 0, 12): 2148 case IP_VERSION(11, 0, 13): 2149 ret = smu_get_asic_power_limits(smu, 2150 &smu->current_power_limit, 2151 NULL, 2152 NULL); 2153 break; 2154 default: 2155 break; 2156 } 2157 *limit = smu->current_power_limit; 2158 break; 2159 case SMU_PPT_LIMIT_DEFAULT: 2160 *limit = smu->default_power_limit; 2161 break; 2162 case SMU_PPT_LIMIT_MAX: 2163 *limit = smu->max_power_limit; 2164 break; 2165 default: 2166 break; 2167 } 2168 } 2169 2170 return ret; 2171 } 2172 2173 static int smu_set_power_limit(void *handle, uint32_t limit) 2174 { 2175 struct smu_context *smu = handle; 2176 uint32_t limit_type = limit >> 24; 2177 int ret = 0; 2178 2179 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2180 return -EOPNOTSUPP; 2181 2182 limit &= (1<<24)-1; 2183 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2184 if (smu->ppt_funcs->set_power_limit) 2185 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2186 2187 if (limit > smu->max_power_limit) { 2188 dev_err(smu->adev->dev, 2189 "New power limit (%d) is over the max allowed %d\n", 2190 limit, smu->max_power_limit); 2191 return -EINVAL; 2192 } 2193 2194 if (!limit) 2195 limit = smu->current_power_limit; 2196 2197 if (smu->ppt_funcs->set_power_limit) { 2198 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2199 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2200 smu->user_dpm_profile.power_limit = limit; 2201 } 2202 2203 return ret; 2204 } 2205 2206 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2207 { 2208 int ret = 0; 2209 2210 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2211 return -EOPNOTSUPP; 2212 2213 if (smu->ppt_funcs->print_clk_levels) 2214 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2215 2216 return ret; 2217 } 2218 2219 static int smu_print_ppclk_levels(void *handle, 2220 enum pp_clock_type type, 2221 char *buf) 2222 { 2223 struct smu_context *smu = handle; 2224 enum smu_clk_type clk_type; 2225 2226 switch (type) { 2227 case PP_SCLK: 2228 clk_type = SMU_SCLK; break; 2229 case PP_MCLK: 2230 clk_type = SMU_MCLK; break; 2231 case PP_PCIE: 2232 clk_type = SMU_PCIE; break; 2233 case PP_SOCCLK: 2234 clk_type = SMU_SOCCLK; break; 2235 case PP_FCLK: 2236 clk_type = SMU_FCLK; break; 2237 case PP_DCEFCLK: 2238 clk_type = SMU_DCEFCLK; break; 2239 case PP_VCLK: 2240 clk_type = SMU_VCLK; break; 2241 case PP_DCLK: 2242 clk_type = SMU_DCLK; break; 2243 case OD_SCLK: 2244 clk_type = SMU_OD_SCLK; break; 2245 case OD_MCLK: 2246 clk_type = SMU_OD_MCLK; break; 2247 case OD_VDDC_CURVE: 2248 clk_type = SMU_OD_VDDC_CURVE; break; 2249 case OD_RANGE: 2250 clk_type = SMU_OD_RANGE; break; 2251 case OD_VDDGFX_OFFSET: 2252 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2253 case OD_CCLK: 2254 clk_type = SMU_OD_CCLK; break; 2255 default: 2256 return -EINVAL; 2257 } 2258 2259 return smu_print_smuclk_levels(smu, clk_type, buf); 2260 } 2261 2262 static int smu_od_edit_dpm_table(void *handle, 2263 enum PP_OD_DPM_TABLE_COMMAND type, 2264 long *input, uint32_t size) 2265 { 2266 struct smu_context *smu = handle; 2267 int ret = 0; 2268 2269 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2270 return -EOPNOTSUPP; 2271 2272 if (smu->ppt_funcs->od_edit_dpm_table) { 2273 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2274 } 2275 2276 return ret; 2277 } 2278 2279 static int smu_read_sensor(void *handle, 2280 int sensor, 2281 void *data, 2282 int *size_arg) 2283 { 2284 struct smu_context *smu = handle; 2285 struct smu_umd_pstate_table *pstate_table = 2286 &smu->pstate_table; 2287 int ret = 0; 2288 uint32_t *size, size_val; 2289 2290 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2291 return -EOPNOTSUPP; 2292 2293 if (!data || !size_arg) 2294 return -EINVAL; 2295 2296 size_val = *size_arg; 2297 size = &size_val; 2298 2299 if (smu->ppt_funcs->read_sensor) 2300 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2301 goto unlock; 2302 2303 switch (sensor) { 2304 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2305 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2306 *size = 4; 2307 break; 2308 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2309 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2310 *size = 4; 2311 break; 2312 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2313 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2314 *size = 8; 2315 break; 2316 case AMDGPU_PP_SENSOR_UVD_POWER: 2317 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2318 *size = 4; 2319 break; 2320 case AMDGPU_PP_SENSOR_VCE_POWER: 2321 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2322 *size = 4; 2323 break; 2324 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2325 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2326 *size = 4; 2327 break; 2328 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2329 *(uint32_t *)data = 0; 2330 *size = 4; 2331 break; 2332 default: 2333 *size = 0; 2334 ret = -EOPNOTSUPP; 2335 break; 2336 } 2337 2338 unlock: 2339 // assign uint32_t to int 2340 *size_arg = size_val; 2341 2342 return ret; 2343 } 2344 2345 static int smu_get_power_profile_mode(void *handle, char *buf) 2346 { 2347 struct smu_context *smu = handle; 2348 2349 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2350 !smu->ppt_funcs->get_power_profile_mode) 2351 return -EOPNOTSUPP; 2352 if (!buf) 2353 return -EINVAL; 2354 2355 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2356 } 2357 2358 static int smu_set_power_profile_mode(void *handle, 2359 long *param, 2360 uint32_t param_size) 2361 { 2362 struct smu_context *smu = handle; 2363 2364 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2365 !smu->ppt_funcs->set_power_profile_mode) 2366 return -EOPNOTSUPP; 2367 2368 return smu_bump_power_profile_mode(smu, param, param_size); 2369 } 2370 2371 2372 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2373 { 2374 struct smu_context *smu = handle; 2375 2376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2377 return -EOPNOTSUPP; 2378 2379 if (!smu->ppt_funcs->get_fan_control_mode) 2380 return -EOPNOTSUPP; 2381 2382 if (!fan_mode) 2383 return -EINVAL; 2384 2385 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2386 2387 return 0; 2388 } 2389 2390 static int smu_set_fan_control_mode(void *handle, u32 value) 2391 { 2392 struct smu_context *smu = handle; 2393 int ret = 0; 2394 2395 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2396 return -EOPNOTSUPP; 2397 2398 if (!smu->ppt_funcs->set_fan_control_mode) 2399 return -EOPNOTSUPP; 2400 2401 if (value == U32_MAX) 2402 return -EINVAL; 2403 2404 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2405 if (ret) 2406 goto out; 2407 2408 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2409 smu->user_dpm_profile.fan_mode = value; 2410 2411 /* reset user dpm fan speed */ 2412 if (value != AMD_FAN_CTRL_MANUAL) { 2413 smu->user_dpm_profile.fan_speed_pwm = 0; 2414 smu->user_dpm_profile.fan_speed_rpm = 0; 2415 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2416 } 2417 } 2418 2419 out: 2420 return ret; 2421 } 2422 2423 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2424 { 2425 struct smu_context *smu = handle; 2426 int ret = 0; 2427 2428 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2429 return -EOPNOTSUPP; 2430 2431 if (!smu->ppt_funcs->get_fan_speed_pwm) 2432 return -EOPNOTSUPP; 2433 2434 if (!speed) 2435 return -EINVAL; 2436 2437 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2438 2439 return ret; 2440 } 2441 2442 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2443 { 2444 struct smu_context *smu = handle; 2445 int ret = 0; 2446 2447 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2448 return -EOPNOTSUPP; 2449 2450 if (!smu->ppt_funcs->set_fan_speed_pwm) 2451 return -EOPNOTSUPP; 2452 2453 if (speed == U32_MAX) 2454 return -EINVAL; 2455 2456 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2457 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2458 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2459 smu->user_dpm_profile.fan_speed_pwm = speed; 2460 2461 /* Override custom RPM setting as they cannot co-exist */ 2462 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2463 smu->user_dpm_profile.fan_speed_rpm = 0; 2464 } 2465 2466 return ret; 2467 } 2468 2469 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2470 { 2471 struct smu_context *smu = handle; 2472 int ret = 0; 2473 2474 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2475 return -EOPNOTSUPP; 2476 2477 if (!smu->ppt_funcs->get_fan_speed_rpm) 2478 return -EOPNOTSUPP; 2479 2480 if (!speed) 2481 return -EINVAL; 2482 2483 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2484 2485 return ret; 2486 } 2487 2488 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2489 { 2490 struct smu_context *smu = handle; 2491 2492 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2493 return -EOPNOTSUPP; 2494 2495 return smu_set_min_dcef_deep_sleep(smu, clk); 2496 } 2497 2498 static int smu_get_clock_by_type_with_latency(void *handle, 2499 enum amd_pp_clock_type type, 2500 struct pp_clock_levels_with_latency *clocks) 2501 { 2502 struct smu_context *smu = handle; 2503 enum smu_clk_type clk_type; 2504 int ret = 0; 2505 2506 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2507 return -EOPNOTSUPP; 2508 2509 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2510 switch (type) { 2511 case amd_pp_sys_clock: 2512 clk_type = SMU_GFXCLK; 2513 break; 2514 case amd_pp_mem_clock: 2515 clk_type = SMU_MCLK; 2516 break; 2517 case amd_pp_dcef_clock: 2518 clk_type = SMU_DCEFCLK; 2519 break; 2520 case amd_pp_disp_clock: 2521 clk_type = SMU_DISPCLK; 2522 break; 2523 default: 2524 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2525 return -EINVAL; 2526 } 2527 2528 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2529 } 2530 2531 return ret; 2532 } 2533 2534 static int smu_display_clock_voltage_request(void *handle, 2535 struct pp_display_clock_request *clock_req) 2536 { 2537 struct smu_context *smu = handle; 2538 int ret = 0; 2539 2540 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2541 return -EOPNOTSUPP; 2542 2543 if (smu->ppt_funcs->display_clock_voltage_request) 2544 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2545 2546 return ret; 2547 } 2548 2549 2550 static int smu_display_disable_memory_clock_switch(void *handle, 2551 bool disable_memory_clock_switch) 2552 { 2553 struct smu_context *smu = handle; 2554 int ret = -EINVAL; 2555 2556 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2557 return -EOPNOTSUPP; 2558 2559 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2560 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2561 2562 return ret; 2563 } 2564 2565 static int smu_set_xgmi_pstate(void *handle, 2566 uint32_t pstate) 2567 { 2568 struct smu_context *smu = handle; 2569 int ret = 0; 2570 2571 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2572 return -EOPNOTSUPP; 2573 2574 if (smu->ppt_funcs->set_xgmi_pstate) 2575 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2576 2577 if(ret) 2578 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2579 2580 return ret; 2581 } 2582 2583 static int smu_get_baco_capability(void *handle, bool *cap) 2584 { 2585 struct smu_context *smu = handle; 2586 2587 *cap = false; 2588 2589 if (!smu->pm_enabled) 2590 return 0; 2591 2592 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2593 *cap = smu->ppt_funcs->baco_is_support(smu); 2594 2595 return 0; 2596 } 2597 2598 static int smu_baco_set_state(void *handle, int state) 2599 { 2600 struct smu_context *smu = handle; 2601 int ret = 0; 2602 2603 if (!smu->pm_enabled) 2604 return -EOPNOTSUPP; 2605 2606 if (state == 0) { 2607 if (smu->ppt_funcs->baco_exit) 2608 ret = smu->ppt_funcs->baco_exit(smu); 2609 } else if (state == 1) { 2610 if (smu->ppt_funcs->baco_enter) 2611 ret = smu->ppt_funcs->baco_enter(smu); 2612 } else { 2613 return -EINVAL; 2614 } 2615 2616 if (ret) 2617 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2618 (state)?"enter":"exit"); 2619 2620 return ret; 2621 } 2622 2623 bool smu_mode1_reset_is_support(struct smu_context *smu) 2624 { 2625 bool ret = false; 2626 2627 if (!smu->pm_enabled) 2628 return false; 2629 2630 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2631 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2632 2633 return ret; 2634 } 2635 2636 bool smu_mode2_reset_is_support(struct smu_context *smu) 2637 { 2638 bool ret = false; 2639 2640 if (!smu->pm_enabled) 2641 return false; 2642 2643 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2644 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2645 2646 return ret; 2647 } 2648 2649 int smu_mode1_reset(struct smu_context *smu) 2650 { 2651 int ret = 0; 2652 2653 if (!smu->pm_enabled) 2654 return -EOPNOTSUPP; 2655 2656 if (smu->ppt_funcs->mode1_reset) 2657 ret = smu->ppt_funcs->mode1_reset(smu); 2658 2659 return ret; 2660 } 2661 2662 static int smu_mode2_reset(void *handle) 2663 { 2664 struct smu_context *smu = handle; 2665 int ret = 0; 2666 2667 if (!smu->pm_enabled) 2668 return -EOPNOTSUPP; 2669 2670 if (smu->ppt_funcs->mode2_reset) 2671 ret = smu->ppt_funcs->mode2_reset(smu); 2672 2673 if (ret) 2674 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2675 2676 return ret; 2677 } 2678 2679 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2680 struct pp_smu_nv_clock_table *max_clocks) 2681 { 2682 struct smu_context *smu = handle; 2683 int ret = 0; 2684 2685 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2686 return -EOPNOTSUPP; 2687 2688 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2689 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2690 2691 return ret; 2692 } 2693 2694 static int smu_get_uclk_dpm_states(void *handle, 2695 unsigned int *clock_values_in_khz, 2696 unsigned int *num_states) 2697 { 2698 struct smu_context *smu = handle; 2699 int ret = 0; 2700 2701 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2702 return -EOPNOTSUPP; 2703 2704 if (smu->ppt_funcs->get_uclk_dpm_states) 2705 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2706 2707 return ret; 2708 } 2709 2710 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2711 { 2712 struct smu_context *smu = handle; 2713 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2714 2715 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2716 return -EOPNOTSUPP; 2717 2718 if (smu->ppt_funcs->get_current_power_state) 2719 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2720 2721 return pm_state; 2722 } 2723 2724 static int smu_get_dpm_clock_table(void *handle, 2725 struct dpm_clocks *clock_table) 2726 { 2727 struct smu_context *smu = handle; 2728 int ret = 0; 2729 2730 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2731 return -EOPNOTSUPP; 2732 2733 if (smu->ppt_funcs->get_dpm_clock_table) 2734 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2735 2736 return ret; 2737 } 2738 2739 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2740 { 2741 struct smu_context *smu = handle; 2742 2743 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2744 return -EOPNOTSUPP; 2745 2746 if (!smu->ppt_funcs->get_gpu_metrics) 2747 return -EOPNOTSUPP; 2748 2749 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2750 } 2751 2752 static int smu_enable_mgpu_fan_boost(void *handle) 2753 { 2754 struct smu_context *smu = handle; 2755 int ret = 0; 2756 2757 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2758 return -EOPNOTSUPP; 2759 2760 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2761 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2762 2763 return ret; 2764 } 2765 2766 static int smu_gfx_state_change_set(void *handle, 2767 uint32_t state) 2768 { 2769 struct smu_context *smu = handle; 2770 int ret = 0; 2771 2772 if (smu->ppt_funcs->gfx_state_change_set) 2773 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2774 2775 return ret; 2776 } 2777 2778 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2779 { 2780 int ret = 0; 2781 2782 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2783 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2784 2785 return ret; 2786 } 2787 2788 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2789 { 2790 int ret = -EOPNOTSUPP; 2791 2792 if (smu->ppt_funcs && 2793 smu->ppt_funcs->get_ecc_info) 2794 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2795 2796 return ret; 2797 2798 } 2799 2800 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2801 { 2802 struct smu_context *smu = handle; 2803 struct smu_table_context *smu_table = &smu->smu_table; 2804 struct smu_table *memory_pool = &smu_table->memory_pool; 2805 2806 if (!addr || !size) 2807 return -EINVAL; 2808 2809 *addr = NULL; 2810 *size = 0; 2811 if (memory_pool->bo) { 2812 *addr = memory_pool->cpu_addr; 2813 *size = memory_pool->size; 2814 } 2815 2816 return 0; 2817 } 2818 2819 static const struct amd_pm_funcs swsmu_pm_funcs = { 2820 /* export for sysfs */ 2821 .set_fan_control_mode = smu_set_fan_control_mode, 2822 .get_fan_control_mode = smu_get_fan_control_mode, 2823 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 2824 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 2825 .force_clock_level = smu_force_ppclk_levels, 2826 .print_clock_levels = smu_print_ppclk_levels, 2827 .force_performance_level = smu_force_performance_level, 2828 .read_sensor = smu_read_sensor, 2829 .get_performance_level = smu_get_performance_level, 2830 .get_current_power_state = smu_get_current_power_state, 2831 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 2832 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 2833 .get_pp_num_states = smu_get_power_num_states, 2834 .get_pp_table = smu_sys_get_pp_table, 2835 .set_pp_table = smu_sys_set_pp_table, 2836 .switch_power_profile = smu_switch_power_profile, 2837 /* export to amdgpu */ 2838 .dispatch_tasks = smu_handle_dpm_task, 2839 .load_firmware = smu_load_microcode, 2840 .set_powergating_by_smu = smu_dpm_set_power_gate, 2841 .set_power_limit = smu_set_power_limit, 2842 .get_power_limit = smu_get_power_limit, 2843 .get_power_profile_mode = smu_get_power_profile_mode, 2844 .set_power_profile_mode = smu_set_power_profile_mode, 2845 .odn_edit_dpm_table = smu_od_edit_dpm_table, 2846 .set_mp1_state = smu_set_mp1_state, 2847 .gfx_state_change_set = smu_gfx_state_change_set, 2848 /* export to DC */ 2849 .get_sclk = smu_get_sclk, 2850 .get_mclk = smu_get_mclk, 2851 .display_configuration_change = smu_display_configuration_change, 2852 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 2853 .display_clock_voltage_request = smu_display_clock_voltage_request, 2854 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 2855 .set_active_display_count = smu_set_display_count, 2856 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 2857 .get_asic_baco_capability = smu_get_baco_capability, 2858 .set_asic_baco_state = smu_baco_set_state, 2859 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 2860 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 2861 .asic_reset_mode_2 = smu_mode2_reset, 2862 .set_df_cstate = smu_set_df_cstate, 2863 .set_xgmi_pstate = smu_set_xgmi_pstate, 2864 .get_gpu_metrics = smu_sys_get_gpu_metrics, 2865 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 2866 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 2867 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 2868 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 2869 .get_dpm_clock_table = smu_get_dpm_clock_table, 2870 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 2871 }; 2872 2873 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 2874 uint64_t event_arg) 2875 { 2876 int ret = -EINVAL; 2877 2878 if (smu->ppt_funcs->wait_for_event) 2879 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 2880 2881 return ret; 2882 } 2883 2884 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 2885 { 2886 2887 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 2888 return -EOPNOTSUPP; 2889 2890 /* Confirm the buffer allocated is of correct size */ 2891 if (size != smu->stb_context.stb_buf_size) 2892 return -EINVAL; 2893 2894 /* 2895 * No need to lock smu mutex as we access STB directly through MMIO 2896 * and not going through SMU messaging route (for now at least). 2897 * For registers access rely on implementation internal locking. 2898 */ 2899 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 2900 } 2901 2902 #if defined(CONFIG_DEBUG_FS) 2903 2904 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 2905 { 2906 struct amdgpu_device *adev = filp->f_inode->i_private; 2907 struct smu_context *smu = adev->powerplay.pp_handle; 2908 unsigned char *buf; 2909 int r; 2910 2911 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 2912 if (!buf) 2913 return -ENOMEM; 2914 2915 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 2916 if (r) 2917 goto out; 2918 2919 filp->private_data = buf; 2920 2921 return 0; 2922 2923 out: 2924 kvfree(buf); 2925 return r; 2926 } 2927 2928 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 2929 loff_t *pos) 2930 { 2931 struct amdgpu_device *adev = filp->f_inode->i_private; 2932 struct smu_context *smu = adev->powerplay.pp_handle; 2933 2934 2935 if (!filp->private_data) 2936 return -EINVAL; 2937 2938 return simple_read_from_buffer(buf, 2939 size, 2940 pos, filp->private_data, 2941 smu->stb_context.stb_buf_size); 2942 } 2943 2944 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 2945 { 2946 kvfree(filp->private_data); 2947 filp->private_data = NULL; 2948 2949 return 0; 2950 } 2951 2952 /* 2953 * We have to define not only read method but also 2954 * open and release because .read takes up to PAGE_SIZE 2955 * data each time so and so is invoked multiple times. 2956 * We allocate the STB buffer in .open and release it 2957 * in .release 2958 */ 2959 static const struct file_operations smu_stb_debugfs_fops = { 2960 .owner = THIS_MODULE, 2961 .open = smu_stb_debugfs_open, 2962 .read = smu_stb_debugfs_read, 2963 .release = smu_stb_debugfs_release, 2964 .llseek = default_llseek, 2965 }; 2966 2967 #endif 2968 2969 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 2970 { 2971 #if defined(CONFIG_DEBUG_FS) 2972 2973 struct smu_context *smu = adev->powerplay.pp_handle; 2974 2975 if (!smu->stb_context.stb_buf_size) 2976 return; 2977 2978 debugfs_create_file_size("amdgpu_smu_stb_dump", 2979 S_IRUSR, 2980 adev_to_drm(adev)->primary->debugfs_root, 2981 adev, 2982 &smu_stb_debugfs_fops, 2983 smu->stb_context.stb_buf_size); 2984 #endif 2985 } 2986 2987 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 2988 { 2989 int ret = 0; 2990 2991 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 2992 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 2993 2994 return ret; 2995 } 2996