1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = 0; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 281 dev_WARN(smu->adev->dev, 282 "SMU uninitialized but power %s requested for %u!\n", 283 gate ? "gate" : "ungate", block_type); 284 return -EOPNOTSUPP; 285 } 286 287 switch (block_type) { 288 /* 289 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 290 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 291 */ 292 case AMD_IP_BLOCK_TYPE_UVD: 293 case AMD_IP_BLOCK_TYPE_VCN: 294 ret = smu_dpm_set_vcn_enable(smu, !gate); 295 if (ret) 296 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 297 gate ? "gate" : "ungate"); 298 break; 299 case AMD_IP_BLOCK_TYPE_GFX: 300 ret = smu_gfx_off_control(smu, gate); 301 if (ret) 302 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 303 gate ? "enable" : "disable"); 304 break; 305 case AMD_IP_BLOCK_TYPE_SDMA: 306 ret = smu_powergate_sdma(smu, gate); 307 if (ret) 308 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 309 gate ? "gate" : "ungate"); 310 break; 311 case AMD_IP_BLOCK_TYPE_JPEG: 312 ret = smu_dpm_set_jpeg_enable(smu, !gate); 313 if (ret) 314 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 315 gate ? "gate" : "ungate"); 316 break; 317 default: 318 dev_err(smu->adev->dev, "Unsupported block type!\n"); 319 return -EINVAL; 320 } 321 322 return ret; 323 } 324 325 /** 326 * smu_set_user_clk_dependencies - set user profile clock dependencies 327 * 328 * @smu: smu_context pointer 329 * @clk: enum smu_clk_type type 330 * 331 * Enable/Disable the clock dependency for the @clk type. 332 */ 333 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 334 { 335 if (smu->adev->in_suspend) 336 return; 337 338 if (clk == SMU_MCLK) { 339 smu->user_dpm_profile.clk_dependency = 0; 340 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 341 } else if (clk == SMU_FCLK) { 342 /* MCLK takes precedence over FCLK */ 343 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 344 return; 345 346 smu->user_dpm_profile.clk_dependency = 0; 347 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 348 } else if (clk == SMU_SOCCLK) { 349 /* MCLK takes precedence over SOCCLK */ 350 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 351 return; 352 353 smu->user_dpm_profile.clk_dependency = 0; 354 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 355 } else 356 /* Add clk dependencies here, if any */ 357 return; 358 } 359 360 /** 361 * smu_restore_dpm_user_profile - reinstate user dpm profile 362 * 363 * @smu: smu_context pointer 364 * 365 * Restore the saved user power configurations include power limit, 366 * clock frequencies, fan control mode and fan speed. 367 */ 368 static void smu_restore_dpm_user_profile(struct smu_context *smu) 369 { 370 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 371 int ret = 0; 372 373 if (!smu->adev->in_suspend) 374 return; 375 376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 377 return; 378 379 /* Enable restore flag */ 380 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 381 382 /* set the user dpm power limit */ 383 if (smu->user_dpm_profile.power_limit) { 384 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 385 if (ret) 386 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 387 } 388 389 /* set the user dpm clock configurations */ 390 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 391 enum smu_clk_type clk_type; 392 393 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 394 /* 395 * Iterate over smu clk type and force the saved user clk 396 * configs, skip if clock dependency is enabled 397 */ 398 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 399 smu->user_dpm_profile.clk_mask[clk_type]) { 400 ret = smu_force_smuclk_levels(smu, clk_type, 401 smu->user_dpm_profile.clk_mask[clk_type]); 402 if (ret) 403 dev_err(smu->adev->dev, 404 "Failed to set clock type = %d\n", clk_type); 405 } 406 } 407 } 408 409 /* set the user dpm fan configurations */ 410 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 411 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 412 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 413 if (ret) { 414 smu->user_dpm_profile.fan_speed_pwm = 0; 415 smu->user_dpm_profile.fan_speed_rpm = 0; 416 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 417 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 418 } 419 420 if (smu->user_dpm_profile.fan_speed_pwm) { 421 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 422 if (ret) 423 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 424 } 425 426 if (smu->user_dpm_profile.fan_speed_rpm) { 427 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 428 if (ret) 429 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 430 } 431 } 432 433 /* Restore user customized OD settings */ 434 if (smu->user_dpm_profile.user_od) { 435 if (smu->ppt_funcs->restore_user_od_settings) { 436 ret = smu->ppt_funcs->restore_user_od_settings(smu); 437 if (ret) 438 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 439 } 440 } 441 442 /* Disable restore flag */ 443 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 444 } 445 446 static int smu_get_power_num_states(void *handle, 447 struct pp_states_info *state_info) 448 { 449 if (!state_info) 450 return -EINVAL; 451 452 /* not support power state */ 453 memset(state_info, 0, sizeof(struct pp_states_info)); 454 state_info->nums = 1; 455 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 456 457 return 0; 458 } 459 460 bool is_support_sw_smu(struct amdgpu_device *adev) 461 { 462 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 463 if (adev->asic_type == CHIP_VEGA20) 464 return false; 465 466 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 467 return true; 468 469 return false; 470 } 471 472 bool is_support_cclk_dpm(struct amdgpu_device *adev) 473 { 474 struct smu_context *smu = &adev->smu; 475 476 if (!is_support_sw_smu(adev)) 477 return false; 478 479 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 480 return false; 481 482 return true; 483 } 484 485 486 static int smu_sys_get_pp_table(void *handle, 487 char **table) 488 { 489 struct smu_context *smu = handle; 490 struct smu_table_context *smu_table = &smu->smu_table; 491 uint32_t powerplay_table_size; 492 493 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 494 return -EOPNOTSUPP; 495 496 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 497 return -EINVAL; 498 499 mutex_lock(&smu->mutex); 500 501 if (smu_table->hardcode_pptable) 502 *table = smu_table->hardcode_pptable; 503 else 504 *table = smu_table->power_play_table; 505 506 powerplay_table_size = smu_table->power_play_table_size; 507 508 mutex_unlock(&smu->mutex); 509 510 return powerplay_table_size; 511 } 512 513 static int smu_sys_set_pp_table(void *handle, 514 const char *buf, 515 size_t size) 516 { 517 struct smu_context *smu = handle; 518 struct smu_table_context *smu_table = &smu->smu_table; 519 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 520 int ret = 0; 521 522 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 523 return -EOPNOTSUPP; 524 525 if (header->usStructureSize != size) { 526 dev_err(smu->adev->dev, "pp table size not matched !\n"); 527 return -EIO; 528 } 529 530 mutex_lock(&smu->mutex); 531 if (!smu_table->hardcode_pptable) 532 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 533 if (!smu_table->hardcode_pptable) { 534 ret = -ENOMEM; 535 goto failed; 536 } 537 538 memcpy(smu_table->hardcode_pptable, buf, size); 539 smu_table->power_play_table = smu_table->hardcode_pptable; 540 smu_table->power_play_table_size = size; 541 542 /* 543 * Special hw_fini action(for Navi1x, the DPMs disablement will be 544 * skipped) may be needed for custom pptable uploading. 545 */ 546 smu->uploading_custom_pp_table = true; 547 548 ret = smu_reset(smu); 549 if (ret) 550 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 551 552 smu->uploading_custom_pp_table = false; 553 554 failed: 555 mutex_unlock(&smu->mutex); 556 return ret; 557 } 558 559 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 560 { 561 struct smu_feature *feature = &smu->smu_feature; 562 int ret = 0; 563 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 564 565 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 566 567 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 568 SMU_FEATURE_MAX/32); 569 if (ret) 570 return ret; 571 572 bitmap_or(feature->allowed, feature->allowed, 573 (unsigned long *)allowed_feature_mask, 574 feature->feature_num); 575 576 return ret; 577 } 578 579 static int smu_set_funcs(struct amdgpu_device *adev) 580 { 581 struct smu_context *smu = &adev->smu; 582 583 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 584 smu->od_enabled = true; 585 586 switch (adev->ip_versions[MP1_HWIP][0]) { 587 case IP_VERSION(11, 0, 0): 588 case IP_VERSION(11, 0, 5): 589 case IP_VERSION(11, 0, 9): 590 navi10_set_ppt_funcs(smu); 591 break; 592 case IP_VERSION(11, 0, 7): 593 case IP_VERSION(11, 0, 11): 594 case IP_VERSION(11, 0, 12): 595 case IP_VERSION(11, 0, 13): 596 sienna_cichlid_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(12, 0, 0): 599 case IP_VERSION(12, 0, 1): 600 renoir_set_ppt_funcs(smu); 601 break; 602 case IP_VERSION(11, 5, 0): 603 vangogh_set_ppt_funcs(smu); 604 break; 605 case IP_VERSION(13, 0, 1): 606 case IP_VERSION(13, 0, 3): 607 yellow_carp_set_ppt_funcs(smu); 608 break; 609 case IP_VERSION(11, 0, 8): 610 cyan_skillfish_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(11, 0, 2): 613 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 614 arcturus_set_ppt_funcs(smu); 615 /* OD is not supported on Arcturus */ 616 smu->od_enabled =false; 617 break; 618 case IP_VERSION(13, 0, 2): 619 aldebaran_set_ppt_funcs(smu); 620 /* Enable pp_od_clk_voltage node */ 621 smu->od_enabled = true; 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 static int smu_early_init(void *handle) 631 { 632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633 struct smu_context *smu = &adev->smu; 634 635 smu->adev = adev; 636 smu->pm_enabled = !!amdgpu_dpm; 637 smu->is_apu = false; 638 mutex_init(&smu->mutex); 639 mutex_init(&smu->smu_baco.mutex); 640 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 641 smu->smu_baco.platform_support = false; 642 smu->user_dpm_profile.fan_mode = -1; 643 644 adev->powerplay.pp_handle = smu; 645 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 646 647 return smu_set_funcs(adev); 648 } 649 650 static int smu_set_default_dpm_table(struct smu_context *smu) 651 { 652 struct smu_power_context *smu_power = &smu->smu_power; 653 struct smu_power_gate *power_gate = &smu_power->power_gate; 654 int vcn_gate, jpeg_gate; 655 int ret = 0; 656 657 if (!smu->ppt_funcs->set_default_dpm_table) 658 return 0; 659 660 mutex_lock(&power_gate->vcn_gate_lock); 661 mutex_lock(&power_gate->jpeg_gate_lock); 662 663 vcn_gate = atomic_read(&power_gate->vcn_gated); 664 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 665 666 ret = smu_dpm_set_vcn_enable_locked(smu, true); 667 if (ret) 668 goto err0_out; 669 670 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 671 if (ret) 672 goto err1_out; 673 674 ret = smu->ppt_funcs->set_default_dpm_table(smu); 675 if (ret) 676 dev_err(smu->adev->dev, 677 "Failed to setup default dpm clock tables!\n"); 678 679 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 680 err1_out: 681 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 682 err0_out: 683 mutex_unlock(&power_gate->jpeg_gate_lock); 684 mutex_unlock(&power_gate->vcn_gate_lock); 685 686 return ret; 687 } 688 689 690 static int smu_late_init(void *handle) 691 { 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 struct smu_context *smu = &adev->smu; 694 int ret = 0; 695 696 smu_set_fine_grain_gfx_freq_parameters(smu); 697 698 if (!smu->pm_enabled) 699 return 0; 700 701 ret = smu_post_init(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to post smu init!\n"); 704 return ret; 705 } 706 707 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 708 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 709 return 0; 710 711 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 712 ret = smu_set_default_od_settings(smu); 713 if (ret) { 714 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 715 return ret; 716 } 717 } 718 719 ret = smu_populate_umd_state_clk(smu); 720 if (ret) { 721 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 722 return ret; 723 } 724 725 ret = smu_get_asic_power_limits(smu, 726 &smu->current_power_limit, 727 &smu->default_power_limit, 728 &smu->max_power_limit); 729 if (ret) { 730 dev_err(adev->dev, "Failed to get asic power limits!\n"); 731 return ret; 732 } 733 734 if (!amdgpu_sriov_vf(adev)) 735 smu_get_unique_id(smu); 736 737 smu_get_fan_parameters(smu); 738 739 smu_handle_task(&adev->smu, 740 smu->smu_dpm.dpm_level, 741 AMD_PP_TASK_COMPLETE_INIT, 742 false); 743 744 smu_restore_dpm_user_profile(smu); 745 746 return 0; 747 } 748 749 static int smu_init_fb_allocations(struct smu_context *smu) 750 { 751 struct amdgpu_device *adev = smu->adev; 752 struct smu_table_context *smu_table = &smu->smu_table; 753 struct smu_table *tables = smu_table->tables; 754 struct smu_table *driver_table = &(smu_table->driver_table); 755 uint32_t max_table_size = 0; 756 int ret, i; 757 758 /* VRAM allocation for tool table */ 759 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 760 ret = amdgpu_bo_create_kernel(adev, 761 tables[SMU_TABLE_PMSTATUSLOG].size, 762 tables[SMU_TABLE_PMSTATUSLOG].align, 763 tables[SMU_TABLE_PMSTATUSLOG].domain, 764 &tables[SMU_TABLE_PMSTATUSLOG].bo, 765 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 766 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 767 if (ret) { 768 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 769 return ret; 770 } 771 } 772 773 /* VRAM allocation for driver table */ 774 for (i = 0; i < SMU_TABLE_COUNT; i++) { 775 if (tables[i].size == 0) 776 continue; 777 778 if (i == SMU_TABLE_PMSTATUSLOG) 779 continue; 780 781 if (max_table_size < tables[i].size) 782 max_table_size = tables[i].size; 783 } 784 785 driver_table->size = max_table_size; 786 driver_table->align = PAGE_SIZE; 787 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 788 789 ret = amdgpu_bo_create_kernel(adev, 790 driver_table->size, 791 driver_table->align, 792 driver_table->domain, 793 &driver_table->bo, 794 &driver_table->mc_address, 795 &driver_table->cpu_addr); 796 if (ret) { 797 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 798 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 799 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 800 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 801 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 802 } 803 804 return ret; 805 } 806 807 static int smu_fini_fb_allocations(struct smu_context *smu) 808 { 809 struct smu_table_context *smu_table = &smu->smu_table; 810 struct smu_table *tables = smu_table->tables; 811 struct smu_table *driver_table = &(smu_table->driver_table); 812 813 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 814 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 815 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 816 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 817 818 amdgpu_bo_free_kernel(&driver_table->bo, 819 &driver_table->mc_address, 820 &driver_table->cpu_addr); 821 822 return 0; 823 } 824 825 /** 826 * smu_alloc_memory_pool - allocate memory pool in the system memory 827 * 828 * @smu: amdgpu_device pointer 829 * 830 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 831 * and DramLogSetDramAddr can notify it changed. 832 * 833 * Returns 0 on success, error on failure. 834 */ 835 static int smu_alloc_memory_pool(struct smu_context *smu) 836 { 837 struct amdgpu_device *adev = smu->adev; 838 struct smu_table_context *smu_table = &smu->smu_table; 839 struct smu_table *memory_pool = &smu_table->memory_pool; 840 uint64_t pool_size = smu->pool_size; 841 int ret = 0; 842 843 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 844 return ret; 845 846 memory_pool->size = pool_size; 847 memory_pool->align = PAGE_SIZE; 848 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 849 850 switch (pool_size) { 851 case SMU_MEMORY_POOL_SIZE_256_MB: 852 case SMU_MEMORY_POOL_SIZE_512_MB: 853 case SMU_MEMORY_POOL_SIZE_1_GB: 854 case SMU_MEMORY_POOL_SIZE_2_GB: 855 ret = amdgpu_bo_create_kernel(adev, 856 memory_pool->size, 857 memory_pool->align, 858 memory_pool->domain, 859 &memory_pool->bo, 860 &memory_pool->mc_address, 861 &memory_pool->cpu_addr); 862 if (ret) 863 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 864 break; 865 default: 866 break; 867 } 868 869 return ret; 870 } 871 872 static int smu_free_memory_pool(struct smu_context *smu) 873 { 874 struct smu_table_context *smu_table = &smu->smu_table; 875 struct smu_table *memory_pool = &smu_table->memory_pool; 876 877 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 878 return 0; 879 880 amdgpu_bo_free_kernel(&memory_pool->bo, 881 &memory_pool->mc_address, 882 &memory_pool->cpu_addr); 883 884 memset(memory_pool, 0, sizeof(struct smu_table)); 885 886 return 0; 887 } 888 889 static int smu_alloc_dummy_read_table(struct smu_context *smu) 890 { 891 struct smu_table_context *smu_table = &smu->smu_table; 892 struct smu_table *dummy_read_1_table = 893 &smu_table->dummy_read_1_table; 894 struct amdgpu_device *adev = smu->adev; 895 int ret = 0; 896 897 dummy_read_1_table->size = 0x40000; 898 dummy_read_1_table->align = PAGE_SIZE; 899 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 900 901 ret = amdgpu_bo_create_kernel(adev, 902 dummy_read_1_table->size, 903 dummy_read_1_table->align, 904 dummy_read_1_table->domain, 905 &dummy_read_1_table->bo, 906 &dummy_read_1_table->mc_address, 907 &dummy_read_1_table->cpu_addr); 908 if (ret) 909 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 910 911 return ret; 912 } 913 914 static void smu_free_dummy_read_table(struct smu_context *smu) 915 { 916 struct smu_table_context *smu_table = &smu->smu_table; 917 struct smu_table *dummy_read_1_table = 918 &smu_table->dummy_read_1_table; 919 920 921 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 922 &dummy_read_1_table->mc_address, 923 &dummy_read_1_table->cpu_addr); 924 925 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 926 } 927 928 static int smu_smc_table_sw_init(struct smu_context *smu) 929 { 930 int ret; 931 932 /** 933 * Create smu_table structure, and init smc tables such as 934 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 935 */ 936 ret = smu_init_smc_tables(smu); 937 if (ret) { 938 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 939 return ret; 940 } 941 942 /** 943 * Create smu_power_context structure, and allocate smu_dpm_context and 944 * context size to fill the smu_power_context data. 945 */ 946 ret = smu_init_power(smu); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 949 return ret; 950 } 951 952 /* 953 * allocate vram bos to store smc table contents. 954 */ 955 ret = smu_init_fb_allocations(smu); 956 if (ret) 957 return ret; 958 959 ret = smu_alloc_memory_pool(smu); 960 if (ret) 961 return ret; 962 963 ret = smu_alloc_dummy_read_table(smu); 964 if (ret) 965 return ret; 966 967 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 968 if (ret) 969 return ret; 970 971 return 0; 972 } 973 974 static int smu_smc_table_sw_fini(struct smu_context *smu) 975 { 976 int ret; 977 978 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 979 980 smu_free_dummy_read_table(smu); 981 982 ret = smu_free_memory_pool(smu); 983 if (ret) 984 return ret; 985 986 ret = smu_fini_fb_allocations(smu); 987 if (ret) 988 return ret; 989 990 ret = smu_fini_power(smu); 991 if (ret) { 992 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 993 return ret; 994 } 995 996 ret = smu_fini_smc_tables(smu); 997 if (ret) { 998 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 999 return ret; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static void smu_throttling_logging_work_fn(struct work_struct *work) 1006 { 1007 struct smu_context *smu = container_of(work, struct smu_context, 1008 throttling_logging_work); 1009 1010 smu_log_thermal_throttling(smu); 1011 } 1012 1013 static void smu_interrupt_work_fn(struct work_struct *work) 1014 { 1015 struct smu_context *smu = container_of(work, struct smu_context, 1016 interrupt_work); 1017 1018 mutex_lock(&smu->mutex); 1019 1020 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1021 smu->ppt_funcs->interrupt_work(smu); 1022 1023 mutex_unlock(&smu->mutex); 1024 } 1025 1026 static int smu_sw_init(void *handle) 1027 { 1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1029 struct smu_context *smu = &adev->smu; 1030 int ret; 1031 1032 smu->pool_size = adev->pm.smu_prv_buffer_size; 1033 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1034 mutex_init(&smu->smu_feature.mutex); 1035 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1036 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1037 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1038 1039 mutex_init(&smu->sensor_lock); 1040 mutex_init(&smu->metrics_lock); 1041 mutex_init(&smu->message_lock); 1042 1043 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1044 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1045 atomic64_set(&smu->throttle_int_counter, 0); 1046 smu->watermarks_bitmap = 0; 1047 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1048 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1049 1050 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1051 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1052 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1053 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1054 1055 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1056 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1057 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1058 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1059 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1060 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1061 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1062 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1063 1064 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1065 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1066 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1067 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1068 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1069 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1070 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1071 smu->display_config = &adev->pm.pm_display_cfg; 1072 1073 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1074 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1075 1076 ret = smu_init_microcode(smu); 1077 if (ret) { 1078 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1079 return ret; 1080 } 1081 1082 ret = smu_smc_table_sw_init(smu); 1083 if (ret) { 1084 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1085 return ret; 1086 } 1087 1088 ret = smu_register_irq_handler(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1091 return ret; 1092 } 1093 1094 /* If there is no way to query fan control mode, fan control is not supported */ 1095 if (!smu->ppt_funcs->get_fan_control_mode) 1096 smu->adev->pm.no_fan = true; 1097 1098 return 0; 1099 } 1100 1101 static int smu_sw_fini(void *handle) 1102 { 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1104 struct smu_context *smu = &adev->smu; 1105 int ret; 1106 1107 ret = smu_smc_table_sw_fini(smu); 1108 if (ret) { 1109 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1110 return ret; 1111 } 1112 1113 smu_fini_microcode(smu); 1114 1115 return 0; 1116 } 1117 1118 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1119 { 1120 struct amdgpu_device *adev = smu->adev; 1121 struct smu_temperature_range *range = 1122 &smu->thermal_range; 1123 int ret = 0; 1124 1125 if (!smu->ppt_funcs->get_thermal_temperature_range) 1126 return 0; 1127 1128 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1129 if (ret) 1130 return ret; 1131 1132 adev->pm.dpm.thermal.min_temp = range->min; 1133 adev->pm.dpm.thermal.max_temp = range->max; 1134 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1135 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1136 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1137 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1138 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1139 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1140 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1141 1142 return ret; 1143 } 1144 1145 static int smu_smc_hw_setup(struct smu_context *smu) 1146 { 1147 struct amdgpu_device *adev = smu->adev; 1148 uint32_t pcie_gen = 0, pcie_width = 0; 1149 int ret = 0; 1150 1151 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1152 dev_info(adev->dev, "dpm has been enabled\n"); 1153 /* this is needed specifically */ 1154 switch (adev->ip_versions[MP1_HWIP][0]) { 1155 case IP_VERSION(11, 0, 7): 1156 case IP_VERSION(11, 0, 11): 1157 case IP_VERSION(11, 5, 0): 1158 case IP_VERSION(11, 0, 12): 1159 ret = smu_system_features_control(smu, true); 1160 if (ret) 1161 dev_err(adev->dev, "Failed system features control!\n"); 1162 break; 1163 default: 1164 break; 1165 } 1166 return ret; 1167 } 1168 1169 ret = smu_init_display_count(smu, 0); 1170 if (ret) { 1171 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1172 return ret; 1173 } 1174 1175 ret = smu_set_driver_table_location(smu); 1176 if (ret) { 1177 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1178 return ret; 1179 } 1180 1181 /* 1182 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1183 */ 1184 ret = smu_set_tool_table_location(smu); 1185 if (ret) { 1186 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1187 return ret; 1188 } 1189 1190 /* 1191 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1192 * pool location. 1193 */ 1194 ret = smu_notify_memory_pool_location(smu); 1195 if (ret) { 1196 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1197 return ret; 1198 } 1199 1200 /* smu_dump_pptable(smu); */ 1201 /* 1202 * Copy pptable bo in the vram to smc with SMU MSGs such as 1203 * SetDriverDramAddr and TransferTableDram2Smu. 1204 */ 1205 ret = smu_write_pptable(smu); 1206 if (ret) { 1207 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1208 return ret; 1209 } 1210 1211 /* issue Run*Btc msg */ 1212 ret = smu_run_btc(smu); 1213 if (ret) 1214 return ret; 1215 1216 ret = smu_feature_set_allowed_mask(smu); 1217 if (ret) { 1218 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1219 return ret; 1220 } 1221 1222 ret = smu_system_features_control(smu, true); 1223 if (ret) { 1224 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1225 return ret; 1226 } 1227 1228 if (!smu_is_dpm_running(smu)) 1229 dev_info(adev->dev, "dpm has been disabled\n"); 1230 1231 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1232 pcie_gen = 3; 1233 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1234 pcie_gen = 2; 1235 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1236 pcie_gen = 1; 1237 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1238 pcie_gen = 0; 1239 1240 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1241 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1242 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1243 */ 1244 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1245 pcie_width = 6; 1246 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1247 pcie_width = 5; 1248 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1249 pcie_width = 4; 1250 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1251 pcie_width = 3; 1252 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1253 pcie_width = 2; 1254 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1255 pcie_width = 1; 1256 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1257 if (ret) { 1258 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1259 return ret; 1260 } 1261 1262 ret = smu_get_thermal_temperature_range(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1265 return ret; 1266 } 1267 1268 ret = smu_enable_thermal_alert(smu); 1269 if (ret) { 1270 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1271 return ret; 1272 } 1273 1274 /* 1275 * Set initialized values (get from vbios) to dpm tables context such as 1276 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1277 * type of clks. 1278 */ 1279 ret = smu_set_default_dpm_table(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1282 return ret; 1283 } 1284 1285 ret = smu_notify_display_change(smu); 1286 if (ret) { 1287 dev_err(adev->dev, "Failed to notify display change!\n"); 1288 return ret; 1289 } 1290 1291 /* 1292 * Set min deep sleep dce fclk with bootup value from vbios via 1293 * SetMinDeepSleepDcefclk MSG. 1294 */ 1295 ret = smu_set_min_dcef_deep_sleep(smu, 1296 smu->smu_table.boot_values.dcefclk / 100); 1297 1298 return ret; 1299 } 1300 1301 static int smu_start_smc_engine(struct smu_context *smu) 1302 { 1303 struct amdgpu_device *adev = smu->adev; 1304 int ret = 0; 1305 1306 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1307 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1308 if (smu->ppt_funcs->load_microcode) { 1309 ret = smu->ppt_funcs->load_microcode(smu); 1310 if (ret) 1311 return ret; 1312 } 1313 } 1314 } 1315 1316 if (smu->ppt_funcs->check_fw_status) { 1317 ret = smu->ppt_funcs->check_fw_status(smu); 1318 if (ret) { 1319 dev_err(adev->dev, "SMC is not ready\n"); 1320 return ret; 1321 } 1322 } 1323 1324 /* 1325 * Send msg GetDriverIfVersion to check if the return value is equal 1326 * with DRIVER_IF_VERSION of smc header. 1327 */ 1328 ret = smu_check_fw_version(smu); 1329 if (ret) 1330 return ret; 1331 1332 return ret; 1333 } 1334 1335 static int smu_hw_init(void *handle) 1336 { 1337 int ret; 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 struct smu_context *smu = &adev->smu; 1340 1341 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1342 smu->pm_enabled = false; 1343 return 0; 1344 } 1345 1346 ret = smu_start_smc_engine(smu); 1347 if (ret) { 1348 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1349 return ret; 1350 } 1351 1352 if (smu->is_apu) { 1353 smu_powergate_sdma(&adev->smu, false); 1354 smu_dpm_set_vcn_enable(smu, true); 1355 smu_dpm_set_jpeg_enable(smu, true); 1356 smu_set_gfx_cgpg(&adev->smu, true); 1357 } 1358 1359 if (!smu->pm_enabled) 1360 return 0; 1361 1362 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1363 ret = smu_get_vbios_bootup_values(smu); 1364 if (ret) { 1365 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1366 return ret; 1367 } 1368 1369 ret = smu_setup_pptable(smu); 1370 if (ret) { 1371 dev_err(adev->dev, "Failed to setup pptable!\n"); 1372 return ret; 1373 } 1374 1375 ret = smu_get_driver_allowed_feature_mask(smu); 1376 if (ret) 1377 return ret; 1378 1379 ret = smu_smc_hw_setup(smu); 1380 if (ret) { 1381 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1382 return ret; 1383 } 1384 1385 /* 1386 * Move maximum sustainable clock retrieving here considering 1387 * 1. It is not needed on resume(from S3). 1388 * 2. DAL settings come between .hw_init and .late_init of SMU. 1389 * And DAL needs to know the maximum sustainable clocks. Thus 1390 * it cannot be put in .late_init(). 1391 */ 1392 ret = smu_init_max_sustainable_clocks(smu); 1393 if (ret) { 1394 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1395 return ret; 1396 } 1397 1398 adev->pm.dpm_enabled = true; 1399 1400 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1401 1402 return 0; 1403 } 1404 1405 static int smu_disable_dpms(struct smu_context *smu) 1406 { 1407 struct amdgpu_device *adev = smu->adev; 1408 int ret = 0; 1409 bool use_baco = !smu->is_apu && 1410 ((amdgpu_in_reset(adev) && 1411 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1412 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1413 1414 /* 1415 * For custom pptable uploading, skip the DPM features 1416 * disable process on Navi1x ASICs. 1417 * - As the gfx related features are under control of 1418 * RLC on those ASICs. RLC reinitialization will be 1419 * needed to reenable them. That will cost much more 1420 * efforts. 1421 * 1422 * - SMU firmware can handle the DPM reenablement 1423 * properly. 1424 */ 1425 if (smu->uploading_custom_pp_table) { 1426 switch (adev->ip_versions[MP1_HWIP][0]) { 1427 case IP_VERSION(11, 0, 0): 1428 case IP_VERSION(11, 0, 5): 1429 case IP_VERSION(11, 0, 9): 1430 case IP_VERSION(11, 0, 7): 1431 case IP_VERSION(11, 0, 11): 1432 case IP_VERSION(11, 5, 0): 1433 case IP_VERSION(11, 0, 12): 1434 case IP_VERSION(11, 0, 13): 1435 return smu_disable_all_features_with_exception(smu, 1436 true, 1437 SMU_FEATURE_COUNT); 1438 default: 1439 break; 1440 } 1441 } 1442 1443 /* 1444 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1445 * on BACO in. Driver involvement is unnecessary. 1446 */ 1447 if (use_baco) { 1448 switch (adev->ip_versions[MP1_HWIP][0]) { 1449 case IP_VERSION(11, 0, 7): 1450 case IP_VERSION(11, 0, 0): 1451 case IP_VERSION(11, 0, 5): 1452 case IP_VERSION(11, 0, 9): 1453 return smu_disable_all_features_with_exception(smu, 1454 true, 1455 SMU_FEATURE_BACO_BIT); 1456 default: 1457 break; 1458 } 1459 } 1460 1461 /* 1462 * For gpu reset, runpm and hibernation through BACO, 1463 * BACO feature has to be kept enabled. 1464 */ 1465 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1466 ret = smu_disable_all_features_with_exception(smu, 1467 false, 1468 SMU_FEATURE_BACO_BIT); 1469 if (ret) 1470 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1471 } else { 1472 ret = smu_system_features_control(smu, false); 1473 if (ret) 1474 dev_err(adev->dev, "Failed to disable smu features.\n"); 1475 } 1476 1477 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1478 adev->gfx.rlc.funcs->stop) 1479 adev->gfx.rlc.funcs->stop(adev); 1480 1481 return ret; 1482 } 1483 1484 static int smu_smc_hw_cleanup(struct smu_context *smu) 1485 { 1486 struct amdgpu_device *adev = smu->adev; 1487 int ret = 0; 1488 1489 cancel_work_sync(&smu->throttling_logging_work); 1490 cancel_work_sync(&smu->interrupt_work); 1491 1492 ret = smu_disable_thermal_alert(smu); 1493 if (ret) { 1494 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1495 return ret; 1496 } 1497 1498 ret = smu_disable_dpms(smu); 1499 if (ret) { 1500 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1501 return ret; 1502 } 1503 1504 return 0; 1505 } 1506 1507 static int smu_hw_fini(void *handle) 1508 { 1509 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1510 struct smu_context *smu = &adev->smu; 1511 1512 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1513 return 0; 1514 1515 if (smu->is_apu) { 1516 smu_powergate_sdma(&adev->smu, true); 1517 } 1518 1519 smu_dpm_set_vcn_enable(smu, false); 1520 smu_dpm_set_jpeg_enable(smu, false); 1521 1522 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1523 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1524 1525 if (!smu->pm_enabled) 1526 return 0; 1527 1528 adev->pm.dpm_enabled = false; 1529 1530 return smu_smc_hw_cleanup(smu); 1531 } 1532 1533 static int smu_reset(struct smu_context *smu) 1534 { 1535 struct amdgpu_device *adev = smu->adev; 1536 int ret; 1537 1538 amdgpu_gfx_off_ctrl(smu->adev, false); 1539 1540 ret = smu_hw_fini(adev); 1541 if (ret) 1542 return ret; 1543 1544 ret = smu_hw_init(adev); 1545 if (ret) 1546 return ret; 1547 1548 ret = smu_late_init(adev); 1549 if (ret) 1550 return ret; 1551 1552 amdgpu_gfx_off_ctrl(smu->adev, true); 1553 1554 return 0; 1555 } 1556 1557 static int smu_suspend(void *handle) 1558 { 1559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1560 struct smu_context *smu = &adev->smu; 1561 int ret; 1562 1563 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1564 return 0; 1565 1566 if (!smu->pm_enabled) 1567 return 0; 1568 1569 adev->pm.dpm_enabled = false; 1570 1571 ret = smu_smc_hw_cleanup(smu); 1572 if (ret) 1573 return ret; 1574 1575 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1576 1577 /* skip CGPG when in S0ix */ 1578 if (smu->is_apu && !adev->in_s0ix) 1579 smu_set_gfx_cgpg(&adev->smu, false); 1580 1581 return 0; 1582 } 1583 1584 static int smu_resume(void *handle) 1585 { 1586 int ret; 1587 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1588 struct smu_context *smu = &adev->smu; 1589 1590 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1591 return 0; 1592 1593 if (!smu->pm_enabled) 1594 return 0; 1595 1596 dev_info(adev->dev, "SMU is resuming...\n"); 1597 1598 ret = smu_start_smc_engine(smu); 1599 if (ret) { 1600 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1601 return ret; 1602 } 1603 1604 ret = smu_smc_hw_setup(smu); 1605 if (ret) { 1606 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1607 return ret; 1608 } 1609 1610 if (smu->is_apu) 1611 smu_set_gfx_cgpg(&adev->smu, true); 1612 1613 smu->disable_uclk_switch = 0; 1614 1615 adev->pm.dpm_enabled = true; 1616 1617 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1618 1619 return 0; 1620 } 1621 1622 static int smu_display_configuration_change(void *handle, 1623 const struct amd_pp_display_configuration *display_config) 1624 { 1625 struct smu_context *smu = handle; 1626 int index = 0; 1627 int num_of_active_display = 0; 1628 1629 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1630 return -EOPNOTSUPP; 1631 1632 if (!display_config) 1633 return -EINVAL; 1634 1635 mutex_lock(&smu->mutex); 1636 1637 smu_set_min_dcef_deep_sleep(smu, 1638 display_config->min_dcef_deep_sleep_set_clk / 100); 1639 1640 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1641 if (display_config->displays[index].controller_id != 0) 1642 num_of_active_display++; 1643 } 1644 1645 mutex_unlock(&smu->mutex); 1646 1647 return 0; 1648 } 1649 1650 static int smu_set_clockgating_state(void *handle, 1651 enum amd_clockgating_state state) 1652 { 1653 return 0; 1654 } 1655 1656 static int smu_set_powergating_state(void *handle, 1657 enum amd_powergating_state state) 1658 { 1659 return 0; 1660 } 1661 1662 static int smu_enable_umd_pstate(void *handle, 1663 enum amd_dpm_forced_level *level) 1664 { 1665 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1666 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1667 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1668 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1669 1670 struct smu_context *smu = (struct smu_context*)(handle); 1671 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1672 1673 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1674 return -EINVAL; 1675 1676 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1677 /* enter umd pstate, save current level, disable gfx cg*/ 1678 if (*level & profile_mode_mask) { 1679 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1680 smu_dpm_ctx->enable_umd_pstate = true; 1681 smu_gpo_control(smu, false); 1682 amdgpu_device_ip_set_powergating_state(smu->adev, 1683 AMD_IP_BLOCK_TYPE_GFX, 1684 AMD_PG_STATE_UNGATE); 1685 amdgpu_device_ip_set_clockgating_state(smu->adev, 1686 AMD_IP_BLOCK_TYPE_GFX, 1687 AMD_CG_STATE_UNGATE); 1688 smu_gfx_ulv_control(smu, false); 1689 smu_deep_sleep_control(smu, false); 1690 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1691 } 1692 } else { 1693 /* exit umd pstate, restore level, enable gfx cg*/ 1694 if (!(*level & profile_mode_mask)) { 1695 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1696 *level = smu_dpm_ctx->saved_dpm_level; 1697 smu_dpm_ctx->enable_umd_pstate = false; 1698 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1699 smu_deep_sleep_control(smu, true); 1700 smu_gfx_ulv_control(smu, true); 1701 amdgpu_device_ip_set_clockgating_state(smu->adev, 1702 AMD_IP_BLOCK_TYPE_GFX, 1703 AMD_CG_STATE_GATE); 1704 amdgpu_device_ip_set_powergating_state(smu->adev, 1705 AMD_IP_BLOCK_TYPE_GFX, 1706 AMD_PG_STATE_GATE); 1707 smu_gpo_control(smu, true); 1708 } 1709 } 1710 1711 return 0; 1712 } 1713 1714 static int smu_bump_power_profile_mode(struct smu_context *smu, 1715 long *param, 1716 uint32_t param_size) 1717 { 1718 int ret = 0; 1719 1720 if (smu->ppt_funcs->set_power_profile_mode) 1721 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1722 1723 return ret; 1724 } 1725 1726 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1727 enum amd_dpm_forced_level level, 1728 bool skip_display_settings) 1729 { 1730 int ret = 0; 1731 int index = 0; 1732 long workload; 1733 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1734 1735 if (!skip_display_settings) { 1736 ret = smu_display_config_changed(smu); 1737 if (ret) { 1738 dev_err(smu->adev->dev, "Failed to change display config!"); 1739 return ret; 1740 } 1741 } 1742 1743 ret = smu_apply_clocks_adjust_rules(smu); 1744 if (ret) { 1745 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1746 return ret; 1747 } 1748 1749 if (!skip_display_settings) { 1750 ret = smu_notify_smc_display_config(smu); 1751 if (ret) { 1752 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1753 return ret; 1754 } 1755 } 1756 1757 if (smu_dpm_ctx->dpm_level != level) { 1758 ret = smu_asic_set_performance_level(smu, level); 1759 if (ret) { 1760 dev_err(smu->adev->dev, "Failed to set performance level!"); 1761 return ret; 1762 } 1763 1764 /* update the saved copy */ 1765 smu_dpm_ctx->dpm_level = level; 1766 } 1767 1768 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1769 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1770 index = fls(smu->workload_mask); 1771 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1772 workload = smu->workload_setting[index]; 1773 1774 if (smu->power_profile_mode != workload) 1775 smu_bump_power_profile_mode(smu, &workload, 0); 1776 } 1777 1778 return ret; 1779 } 1780 1781 static int smu_handle_task(struct smu_context *smu, 1782 enum amd_dpm_forced_level level, 1783 enum amd_pp_task task_id, 1784 bool lock_needed) 1785 { 1786 int ret = 0; 1787 1788 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1789 return -EOPNOTSUPP; 1790 1791 if (lock_needed) 1792 mutex_lock(&smu->mutex); 1793 1794 switch (task_id) { 1795 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1796 ret = smu_pre_display_config_changed(smu); 1797 if (ret) 1798 goto out; 1799 ret = smu_adjust_power_state_dynamic(smu, level, false); 1800 break; 1801 case AMD_PP_TASK_COMPLETE_INIT: 1802 case AMD_PP_TASK_READJUST_POWER_STATE: 1803 ret = smu_adjust_power_state_dynamic(smu, level, true); 1804 break; 1805 default: 1806 break; 1807 } 1808 1809 out: 1810 if (lock_needed) 1811 mutex_unlock(&smu->mutex); 1812 1813 return ret; 1814 } 1815 1816 static int smu_handle_dpm_task(void *handle, 1817 enum amd_pp_task task_id, 1818 enum amd_pm_state_type *user_state) 1819 { 1820 struct smu_context *smu = handle; 1821 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1822 1823 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1824 1825 } 1826 1827 static int smu_switch_power_profile(void *handle, 1828 enum PP_SMC_POWER_PROFILE type, 1829 bool en) 1830 { 1831 struct smu_context *smu = handle; 1832 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1833 long workload; 1834 uint32_t index; 1835 1836 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1837 return -EOPNOTSUPP; 1838 1839 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1840 return -EINVAL; 1841 1842 mutex_lock(&smu->mutex); 1843 1844 if (!en) { 1845 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1846 index = fls(smu->workload_mask); 1847 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1848 workload = smu->workload_setting[index]; 1849 } else { 1850 smu->workload_mask |= (1 << smu->workload_prority[type]); 1851 index = fls(smu->workload_mask); 1852 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1853 workload = smu->workload_setting[index]; 1854 } 1855 1856 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1857 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1858 smu_bump_power_profile_mode(smu, &workload, 0); 1859 1860 mutex_unlock(&smu->mutex); 1861 1862 return 0; 1863 } 1864 1865 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1866 { 1867 struct smu_context *smu = handle; 1868 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1869 enum amd_dpm_forced_level level; 1870 1871 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1872 return -EOPNOTSUPP; 1873 1874 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1875 return -EINVAL; 1876 1877 mutex_lock(&(smu->mutex)); 1878 level = smu_dpm_ctx->dpm_level; 1879 mutex_unlock(&(smu->mutex)); 1880 1881 return level; 1882 } 1883 1884 static int smu_force_performance_level(void *handle, 1885 enum amd_dpm_forced_level level) 1886 { 1887 struct smu_context *smu = handle; 1888 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1889 int ret = 0; 1890 1891 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1892 return -EOPNOTSUPP; 1893 1894 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1895 return -EINVAL; 1896 1897 mutex_lock(&smu->mutex); 1898 1899 ret = smu_enable_umd_pstate(smu, &level); 1900 if (ret) { 1901 mutex_unlock(&smu->mutex); 1902 return ret; 1903 } 1904 1905 ret = smu_handle_task(smu, level, 1906 AMD_PP_TASK_READJUST_POWER_STATE, 1907 false); 1908 1909 mutex_unlock(&smu->mutex); 1910 1911 /* reset user dpm clock state */ 1912 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1913 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1914 smu->user_dpm_profile.clk_dependency = 0; 1915 } 1916 1917 return ret; 1918 } 1919 1920 static int smu_set_display_count(void *handle, uint32_t count) 1921 { 1922 struct smu_context *smu = handle; 1923 int ret = 0; 1924 1925 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1926 return -EOPNOTSUPP; 1927 1928 mutex_lock(&smu->mutex); 1929 ret = smu_init_display_count(smu, count); 1930 mutex_unlock(&smu->mutex); 1931 1932 return ret; 1933 } 1934 1935 static int smu_force_smuclk_levels(struct smu_context *smu, 1936 enum smu_clk_type clk_type, 1937 uint32_t mask) 1938 { 1939 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1940 int ret = 0; 1941 1942 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1943 return -EOPNOTSUPP; 1944 1945 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1946 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1947 return -EINVAL; 1948 } 1949 1950 mutex_lock(&smu->mutex); 1951 1952 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1953 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1954 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1955 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1956 smu_set_user_clk_dependencies(smu, clk_type); 1957 } 1958 } 1959 1960 mutex_unlock(&smu->mutex); 1961 1962 return ret; 1963 } 1964 1965 static int smu_force_ppclk_levels(void *handle, 1966 enum pp_clock_type type, 1967 uint32_t mask) 1968 { 1969 struct smu_context *smu = handle; 1970 enum smu_clk_type clk_type; 1971 1972 switch (type) { 1973 case PP_SCLK: 1974 clk_type = SMU_SCLK; break; 1975 case PP_MCLK: 1976 clk_type = SMU_MCLK; break; 1977 case PP_PCIE: 1978 clk_type = SMU_PCIE; break; 1979 case PP_SOCCLK: 1980 clk_type = SMU_SOCCLK; break; 1981 case PP_FCLK: 1982 clk_type = SMU_FCLK; break; 1983 case PP_DCEFCLK: 1984 clk_type = SMU_DCEFCLK; break; 1985 case PP_VCLK: 1986 clk_type = SMU_VCLK; break; 1987 case PP_DCLK: 1988 clk_type = SMU_DCLK; break; 1989 case OD_SCLK: 1990 clk_type = SMU_OD_SCLK; break; 1991 case OD_MCLK: 1992 clk_type = SMU_OD_MCLK; break; 1993 case OD_VDDC_CURVE: 1994 clk_type = SMU_OD_VDDC_CURVE; break; 1995 case OD_RANGE: 1996 clk_type = SMU_OD_RANGE; break; 1997 default: 1998 return -EINVAL; 1999 } 2000 2001 return smu_force_smuclk_levels(smu, clk_type, mask); 2002 } 2003 2004 /* 2005 * On system suspending or resetting, the dpm_enabled 2006 * flag will be cleared. So that those SMU services which 2007 * are not supported will be gated. 2008 * However, the mp1 state setting should still be granted 2009 * even if the dpm_enabled cleared. 2010 */ 2011 static int smu_set_mp1_state(void *handle, 2012 enum pp_mp1_state mp1_state) 2013 { 2014 struct smu_context *smu = handle; 2015 int ret = 0; 2016 2017 if (!smu->pm_enabled) 2018 return -EOPNOTSUPP; 2019 2020 mutex_lock(&smu->mutex); 2021 2022 if (smu->ppt_funcs && 2023 smu->ppt_funcs->set_mp1_state) 2024 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2025 2026 mutex_unlock(&smu->mutex); 2027 2028 return ret; 2029 } 2030 2031 static int smu_set_df_cstate(void *handle, 2032 enum pp_df_cstate state) 2033 { 2034 struct smu_context *smu = handle; 2035 int ret = 0; 2036 2037 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2038 return -EOPNOTSUPP; 2039 2040 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2041 return 0; 2042 2043 mutex_lock(&smu->mutex); 2044 2045 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2046 if (ret) 2047 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2048 2049 mutex_unlock(&smu->mutex); 2050 2051 return ret; 2052 } 2053 2054 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2055 { 2056 int ret = 0; 2057 2058 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2059 return -EOPNOTSUPP; 2060 2061 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2062 return 0; 2063 2064 mutex_lock(&smu->mutex); 2065 2066 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2067 if (ret) 2068 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2069 2070 mutex_unlock(&smu->mutex); 2071 2072 return ret; 2073 } 2074 2075 int smu_write_watermarks_table(struct smu_context *smu) 2076 { 2077 int ret = 0; 2078 2079 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2080 return -EOPNOTSUPP; 2081 2082 mutex_lock(&smu->mutex); 2083 2084 ret = smu_set_watermarks_table(smu, NULL); 2085 2086 mutex_unlock(&smu->mutex); 2087 2088 return ret; 2089 } 2090 2091 static int smu_set_watermarks_for_clock_ranges(void *handle, 2092 struct pp_smu_wm_range_sets *clock_ranges) 2093 { 2094 struct smu_context *smu = handle; 2095 int ret = 0; 2096 2097 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2098 return -EOPNOTSUPP; 2099 2100 if (smu->disable_watermark) 2101 return 0; 2102 2103 mutex_lock(&smu->mutex); 2104 2105 ret = smu_set_watermarks_table(smu, clock_ranges); 2106 2107 mutex_unlock(&smu->mutex); 2108 2109 return ret; 2110 } 2111 2112 int smu_set_ac_dc(struct smu_context *smu) 2113 { 2114 int ret = 0; 2115 2116 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2117 return -EOPNOTSUPP; 2118 2119 /* controlled by firmware */ 2120 if (smu->dc_controlled_by_gpio) 2121 return 0; 2122 2123 mutex_lock(&smu->mutex); 2124 ret = smu_set_power_source(smu, 2125 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2126 SMU_POWER_SOURCE_DC); 2127 if (ret) 2128 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2129 smu->adev->pm.ac_power ? "AC" : "DC"); 2130 mutex_unlock(&smu->mutex); 2131 2132 return ret; 2133 } 2134 2135 const struct amd_ip_funcs smu_ip_funcs = { 2136 .name = "smu", 2137 .early_init = smu_early_init, 2138 .late_init = smu_late_init, 2139 .sw_init = smu_sw_init, 2140 .sw_fini = smu_sw_fini, 2141 .hw_init = smu_hw_init, 2142 .hw_fini = smu_hw_fini, 2143 .suspend = smu_suspend, 2144 .resume = smu_resume, 2145 .is_idle = NULL, 2146 .check_soft_reset = NULL, 2147 .wait_for_idle = NULL, 2148 .soft_reset = NULL, 2149 .set_clockgating_state = smu_set_clockgating_state, 2150 .set_powergating_state = smu_set_powergating_state, 2151 .enable_umd_pstate = smu_enable_umd_pstate, 2152 }; 2153 2154 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2155 { 2156 .type = AMD_IP_BLOCK_TYPE_SMC, 2157 .major = 11, 2158 .minor = 0, 2159 .rev = 0, 2160 .funcs = &smu_ip_funcs, 2161 }; 2162 2163 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2164 { 2165 .type = AMD_IP_BLOCK_TYPE_SMC, 2166 .major = 12, 2167 .minor = 0, 2168 .rev = 0, 2169 .funcs = &smu_ip_funcs, 2170 }; 2171 2172 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2173 { 2174 .type = AMD_IP_BLOCK_TYPE_SMC, 2175 .major = 13, 2176 .minor = 0, 2177 .rev = 0, 2178 .funcs = &smu_ip_funcs, 2179 }; 2180 2181 static int smu_load_microcode(void *handle) 2182 { 2183 struct smu_context *smu = handle; 2184 struct amdgpu_device *adev = smu->adev; 2185 int ret = 0; 2186 2187 if (!smu->pm_enabled) 2188 return -EOPNOTSUPP; 2189 2190 /* This should be used for non PSP loading */ 2191 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2192 return 0; 2193 2194 if (smu->ppt_funcs->load_microcode) { 2195 ret = smu->ppt_funcs->load_microcode(smu); 2196 if (ret) { 2197 dev_err(adev->dev, "Load microcode failed\n"); 2198 return ret; 2199 } 2200 } 2201 2202 if (smu->ppt_funcs->check_fw_status) { 2203 ret = smu->ppt_funcs->check_fw_status(smu); 2204 if (ret) { 2205 dev_err(adev->dev, "SMC is not ready\n"); 2206 return ret; 2207 } 2208 } 2209 2210 return ret; 2211 } 2212 2213 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2214 { 2215 int ret = 0; 2216 2217 mutex_lock(&smu->mutex); 2218 2219 if (smu->ppt_funcs->set_gfx_cgpg) 2220 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2221 2222 mutex_unlock(&smu->mutex); 2223 2224 return ret; 2225 } 2226 2227 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2228 { 2229 struct smu_context *smu = handle; 2230 int ret = 0; 2231 2232 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2233 return -EOPNOTSUPP; 2234 2235 mutex_lock(&smu->mutex); 2236 2237 if (smu->ppt_funcs->set_fan_speed_rpm) { 2238 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2239 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2240 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2241 smu->user_dpm_profile.fan_speed_rpm = speed; 2242 2243 /* Override custom PWM setting as they cannot co-exist */ 2244 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2245 smu->user_dpm_profile.fan_speed_pwm = 0; 2246 } 2247 } 2248 2249 mutex_unlock(&smu->mutex); 2250 2251 return ret; 2252 } 2253 2254 /** 2255 * smu_get_power_limit - Request one of the SMU Power Limits 2256 * 2257 * @handle: pointer to smu context 2258 * @limit: requested limit is written back to this variable 2259 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2260 * @pp_power_type: &pp_power_type type of power 2261 * Return: 0 on success, <0 on error 2262 * 2263 */ 2264 int smu_get_power_limit(void *handle, 2265 uint32_t *limit, 2266 enum pp_power_limit_level pp_limit_level, 2267 enum pp_power_type pp_power_type) 2268 { 2269 struct smu_context *smu = handle; 2270 struct amdgpu_device *adev = smu->adev; 2271 enum smu_ppt_limit_level limit_level; 2272 uint32_t limit_type; 2273 int ret = 0; 2274 2275 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2276 return -EOPNOTSUPP; 2277 2278 switch(pp_power_type) { 2279 case PP_PWR_TYPE_SUSTAINED: 2280 limit_type = SMU_DEFAULT_PPT_LIMIT; 2281 break; 2282 case PP_PWR_TYPE_FAST: 2283 limit_type = SMU_FAST_PPT_LIMIT; 2284 break; 2285 default: 2286 return -EOPNOTSUPP; 2287 break; 2288 } 2289 2290 switch(pp_limit_level){ 2291 case PP_PWR_LIMIT_CURRENT: 2292 limit_level = SMU_PPT_LIMIT_CURRENT; 2293 break; 2294 case PP_PWR_LIMIT_DEFAULT: 2295 limit_level = SMU_PPT_LIMIT_DEFAULT; 2296 break; 2297 case PP_PWR_LIMIT_MAX: 2298 limit_level = SMU_PPT_LIMIT_MAX; 2299 break; 2300 case PP_PWR_LIMIT_MIN: 2301 default: 2302 return -EOPNOTSUPP; 2303 break; 2304 } 2305 2306 mutex_lock(&smu->mutex); 2307 2308 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2309 if (smu->ppt_funcs->get_ppt_limit) 2310 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2311 } else { 2312 switch (limit_level) { 2313 case SMU_PPT_LIMIT_CURRENT: 2314 switch (adev->ip_versions[MP1_HWIP][0]) { 2315 case IP_VERSION(13, 0, 2): 2316 case IP_VERSION(11, 0, 7): 2317 case IP_VERSION(11, 0, 11): 2318 case IP_VERSION(11, 0, 12): 2319 case IP_VERSION(11, 0, 13): 2320 ret = smu_get_asic_power_limits(smu, 2321 &smu->current_power_limit, 2322 NULL, 2323 NULL); 2324 break; 2325 default: 2326 break; 2327 } 2328 *limit = smu->current_power_limit; 2329 break; 2330 case SMU_PPT_LIMIT_DEFAULT: 2331 *limit = smu->default_power_limit; 2332 break; 2333 case SMU_PPT_LIMIT_MAX: 2334 *limit = smu->max_power_limit; 2335 break; 2336 default: 2337 break; 2338 } 2339 } 2340 2341 mutex_unlock(&smu->mutex); 2342 2343 return ret; 2344 } 2345 2346 static int smu_set_power_limit(void *handle, uint32_t limit) 2347 { 2348 struct smu_context *smu = handle; 2349 uint32_t limit_type = limit >> 24; 2350 int ret = 0; 2351 2352 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2353 return -EOPNOTSUPP; 2354 2355 mutex_lock(&smu->mutex); 2356 2357 limit &= (1<<24)-1; 2358 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2359 if (smu->ppt_funcs->set_power_limit) { 2360 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2361 goto out; 2362 } 2363 2364 if (limit > smu->max_power_limit) { 2365 dev_err(smu->adev->dev, 2366 "New power limit (%d) is over the max allowed %d\n", 2367 limit, smu->max_power_limit); 2368 ret = -EINVAL; 2369 goto out; 2370 } 2371 2372 if (!limit) 2373 limit = smu->current_power_limit; 2374 2375 if (smu->ppt_funcs->set_power_limit) { 2376 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2377 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2378 smu->user_dpm_profile.power_limit = limit; 2379 } 2380 2381 out: 2382 mutex_unlock(&smu->mutex); 2383 2384 return ret; 2385 } 2386 2387 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2388 { 2389 int ret = 0; 2390 2391 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2392 return -EOPNOTSUPP; 2393 2394 mutex_lock(&smu->mutex); 2395 2396 if (smu->ppt_funcs->print_clk_levels) 2397 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2398 2399 mutex_unlock(&smu->mutex); 2400 2401 return ret; 2402 } 2403 2404 static int smu_print_ppclk_levels(void *handle, 2405 enum pp_clock_type type, 2406 char *buf) 2407 { 2408 struct smu_context *smu = handle; 2409 enum smu_clk_type clk_type; 2410 2411 switch (type) { 2412 case PP_SCLK: 2413 clk_type = SMU_SCLK; break; 2414 case PP_MCLK: 2415 clk_type = SMU_MCLK; break; 2416 case PP_PCIE: 2417 clk_type = SMU_PCIE; break; 2418 case PP_SOCCLK: 2419 clk_type = SMU_SOCCLK; break; 2420 case PP_FCLK: 2421 clk_type = SMU_FCLK; break; 2422 case PP_DCEFCLK: 2423 clk_type = SMU_DCEFCLK; break; 2424 case PP_VCLK: 2425 clk_type = SMU_VCLK; break; 2426 case PP_DCLK: 2427 clk_type = SMU_DCLK; break; 2428 case OD_SCLK: 2429 clk_type = SMU_OD_SCLK; break; 2430 case OD_MCLK: 2431 clk_type = SMU_OD_MCLK; break; 2432 case OD_VDDC_CURVE: 2433 clk_type = SMU_OD_VDDC_CURVE; break; 2434 case OD_RANGE: 2435 clk_type = SMU_OD_RANGE; break; 2436 case OD_VDDGFX_OFFSET: 2437 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2438 case OD_CCLK: 2439 clk_type = SMU_OD_CCLK; break; 2440 default: 2441 return -EINVAL; 2442 } 2443 2444 return smu_print_smuclk_levels(smu, clk_type, buf); 2445 } 2446 2447 static int smu_od_edit_dpm_table(void *handle, 2448 enum PP_OD_DPM_TABLE_COMMAND type, 2449 long *input, uint32_t size) 2450 { 2451 struct smu_context *smu = handle; 2452 int ret = 0; 2453 2454 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2455 return -EOPNOTSUPP; 2456 2457 mutex_lock(&smu->mutex); 2458 2459 if (smu->ppt_funcs->od_edit_dpm_table) { 2460 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2461 } 2462 2463 mutex_unlock(&smu->mutex); 2464 2465 return ret; 2466 } 2467 2468 static int smu_read_sensor(void *handle, 2469 int sensor, 2470 void *data, 2471 int *size_arg) 2472 { 2473 struct smu_context *smu = handle; 2474 struct smu_umd_pstate_table *pstate_table = 2475 &smu->pstate_table; 2476 int ret = 0; 2477 uint32_t *size, size_val; 2478 2479 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2480 return -EOPNOTSUPP; 2481 2482 if (!data || !size_arg) 2483 return -EINVAL; 2484 2485 size_val = *size_arg; 2486 size = &size_val; 2487 2488 mutex_lock(&smu->mutex); 2489 2490 if (smu->ppt_funcs->read_sensor) 2491 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2492 goto unlock; 2493 2494 switch (sensor) { 2495 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2496 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2497 *size = 4; 2498 break; 2499 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2500 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2501 *size = 4; 2502 break; 2503 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2504 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2505 *size = 8; 2506 break; 2507 case AMDGPU_PP_SENSOR_UVD_POWER: 2508 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2509 *size = 4; 2510 break; 2511 case AMDGPU_PP_SENSOR_VCE_POWER: 2512 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2513 *size = 4; 2514 break; 2515 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2516 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2517 *size = 4; 2518 break; 2519 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2520 *(uint32_t *)data = 0; 2521 *size = 4; 2522 break; 2523 default: 2524 *size = 0; 2525 ret = -EOPNOTSUPP; 2526 break; 2527 } 2528 2529 unlock: 2530 mutex_unlock(&smu->mutex); 2531 2532 // assign uint32_t to int 2533 *size_arg = size_val; 2534 2535 return ret; 2536 } 2537 2538 static int smu_get_power_profile_mode(void *handle, char *buf) 2539 { 2540 struct smu_context *smu = handle; 2541 int ret = 0; 2542 2543 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2544 !smu->ppt_funcs->get_power_profile_mode) 2545 return -EOPNOTSUPP; 2546 if (!buf) 2547 return -EINVAL; 2548 2549 mutex_lock(&smu->mutex); 2550 2551 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2552 2553 mutex_unlock(&smu->mutex); 2554 2555 return ret; 2556 } 2557 2558 static int smu_set_power_profile_mode(void *handle, 2559 long *param, 2560 uint32_t param_size) 2561 { 2562 struct smu_context *smu = handle; 2563 int ret = 0; 2564 2565 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2566 !smu->ppt_funcs->set_power_profile_mode) 2567 return -EOPNOTSUPP; 2568 2569 mutex_lock(&smu->mutex); 2570 2571 smu_bump_power_profile_mode(smu, param, param_size); 2572 2573 mutex_unlock(&smu->mutex); 2574 2575 return ret; 2576 } 2577 2578 2579 static u32 smu_get_fan_control_mode(void *handle) 2580 { 2581 struct smu_context *smu = handle; 2582 u32 ret = 0; 2583 2584 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2585 return AMD_FAN_CTRL_NONE; 2586 2587 mutex_lock(&smu->mutex); 2588 2589 if (smu->ppt_funcs->get_fan_control_mode) 2590 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2591 2592 mutex_unlock(&smu->mutex); 2593 2594 return ret; 2595 } 2596 2597 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2598 { 2599 int ret = 0; 2600 2601 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2602 return -EOPNOTSUPP; 2603 2604 mutex_lock(&smu->mutex); 2605 2606 if (smu->ppt_funcs->set_fan_control_mode) { 2607 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2608 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2609 smu->user_dpm_profile.fan_mode = value; 2610 } 2611 2612 mutex_unlock(&smu->mutex); 2613 2614 /* reset user dpm fan speed */ 2615 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2616 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2617 smu->user_dpm_profile.fan_speed_pwm = 0; 2618 smu->user_dpm_profile.fan_speed_rpm = 0; 2619 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2620 } 2621 2622 return ret; 2623 } 2624 2625 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2626 { 2627 struct smu_context *smu = handle; 2628 2629 smu_set_fan_control_mode(smu, value); 2630 } 2631 2632 2633 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2634 { 2635 struct smu_context *smu = handle; 2636 int ret = 0; 2637 2638 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2639 return -EOPNOTSUPP; 2640 2641 mutex_lock(&smu->mutex); 2642 2643 if (smu->ppt_funcs->get_fan_speed_pwm) 2644 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2645 2646 mutex_unlock(&smu->mutex); 2647 2648 return ret; 2649 } 2650 2651 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2652 { 2653 struct smu_context *smu = handle; 2654 int ret = 0; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 mutex_lock(&smu->mutex); 2660 2661 if (smu->ppt_funcs->set_fan_speed_pwm) { 2662 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2663 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2664 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2665 smu->user_dpm_profile.fan_speed_pwm = speed; 2666 2667 /* Override custom RPM setting as they cannot co-exist */ 2668 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2669 smu->user_dpm_profile.fan_speed_rpm = 0; 2670 } 2671 } 2672 2673 mutex_unlock(&smu->mutex); 2674 2675 return ret; 2676 } 2677 2678 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2679 { 2680 struct smu_context *smu = handle; 2681 int ret = 0; 2682 2683 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2684 return -EOPNOTSUPP; 2685 2686 mutex_lock(&smu->mutex); 2687 2688 if (smu->ppt_funcs->get_fan_speed_rpm) 2689 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2690 2691 mutex_unlock(&smu->mutex); 2692 2693 return ret; 2694 } 2695 2696 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2697 { 2698 struct smu_context *smu = handle; 2699 int ret = 0; 2700 2701 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2702 return -EOPNOTSUPP; 2703 2704 mutex_lock(&smu->mutex); 2705 2706 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2707 2708 mutex_unlock(&smu->mutex); 2709 2710 return ret; 2711 } 2712 2713 static int smu_get_clock_by_type_with_latency(void *handle, 2714 enum amd_pp_clock_type type, 2715 struct pp_clock_levels_with_latency *clocks) 2716 { 2717 struct smu_context *smu = handle; 2718 enum smu_clk_type clk_type; 2719 int ret = 0; 2720 2721 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2722 return -EOPNOTSUPP; 2723 2724 mutex_lock(&smu->mutex); 2725 2726 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2727 switch (type) { 2728 case amd_pp_sys_clock: 2729 clk_type = SMU_GFXCLK; 2730 break; 2731 case amd_pp_mem_clock: 2732 clk_type = SMU_MCLK; 2733 break; 2734 case amd_pp_dcef_clock: 2735 clk_type = SMU_DCEFCLK; 2736 break; 2737 case amd_pp_disp_clock: 2738 clk_type = SMU_DISPCLK; 2739 break; 2740 default: 2741 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2742 mutex_unlock(&smu->mutex); 2743 return -EINVAL; 2744 } 2745 2746 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2747 } 2748 2749 mutex_unlock(&smu->mutex); 2750 2751 return ret; 2752 } 2753 2754 static int smu_display_clock_voltage_request(void *handle, 2755 struct pp_display_clock_request *clock_req) 2756 { 2757 struct smu_context *smu = handle; 2758 int ret = 0; 2759 2760 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2761 return -EOPNOTSUPP; 2762 2763 mutex_lock(&smu->mutex); 2764 2765 if (smu->ppt_funcs->display_clock_voltage_request) 2766 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2767 2768 mutex_unlock(&smu->mutex); 2769 2770 return ret; 2771 } 2772 2773 2774 static int smu_display_disable_memory_clock_switch(void *handle, 2775 bool disable_memory_clock_switch) 2776 { 2777 struct smu_context *smu = handle; 2778 int ret = -EINVAL; 2779 2780 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2781 return -EOPNOTSUPP; 2782 2783 mutex_lock(&smu->mutex); 2784 2785 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2786 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2787 2788 mutex_unlock(&smu->mutex); 2789 2790 return ret; 2791 } 2792 2793 static int smu_set_xgmi_pstate(void *handle, 2794 uint32_t pstate) 2795 { 2796 struct smu_context *smu = handle; 2797 int ret = 0; 2798 2799 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2800 return -EOPNOTSUPP; 2801 2802 mutex_lock(&smu->mutex); 2803 2804 if (smu->ppt_funcs->set_xgmi_pstate) 2805 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2806 2807 mutex_unlock(&smu->mutex); 2808 2809 if(ret) 2810 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2811 2812 return ret; 2813 } 2814 2815 static int smu_get_baco_capability(void *handle, bool *cap) 2816 { 2817 struct smu_context *smu = handle; 2818 int ret = 0; 2819 2820 *cap = false; 2821 2822 if (!smu->pm_enabled) 2823 return 0; 2824 2825 mutex_lock(&smu->mutex); 2826 2827 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2828 *cap = smu->ppt_funcs->baco_is_support(smu); 2829 2830 mutex_unlock(&smu->mutex); 2831 2832 return ret; 2833 } 2834 2835 static int smu_baco_set_state(void *handle, int state) 2836 { 2837 struct smu_context *smu = handle; 2838 int ret = 0; 2839 2840 if (!smu->pm_enabled) 2841 return -EOPNOTSUPP; 2842 2843 if (state == 0) { 2844 mutex_lock(&smu->mutex); 2845 2846 if (smu->ppt_funcs->baco_exit) 2847 ret = smu->ppt_funcs->baco_exit(smu); 2848 2849 mutex_unlock(&smu->mutex); 2850 } else if (state == 1) { 2851 mutex_lock(&smu->mutex); 2852 2853 if (smu->ppt_funcs->baco_enter) 2854 ret = smu->ppt_funcs->baco_enter(smu); 2855 2856 mutex_unlock(&smu->mutex); 2857 2858 } else { 2859 return -EINVAL; 2860 } 2861 2862 if (ret) 2863 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2864 (state)?"enter":"exit"); 2865 2866 return ret; 2867 } 2868 2869 bool smu_mode1_reset_is_support(struct smu_context *smu) 2870 { 2871 bool ret = false; 2872 2873 if (!smu->pm_enabled) 2874 return false; 2875 2876 mutex_lock(&smu->mutex); 2877 2878 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2879 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2880 2881 mutex_unlock(&smu->mutex); 2882 2883 return ret; 2884 } 2885 2886 bool smu_mode2_reset_is_support(struct smu_context *smu) 2887 { 2888 bool ret = false; 2889 2890 if (!smu->pm_enabled) 2891 return false; 2892 2893 mutex_lock(&smu->mutex); 2894 2895 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2896 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2897 2898 mutex_unlock(&smu->mutex); 2899 2900 return ret; 2901 } 2902 2903 int smu_mode1_reset(struct smu_context *smu) 2904 { 2905 int ret = 0; 2906 2907 if (!smu->pm_enabled) 2908 return -EOPNOTSUPP; 2909 2910 mutex_lock(&smu->mutex); 2911 2912 if (smu->ppt_funcs->mode1_reset) 2913 ret = smu->ppt_funcs->mode1_reset(smu); 2914 2915 mutex_unlock(&smu->mutex); 2916 2917 return ret; 2918 } 2919 2920 static int smu_mode2_reset(void *handle) 2921 { 2922 struct smu_context *smu = handle; 2923 int ret = 0; 2924 2925 if (!smu->pm_enabled) 2926 return -EOPNOTSUPP; 2927 2928 mutex_lock(&smu->mutex); 2929 2930 if (smu->ppt_funcs->mode2_reset) 2931 ret = smu->ppt_funcs->mode2_reset(smu); 2932 2933 mutex_unlock(&smu->mutex); 2934 2935 if (ret) 2936 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2937 2938 return ret; 2939 } 2940 2941 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2942 struct pp_smu_nv_clock_table *max_clocks) 2943 { 2944 struct smu_context *smu = handle; 2945 int ret = 0; 2946 2947 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2948 return -EOPNOTSUPP; 2949 2950 mutex_lock(&smu->mutex); 2951 2952 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2953 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2954 2955 mutex_unlock(&smu->mutex); 2956 2957 return ret; 2958 } 2959 2960 static int smu_get_uclk_dpm_states(void *handle, 2961 unsigned int *clock_values_in_khz, 2962 unsigned int *num_states) 2963 { 2964 struct smu_context *smu = handle; 2965 int ret = 0; 2966 2967 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2968 return -EOPNOTSUPP; 2969 2970 mutex_lock(&smu->mutex); 2971 2972 if (smu->ppt_funcs->get_uclk_dpm_states) 2973 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2974 2975 mutex_unlock(&smu->mutex); 2976 2977 return ret; 2978 } 2979 2980 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2981 { 2982 struct smu_context *smu = handle; 2983 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2984 2985 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2986 return -EOPNOTSUPP; 2987 2988 mutex_lock(&smu->mutex); 2989 2990 if (smu->ppt_funcs->get_current_power_state) 2991 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2992 2993 mutex_unlock(&smu->mutex); 2994 2995 return pm_state; 2996 } 2997 2998 static int smu_get_dpm_clock_table(void *handle, 2999 struct dpm_clocks *clock_table) 3000 { 3001 struct smu_context *smu = handle; 3002 int ret = 0; 3003 3004 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3005 return -EOPNOTSUPP; 3006 3007 mutex_lock(&smu->mutex); 3008 3009 if (smu->ppt_funcs->get_dpm_clock_table) 3010 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3011 3012 mutex_unlock(&smu->mutex); 3013 3014 return ret; 3015 } 3016 3017 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3018 { 3019 struct smu_context *smu = handle; 3020 ssize_t size; 3021 3022 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3023 return -EOPNOTSUPP; 3024 3025 if (!smu->ppt_funcs->get_gpu_metrics) 3026 return -EOPNOTSUPP; 3027 3028 mutex_lock(&smu->mutex); 3029 3030 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 3031 3032 mutex_unlock(&smu->mutex); 3033 3034 return size; 3035 } 3036 3037 static int smu_enable_mgpu_fan_boost(void *handle) 3038 { 3039 struct smu_context *smu = handle; 3040 int ret = 0; 3041 3042 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3043 return -EOPNOTSUPP; 3044 3045 mutex_lock(&smu->mutex); 3046 3047 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3048 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3049 3050 mutex_unlock(&smu->mutex); 3051 3052 return ret; 3053 } 3054 3055 static int smu_gfx_state_change_set(void *handle, 3056 uint32_t state) 3057 { 3058 struct smu_context *smu = handle; 3059 int ret = 0; 3060 3061 mutex_lock(&smu->mutex); 3062 if (smu->ppt_funcs->gfx_state_change_set) 3063 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3064 mutex_unlock(&smu->mutex); 3065 3066 return ret; 3067 } 3068 3069 int smu_set_light_sbr(struct smu_context *smu, bool enable) 3070 { 3071 int ret = 0; 3072 3073 mutex_lock(&smu->mutex); 3074 if (smu->ppt_funcs->set_light_sbr) 3075 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 3076 mutex_unlock(&smu->mutex); 3077 3078 return ret; 3079 } 3080 3081 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3082 { 3083 int ret = -EOPNOTSUPP; 3084 3085 mutex_lock(&smu->mutex); 3086 if (smu->ppt_funcs && 3087 smu->ppt_funcs->get_ecc_info) 3088 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3089 mutex_unlock(&smu->mutex); 3090 3091 return ret; 3092 3093 } 3094 3095 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3096 { 3097 struct smu_context *smu = handle; 3098 struct smu_table_context *smu_table = &smu->smu_table; 3099 struct smu_table *memory_pool = &smu_table->memory_pool; 3100 3101 if (!addr || !size) 3102 return -EINVAL; 3103 3104 *addr = NULL; 3105 *size = 0; 3106 mutex_lock(&smu->mutex); 3107 if (memory_pool->bo) { 3108 *addr = memory_pool->cpu_addr; 3109 *size = memory_pool->size; 3110 } 3111 mutex_unlock(&smu->mutex); 3112 3113 return 0; 3114 } 3115 3116 static const struct amd_pm_funcs swsmu_pm_funcs = { 3117 /* export for sysfs */ 3118 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3119 .get_fan_control_mode = smu_get_fan_control_mode, 3120 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3121 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3122 .force_clock_level = smu_force_ppclk_levels, 3123 .print_clock_levels = smu_print_ppclk_levels, 3124 .force_performance_level = smu_force_performance_level, 3125 .read_sensor = smu_read_sensor, 3126 .get_performance_level = smu_get_performance_level, 3127 .get_current_power_state = smu_get_current_power_state, 3128 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3129 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3130 .get_pp_num_states = smu_get_power_num_states, 3131 .get_pp_table = smu_sys_get_pp_table, 3132 .set_pp_table = smu_sys_set_pp_table, 3133 .switch_power_profile = smu_switch_power_profile, 3134 /* export to amdgpu */ 3135 .dispatch_tasks = smu_handle_dpm_task, 3136 .load_firmware = smu_load_microcode, 3137 .set_powergating_by_smu = smu_dpm_set_power_gate, 3138 .set_power_limit = smu_set_power_limit, 3139 .get_power_limit = smu_get_power_limit, 3140 .get_power_profile_mode = smu_get_power_profile_mode, 3141 .set_power_profile_mode = smu_set_power_profile_mode, 3142 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3143 .set_mp1_state = smu_set_mp1_state, 3144 .gfx_state_change_set = smu_gfx_state_change_set, 3145 /* export to DC */ 3146 .get_sclk = smu_get_sclk, 3147 .get_mclk = smu_get_mclk, 3148 .display_configuration_change = smu_display_configuration_change, 3149 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3150 .display_clock_voltage_request = smu_display_clock_voltage_request, 3151 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3152 .set_active_display_count = smu_set_display_count, 3153 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3154 .get_asic_baco_capability = smu_get_baco_capability, 3155 .set_asic_baco_state = smu_baco_set_state, 3156 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3157 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3158 .asic_reset_mode_2 = smu_mode2_reset, 3159 .set_df_cstate = smu_set_df_cstate, 3160 .set_xgmi_pstate = smu_set_xgmi_pstate, 3161 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3162 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3163 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3164 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3165 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3166 .get_dpm_clock_table = smu_get_dpm_clock_table, 3167 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3168 }; 3169 3170 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3171 uint64_t event_arg) 3172 { 3173 int ret = -EINVAL; 3174 struct smu_context *smu = &adev->smu; 3175 3176 if (smu->ppt_funcs->wait_for_event) { 3177 mutex_lock(&smu->mutex); 3178 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3179 mutex_unlock(&smu->mutex); 3180 } 3181 3182 return ret; 3183 } 3184 3185 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3186 { 3187 3188 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3189 return -EOPNOTSUPP; 3190 3191 /* Confirm the buffer allocated is of correct size */ 3192 if (size != smu->stb_context.stb_buf_size) 3193 return -EINVAL; 3194 3195 /* 3196 * No need to lock smu mutex as we access STB directly through MMIO 3197 * and not going through SMU messaging route (for now at least). 3198 * For registers access rely on implementation internal locking. 3199 */ 3200 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3201 } 3202 3203 #if defined(CONFIG_DEBUG_FS) 3204 3205 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3206 { 3207 struct amdgpu_device *adev = filp->f_inode->i_private; 3208 struct smu_context *smu = &adev->smu; 3209 unsigned char *buf; 3210 int r; 3211 3212 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3213 if (!buf) 3214 return -ENOMEM; 3215 3216 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3217 if (r) 3218 goto out; 3219 3220 filp->private_data = buf; 3221 3222 return 0; 3223 3224 out: 3225 kvfree(buf); 3226 return r; 3227 } 3228 3229 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3230 loff_t *pos) 3231 { 3232 struct amdgpu_device *adev = filp->f_inode->i_private; 3233 struct smu_context *smu = &adev->smu; 3234 3235 3236 if (!filp->private_data) 3237 return -EINVAL; 3238 3239 return simple_read_from_buffer(buf, 3240 size, 3241 pos, filp->private_data, 3242 smu->stb_context.stb_buf_size); 3243 } 3244 3245 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3246 { 3247 kvfree(filp->private_data); 3248 filp->private_data = NULL; 3249 3250 return 0; 3251 } 3252 3253 /* 3254 * We have to define not only read method but also 3255 * open and release because .read takes up to PAGE_SIZE 3256 * data each time so and so is invoked multiple times. 3257 * We allocate the STB buffer in .open and release it 3258 * in .release 3259 */ 3260 static const struct file_operations smu_stb_debugfs_fops = { 3261 .owner = THIS_MODULE, 3262 .open = smu_stb_debugfs_open, 3263 .read = smu_stb_debugfs_read, 3264 .release = smu_stb_debugfs_release, 3265 .llseek = default_llseek, 3266 }; 3267 3268 #endif 3269 3270 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3271 { 3272 #if defined(CONFIG_DEBUG_FS) 3273 3274 struct smu_context *smu = &adev->smu; 3275 3276 if (!smu->stb_context.stb_buf_size) 3277 return; 3278 3279 debugfs_create_file_size("amdgpu_smu_stb_dump", 3280 S_IRUSR, 3281 adev_to_drm(adev)->primary->debugfs_root, 3282 adev, 3283 &smu_stb_debugfs_fops, 3284 smu->stb_context.stb_buf_size); 3285 #endif 3286 3287 } 3288