1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "amd_pcie.h" 41 42 /* 43 * DO NOT use these for err/warn/info/debug messages. 44 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 45 * They are more MGPU friendly. 46 */ 47 #undef pr_err 48 #undef pr_warn 49 #undef pr_info 50 #undef pr_debug 51 52 static const struct amd_pm_funcs swsmu_pm_funcs; 53 static int smu_force_smuclk_levels(struct smu_context *smu, 54 enum smu_clk_type clk_type, 55 uint32_t mask); 56 static int smu_handle_task(struct smu_context *smu, 57 enum amd_dpm_forced_level level, 58 enum amd_pp_task task_id, 59 bool lock_needed); 60 static int smu_reset(struct smu_context *smu); 61 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 62 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 63 static int smu_set_power_limit(void *handle, uint32_t limit); 64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 66 67 static int smu_sys_get_pp_feature_mask(void *handle, 68 char *buf) 69 { 70 struct smu_context *smu = handle; 71 int size = 0; 72 73 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 74 return -EOPNOTSUPP; 75 76 mutex_lock(&smu->mutex); 77 78 size = smu_get_pp_feature_mask(smu, buf); 79 80 mutex_unlock(&smu->mutex); 81 82 return size; 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 int ret = 0; 90 91 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 92 return -EOPNOTSUPP; 93 94 mutex_lock(&smu->mutex); 95 96 ret = smu_set_pp_feature_mask(smu, new_mask); 97 98 mutex_unlock(&smu->mutex); 99 100 return ret; 101 } 102 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 104 { 105 int ret = 0; 106 struct smu_context *smu = &adev->smu; 107 108 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 109 *value = smu_get_gfx_off_status(smu); 110 else 111 ret = -EINVAL; 112 113 return ret; 114 } 115 116 int smu_set_soft_freq_range(struct smu_context *smu, 117 enum smu_clk_type clk_type, 118 uint32_t min, 119 uint32_t max) 120 { 121 int ret = 0; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->set_soft_freq_limited_range) 126 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 int smu_get_dpm_freq_range(struct smu_context *smu, 137 enum smu_clk_type clk_type, 138 uint32_t *min, 139 uint32_t *max) 140 { 141 int ret = 0; 142 143 if (!min && !max) 144 return -EINVAL; 145 146 mutex_lock(&smu->mutex); 147 148 if (smu->ppt_funcs->get_dpm_ultimate_freq) 149 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 150 clk_type, 151 min, 152 max); 153 154 mutex_unlock(&smu->mutex); 155 156 return ret; 157 } 158 159 static u32 smu_get_mclk(void *handle, bool low) 160 { 161 struct smu_context *smu = handle; 162 uint32_t clk_freq; 163 int ret = 0; 164 165 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 166 low ? &clk_freq : NULL, 167 !low ? &clk_freq : NULL); 168 if (ret) 169 return 0; 170 return clk_freq * 100; 171 } 172 173 static u32 smu_get_sclk(void *handle, bool low) 174 { 175 struct smu_context *smu = handle; 176 uint32_t clk_freq; 177 int ret = 0; 178 179 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 180 low ? &clk_freq : NULL, 181 !low ? &clk_freq : NULL); 182 if (ret) 183 return 0; 184 return clk_freq * 100; 185 } 186 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 188 bool enable) 189 { 190 struct smu_power_context *smu_power = &smu->smu_power; 191 struct smu_power_gate *power_gate = &smu_power->power_gate; 192 int ret = 0; 193 194 if (!smu->ppt_funcs->dpm_set_vcn_enable) 195 return 0; 196 197 if (atomic_read(&power_gate->vcn_gated) ^ enable) 198 return 0; 199 200 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 201 if (!ret) 202 atomic_set(&power_gate->vcn_gated, !enable); 203 204 return ret; 205 } 206 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 208 bool enable) 209 { 210 struct smu_power_context *smu_power = &smu->smu_power; 211 struct smu_power_gate *power_gate = &smu_power->power_gate; 212 int ret = 0; 213 214 mutex_lock(&power_gate->vcn_gate_lock); 215 216 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 217 218 mutex_unlock(&power_gate->vcn_gate_lock); 219 220 return ret; 221 } 222 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 224 bool enable) 225 { 226 struct smu_power_context *smu_power = &smu->smu_power; 227 struct smu_power_gate *power_gate = &smu_power->power_gate; 228 int ret = 0; 229 230 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 231 return 0; 232 233 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 234 return 0; 235 236 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 237 if (!ret) 238 atomic_set(&power_gate->jpeg_gated, !enable); 239 240 return ret; 241 } 242 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 244 bool enable) 245 { 246 struct smu_power_context *smu_power = &smu->smu_power; 247 struct smu_power_gate *power_gate = &smu_power->power_gate; 248 int ret = 0; 249 250 mutex_lock(&power_gate->jpeg_gate_lock); 251 252 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 253 254 mutex_unlock(&power_gate->jpeg_gate_lock); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 281 dev_WARN(smu->adev->dev, 282 "SMU uninitialized but power %s requested for %u!\n", 283 gate ? "gate" : "ungate", block_type); 284 return -EOPNOTSUPP; 285 } 286 287 switch (block_type) { 288 /* 289 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 290 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 291 */ 292 case AMD_IP_BLOCK_TYPE_UVD: 293 case AMD_IP_BLOCK_TYPE_VCN: 294 ret = smu_dpm_set_vcn_enable(smu, !gate); 295 if (ret) 296 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 297 gate ? "gate" : "ungate"); 298 break; 299 case AMD_IP_BLOCK_TYPE_GFX: 300 ret = smu_gfx_off_control(smu, gate); 301 if (ret) 302 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 303 gate ? "enable" : "disable"); 304 break; 305 case AMD_IP_BLOCK_TYPE_SDMA: 306 ret = smu_powergate_sdma(smu, gate); 307 if (ret) 308 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 309 gate ? "gate" : "ungate"); 310 break; 311 case AMD_IP_BLOCK_TYPE_JPEG: 312 ret = smu_dpm_set_jpeg_enable(smu, !gate); 313 if (ret) 314 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 315 gate ? "gate" : "ungate"); 316 break; 317 default: 318 dev_err(smu->adev->dev, "Unsupported block type!\n"); 319 return -EINVAL; 320 } 321 322 return ret; 323 } 324 325 /** 326 * smu_set_user_clk_dependencies - set user profile clock dependencies 327 * 328 * @smu: smu_context pointer 329 * @clk: enum smu_clk_type type 330 * 331 * Enable/Disable the clock dependency for the @clk type. 332 */ 333 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 334 { 335 if (smu->adev->in_suspend) 336 return; 337 338 if (clk == SMU_MCLK) { 339 smu->user_dpm_profile.clk_dependency = 0; 340 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 341 } else if (clk == SMU_FCLK) { 342 /* MCLK takes precedence over FCLK */ 343 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 344 return; 345 346 smu->user_dpm_profile.clk_dependency = 0; 347 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 348 } else if (clk == SMU_SOCCLK) { 349 /* MCLK takes precedence over SOCCLK */ 350 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 351 return; 352 353 smu->user_dpm_profile.clk_dependency = 0; 354 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 355 } else 356 /* Add clk dependencies here, if any */ 357 return; 358 } 359 360 /** 361 * smu_restore_dpm_user_profile - reinstate user dpm profile 362 * 363 * @smu: smu_context pointer 364 * 365 * Restore the saved user power configurations include power limit, 366 * clock frequencies, fan control mode and fan speed. 367 */ 368 static void smu_restore_dpm_user_profile(struct smu_context *smu) 369 { 370 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 371 int ret = 0; 372 373 if (!smu->adev->in_suspend) 374 return; 375 376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 377 return; 378 379 /* Enable restore flag */ 380 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 381 382 /* set the user dpm power limit */ 383 if (smu->user_dpm_profile.power_limit) { 384 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 385 if (ret) 386 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 387 } 388 389 /* set the user dpm clock configurations */ 390 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 391 enum smu_clk_type clk_type; 392 393 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 394 /* 395 * Iterate over smu clk type and force the saved user clk 396 * configs, skip if clock dependency is enabled 397 */ 398 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 399 smu->user_dpm_profile.clk_mask[clk_type]) { 400 ret = smu_force_smuclk_levels(smu, clk_type, 401 smu->user_dpm_profile.clk_mask[clk_type]); 402 if (ret) 403 dev_err(smu->adev->dev, 404 "Failed to set clock type = %d\n", clk_type); 405 } 406 } 407 } 408 409 /* set the user dpm fan configurations */ 410 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 411 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 412 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 413 if (ret) { 414 smu->user_dpm_profile.fan_speed_pwm = 0; 415 smu->user_dpm_profile.fan_speed_rpm = 0; 416 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 417 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 418 } 419 420 if (smu->user_dpm_profile.fan_speed_pwm) { 421 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 422 if (ret) 423 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 424 } 425 426 if (smu->user_dpm_profile.fan_speed_rpm) { 427 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 428 if (ret) 429 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 430 } 431 } 432 433 /* Restore user customized OD settings */ 434 if (smu->user_dpm_profile.user_od) { 435 if (smu->ppt_funcs->restore_user_od_settings) { 436 ret = smu->ppt_funcs->restore_user_od_settings(smu); 437 if (ret) 438 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 439 } 440 } 441 442 /* Disable restore flag */ 443 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 444 } 445 446 static int smu_get_power_num_states(void *handle, 447 struct pp_states_info *state_info) 448 { 449 if (!state_info) 450 return -EINVAL; 451 452 /* not support power state */ 453 memset(state_info, 0, sizeof(struct pp_states_info)); 454 state_info->nums = 1; 455 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 456 457 return 0; 458 } 459 460 bool is_support_sw_smu(struct amdgpu_device *adev) 461 { 462 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 463 if (adev->asic_type == CHIP_VEGA20) 464 return false; 465 466 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 467 return true; 468 469 return false; 470 } 471 472 bool is_support_cclk_dpm(struct amdgpu_device *adev) 473 { 474 struct smu_context *smu = &adev->smu; 475 476 if (!is_support_sw_smu(adev)) 477 return false; 478 479 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 480 return false; 481 482 return true; 483 } 484 485 486 static int smu_sys_get_pp_table(void *handle, 487 char **table) 488 { 489 struct smu_context *smu = handle; 490 struct smu_table_context *smu_table = &smu->smu_table; 491 uint32_t powerplay_table_size; 492 493 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 494 return -EOPNOTSUPP; 495 496 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 497 return -EINVAL; 498 499 mutex_lock(&smu->mutex); 500 501 if (smu_table->hardcode_pptable) 502 *table = smu_table->hardcode_pptable; 503 else 504 *table = smu_table->power_play_table; 505 506 powerplay_table_size = smu_table->power_play_table_size; 507 508 mutex_unlock(&smu->mutex); 509 510 return powerplay_table_size; 511 } 512 513 static int smu_sys_set_pp_table(void *handle, 514 const char *buf, 515 size_t size) 516 { 517 struct smu_context *smu = handle; 518 struct smu_table_context *smu_table = &smu->smu_table; 519 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 520 int ret = 0; 521 522 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 523 return -EOPNOTSUPP; 524 525 if (header->usStructureSize != size) { 526 dev_err(smu->adev->dev, "pp table size not matched !\n"); 527 return -EIO; 528 } 529 530 mutex_lock(&smu->mutex); 531 if (!smu_table->hardcode_pptable) 532 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 533 if (!smu_table->hardcode_pptable) { 534 ret = -ENOMEM; 535 goto failed; 536 } 537 538 memcpy(smu_table->hardcode_pptable, buf, size); 539 smu_table->power_play_table = smu_table->hardcode_pptable; 540 smu_table->power_play_table_size = size; 541 542 /* 543 * Special hw_fini action(for Navi1x, the DPMs disablement will be 544 * skipped) may be needed for custom pptable uploading. 545 */ 546 smu->uploading_custom_pp_table = true; 547 548 ret = smu_reset(smu); 549 if (ret) 550 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 551 552 smu->uploading_custom_pp_table = false; 553 554 failed: 555 mutex_unlock(&smu->mutex); 556 return ret; 557 } 558 559 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 560 { 561 struct smu_feature *feature = &smu->smu_feature; 562 int ret = 0; 563 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 564 565 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 566 567 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 568 SMU_FEATURE_MAX/32); 569 if (ret) 570 return ret; 571 572 bitmap_or(feature->allowed, feature->allowed, 573 (unsigned long *)allowed_feature_mask, 574 feature->feature_num); 575 576 return ret; 577 } 578 579 static int smu_set_funcs(struct amdgpu_device *adev) 580 { 581 struct smu_context *smu = &adev->smu; 582 583 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 584 smu->od_enabled = true; 585 586 switch (adev->ip_versions[MP1_HWIP][0]) { 587 case IP_VERSION(11, 0, 0): 588 case IP_VERSION(11, 0, 5): 589 case IP_VERSION(11, 0, 9): 590 navi10_set_ppt_funcs(smu); 591 break; 592 case IP_VERSION(11, 0, 7): 593 case IP_VERSION(11, 0, 11): 594 case IP_VERSION(11, 0, 12): 595 case IP_VERSION(11, 0, 13): 596 sienna_cichlid_set_ppt_funcs(smu); 597 break; 598 case IP_VERSION(12, 0, 0): 599 case IP_VERSION(12, 0, 1): 600 renoir_set_ppt_funcs(smu); 601 break; 602 case IP_VERSION(11, 5, 0): 603 vangogh_set_ppt_funcs(smu); 604 break; 605 case IP_VERSION(13, 0, 1): 606 case IP_VERSION(13, 0, 3): 607 yellow_carp_set_ppt_funcs(smu); 608 break; 609 case IP_VERSION(11, 0, 8): 610 cyan_skillfish_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(11, 0, 2): 613 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 614 arcturus_set_ppt_funcs(smu); 615 /* OD is not supported on Arcturus */ 616 smu->od_enabled =false; 617 break; 618 case IP_VERSION(13, 0, 2): 619 aldebaran_set_ppt_funcs(smu); 620 /* Enable pp_od_clk_voltage node */ 621 smu->od_enabled = true; 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 static int smu_early_init(void *handle) 631 { 632 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 633 struct smu_context *smu = &adev->smu; 634 635 smu->adev = adev; 636 smu->pm_enabled = !!amdgpu_dpm; 637 smu->is_apu = false; 638 mutex_init(&smu->mutex); 639 mutex_init(&smu->smu_baco.mutex); 640 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 641 smu->smu_baco.platform_support = false; 642 smu->user_dpm_profile.fan_mode = -1; 643 644 adev->powerplay.pp_handle = smu; 645 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 646 647 return smu_set_funcs(adev); 648 } 649 650 static int smu_set_default_dpm_table(struct smu_context *smu) 651 { 652 struct smu_power_context *smu_power = &smu->smu_power; 653 struct smu_power_gate *power_gate = &smu_power->power_gate; 654 int vcn_gate, jpeg_gate; 655 int ret = 0; 656 657 if (!smu->ppt_funcs->set_default_dpm_table) 658 return 0; 659 660 mutex_lock(&power_gate->vcn_gate_lock); 661 mutex_lock(&power_gate->jpeg_gate_lock); 662 663 vcn_gate = atomic_read(&power_gate->vcn_gated); 664 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 665 666 ret = smu_dpm_set_vcn_enable_locked(smu, true); 667 if (ret) 668 goto err0_out; 669 670 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 671 if (ret) 672 goto err1_out; 673 674 ret = smu->ppt_funcs->set_default_dpm_table(smu); 675 if (ret) 676 dev_err(smu->adev->dev, 677 "Failed to setup default dpm clock tables!\n"); 678 679 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 680 err1_out: 681 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 682 err0_out: 683 mutex_unlock(&power_gate->jpeg_gate_lock); 684 mutex_unlock(&power_gate->vcn_gate_lock); 685 686 return ret; 687 } 688 689 690 static int smu_late_init(void *handle) 691 { 692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 693 struct smu_context *smu = &adev->smu; 694 int ret = 0; 695 696 smu_set_fine_grain_gfx_freq_parameters(smu); 697 698 if (!smu->pm_enabled) 699 return 0; 700 701 ret = smu_post_init(smu); 702 if (ret) { 703 dev_err(adev->dev, "Failed to post smu init!\n"); 704 return ret; 705 } 706 707 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 708 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 709 return 0; 710 711 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 712 ret = smu_set_default_od_settings(smu); 713 if (ret) { 714 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 715 return ret; 716 } 717 } 718 719 ret = smu_populate_umd_state_clk(smu); 720 if (ret) { 721 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 722 return ret; 723 } 724 725 ret = smu_get_asic_power_limits(smu, 726 &smu->current_power_limit, 727 &smu->default_power_limit, 728 &smu->max_power_limit); 729 if (ret) { 730 dev_err(adev->dev, "Failed to get asic power limits!\n"); 731 return ret; 732 } 733 734 if (!amdgpu_sriov_vf(adev)) 735 smu_get_unique_id(smu); 736 737 smu_get_fan_parameters(smu); 738 739 smu_handle_task(&adev->smu, 740 smu->smu_dpm.dpm_level, 741 AMD_PP_TASK_COMPLETE_INIT, 742 false); 743 744 smu_restore_dpm_user_profile(smu); 745 746 return 0; 747 } 748 749 static int smu_init_fb_allocations(struct smu_context *smu) 750 { 751 struct amdgpu_device *adev = smu->adev; 752 struct smu_table_context *smu_table = &smu->smu_table; 753 struct smu_table *tables = smu_table->tables; 754 struct smu_table *driver_table = &(smu_table->driver_table); 755 uint32_t max_table_size = 0; 756 int ret, i; 757 758 /* VRAM allocation for tool table */ 759 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 760 ret = amdgpu_bo_create_kernel(adev, 761 tables[SMU_TABLE_PMSTATUSLOG].size, 762 tables[SMU_TABLE_PMSTATUSLOG].align, 763 tables[SMU_TABLE_PMSTATUSLOG].domain, 764 &tables[SMU_TABLE_PMSTATUSLOG].bo, 765 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 766 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 767 if (ret) { 768 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 769 return ret; 770 } 771 } 772 773 /* VRAM allocation for driver table */ 774 for (i = 0; i < SMU_TABLE_COUNT; i++) { 775 if (tables[i].size == 0) 776 continue; 777 778 if (i == SMU_TABLE_PMSTATUSLOG) 779 continue; 780 781 if (max_table_size < tables[i].size) 782 max_table_size = tables[i].size; 783 } 784 785 driver_table->size = max_table_size; 786 driver_table->align = PAGE_SIZE; 787 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 788 789 ret = amdgpu_bo_create_kernel(adev, 790 driver_table->size, 791 driver_table->align, 792 driver_table->domain, 793 &driver_table->bo, 794 &driver_table->mc_address, 795 &driver_table->cpu_addr); 796 if (ret) { 797 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 798 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 799 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 800 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 801 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 802 } 803 804 return ret; 805 } 806 807 static int smu_fini_fb_allocations(struct smu_context *smu) 808 { 809 struct smu_table_context *smu_table = &smu->smu_table; 810 struct smu_table *tables = smu_table->tables; 811 struct smu_table *driver_table = &(smu_table->driver_table); 812 813 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 814 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 815 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 816 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 817 818 amdgpu_bo_free_kernel(&driver_table->bo, 819 &driver_table->mc_address, 820 &driver_table->cpu_addr); 821 822 return 0; 823 } 824 825 /** 826 * smu_alloc_memory_pool - allocate memory pool in the system memory 827 * 828 * @smu: amdgpu_device pointer 829 * 830 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 831 * and DramLogSetDramAddr can notify it changed. 832 * 833 * Returns 0 on success, error on failure. 834 */ 835 static int smu_alloc_memory_pool(struct smu_context *smu) 836 { 837 struct amdgpu_device *adev = smu->adev; 838 struct smu_table_context *smu_table = &smu->smu_table; 839 struct smu_table *memory_pool = &smu_table->memory_pool; 840 uint64_t pool_size = smu->pool_size; 841 int ret = 0; 842 843 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 844 return ret; 845 846 memory_pool->size = pool_size; 847 memory_pool->align = PAGE_SIZE; 848 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 849 850 switch (pool_size) { 851 case SMU_MEMORY_POOL_SIZE_256_MB: 852 case SMU_MEMORY_POOL_SIZE_512_MB: 853 case SMU_MEMORY_POOL_SIZE_1_GB: 854 case SMU_MEMORY_POOL_SIZE_2_GB: 855 ret = amdgpu_bo_create_kernel(adev, 856 memory_pool->size, 857 memory_pool->align, 858 memory_pool->domain, 859 &memory_pool->bo, 860 &memory_pool->mc_address, 861 &memory_pool->cpu_addr); 862 if (ret) 863 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 864 break; 865 default: 866 break; 867 } 868 869 return ret; 870 } 871 872 static int smu_free_memory_pool(struct smu_context *smu) 873 { 874 struct smu_table_context *smu_table = &smu->smu_table; 875 struct smu_table *memory_pool = &smu_table->memory_pool; 876 877 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 878 return 0; 879 880 amdgpu_bo_free_kernel(&memory_pool->bo, 881 &memory_pool->mc_address, 882 &memory_pool->cpu_addr); 883 884 memset(memory_pool, 0, sizeof(struct smu_table)); 885 886 return 0; 887 } 888 889 static int smu_alloc_dummy_read_table(struct smu_context *smu) 890 { 891 struct smu_table_context *smu_table = &smu->smu_table; 892 struct smu_table *dummy_read_1_table = 893 &smu_table->dummy_read_1_table; 894 struct amdgpu_device *adev = smu->adev; 895 int ret = 0; 896 897 dummy_read_1_table->size = 0x40000; 898 dummy_read_1_table->align = PAGE_SIZE; 899 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 900 901 ret = amdgpu_bo_create_kernel(adev, 902 dummy_read_1_table->size, 903 dummy_read_1_table->align, 904 dummy_read_1_table->domain, 905 &dummy_read_1_table->bo, 906 &dummy_read_1_table->mc_address, 907 &dummy_read_1_table->cpu_addr); 908 if (ret) 909 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 910 911 return ret; 912 } 913 914 static void smu_free_dummy_read_table(struct smu_context *smu) 915 { 916 struct smu_table_context *smu_table = &smu->smu_table; 917 struct smu_table *dummy_read_1_table = 918 &smu_table->dummy_read_1_table; 919 920 921 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 922 &dummy_read_1_table->mc_address, 923 &dummy_read_1_table->cpu_addr); 924 925 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 926 } 927 928 static int smu_smc_table_sw_init(struct smu_context *smu) 929 { 930 int ret; 931 932 /** 933 * Create smu_table structure, and init smc tables such as 934 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 935 */ 936 ret = smu_init_smc_tables(smu); 937 if (ret) { 938 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 939 return ret; 940 } 941 942 /** 943 * Create smu_power_context structure, and allocate smu_dpm_context and 944 * context size to fill the smu_power_context data. 945 */ 946 ret = smu_init_power(smu); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 949 return ret; 950 } 951 952 /* 953 * allocate vram bos to store smc table contents. 954 */ 955 ret = smu_init_fb_allocations(smu); 956 if (ret) 957 return ret; 958 959 ret = smu_alloc_memory_pool(smu); 960 if (ret) 961 return ret; 962 963 ret = smu_alloc_dummy_read_table(smu); 964 if (ret) 965 return ret; 966 967 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 968 if (ret) 969 return ret; 970 971 return 0; 972 } 973 974 static int smu_smc_table_sw_fini(struct smu_context *smu) 975 { 976 int ret; 977 978 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 979 980 smu_free_dummy_read_table(smu); 981 982 ret = smu_free_memory_pool(smu); 983 if (ret) 984 return ret; 985 986 ret = smu_fini_fb_allocations(smu); 987 if (ret) 988 return ret; 989 990 ret = smu_fini_power(smu); 991 if (ret) { 992 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 993 return ret; 994 } 995 996 ret = smu_fini_smc_tables(smu); 997 if (ret) { 998 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 999 return ret; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static void smu_throttling_logging_work_fn(struct work_struct *work) 1006 { 1007 struct smu_context *smu = container_of(work, struct smu_context, 1008 throttling_logging_work); 1009 1010 smu_log_thermal_throttling(smu); 1011 } 1012 1013 static void smu_interrupt_work_fn(struct work_struct *work) 1014 { 1015 struct smu_context *smu = container_of(work, struct smu_context, 1016 interrupt_work); 1017 1018 mutex_lock(&smu->mutex); 1019 1020 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1021 smu->ppt_funcs->interrupt_work(smu); 1022 1023 mutex_unlock(&smu->mutex); 1024 } 1025 1026 static int smu_sw_init(void *handle) 1027 { 1028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1029 struct smu_context *smu = &adev->smu; 1030 int ret; 1031 1032 smu->pool_size = adev->pm.smu_prv_buffer_size; 1033 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1034 mutex_init(&smu->smu_feature.mutex); 1035 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1036 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1037 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1038 1039 mutex_init(&smu->sensor_lock); 1040 mutex_init(&smu->metrics_lock); 1041 mutex_init(&smu->message_lock); 1042 1043 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1044 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1045 atomic64_set(&smu->throttle_int_counter, 0); 1046 smu->watermarks_bitmap = 0; 1047 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1048 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1049 1050 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1051 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1052 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1053 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1054 1055 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1056 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1057 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1058 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1059 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1060 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1061 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1062 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1063 1064 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1065 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1066 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1067 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1068 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1069 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1070 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1071 smu->display_config = &adev->pm.pm_display_cfg; 1072 1073 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1074 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1075 1076 ret = smu_init_microcode(smu); 1077 if (ret) { 1078 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1079 return ret; 1080 } 1081 1082 ret = smu_smc_table_sw_init(smu); 1083 if (ret) { 1084 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1085 return ret; 1086 } 1087 1088 ret = smu_register_irq_handler(smu); 1089 if (ret) { 1090 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1091 return ret; 1092 } 1093 1094 /* If there is no way to query fan control mode, fan control is not supported */ 1095 if (!smu->ppt_funcs->get_fan_control_mode) 1096 smu->adev->pm.no_fan = true; 1097 1098 return 0; 1099 } 1100 1101 static int smu_sw_fini(void *handle) 1102 { 1103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1104 struct smu_context *smu = &adev->smu; 1105 int ret; 1106 1107 ret = smu_smc_table_sw_fini(smu); 1108 if (ret) { 1109 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1110 return ret; 1111 } 1112 1113 smu_fini_microcode(smu); 1114 1115 return 0; 1116 } 1117 1118 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1119 { 1120 struct amdgpu_device *adev = smu->adev; 1121 struct smu_temperature_range *range = 1122 &smu->thermal_range; 1123 int ret = 0; 1124 1125 if (!smu->ppt_funcs->get_thermal_temperature_range) 1126 return 0; 1127 1128 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1129 if (ret) 1130 return ret; 1131 1132 adev->pm.dpm.thermal.min_temp = range->min; 1133 adev->pm.dpm.thermal.max_temp = range->max; 1134 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1135 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1136 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1137 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1138 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1139 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1140 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1141 1142 return ret; 1143 } 1144 1145 static int smu_smc_hw_setup(struct smu_context *smu) 1146 { 1147 struct amdgpu_device *adev = smu->adev; 1148 uint32_t pcie_gen = 0, pcie_width = 0; 1149 int ret = 0; 1150 1151 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1152 dev_info(adev->dev, "dpm has been enabled\n"); 1153 /* this is needed specifically */ 1154 switch (adev->ip_versions[MP1_HWIP][0]) { 1155 case IP_VERSION(11, 0, 7): 1156 case IP_VERSION(11, 0, 11): 1157 case IP_VERSION(11, 5, 0): 1158 case IP_VERSION(11, 0, 12): 1159 ret = smu_system_features_control(smu, true); 1160 if (ret) 1161 dev_err(adev->dev, "Failed system features control!\n"); 1162 break; 1163 default: 1164 break; 1165 } 1166 return ret; 1167 } 1168 1169 ret = smu_init_display_count(smu, 0); 1170 if (ret) { 1171 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1172 return ret; 1173 } 1174 1175 ret = smu_set_driver_table_location(smu); 1176 if (ret) { 1177 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1178 return ret; 1179 } 1180 1181 /* 1182 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1183 */ 1184 ret = smu_set_tool_table_location(smu); 1185 if (ret) { 1186 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1187 return ret; 1188 } 1189 1190 /* 1191 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1192 * pool location. 1193 */ 1194 ret = smu_notify_memory_pool_location(smu); 1195 if (ret) { 1196 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1197 return ret; 1198 } 1199 1200 /* smu_dump_pptable(smu); */ 1201 /* 1202 * Copy pptable bo in the vram to smc with SMU MSGs such as 1203 * SetDriverDramAddr and TransferTableDram2Smu. 1204 */ 1205 ret = smu_write_pptable(smu); 1206 if (ret) { 1207 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1208 return ret; 1209 } 1210 1211 /* issue Run*Btc msg */ 1212 ret = smu_run_btc(smu); 1213 if (ret) 1214 return ret; 1215 1216 ret = smu_feature_set_allowed_mask(smu); 1217 if (ret) { 1218 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1219 return ret; 1220 } 1221 1222 ret = smu_system_features_control(smu, true); 1223 if (ret) { 1224 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1225 return ret; 1226 } 1227 1228 if (!smu_is_dpm_running(smu)) 1229 dev_info(adev->dev, "dpm has been disabled\n"); 1230 1231 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1232 pcie_gen = 3; 1233 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1234 pcie_gen = 2; 1235 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1236 pcie_gen = 1; 1237 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1238 pcie_gen = 0; 1239 1240 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1241 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1242 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1243 */ 1244 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1245 pcie_width = 6; 1246 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1247 pcie_width = 5; 1248 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1249 pcie_width = 4; 1250 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1251 pcie_width = 3; 1252 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1253 pcie_width = 2; 1254 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1255 pcie_width = 1; 1256 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1257 if (ret) { 1258 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1259 return ret; 1260 } 1261 1262 ret = smu_get_thermal_temperature_range(smu); 1263 if (ret) { 1264 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1265 return ret; 1266 } 1267 1268 ret = smu_enable_thermal_alert(smu); 1269 if (ret) { 1270 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1271 return ret; 1272 } 1273 1274 /* 1275 * Set initialized values (get from vbios) to dpm tables context such as 1276 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1277 * type of clks. 1278 */ 1279 ret = smu_set_default_dpm_table(smu); 1280 if (ret) { 1281 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1282 return ret; 1283 } 1284 1285 ret = smu_notify_display_change(smu); 1286 if (ret) { 1287 dev_err(adev->dev, "Failed to notify display change!\n"); 1288 return ret; 1289 } 1290 1291 /* 1292 * Set min deep sleep dce fclk with bootup value from vbios via 1293 * SetMinDeepSleepDcefclk MSG. 1294 */ 1295 ret = smu_set_min_dcef_deep_sleep(smu, 1296 smu->smu_table.boot_values.dcefclk / 100); 1297 1298 return ret; 1299 } 1300 1301 static int smu_start_smc_engine(struct smu_context *smu) 1302 { 1303 struct amdgpu_device *adev = smu->adev; 1304 int ret = 0; 1305 1306 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1307 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1308 if (smu->ppt_funcs->load_microcode) { 1309 ret = smu->ppt_funcs->load_microcode(smu); 1310 if (ret) 1311 return ret; 1312 } 1313 } 1314 } 1315 1316 if (smu->ppt_funcs->check_fw_status) { 1317 ret = smu->ppt_funcs->check_fw_status(smu); 1318 if (ret) { 1319 dev_err(adev->dev, "SMC is not ready\n"); 1320 return ret; 1321 } 1322 } 1323 1324 /* 1325 * Send msg GetDriverIfVersion to check if the return value is equal 1326 * with DRIVER_IF_VERSION of smc header. 1327 */ 1328 ret = smu_check_fw_version(smu); 1329 if (ret) 1330 return ret; 1331 1332 return ret; 1333 } 1334 1335 static int smu_hw_init(void *handle) 1336 { 1337 int ret; 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 struct smu_context *smu = &adev->smu; 1340 1341 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1342 smu->pm_enabled = false; 1343 return 0; 1344 } 1345 1346 ret = smu_start_smc_engine(smu); 1347 if (ret) { 1348 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1349 return ret; 1350 } 1351 1352 if (smu->is_apu) { 1353 smu_dpm_set_vcn_enable(smu, true); 1354 smu_dpm_set_jpeg_enable(smu, true); 1355 smu_set_gfx_cgpg(&adev->smu, true); 1356 } 1357 1358 if (!smu->pm_enabled) 1359 return 0; 1360 1361 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1362 ret = smu_get_vbios_bootup_values(smu); 1363 if (ret) { 1364 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1365 return ret; 1366 } 1367 1368 ret = smu_setup_pptable(smu); 1369 if (ret) { 1370 dev_err(adev->dev, "Failed to setup pptable!\n"); 1371 return ret; 1372 } 1373 1374 ret = smu_get_driver_allowed_feature_mask(smu); 1375 if (ret) 1376 return ret; 1377 1378 ret = smu_smc_hw_setup(smu); 1379 if (ret) { 1380 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1381 return ret; 1382 } 1383 1384 /* 1385 * Move maximum sustainable clock retrieving here considering 1386 * 1. It is not needed on resume(from S3). 1387 * 2. DAL settings come between .hw_init and .late_init of SMU. 1388 * And DAL needs to know the maximum sustainable clocks. Thus 1389 * it cannot be put in .late_init(). 1390 */ 1391 ret = smu_init_max_sustainable_clocks(smu); 1392 if (ret) { 1393 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1394 return ret; 1395 } 1396 1397 adev->pm.dpm_enabled = true; 1398 1399 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1400 1401 return 0; 1402 } 1403 1404 static int smu_disable_dpms(struct smu_context *smu) 1405 { 1406 struct amdgpu_device *adev = smu->adev; 1407 int ret = 0; 1408 bool use_baco = !smu->is_apu && 1409 ((amdgpu_in_reset(adev) && 1410 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1411 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1412 1413 /* 1414 * For custom pptable uploading, skip the DPM features 1415 * disable process on Navi1x ASICs. 1416 * - As the gfx related features are under control of 1417 * RLC on those ASICs. RLC reinitialization will be 1418 * needed to reenable them. That will cost much more 1419 * efforts. 1420 * 1421 * - SMU firmware can handle the DPM reenablement 1422 * properly. 1423 */ 1424 if (smu->uploading_custom_pp_table) { 1425 switch (adev->ip_versions[MP1_HWIP][0]) { 1426 case IP_VERSION(11, 0, 0): 1427 case IP_VERSION(11, 0, 5): 1428 case IP_VERSION(11, 0, 9): 1429 case IP_VERSION(11, 0, 7): 1430 case IP_VERSION(11, 0, 11): 1431 case IP_VERSION(11, 5, 0): 1432 case IP_VERSION(11, 0, 12): 1433 case IP_VERSION(11, 0, 13): 1434 return smu_disable_all_features_with_exception(smu, 1435 true, 1436 SMU_FEATURE_COUNT); 1437 default: 1438 break; 1439 } 1440 } 1441 1442 /* 1443 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1444 * on BACO in. Driver involvement is unnecessary. 1445 */ 1446 if (use_baco) { 1447 switch (adev->ip_versions[MP1_HWIP][0]) { 1448 case IP_VERSION(11, 0, 7): 1449 case IP_VERSION(11, 0, 0): 1450 case IP_VERSION(11, 0, 5): 1451 case IP_VERSION(11, 0, 9): 1452 return smu_disable_all_features_with_exception(smu, 1453 true, 1454 SMU_FEATURE_BACO_BIT); 1455 default: 1456 break; 1457 } 1458 } 1459 1460 /* 1461 * For gpu reset, runpm and hibernation through BACO, 1462 * BACO feature has to be kept enabled. 1463 */ 1464 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1465 ret = smu_disable_all_features_with_exception(smu, 1466 false, 1467 SMU_FEATURE_BACO_BIT); 1468 if (ret) 1469 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1470 } else { 1471 ret = smu_system_features_control(smu, false); 1472 if (ret) 1473 dev_err(adev->dev, "Failed to disable smu features.\n"); 1474 } 1475 1476 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1477 adev->gfx.rlc.funcs->stop) 1478 adev->gfx.rlc.funcs->stop(adev); 1479 1480 return ret; 1481 } 1482 1483 static int smu_smc_hw_cleanup(struct smu_context *smu) 1484 { 1485 struct amdgpu_device *adev = smu->adev; 1486 int ret = 0; 1487 1488 cancel_work_sync(&smu->throttling_logging_work); 1489 cancel_work_sync(&smu->interrupt_work); 1490 1491 ret = smu_disable_thermal_alert(smu); 1492 if (ret) { 1493 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1494 return ret; 1495 } 1496 1497 ret = smu_disable_dpms(smu); 1498 if (ret) { 1499 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1500 return ret; 1501 } 1502 1503 return 0; 1504 } 1505 1506 static int smu_hw_fini(void *handle) 1507 { 1508 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1509 struct smu_context *smu = &adev->smu; 1510 1511 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1512 return 0; 1513 1514 smu_dpm_set_vcn_enable(smu, false); 1515 smu_dpm_set_jpeg_enable(smu, false); 1516 1517 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1518 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1519 1520 if (!smu->pm_enabled) 1521 return 0; 1522 1523 adev->pm.dpm_enabled = false; 1524 1525 return smu_smc_hw_cleanup(smu); 1526 } 1527 1528 static int smu_reset(struct smu_context *smu) 1529 { 1530 struct amdgpu_device *adev = smu->adev; 1531 int ret; 1532 1533 amdgpu_gfx_off_ctrl(smu->adev, false); 1534 1535 ret = smu_hw_fini(adev); 1536 if (ret) 1537 return ret; 1538 1539 ret = smu_hw_init(adev); 1540 if (ret) 1541 return ret; 1542 1543 ret = smu_late_init(adev); 1544 if (ret) 1545 return ret; 1546 1547 amdgpu_gfx_off_ctrl(smu->adev, true); 1548 1549 return 0; 1550 } 1551 1552 static int smu_suspend(void *handle) 1553 { 1554 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1555 struct smu_context *smu = &adev->smu; 1556 int ret; 1557 1558 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1559 return 0; 1560 1561 if (!smu->pm_enabled) 1562 return 0; 1563 1564 adev->pm.dpm_enabled = false; 1565 1566 ret = smu_smc_hw_cleanup(smu); 1567 if (ret) 1568 return ret; 1569 1570 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1571 1572 /* skip CGPG when in S0ix */ 1573 if (smu->is_apu && !adev->in_s0ix) 1574 smu_set_gfx_cgpg(&adev->smu, false); 1575 1576 return 0; 1577 } 1578 1579 static int smu_resume(void *handle) 1580 { 1581 int ret; 1582 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1583 struct smu_context *smu = &adev->smu; 1584 1585 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1586 return 0; 1587 1588 if (!smu->pm_enabled) 1589 return 0; 1590 1591 dev_info(adev->dev, "SMU is resuming...\n"); 1592 1593 ret = smu_start_smc_engine(smu); 1594 if (ret) { 1595 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1596 return ret; 1597 } 1598 1599 ret = smu_smc_hw_setup(smu); 1600 if (ret) { 1601 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1602 return ret; 1603 } 1604 1605 if (smu->is_apu) 1606 smu_set_gfx_cgpg(&adev->smu, true); 1607 1608 smu->disable_uclk_switch = 0; 1609 1610 adev->pm.dpm_enabled = true; 1611 1612 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1613 1614 return 0; 1615 } 1616 1617 static int smu_display_configuration_change(void *handle, 1618 const struct amd_pp_display_configuration *display_config) 1619 { 1620 struct smu_context *smu = handle; 1621 int index = 0; 1622 int num_of_active_display = 0; 1623 1624 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1625 return -EOPNOTSUPP; 1626 1627 if (!display_config) 1628 return -EINVAL; 1629 1630 mutex_lock(&smu->mutex); 1631 1632 smu_set_min_dcef_deep_sleep(smu, 1633 display_config->min_dcef_deep_sleep_set_clk / 100); 1634 1635 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1636 if (display_config->displays[index].controller_id != 0) 1637 num_of_active_display++; 1638 } 1639 1640 mutex_unlock(&smu->mutex); 1641 1642 return 0; 1643 } 1644 1645 static int smu_set_clockgating_state(void *handle, 1646 enum amd_clockgating_state state) 1647 { 1648 return 0; 1649 } 1650 1651 static int smu_set_powergating_state(void *handle, 1652 enum amd_powergating_state state) 1653 { 1654 return 0; 1655 } 1656 1657 static int smu_enable_umd_pstate(void *handle, 1658 enum amd_dpm_forced_level *level) 1659 { 1660 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1661 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1662 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1663 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1664 1665 struct smu_context *smu = (struct smu_context*)(handle); 1666 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1667 1668 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1669 return -EINVAL; 1670 1671 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1672 /* enter umd pstate, save current level, disable gfx cg*/ 1673 if (*level & profile_mode_mask) { 1674 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1675 smu_dpm_ctx->enable_umd_pstate = true; 1676 smu_gpo_control(smu, false); 1677 amdgpu_device_ip_set_powergating_state(smu->adev, 1678 AMD_IP_BLOCK_TYPE_GFX, 1679 AMD_PG_STATE_UNGATE); 1680 amdgpu_device_ip_set_clockgating_state(smu->adev, 1681 AMD_IP_BLOCK_TYPE_GFX, 1682 AMD_CG_STATE_UNGATE); 1683 smu_gfx_ulv_control(smu, false); 1684 smu_deep_sleep_control(smu, false); 1685 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1686 } 1687 } else { 1688 /* exit umd pstate, restore level, enable gfx cg*/ 1689 if (!(*level & profile_mode_mask)) { 1690 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1691 *level = smu_dpm_ctx->saved_dpm_level; 1692 smu_dpm_ctx->enable_umd_pstate = false; 1693 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1694 smu_deep_sleep_control(smu, true); 1695 smu_gfx_ulv_control(smu, true); 1696 amdgpu_device_ip_set_clockgating_state(smu->adev, 1697 AMD_IP_BLOCK_TYPE_GFX, 1698 AMD_CG_STATE_GATE); 1699 amdgpu_device_ip_set_powergating_state(smu->adev, 1700 AMD_IP_BLOCK_TYPE_GFX, 1701 AMD_PG_STATE_GATE); 1702 smu_gpo_control(smu, true); 1703 } 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int smu_bump_power_profile_mode(struct smu_context *smu, 1710 long *param, 1711 uint32_t param_size) 1712 { 1713 int ret = 0; 1714 1715 if (smu->ppt_funcs->set_power_profile_mode) 1716 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1717 1718 return ret; 1719 } 1720 1721 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1722 enum amd_dpm_forced_level level, 1723 bool skip_display_settings) 1724 { 1725 int ret = 0; 1726 int index = 0; 1727 long workload; 1728 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1729 1730 if (!skip_display_settings) { 1731 ret = smu_display_config_changed(smu); 1732 if (ret) { 1733 dev_err(smu->adev->dev, "Failed to change display config!"); 1734 return ret; 1735 } 1736 } 1737 1738 ret = smu_apply_clocks_adjust_rules(smu); 1739 if (ret) { 1740 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1741 return ret; 1742 } 1743 1744 if (!skip_display_settings) { 1745 ret = smu_notify_smc_display_config(smu); 1746 if (ret) { 1747 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1748 return ret; 1749 } 1750 } 1751 1752 if (smu_dpm_ctx->dpm_level != level) { 1753 ret = smu_asic_set_performance_level(smu, level); 1754 if (ret) { 1755 dev_err(smu->adev->dev, "Failed to set performance level!"); 1756 return ret; 1757 } 1758 1759 /* update the saved copy */ 1760 smu_dpm_ctx->dpm_level = level; 1761 } 1762 1763 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1764 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1765 index = fls(smu->workload_mask); 1766 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1767 workload = smu->workload_setting[index]; 1768 1769 if (smu->power_profile_mode != workload) 1770 smu_bump_power_profile_mode(smu, &workload, 0); 1771 } 1772 1773 return ret; 1774 } 1775 1776 static int smu_handle_task(struct smu_context *smu, 1777 enum amd_dpm_forced_level level, 1778 enum amd_pp_task task_id, 1779 bool lock_needed) 1780 { 1781 int ret = 0; 1782 1783 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1784 return -EOPNOTSUPP; 1785 1786 if (lock_needed) 1787 mutex_lock(&smu->mutex); 1788 1789 switch (task_id) { 1790 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1791 ret = smu_pre_display_config_changed(smu); 1792 if (ret) 1793 goto out; 1794 ret = smu_adjust_power_state_dynamic(smu, level, false); 1795 break; 1796 case AMD_PP_TASK_COMPLETE_INIT: 1797 case AMD_PP_TASK_READJUST_POWER_STATE: 1798 ret = smu_adjust_power_state_dynamic(smu, level, true); 1799 break; 1800 default: 1801 break; 1802 } 1803 1804 out: 1805 if (lock_needed) 1806 mutex_unlock(&smu->mutex); 1807 1808 return ret; 1809 } 1810 1811 static int smu_handle_dpm_task(void *handle, 1812 enum amd_pp_task task_id, 1813 enum amd_pm_state_type *user_state) 1814 { 1815 struct smu_context *smu = handle; 1816 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1817 1818 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1819 1820 } 1821 1822 static int smu_switch_power_profile(void *handle, 1823 enum PP_SMC_POWER_PROFILE type, 1824 bool en) 1825 { 1826 struct smu_context *smu = handle; 1827 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1828 long workload; 1829 uint32_t index; 1830 1831 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1832 return -EOPNOTSUPP; 1833 1834 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1835 return -EINVAL; 1836 1837 mutex_lock(&smu->mutex); 1838 1839 if (!en) { 1840 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1841 index = fls(smu->workload_mask); 1842 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1843 workload = smu->workload_setting[index]; 1844 } else { 1845 smu->workload_mask |= (1 << smu->workload_prority[type]); 1846 index = fls(smu->workload_mask); 1847 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1848 workload = smu->workload_setting[index]; 1849 } 1850 1851 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1852 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1853 smu_bump_power_profile_mode(smu, &workload, 0); 1854 1855 mutex_unlock(&smu->mutex); 1856 1857 return 0; 1858 } 1859 1860 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1861 { 1862 struct smu_context *smu = handle; 1863 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1864 enum amd_dpm_forced_level level; 1865 1866 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1867 return -EOPNOTSUPP; 1868 1869 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1870 return -EINVAL; 1871 1872 mutex_lock(&(smu->mutex)); 1873 level = smu_dpm_ctx->dpm_level; 1874 mutex_unlock(&(smu->mutex)); 1875 1876 return level; 1877 } 1878 1879 static int smu_force_performance_level(void *handle, 1880 enum amd_dpm_forced_level level) 1881 { 1882 struct smu_context *smu = handle; 1883 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1884 int ret = 0; 1885 1886 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1887 return -EOPNOTSUPP; 1888 1889 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1890 return -EINVAL; 1891 1892 mutex_lock(&smu->mutex); 1893 1894 ret = smu_enable_umd_pstate(smu, &level); 1895 if (ret) { 1896 mutex_unlock(&smu->mutex); 1897 return ret; 1898 } 1899 1900 ret = smu_handle_task(smu, level, 1901 AMD_PP_TASK_READJUST_POWER_STATE, 1902 false); 1903 1904 mutex_unlock(&smu->mutex); 1905 1906 /* reset user dpm clock state */ 1907 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1908 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1909 smu->user_dpm_profile.clk_dependency = 0; 1910 } 1911 1912 return ret; 1913 } 1914 1915 static int smu_set_display_count(void *handle, uint32_t count) 1916 { 1917 struct smu_context *smu = handle; 1918 int ret = 0; 1919 1920 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1921 return -EOPNOTSUPP; 1922 1923 mutex_lock(&smu->mutex); 1924 ret = smu_init_display_count(smu, count); 1925 mutex_unlock(&smu->mutex); 1926 1927 return ret; 1928 } 1929 1930 static int smu_force_smuclk_levels(struct smu_context *smu, 1931 enum smu_clk_type clk_type, 1932 uint32_t mask) 1933 { 1934 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1935 int ret = 0; 1936 1937 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1938 return -EOPNOTSUPP; 1939 1940 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1941 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1942 return -EINVAL; 1943 } 1944 1945 mutex_lock(&smu->mutex); 1946 1947 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1948 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1949 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1950 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1951 smu_set_user_clk_dependencies(smu, clk_type); 1952 } 1953 } 1954 1955 mutex_unlock(&smu->mutex); 1956 1957 return ret; 1958 } 1959 1960 static int smu_force_ppclk_levels(void *handle, 1961 enum pp_clock_type type, 1962 uint32_t mask) 1963 { 1964 struct smu_context *smu = handle; 1965 enum smu_clk_type clk_type; 1966 1967 switch (type) { 1968 case PP_SCLK: 1969 clk_type = SMU_SCLK; break; 1970 case PP_MCLK: 1971 clk_type = SMU_MCLK; break; 1972 case PP_PCIE: 1973 clk_type = SMU_PCIE; break; 1974 case PP_SOCCLK: 1975 clk_type = SMU_SOCCLK; break; 1976 case PP_FCLK: 1977 clk_type = SMU_FCLK; break; 1978 case PP_DCEFCLK: 1979 clk_type = SMU_DCEFCLK; break; 1980 case PP_VCLK: 1981 clk_type = SMU_VCLK; break; 1982 case PP_DCLK: 1983 clk_type = SMU_DCLK; break; 1984 case OD_SCLK: 1985 clk_type = SMU_OD_SCLK; break; 1986 case OD_MCLK: 1987 clk_type = SMU_OD_MCLK; break; 1988 case OD_VDDC_CURVE: 1989 clk_type = SMU_OD_VDDC_CURVE; break; 1990 case OD_RANGE: 1991 clk_type = SMU_OD_RANGE; break; 1992 default: 1993 return -EINVAL; 1994 } 1995 1996 return smu_force_smuclk_levels(smu, clk_type, mask); 1997 } 1998 1999 /* 2000 * On system suspending or resetting, the dpm_enabled 2001 * flag will be cleared. So that those SMU services which 2002 * are not supported will be gated. 2003 * However, the mp1 state setting should still be granted 2004 * even if the dpm_enabled cleared. 2005 */ 2006 static int smu_set_mp1_state(void *handle, 2007 enum pp_mp1_state mp1_state) 2008 { 2009 struct smu_context *smu = handle; 2010 int ret = 0; 2011 2012 if (!smu->pm_enabled) 2013 return -EOPNOTSUPP; 2014 2015 mutex_lock(&smu->mutex); 2016 2017 if (smu->ppt_funcs && 2018 smu->ppt_funcs->set_mp1_state) 2019 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2020 2021 mutex_unlock(&smu->mutex); 2022 2023 return ret; 2024 } 2025 2026 static int smu_set_df_cstate(void *handle, 2027 enum pp_df_cstate state) 2028 { 2029 struct smu_context *smu = handle; 2030 int ret = 0; 2031 2032 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2033 return -EOPNOTSUPP; 2034 2035 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2036 return 0; 2037 2038 mutex_lock(&smu->mutex); 2039 2040 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2041 if (ret) 2042 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2043 2044 mutex_unlock(&smu->mutex); 2045 2046 return ret; 2047 } 2048 2049 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2050 { 2051 int ret = 0; 2052 2053 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2054 return -EOPNOTSUPP; 2055 2056 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2057 return 0; 2058 2059 mutex_lock(&smu->mutex); 2060 2061 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2062 if (ret) 2063 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2064 2065 mutex_unlock(&smu->mutex); 2066 2067 return ret; 2068 } 2069 2070 int smu_write_watermarks_table(struct smu_context *smu) 2071 { 2072 int ret = 0; 2073 2074 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2075 return -EOPNOTSUPP; 2076 2077 mutex_lock(&smu->mutex); 2078 2079 ret = smu_set_watermarks_table(smu, NULL); 2080 2081 mutex_unlock(&smu->mutex); 2082 2083 return ret; 2084 } 2085 2086 static int smu_set_watermarks_for_clock_ranges(void *handle, 2087 struct pp_smu_wm_range_sets *clock_ranges) 2088 { 2089 struct smu_context *smu = handle; 2090 int ret = 0; 2091 2092 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2093 return -EOPNOTSUPP; 2094 2095 if (smu->disable_watermark) 2096 return 0; 2097 2098 mutex_lock(&smu->mutex); 2099 2100 ret = smu_set_watermarks_table(smu, clock_ranges); 2101 2102 mutex_unlock(&smu->mutex); 2103 2104 return ret; 2105 } 2106 2107 int smu_set_ac_dc(struct smu_context *smu) 2108 { 2109 int ret = 0; 2110 2111 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2112 return -EOPNOTSUPP; 2113 2114 /* controlled by firmware */ 2115 if (smu->dc_controlled_by_gpio) 2116 return 0; 2117 2118 mutex_lock(&smu->mutex); 2119 ret = smu_set_power_source(smu, 2120 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2121 SMU_POWER_SOURCE_DC); 2122 if (ret) 2123 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2124 smu->adev->pm.ac_power ? "AC" : "DC"); 2125 mutex_unlock(&smu->mutex); 2126 2127 return ret; 2128 } 2129 2130 const struct amd_ip_funcs smu_ip_funcs = { 2131 .name = "smu", 2132 .early_init = smu_early_init, 2133 .late_init = smu_late_init, 2134 .sw_init = smu_sw_init, 2135 .sw_fini = smu_sw_fini, 2136 .hw_init = smu_hw_init, 2137 .hw_fini = smu_hw_fini, 2138 .suspend = smu_suspend, 2139 .resume = smu_resume, 2140 .is_idle = NULL, 2141 .check_soft_reset = NULL, 2142 .wait_for_idle = NULL, 2143 .soft_reset = NULL, 2144 .set_clockgating_state = smu_set_clockgating_state, 2145 .set_powergating_state = smu_set_powergating_state, 2146 .enable_umd_pstate = smu_enable_umd_pstate, 2147 }; 2148 2149 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2150 { 2151 .type = AMD_IP_BLOCK_TYPE_SMC, 2152 .major = 11, 2153 .minor = 0, 2154 .rev = 0, 2155 .funcs = &smu_ip_funcs, 2156 }; 2157 2158 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2159 { 2160 .type = AMD_IP_BLOCK_TYPE_SMC, 2161 .major = 12, 2162 .minor = 0, 2163 .rev = 0, 2164 .funcs = &smu_ip_funcs, 2165 }; 2166 2167 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2168 { 2169 .type = AMD_IP_BLOCK_TYPE_SMC, 2170 .major = 13, 2171 .minor = 0, 2172 .rev = 0, 2173 .funcs = &smu_ip_funcs, 2174 }; 2175 2176 static int smu_load_microcode(void *handle) 2177 { 2178 struct smu_context *smu = handle; 2179 struct amdgpu_device *adev = smu->adev; 2180 int ret = 0; 2181 2182 if (!smu->pm_enabled) 2183 return -EOPNOTSUPP; 2184 2185 /* This should be used for non PSP loading */ 2186 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2187 return 0; 2188 2189 if (smu->ppt_funcs->load_microcode) { 2190 ret = smu->ppt_funcs->load_microcode(smu); 2191 if (ret) { 2192 dev_err(adev->dev, "Load microcode failed\n"); 2193 return ret; 2194 } 2195 } 2196 2197 if (smu->ppt_funcs->check_fw_status) { 2198 ret = smu->ppt_funcs->check_fw_status(smu); 2199 if (ret) { 2200 dev_err(adev->dev, "SMC is not ready\n"); 2201 return ret; 2202 } 2203 } 2204 2205 return ret; 2206 } 2207 2208 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2209 { 2210 int ret = 0; 2211 2212 mutex_lock(&smu->mutex); 2213 2214 if (smu->ppt_funcs->set_gfx_cgpg) 2215 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2216 2217 mutex_unlock(&smu->mutex); 2218 2219 return ret; 2220 } 2221 2222 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2223 { 2224 struct smu_context *smu = handle; 2225 int ret = 0; 2226 2227 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2228 return -EOPNOTSUPP; 2229 2230 mutex_lock(&smu->mutex); 2231 2232 if (smu->ppt_funcs->set_fan_speed_rpm) { 2233 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2234 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2235 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2236 smu->user_dpm_profile.fan_speed_rpm = speed; 2237 2238 /* Override custom PWM setting as they cannot co-exist */ 2239 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2240 smu->user_dpm_profile.fan_speed_pwm = 0; 2241 } 2242 } 2243 2244 mutex_unlock(&smu->mutex); 2245 2246 return ret; 2247 } 2248 2249 /** 2250 * smu_get_power_limit - Request one of the SMU Power Limits 2251 * 2252 * @handle: pointer to smu context 2253 * @limit: requested limit is written back to this variable 2254 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2255 * @pp_power_type: &pp_power_type type of power 2256 * Return: 0 on success, <0 on error 2257 * 2258 */ 2259 int smu_get_power_limit(void *handle, 2260 uint32_t *limit, 2261 enum pp_power_limit_level pp_limit_level, 2262 enum pp_power_type pp_power_type) 2263 { 2264 struct smu_context *smu = handle; 2265 struct amdgpu_device *adev = smu->adev; 2266 enum smu_ppt_limit_level limit_level; 2267 uint32_t limit_type; 2268 int ret = 0; 2269 2270 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2271 return -EOPNOTSUPP; 2272 2273 switch(pp_power_type) { 2274 case PP_PWR_TYPE_SUSTAINED: 2275 limit_type = SMU_DEFAULT_PPT_LIMIT; 2276 break; 2277 case PP_PWR_TYPE_FAST: 2278 limit_type = SMU_FAST_PPT_LIMIT; 2279 break; 2280 default: 2281 return -EOPNOTSUPP; 2282 break; 2283 } 2284 2285 switch(pp_limit_level){ 2286 case PP_PWR_LIMIT_CURRENT: 2287 limit_level = SMU_PPT_LIMIT_CURRENT; 2288 break; 2289 case PP_PWR_LIMIT_DEFAULT: 2290 limit_level = SMU_PPT_LIMIT_DEFAULT; 2291 break; 2292 case PP_PWR_LIMIT_MAX: 2293 limit_level = SMU_PPT_LIMIT_MAX; 2294 break; 2295 case PP_PWR_LIMIT_MIN: 2296 default: 2297 return -EOPNOTSUPP; 2298 break; 2299 } 2300 2301 mutex_lock(&smu->mutex); 2302 2303 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2304 if (smu->ppt_funcs->get_ppt_limit) 2305 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2306 } else { 2307 switch (limit_level) { 2308 case SMU_PPT_LIMIT_CURRENT: 2309 switch (adev->ip_versions[MP1_HWIP][0]) { 2310 case IP_VERSION(13, 0, 2): 2311 case IP_VERSION(11, 0, 7): 2312 case IP_VERSION(11, 0, 11): 2313 case IP_VERSION(11, 0, 12): 2314 case IP_VERSION(11, 0, 13): 2315 ret = smu_get_asic_power_limits(smu, 2316 &smu->current_power_limit, 2317 NULL, 2318 NULL); 2319 break; 2320 default: 2321 break; 2322 } 2323 *limit = smu->current_power_limit; 2324 break; 2325 case SMU_PPT_LIMIT_DEFAULT: 2326 *limit = smu->default_power_limit; 2327 break; 2328 case SMU_PPT_LIMIT_MAX: 2329 *limit = smu->max_power_limit; 2330 break; 2331 default: 2332 break; 2333 } 2334 } 2335 2336 mutex_unlock(&smu->mutex); 2337 2338 return ret; 2339 } 2340 2341 static int smu_set_power_limit(void *handle, uint32_t limit) 2342 { 2343 struct smu_context *smu = handle; 2344 uint32_t limit_type = limit >> 24; 2345 int ret = 0; 2346 2347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2348 return -EOPNOTSUPP; 2349 2350 mutex_lock(&smu->mutex); 2351 2352 limit &= (1<<24)-1; 2353 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2354 if (smu->ppt_funcs->set_power_limit) { 2355 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2356 goto out; 2357 } 2358 2359 if (limit > smu->max_power_limit) { 2360 dev_err(smu->adev->dev, 2361 "New power limit (%d) is over the max allowed %d\n", 2362 limit, smu->max_power_limit); 2363 ret = -EINVAL; 2364 goto out; 2365 } 2366 2367 if (!limit) 2368 limit = smu->current_power_limit; 2369 2370 if (smu->ppt_funcs->set_power_limit) { 2371 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2372 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2373 smu->user_dpm_profile.power_limit = limit; 2374 } 2375 2376 out: 2377 mutex_unlock(&smu->mutex); 2378 2379 return ret; 2380 } 2381 2382 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2383 { 2384 int ret = 0; 2385 2386 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2387 return -EOPNOTSUPP; 2388 2389 mutex_lock(&smu->mutex); 2390 2391 if (smu->ppt_funcs->print_clk_levels) 2392 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2393 2394 mutex_unlock(&smu->mutex); 2395 2396 return ret; 2397 } 2398 2399 static int smu_print_ppclk_levels(void *handle, 2400 enum pp_clock_type type, 2401 char *buf) 2402 { 2403 struct smu_context *smu = handle; 2404 enum smu_clk_type clk_type; 2405 2406 switch (type) { 2407 case PP_SCLK: 2408 clk_type = SMU_SCLK; break; 2409 case PP_MCLK: 2410 clk_type = SMU_MCLK; break; 2411 case PP_PCIE: 2412 clk_type = SMU_PCIE; break; 2413 case PP_SOCCLK: 2414 clk_type = SMU_SOCCLK; break; 2415 case PP_FCLK: 2416 clk_type = SMU_FCLK; break; 2417 case PP_DCEFCLK: 2418 clk_type = SMU_DCEFCLK; break; 2419 case PP_VCLK: 2420 clk_type = SMU_VCLK; break; 2421 case PP_DCLK: 2422 clk_type = SMU_DCLK; break; 2423 case OD_SCLK: 2424 clk_type = SMU_OD_SCLK; break; 2425 case OD_MCLK: 2426 clk_type = SMU_OD_MCLK; break; 2427 case OD_VDDC_CURVE: 2428 clk_type = SMU_OD_VDDC_CURVE; break; 2429 case OD_RANGE: 2430 clk_type = SMU_OD_RANGE; break; 2431 case OD_VDDGFX_OFFSET: 2432 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2433 case OD_CCLK: 2434 clk_type = SMU_OD_CCLK; break; 2435 default: 2436 return -EINVAL; 2437 } 2438 2439 return smu_print_smuclk_levels(smu, clk_type, buf); 2440 } 2441 2442 static int smu_od_edit_dpm_table(void *handle, 2443 enum PP_OD_DPM_TABLE_COMMAND type, 2444 long *input, uint32_t size) 2445 { 2446 struct smu_context *smu = handle; 2447 int ret = 0; 2448 2449 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2450 return -EOPNOTSUPP; 2451 2452 mutex_lock(&smu->mutex); 2453 2454 if (smu->ppt_funcs->od_edit_dpm_table) { 2455 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2456 } 2457 2458 mutex_unlock(&smu->mutex); 2459 2460 return ret; 2461 } 2462 2463 static int smu_read_sensor(void *handle, 2464 int sensor, 2465 void *data, 2466 int *size_arg) 2467 { 2468 struct smu_context *smu = handle; 2469 struct smu_umd_pstate_table *pstate_table = 2470 &smu->pstate_table; 2471 int ret = 0; 2472 uint32_t *size, size_val; 2473 2474 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2475 return -EOPNOTSUPP; 2476 2477 if (!data || !size_arg) 2478 return -EINVAL; 2479 2480 size_val = *size_arg; 2481 size = &size_val; 2482 2483 mutex_lock(&smu->mutex); 2484 2485 if (smu->ppt_funcs->read_sensor) 2486 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2487 goto unlock; 2488 2489 switch (sensor) { 2490 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2491 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2492 *size = 4; 2493 break; 2494 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2495 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2496 *size = 4; 2497 break; 2498 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2499 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2500 *size = 8; 2501 break; 2502 case AMDGPU_PP_SENSOR_UVD_POWER: 2503 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2504 *size = 4; 2505 break; 2506 case AMDGPU_PP_SENSOR_VCE_POWER: 2507 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2508 *size = 4; 2509 break; 2510 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2511 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2512 *size = 4; 2513 break; 2514 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2515 *(uint32_t *)data = 0; 2516 *size = 4; 2517 break; 2518 default: 2519 *size = 0; 2520 ret = -EOPNOTSUPP; 2521 break; 2522 } 2523 2524 unlock: 2525 mutex_unlock(&smu->mutex); 2526 2527 // assign uint32_t to int 2528 *size_arg = size_val; 2529 2530 return ret; 2531 } 2532 2533 static int smu_get_power_profile_mode(void *handle, char *buf) 2534 { 2535 struct smu_context *smu = handle; 2536 int ret = 0; 2537 2538 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2539 !smu->ppt_funcs->get_power_profile_mode) 2540 return -EOPNOTSUPP; 2541 if (!buf) 2542 return -EINVAL; 2543 2544 mutex_lock(&smu->mutex); 2545 2546 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2547 2548 mutex_unlock(&smu->mutex); 2549 2550 return ret; 2551 } 2552 2553 static int smu_set_power_profile_mode(void *handle, 2554 long *param, 2555 uint32_t param_size) 2556 { 2557 struct smu_context *smu = handle; 2558 int ret = 0; 2559 2560 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2561 !smu->ppt_funcs->set_power_profile_mode) 2562 return -EOPNOTSUPP; 2563 2564 mutex_lock(&smu->mutex); 2565 2566 smu_bump_power_profile_mode(smu, param, param_size); 2567 2568 mutex_unlock(&smu->mutex); 2569 2570 return ret; 2571 } 2572 2573 2574 static u32 smu_get_fan_control_mode(void *handle) 2575 { 2576 struct smu_context *smu = handle; 2577 u32 ret = 0; 2578 2579 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2580 return AMD_FAN_CTRL_NONE; 2581 2582 mutex_lock(&smu->mutex); 2583 2584 if (smu->ppt_funcs->get_fan_control_mode) 2585 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2586 2587 mutex_unlock(&smu->mutex); 2588 2589 return ret; 2590 } 2591 2592 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2593 { 2594 int ret = 0; 2595 2596 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2597 return -EOPNOTSUPP; 2598 2599 mutex_lock(&smu->mutex); 2600 2601 if (smu->ppt_funcs->set_fan_control_mode) { 2602 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2603 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2604 smu->user_dpm_profile.fan_mode = value; 2605 } 2606 2607 mutex_unlock(&smu->mutex); 2608 2609 /* reset user dpm fan speed */ 2610 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2611 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2612 smu->user_dpm_profile.fan_speed_pwm = 0; 2613 smu->user_dpm_profile.fan_speed_rpm = 0; 2614 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2615 } 2616 2617 return ret; 2618 } 2619 2620 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2621 { 2622 struct smu_context *smu = handle; 2623 2624 smu_set_fan_control_mode(smu, value); 2625 } 2626 2627 2628 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2629 { 2630 struct smu_context *smu = handle; 2631 int ret = 0; 2632 2633 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2634 return -EOPNOTSUPP; 2635 2636 mutex_lock(&smu->mutex); 2637 2638 if (smu->ppt_funcs->get_fan_speed_pwm) 2639 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2640 2641 mutex_unlock(&smu->mutex); 2642 2643 return ret; 2644 } 2645 2646 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2647 { 2648 struct smu_context *smu = handle; 2649 int ret = 0; 2650 2651 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2652 return -EOPNOTSUPP; 2653 2654 mutex_lock(&smu->mutex); 2655 2656 if (smu->ppt_funcs->set_fan_speed_pwm) { 2657 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2658 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2659 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2660 smu->user_dpm_profile.fan_speed_pwm = speed; 2661 2662 /* Override custom RPM setting as they cannot co-exist */ 2663 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2664 smu->user_dpm_profile.fan_speed_rpm = 0; 2665 } 2666 } 2667 2668 mutex_unlock(&smu->mutex); 2669 2670 return ret; 2671 } 2672 2673 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2674 { 2675 struct smu_context *smu = handle; 2676 int ret = 0; 2677 2678 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2679 return -EOPNOTSUPP; 2680 2681 mutex_lock(&smu->mutex); 2682 2683 if (smu->ppt_funcs->get_fan_speed_rpm) 2684 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2685 2686 mutex_unlock(&smu->mutex); 2687 2688 return ret; 2689 } 2690 2691 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2692 { 2693 struct smu_context *smu = handle; 2694 int ret = 0; 2695 2696 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2697 return -EOPNOTSUPP; 2698 2699 mutex_lock(&smu->mutex); 2700 2701 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2702 2703 mutex_unlock(&smu->mutex); 2704 2705 return ret; 2706 } 2707 2708 static int smu_get_clock_by_type_with_latency(void *handle, 2709 enum amd_pp_clock_type type, 2710 struct pp_clock_levels_with_latency *clocks) 2711 { 2712 struct smu_context *smu = handle; 2713 enum smu_clk_type clk_type; 2714 int ret = 0; 2715 2716 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2717 return -EOPNOTSUPP; 2718 2719 mutex_lock(&smu->mutex); 2720 2721 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2722 switch (type) { 2723 case amd_pp_sys_clock: 2724 clk_type = SMU_GFXCLK; 2725 break; 2726 case amd_pp_mem_clock: 2727 clk_type = SMU_MCLK; 2728 break; 2729 case amd_pp_dcef_clock: 2730 clk_type = SMU_DCEFCLK; 2731 break; 2732 case amd_pp_disp_clock: 2733 clk_type = SMU_DISPCLK; 2734 break; 2735 default: 2736 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2737 mutex_unlock(&smu->mutex); 2738 return -EINVAL; 2739 } 2740 2741 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2742 } 2743 2744 mutex_unlock(&smu->mutex); 2745 2746 return ret; 2747 } 2748 2749 static int smu_display_clock_voltage_request(void *handle, 2750 struct pp_display_clock_request *clock_req) 2751 { 2752 struct smu_context *smu = handle; 2753 int ret = 0; 2754 2755 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2756 return -EOPNOTSUPP; 2757 2758 mutex_lock(&smu->mutex); 2759 2760 if (smu->ppt_funcs->display_clock_voltage_request) 2761 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2762 2763 mutex_unlock(&smu->mutex); 2764 2765 return ret; 2766 } 2767 2768 2769 static int smu_display_disable_memory_clock_switch(void *handle, 2770 bool disable_memory_clock_switch) 2771 { 2772 struct smu_context *smu = handle; 2773 int ret = -EINVAL; 2774 2775 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2776 return -EOPNOTSUPP; 2777 2778 mutex_lock(&smu->mutex); 2779 2780 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2781 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2782 2783 mutex_unlock(&smu->mutex); 2784 2785 return ret; 2786 } 2787 2788 static int smu_set_xgmi_pstate(void *handle, 2789 uint32_t pstate) 2790 { 2791 struct smu_context *smu = handle; 2792 int ret = 0; 2793 2794 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2795 return -EOPNOTSUPP; 2796 2797 mutex_lock(&smu->mutex); 2798 2799 if (smu->ppt_funcs->set_xgmi_pstate) 2800 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2801 2802 mutex_unlock(&smu->mutex); 2803 2804 if(ret) 2805 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2806 2807 return ret; 2808 } 2809 2810 static int smu_get_baco_capability(void *handle, bool *cap) 2811 { 2812 struct smu_context *smu = handle; 2813 int ret = 0; 2814 2815 *cap = false; 2816 2817 if (!smu->pm_enabled) 2818 return 0; 2819 2820 mutex_lock(&smu->mutex); 2821 2822 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2823 *cap = smu->ppt_funcs->baco_is_support(smu); 2824 2825 mutex_unlock(&smu->mutex); 2826 2827 return ret; 2828 } 2829 2830 static int smu_baco_set_state(void *handle, int state) 2831 { 2832 struct smu_context *smu = handle; 2833 int ret = 0; 2834 2835 if (!smu->pm_enabled) 2836 return -EOPNOTSUPP; 2837 2838 if (state == 0) { 2839 mutex_lock(&smu->mutex); 2840 2841 if (smu->ppt_funcs->baco_exit) 2842 ret = smu->ppt_funcs->baco_exit(smu); 2843 2844 mutex_unlock(&smu->mutex); 2845 } else if (state == 1) { 2846 mutex_lock(&smu->mutex); 2847 2848 if (smu->ppt_funcs->baco_enter) 2849 ret = smu->ppt_funcs->baco_enter(smu); 2850 2851 mutex_unlock(&smu->mutex); 2852 2853 } else { 2854 return -EINVAL; 2855 } 2856 2857 if (ret) 2858 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2859 (state)?"enter":"exit"); 2860 2861 return ret; 2862 } 2863 2864 bool smu_mode1_reset_is_support(struct smu_context *smu) 2865 { 2866 bool ret = false; 2867 2868 if (!smu->pm_enabled) 2869 return false; 2870 2871 mutex_lock(&smu->mutex); 2872 2873 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2874 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2875 2876 mutex_unlock(&smu->mutex); 2877 2878 return ret; 2879 } 2880 2881 bool smu_mode2_reset_is_support(struct smu_context *smu) 2882 { 2883 bool ret = false; 2884 2885 if (!smu->pm_enabled) 2886 return false; 2887 2888 mutex_lock(&smu->mutex); 2889 2890 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2891 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2892 2893 mutex_unlock(&smu->mutex); 2894 2895 return ret; 2896 } 2897 2898 int smu_mode1_reset(struct smu_context *smu) 2899 { 2900 int ret = 0; 2901 2902 if (!smu->pm_enabled) 2903 return -EOPNOTSUPP; 2904 2905 mutex_lock(&smu->mutex); 2906 2907 if (smu->ppt_funcs->mode1_reset) 2908 ret = smu->ppt_funcs->mode1_reset(smu); 2909 2910 mutex_unlock(&smu->mutex); 2911 2912 return ret; 2913 } 2914 2915 static int smu_mode2_reset(void *handle) 2916 { 2917 struct smu_context *smu = handle; 2918 int ret = 0; 2919 2920 if (!smu->pm_enabled) 2921 return -EOPNOTSUPP; 2922 2923 mutex_lock(&smu->mutex); 2924 2925 if (smu->ppt_funcs->mode2_reset) 2926 ret = smu->ppt_funcs->mode2_reset(smu); 2927 2928 mutex_unlock(&smu->mutex); 2929 2930 if (ret) 2931 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2932 2933 return ret; 2934 } 2935 2936 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2937 struct pp_smu_nv_clock_table *max_clocks) 2938 { 2939 struct smu_context *smu = handle; 2940 int ret = 0; 2941 2942 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2943 return -EOPNOTSUPP; 2944 2945 mutex_lock(&smu->mutex); 2946 2947 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2948 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2949 2950 mutex_unlock(&smu->mutex); 2951 2952 return ret; 2953 } 2954 2955 static int smu_get_uclk_dpm_states(void *handle, 2956 unsigned int *clock_values_in_khz, 2957 unsigned int *num_states) 2958 { 2959 struct smu_context *smu = handle; 2960 int ret = 0; 2961 2962 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2963 return -EOPNOTSUPP; 2964 2965 mutex_lock(&smu->mutex); 2966 2967 if (smu->ppt_funcs->get_uclk_dpm_states) 2968 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2969 2970 mutex_unlock(&smu->mutex); 2971 2972 return ret; 2973 } 2974 2975 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2976 { 2977 struct smu_context *smu = handle; 2978 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2979 2980 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2981 return -EOPNOTSUPP; 2982 2983 mutex_lock(&smu->mutex); 2984 2985 if (smu->ppt_funcs->get_current_power_state) 2986 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2987 2988 mutex_unlock(&smu->mutex); 2989 2990 return pm_state; 2991 } 2992 2993 static int smu_get_dpm_clock_table(void *handle, 2994 struct dpm_clocks *clock_table) 2995 { 2996 struct smu_context *smu = handle; 2997 int ret = 0; 2998 2999 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3000 return -EOPNOTSUPP; 3001 3002 mutex_lock(&smu->mutex); 3003 3004 if (smu->ppt_funcs->get_dpm_clock_table) 3005 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3006 3007 mutex_unlock(&smu->mutex); 3008 3009 return ret; 3010 } 3011 3012 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3013 { 3014 struct smu_context *smu = handle; 3015 ssize_t size; 3016 3017 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3018 return -EOPNOTSUPP; 3019 3020 if (!smu->ppt_funcs->get_gpu_metrics) 3021 return -EOPNOTSUPP; 3022 3023 mutex_lock(&smu->mutex); 3024 3025 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 3026 3027 mutex_unlock(&smu->mutex); 3028 3029 return size; 3030 } 3031 3032 static int smu_enable_mgpu_fan_boost(void *handle) 3033 { 3034 struct smu_context *smu = handle; 3035 int ret = 0; 3036 3037 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3038 return -EOPNOTSUPP; 3039 3040 mutex_lock(&smu->mutex); 3041 3042 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3043 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3044 3045 mutex_unlock(&smu->mutex); 3046 3047 return ret; 3048 } 3049 3050 static int smu_gfx_state_change_set(void *handle, 3051 uint32_t state) 3052 { 3053 struct smu_context *smu = handle; 3054 int ret = 0; 3055 3056 mutex_lock(&smu->mutex); 3057 if (smu->ppt_funcs->gfx_state_change_set) 3058 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3059 mutex_unlock(&smu->mutex); 3060 3061 return ret; 3062 } 3063 3064 int smu_set_light_sbr(struct smu_context *smu, bool enable) 3065 { 3066 int ret = 0; 3067 3068 mutex_lock(&smu->mutex); 3069 if (smu->ppt_funcs->set_light_sbr) 3070 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 3071 mutex_unlock(&smu->mutex); 3072 3073 return ret; 3074 } 3075 3076 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3077 { 3078 int ret = -EOPNOTSUPP; 3079 3080 mutex_lock(&smu->mutex); 3081 if (smu->ppt_funcs && 3082 smu->ppt_funcs->get_ecc_info) 3083 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3084 mutex_unlock(&smu->mutex); 3085 3086 return ret; 3087 3088 } 3089 3090 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3091 { 3092 struct smu_context *smu = handle; 3093 struct smu_table_context *smu_table = &smu->smu_table; 3094 struct smu_table *memory_pool = &smu_table->memory_pool; 3095 3096 if (!addr || !size) 3097 return -EINVAL; 3098 3099 *addr = NULL; 3100 *size = 0; 3101 mutex_lock(&smu->mutex); 3102 if (memory_pool->bo) { 3103 *addr = memory_pool->cpu_addr; 3104 *size = memory_pool->size; 3105 } 3106 mutex_unlock(&smu->mutex); 3107 3108 return 0; 3109 } 3110 3111 static const struct amd_pm_funcs swsmu_pm_funcs = { 3112 /* export for sysfs */ 3113 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3114 .get_fan_control_mode = smu_get_fan_control_mode, 3115 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3116 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3117 .force_clock_level = smu_force_ppclk_levels, 3118 .print_clock_levels = smu_print_ppclk_levels, 3119 .force_performance_level = smu_force_performance_level, 3120 .read_sensor = smu_read_sensor, 3121 .get_performance_level = smu_get_performance_level, 3122 .get_current_power_state = smu_get_current_power_state, 3123 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3124 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3125 .get_pp_num_states = smu_get_power_num_states, 3126 .get_pp_table = smu_sys_get_pp_table, 3127 .set_pp_table = smu_sys_set_pp_table, 3128 .switch_power_profile = smu_switch_power_profile, 3129 /* export to amdgpu */ 3130 .dispatch_tasks = smu_handle_dpm_task, 3131 .load_firmware = smu_load_microcode, 3132 .set_powergating_by_smu = smu_dpm_set_power_gate, 3133 .set_power_limit = smu_set_power_limit, 3134 .get_power_limit = smu_get_power_limit, 3135 .get_power_profile_mode = smu_get_power_profile_mode, 3136 .set_power_profile_mode = smu_set_power_profile_mode, 3137 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3138 .set_mp1_state = smu_set_mp1_state, 3139 .gfx_state_change_set = smu_gfx_state_change_set, 3140 /* export to DC */ 3141 .get_sclk = smu_get_sclk, 3142 .get_mclk = smu_get_mclk, 3143 .display_configuration_change = smu_display_configuration_change, 3144 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3145 .display_clock_voltage_request = smu_display_clock_voltage_request, 3146 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3147 .set_active_display_count = smu_set_display_count, 3148 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3149 .get_asic_baco_capability = smu_get_baco_capability, 3150 .set_asic_baco_state = smu_baco_set_state, 3151 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3152 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3153 .asic_reset_mode_2 = smu_mode2_reset, 3154 .set_df_cstate = smu_set_df_cstate, 3155 .set_xgmi_pstate = smu_set_xgmi_pstate, 3156 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3157 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3158 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3159 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3160 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3161 .get_dpm_clock_table = smu_get_dpm_clock_table, 3162 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3163 }; 3164 3165 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3166 uint64_t event_arg) 3167 { 3168 int ret = -EINVAL; 3169 struct smu_context *smu = &adev->smu; 3170 3171 if (smu->ppt_funcs->wait_for_event) { 3172 mutex_lock(&smu->mutex); 3173 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3174 mutex_unlock(&smu->mutex); 3175 } 3176 3177 return ret; 3178 } 3179 3180 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3181 { 3182 3183 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3184 return -EOPNOTSUPP; 3185 3186 /* Confirm the buffer allocated is of correct size */ 3187 if (size != smu->stb_context.stb_buf_size) 3188 return -EINVAL; 3189 3190 /* 3191 * No need to lock smu mutex as we access STB directly through MMIO 3192 * and not going through SMU messaging route (for now at least). 3193 * For registers access rely on implementation internal locking. 3194 */ 3195 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3196 } 3197 3198 #if defined(CONFIG_DEBUG_FS) 3199 3200 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3201 { 3202 struct amdgpu_device *adev = filp->f_inode->i_private; 3203 struct smu_context *smu = &adev->smu; 3204 unsigned char *buf; 3205 int r; 3206 3207 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3208 if (!buf) 3209 return -ENOMEM; 3210 3211 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3212 if (r) 3213 goto out; 3214 3215 filp->private_data = buf; 3216 3217 return 0; 3218 3219 out: 3220 kvfree(buf); 3221 return r; 3222 } 3223 3224 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3225 loff_t *pos) 3226 { 3227 struct amdgpu_device *adev = filp->f_inode->i_private; 3228 struct smu_context *smu = &adev->smu; 3229 3230 3231 if (!filp->private_data) 3232 return -EINVAL; 3233 3234 return simple_read_from_buffer(buf, 3235 size, 3236 pos, filp->private_data, 3237 smu->stb_context.stb_buf_size); 3238 } 3239 3240 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3241 { 3242 kvfree(filp->private_data); 3243 filp->private_data = NULL; 3244 3245 return 0; 3246 } 3247 3248 /* 3249 * We have to define not only read method but also 3250 * open and release because .read takes up to PAGE_SIZE 3251 * data each time so and so is invoked multiple times. 3252 * We allocate the STB buffer in .open and release it 3253 * in .release 3254 */ 3255 static const struct file_operations smu_stb_debugfs_fops = { 3256 .owner = THIS_MODULE, 3257 .open = smu_stb_debugfs_open, 3258 .read = smu_stb_debugfs_read, 3259 .release = smu_stb_debugfs_release, 3260 .llseek = default_llseek, 3261 }; 3262 3263 #endif 3264 3265 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3266 { 3267 #if defined(CONFIG_DEBUG_FS) 3268 3269 struct smu_context *smu = &adev->smu; 3270 3271 if (!smu->stb_context.stb_buf_size) 3272 return; 3273 3274 debugfs_create_file_size("amdgpu_smu_stb_dump", 3275 S_IRUSR, 3276 adev_to_drm(adev)->primary->debugfs_root, 3277 adev, 3278 &smu_stb_debugfs_fops, 3279 smu->stb_context.stb_buf_size); 3280 #endif 3281 3282 } 3283