1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 70 71 static int smu_sys_get_pp_feature_mask(void *handle, 72 char *buf) 73 { 74 struct smu_context *smu = handle; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 return smu_get_pp_feature_mask(smu, buf); 80 } 81 82 static int smu_sys_set_pp_feature_mask(void *handle, 83 uint64_t new_mask) 84 { 85 struct smu_context *smu = handle; 86 87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 88 return -EOPNOTSUPP; 89 90 return smu_set_pp_feature_mask(smu, new_mask); 91 } 92 93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 94 { 95 if (!smu->ppt_funcs->set_gfx_off_residency) 96 return -EINVAL; 97 98 return smu_set_gfx_off_residency(smu, value); 99 } 100 101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 102 { 103 if (!smu->ppt_funcs->get_gfx_off_residency) 104 return -EINVAL; 105 106 return smu_get_gfx_off_residency(smu, value); 107 } 108 109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 110 { 111 if (!smu->ppt_funcs->get_gfx_off_entrycount) 112 return -EINVAL; 113 114 return smu_get_gfx_off_entrycount(smu, value); 115 } 116 117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 118 { 119 if (!smu->ppt_funcs->get_gfx_off_status) 120 return -EINVAL; 121 122 *value = smu_get_gfx_off_status(smu); 123 124 return 0; 125 } 126 127 int smu_set_soft_freq_range(struct smu_context *smu, 128 enum smu_clk_type clk_type, 129 uint32_t min, 130 uint32_t max) 131 { 132 int ret = 0; 133 134 if (smu->ppt_funcs->set_soft_freq_limited_range) 135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 136 clk_type, 137 min, 138 max); 139 140 return ret; 141 } 142 143 int smu_get_dpm_freq_range(struct smu_context *smu, 144 enum smu_clk_type clk_type, 145 uint32_t *min, 146 uint32_t *max) 147 { 148 int ret = -ENOTSUPP; 149 150 if (!min && !max) 151 return -EINVAL; 152 153 if (smu->ppt_funcs->get_dpm_ultimate_freq) 154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 155 clk_type, 156 min, 157 max); 158 159 return ret; 160 } 161 162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 163 { 164 if (!smu->ppt_funcs || !smu->ppt_funcs->set_gfx_power_up_by_imu) 165 return -EOPNOTSUPP; 166 167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 168 } 169 170 static u32 smu_get_mclk(void *handle, bool low) 171 { 172 struct smu_context *smu = handle; 173 uint32_t clk_freq; 174 int ret = 0; 175 176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 177 low ? &clk_freq : NULL, 178 !low ? &clk_freq : NULL); 179 if (ret) 180 return 0; 181 return clk_freq * 100; 182 } 183 184 static u32 smu_get_sclk(void *handle, bool low) 185 { 186 struct smu_context *smu = handle; 187 uint32_t clk_freq; 188 int ret = 0; 189 190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 191 low ? &clk_freq : NULL, 192 !low ? &clk_freq : NULL); 193 if (ret) 194 return 0; 195 return clk_freq * 100; 196 } 197 198 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 199 bool enable) 200 { 201 struct smu_power_context *smu_power = &smu->smu_power; 202 struct smu_power_gate *power_gate = &smu_power->power_gate; 203 int ret = 0; 204 205 if (!smu->ppt_funcs->dpm_set_vcn_enable) 206 return 0; 207 208 if (atomic_read(&power_gate->vcn_gated) ^ enable) 209 return 0; 210 211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 212 if (!ret) 213 atomic_set(&power_gate->vcn_gated, !enable); 214 215 return ret; 216 } 217 218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 219 bool enable) 220 { 221 struct smu_power_context *smu_power = &smu->smu_power; 222 struct smu_power_gate *power_gate = &smu_power->power_gate; 223 int ret = 0; 224 225 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 226 return 0; 227 228 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 229 return 0; 230 231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 232 if (!ret) 233 atomic_set(&power_gate->jpeg_gated, !enable); 234 235 return ret; 236 } 237 238 /** 239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 240 * 241 * @handle: smu_context pointer 242 * @block_type: the IP block to power gate/ungate 243 * @gate: to power gate if true, ungate otherwise 244 * 245 * This API uses no smu->mutex lock protection due to: 246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 247 * This is guarded to be race condition free by the caller. 248 * 2. Or get called on user setting request of power_dpm_force_performance_level. 249 * Under this case, the smu->mutex lock protection is already enforced on 250 * the parent API smu_force_performance_level of the call path. 251 */ 252 static int smu_dpm_set_power_gate(void *handle, 253 uint32_t block_type, 254 bool gate) 255 { 256 struct smu_context *smu = handle; 257 int ret = 0; 258 259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 260 dev_WARN(smu->adev->dev, 261 "SMU uninitialized but power %s requested for %u!\n", 262 gate ? "gate" : "ungate", block_type); 263 return -EOPNOTSUPP; 264 } 265 266 switch (block_type) { 267 /* 268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 270 */ 271 case AMD_IP_BLOCK_TYPE_UVD: 272 case AMD_IP_BLOCK_TYPE_VCN: 273 ret = smu_dpm_set_vcn_enable(smu, !gate); 274 if (ret) 275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 276 gate ? "gate" : "ungate"); 277 break; 278 case AMD_IP_BLOCK_TYPE_GFX: 279 ret = smu_gfx_off_control(smu, gate); 280 if (ret) 281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 282 gate ? "enable" : "disable"); 283 break; 284 case AMD_IP_BLOCK_TYPE_SDMA: 285 ret = smu_powergate_sdma(smu, gate); 286 if (ret) 287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 288 gate ? "gate" : "ungate"); 289 break; 290 case AMD_IP_BLOCK_TYPE_JPEG: 291 ret = smu_dpm_set_jpeg_enable(smu, !gate); 292 if (ret) 293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 294 gate ? "gate" : "ungate"); 295 break; 296 default: 297 dev_err(smu->adev->dev, "Unsupported block type!\n"); 298 return -EINVAL; 299 } 300 301 return ret; 302 } 303 304 /** 305 * smu_set_user_clk_dependencies - set user profile clock dependencies 306 * 307 * @smu: smu_context pointer 308 * @clk: enum smu_clk_type type 309 * 310 * Enable/Disable the clock dependency for the @clk type. 311 */ 312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 313 { 314 if (smu->adev->in_suspend) 315 return; 316 317 if (clk == SMU_MCLK) { 318 smu->user_dpm_profile.clk_dependency = 0; 319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 320 } else if (clk == SMU_FCLK) { 321 /* MCLK takes precedence over FCLK */ 322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 323 return; 324 325 smu->user_dpm_profile.clk_dependency = 0; 326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 327 } else if (clk == SMU_SOCCLK) { 328 /* MCLK takes precedence over SOCCLK */ 329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 330 return; 331 332 smu->user_dpm_profile.clk_dependency = 0; 333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 334 } else 335 /* Add clk dependencies here, if any */ 336 return; 337 } 338 339 /** 340 * smu_restore_dpm_user_profile - reinstate user dpm profile 341 * 342 * @smu: smu_context pointer 343 * 344 * Restore the saved user power configurations include power limit, 345 * clock frequencies, fan control mode and fan speed. 346 */ 347 static void smu_restore_dpm_user_profile(struct smu_context *smu) 348 { 349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 350 int ret = 0; 351 352 if (!smu->adev->in_suspend) 353 return; 354 355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 356 return; 357 358 /* Enable restore flag */ 359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 360 361 /* set the user dpm power limit */ 362 if (smu->user_dpm_profile.power_limit) { 363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 364 if (ret) 365 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 366 } 367 368 /* set the user dpm clock configurations */ 369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 370 enum smu_clk_type clk_type; 371 372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 373 /* 374 * Iterate over smu clk type and force the saved user clk 375 * configs, skip if clock dependency is enabled 376 */ 377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 378 smu->user_dpm_profile.clk_mask[clk_type]) { 379 ret = smu_force_smuclk_levels(smu, clk_type, 380 smu->user_dpm_profile.clk_mask[clk_type]); 381 if (ret) 382 dev_err(smu->adev->dev, 383 "Failed to set clock type = %d\n", clk_type); 384 } 385 } 386 } 387 388 /* set the user dpm fan configurations */ 389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 392 if (ret != -EOPNOTSUPP) { 393 smu->user_dpm_profile.fan_speed_pwm = 0; 394 smu->user_dpm_profile.fan_speed_rpm = 0; 395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 397 } 398 399 if (smu->user_dpm_profile.fan_speed_pwm) { 400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 401 if (ret != -EOPNOTSUPP) 402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 403 } 404 405 if (smu->user_dpm_profile.fan_speed_rpm) { 406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 407 if (ret != -EOPNOTSUPP) 408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 409 } 410 } 411 412 /* Restore user customized OD settings */ 413 if (smu->user_dpm_profile.user_od) { 414 if (smu->ppt_funcs->restore_user_od_settings) { 415 ret = smu->ppt_funcs->restore_user_od_settings(smu); 416 if (ret) 417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 418 } 419 } 420 421 /* Disable restore flag */ 422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 423 } 424 425 static int smu_get_power_num_states(void *handle, 426 struct pp_states_info *state_info) 427 { 428 if (!state_info) 429 return -EINVAL; 430 431 /* not support power state */ 432 memset(state_info, 0, sizeof(struct pp_states_info)); 433 state_info->nums = 1; 434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 435 436 return 0; 437 } 438 439 bool is_support_sw_smu(struct amdgpu_device *adev) 440 { 441 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 442 if (adev->asic_type == CHIP_VEGA20) 443 return false; 444 445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 446 return true; 447 448 return false; 449 } 450 451 bool is_support_cclk_dpm(struct amdgpu_device *adev) 452 { 453 struct smu_context *smu = adev->powerplay.pp_handle; 454 455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 456 return false; 457 458 return true; 459 } 460 461 462 static int smu_sys_get_pp_table(void *handle, 463 char **table) 464 { 465 struct smu_context *smu = handle; 466 struct smu_table_context *smu_table = &smu->smu_table; 467 468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 469 return -EOPNOTSUPP; 470 471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 472 return -EINVAL; 473 474 if (smu_table->hardcode_pptable) 475 *table = smu_table->hardcode_pptable; 476 else 477 *table = smu_table->power_play_table; 478 479 return smu_table->power_play_table_size; 480 } 481 482 static int smu_sys_set_pp_table(void *handle, 483 const char *buf, 484 size_t size) 485 { 486 struct smu_context *smu = handle; 487 struct smu_table_context *smu_table = &smu->smu_table; 488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 489 int ret = 0; 490 491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 492 return -EOPNOTSUPP; 493 494 if (header->usStructureSize != size) { 495 dev_err(smu->adev->dev, "pp table size not matched !\n"); 496 return -EIO; 497 } 498 499 if (!smu_table->hardcode_pptable) { 500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 501 if (!smu_table->hardcode_pptable) 502 return -ENOMEM; 503 } 504 505 memcpy(smu_table->hardcode_pptable, buf, size); 506 smu_table->power_play_table = smu_table->hardcode_pptable; 507 smu_table->power_play_table_size = size; 508 509 /* 510 * Special hw_fini action(for Navi1x, the DPMs disablement will be 511 * skipped) may be needed for custom pptable uploading. 512 */ 513 smu->uploading_custom_pp_table = true; 514 515 ret = smu_reset(smu); 516 if (ret) 517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 518 519 smu->uploading_custom_pp_table = false; 520 521 return ret; 522 } 523 524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 525 { 526 struct smu_feature *feature = &smu->smu_feature; 527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 528 int ret = 0; 529 530 /* 531 * With SCPM enabled, the allowed featuremasks setting(via 532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 533 * That means there is no way to let PMFW knows the settings below. 534 * Thus, we just assume all the features are allowed under 535 * such scenario. 536 */ 537 if (smu->adev->scpm_enabled) { 538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 539 return 0; 540 } 541 542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 543 544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 545 SMU_FEATURE_MAX/32); 546 if (ret) 547 return ret; 548 549 bitmap_or(feature->allowed, feature->allowed, 550 (unsigned long *)allowed_feature_mask, 551 feature->feature_num); 552 553 return ret; 554 } 555 556 static int smu_set_funcs(struct amdgpu_device *adev) 557 { 558 struct smu_context *smu = adev->powerplay.pp_handle; 559 560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 561 smu->od_enabled = true; 562 563 switch (adev->ip_versions[MP1_HWIP][0]) { 564 case IP_VERSION(11, 0, 0): 565 case IP_VERSION(11, 0, 5): 566 case IP_VERSION(11, 0, 9): 567 navi10_set_ppt_funcs(smu); 568 break; 569 case IP_VERSION(11, 0, 7): 570 case IP_VERSION(11, 0, 11): 571 case IP_VERSION(11, 0, 12): 572 case IP_VERSION(11, 0, 13): 573 sienna_cichlid_set_ppt_funcs(smu); 574 break; 575 case IP_VERSION(12, 0, 0): 576 case IP_VERSION(12, 0, 1): 577 renoir_set_ppt_funcs(smu); 578 break; 579 case IP_VERSION(11, 5, 0): 580 vangogh_set_ppt_funcs(smu); 581 break; 582 case IP_VERSION(13, 0, 1): 583 case IP_VERSION(13, 0, 3): 584 case IP_VERSION(13, 0, 8): 585 yellow_carp_set_ppt_funcs(smu); 586 break; 587 case IP_VERSION(13, 0, 4): 588 case IP_VERSION(13, 0, 11): 589 smu_v13_0_4_set_ppt_funcs(smu); 590 break; 591 case IP_VERSION(13, 0, 5): 592 smu_v13_0_5_set_ppt_funcs(smu); 593 break; 594 case IP_VERSION(11, 0, 8): 595 cyan_skillfish_set_ppt_funcs(smu); 596 break; 597 case IP_VERSION(11, 0, 2): 598 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 599 arcturus_set_ppt_funcs(smu); 600 /* OD is not supported on Arcturus */ 601 smu->od_enabled =false; 602 break; 603 case IP_VERSION(13, 0, 2): 604 aldebaran_set_ppt_funcs(smu); 605 /* Enable pp_od_clk_voltage node */ 606 smu->od_enabled = true; 607 break; 608 case IP_VERSION(13, 0, 0): 609 case IP_VERSION(13, 0, 10): 610 smu_v13_0_0_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(13, 0, 7): 613 smu_v13_0_7_set_ppt_funcs(smu); 614 break; 615 default: 616 return -EINVAL; 617 } 618 619 return 0; 620 } 621 622 static int smu_early_init(void *handle) 623 { 624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 625 struct smu_context *smu; 626 int r; 627 628 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 629 if (!smu) 630 return -ENOMEM; 631 632 smu->adev = adev; 633 smu->pm_enabled = !!amdgpu_dpm; 634 smu->is_apu = false; 635 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 636 smu->smu_baco.platform_support = false; 637 smu->user_dpm_profile.fan_mode = -1; 638 639 mutex_init(&smu->message_lock); 640 641 adev->powerplay.pp_handle = smu; 642 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 643 644 r = smu_set_funcs(adev); 645 if (r) 646 return r; 647 return smu_init_microcode(smu); 648 } 649 650 static int smu_set_default_dpm_table(struct smu_context *smu) 651 { 652 struct smu_power_context *smu_power = &smu->smu_power; 653 struct smu_power_gate *power_gate = &smu_power->power_gate; 654 int vcn_gate, jpeg_gate; 655 int ret = 0; 656 657 if (!smu->ppt_funcs->set_default_dpm_table) 658 return 0; 659 660 vcn_gate = atomic_read(&power_gate->vcn_gated); 661 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 662 663 ret = smu_dpm_set_vcn_enable(smu, true); 664 if (ret) 665 return ret; 666 667 ret = smu_dpm_set_jpeg_enable(smu, true); 668 if (ret) 669 goto err_out; 670 671 ret = smu->ppt_funcs->set_default_dpm_table(smu); 672 if (ret) 673 dev_err(smu->adev->dev, 674 "Failed to setup default dpm clock tables!\n"); 675 676 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 677 err_out: 678 smu_dpm_set_vcn_enable(smu, !vcn_gate); 679 return ret; 680 } 681 682 static int smu_apply_default_config_table_settings(struct smu_context *smu) 683 { 684 struct amdgpu_device *adev = smu->adev; 685 int ret = 0; 686 687 ret = smu_get_default_config_table_settings(smu, 688 &adev->pm.config_table); 689 if (ret) 690 return ret; 691 692 return smu_set_config_table(smu, &adev->pm.config_table); 693 } 694 695 static int smu_late_init(void *handle) 696 { 697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 698 struct smu_context *smu = adev->powerplay.pp_handle; 699 int ret = 0; 700 701 smu_set_fine_grain_gfx_freq_parameters(smu); 702 703 if (!smu->pm_enabled) 704 return 0; 705 706 ret = smu_post_init(smu); 707 if (ret) { 708 dev_err(adev->dev, "Failed to post smu init!\n"); 709 return ret; 710 } 711 712 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 713 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 714 return 0; 715 716 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 717 ret = smu_set_default_od_settings(smu); 718 if (ret) { 719 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 720 return ret; 721 } 722 } 723 724 ret = smu_populate_umd_state_clk(smu); 725 if (ret) { 726 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 727 return ret; 728 } 729 730 ret = smu_get_asic_power_limits(smu, 731 &smu->current_power_limit, 732 &smu->default_power_limit, 733 &smu->max_power_limit); 734 if (ret) { 735 dev_err(adev->dev, "Failed to get asic power limits!\n"); 736 return ret; 737 } 738 739 if (!amdgpu_sriov_vf(adev)) 740 smu_get_unique_id(smu); 741 742 smu_get_fan_parameters(smu); 743 744 smu_handle_task(smu, 745 smu->smu_dpm.dpm_level, 746 AMD_PP_TASK_COMPLETE_INIT); 747 748 ret = smu_apply_default_config_table_settings(smu); 749 if (ret && (ret != -EOPNOTSUPP)) { 750 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 751 return ret; 752 } 753 754 smu_restore_dpm_user_profile(smu); 755 756 return 0; 757 } 758 759 static int smu_init_fb_allocations(struct smu_context *smu) 760 { 761 struct amdgpu_device *adev = smu->adev; 762 struct smu_table_context *smu_table = &smu->smu_table; 763 struct smu_table *tables = smu_table->tables; 764 struct smu_table *driver_table = &(smu_table->driver_table); 765 uint32_t max_table_size = 0; 766 int ret, i; 767 768 /* VRAM allocation for tool table */ 769 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 770 ret = amdgpu_bo_create_kernel(adev, 771 tables[SMU_TABLE_PMSTATUSLOG].size, 772 tables[SMU_TABLE_PMSTATUSLOG].align, 773 tables[SMU_TABLE_PMSTATUSLOG].domain, 774 &tables[SMU_TABLE_PMSTATUSLOG].bo, 775 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 776 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 777 if (ret) { 778 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 779 return ret; 780 } 781 } 782 783 /* VRAM allocation for driver table */ 784 for (i = 0; i < SMU_TABLE_COUNT; i++) { 785 if (tables[i].size == 0) 786 continue; 787 788 if (i == SMU_TABLE_PMSTATUSLOG) 789 continue; 790 791 if (max_table_size < tables[i].size) 792 max_table_size = tables[i].size; 793 } 794 795 driver_table->size = max_table_size; 796 driver_table->align = PAGE_SIZE; 797 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 798 799 ret = amdgpu_bo_create_kernel(adev, 800 driver_table->size, 801 driver_table->align, 802 driver_table->domain, 803 &driver_table->bo, 804 &driver_table->mc_address, 805 &driver_table->cpu_addr); 806 if (ret) { 807 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 808 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 809 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 810 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 811 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 812 } 813 814 return ret; 815 } 816 817 static int smu_fini_fb_allocations(struct smu_context *smu) 818 { 819 struct smu_table_context *smu_table = &smu->smu_table; 820 struct smu_table *tables = smu_table->tables; 821 struct smu_table *driver_table = &(smu_table->driver_table); 822 823 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 824 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 825 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 826 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 827 828 amdgpu_bo_free_kernel(&driver_table->bo, 829 &driver_table->mc_address, 830 &driver_table->cpu_addr); 831 832 return 0; 833 } 834 835 /** 836 * smu_alloc_memory_pool - allocate memory pool in the system memory 837 * 838 * @smu: amdgpu_device pointer 839 * 840 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 841 * and DramLogSetDramAddr can notify it changed. 842 * 843 * Returns 0 on success, error on failure. 844 */ 845 static int smu_alloc_memory_pool(struct smu_context *smu) 846 { 847 struct amdgpu_device *adev = smu->adev; 848 struct smu_table_context *smu_table = &smu->smu_table; 849 struct smu_table *memory_pool = &smu_table->memory_pool; 850 uint64_t pool_size = smu->pool_size; 851 int ret = 0; 852 853 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 854 return ret; 855 856 memory_pool->size = pool_size; 857 memory_pool->align = PAGE_SIZE; 858 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 859 860 switch (pool_size) { 861 case SMU_MEMORY_POOL_SIZE_256_MB: 862 case SMU_MEMORY_POOL_SIZE_512_MB: 863 case SMU_MEMORY_POOL_SIZE_1_GB: 864 case SMU_MEMORY_POOL_SIZE_2_GB: 865 ret = amdgpu_bo_create_kernel(adev, 866 memory_pool->size, 867 memory_pool->align, 868 memory_pool->domain, 869 &memory_pool->bo, 870 &memory_pool->mc_address, 871 &memory_pool->cpu_addr); 872 if (ret) 873 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 874 break; 875 default: 876 break; 877 } 878 879 return ret; 880 } 881 882 static int smu_free_memory_pool(struct smu_context *smu) 883 { 884 struct smu_table_context *smu_table = &smu->smu_table; 885 struct smu_table *memory_pool = &smu_table->memory_pool; 886 887 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 888 return 0; 889 890 amdgpu_bo_free_kernel(&memory_pool->bo, 891 &memory_pool->mc_address, 892 &memory_pool->cpu_addr); 893 894 memset(memory_pool, 0, sizeof(struct smu_table)); 895 896 return 0; 897 } 898 899 static int smu_alloc_dummy_read_table(struct smu_context *smu) 900 { 901 struct smu_table_context *smu_table = &smu->smu_table; 902 struct smu_table *dummy_read_1_table = 903 &smu_table->dummy_read_1_table; 904 struct amdgpu_device *adev = smu->adev; 905 int ret = 0; 906 907 if (!dummy_read_1_table->size) 908 return 0; 909 910 ret = amdgpu_bo_create_kernel(adev, 911 dummy_read_1_table->size, 912 dummy_read_1_table->align, 913 dummy_read_1_table->domain, 914 &dummy_read_1_table->bo, 915 &dummy_read_1_table->mc_address, 916 &dummy_read_1_table->cpu_addr); 917 if (ret) 918 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 919 920 return ret; 921 } 922 923 static void smu_free_dummy_read_table(struct smu_context *smu) 924 { 925 struct smu_table_context *smu_table = &smu->smu_table; 926 struct smu_table *dummy_read_1_table = 927 &smu_table->dummy_read_1_table; 928 929 930 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 931 &dummy_read_1_table->mc_address, 932 &dummy_read_1_table->cpu_addr); 933 934 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 935 } 936 937 static int smu_smc_table_sw_init(struct smu_context *smu) 938 { 939 int ret; 940 941 /** 942 * Create smu_table structure, and init smc tables such as 943 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 944 */ 945 ret = smu_init_smc_tables(smu); 946 if (ret) { 947 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 948 return ret; 949 } 950 951 /** 952 * Create smu_power_context structure, and allocate smu_dpm_context and 953 * context size to fill the smu_power_context data. 954 */ 955 ret = smu_init_power(smu); 956 if (ret) { 957 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 958 return ret; 959 } 960 961 /* 962 * allocate vram bos to store smc table contents. 963 */ 964 ret = smu_init_fb_allocations(smu); 965 if (ret) 966 return ret; 967 968 ret = smu_alloc_memory_pool(smu); 969 if (ret) 970 return ret; 971 972 ret = smu_alloc_dummy_read_table(smu); 973 if (ret) 974 return ret; 975 976 ret = smu_i2c_init(smu); 977 if (ret) 978 return ret; 979 980 return 0; 981 } 982 983 static int smu_smc_table_sw_fini(struct smu_context *smu) 984 { 985 int ret; 986 987 smu_i2c_fini(smu); 988 989 smu_free_dummy_read_table(smu); 990 991 ret = smu_free_memory_pool(smu); 992 if (ret) 993 return ret; 994 995 ret = smu_fini_fb_allocations(smu); 996 if (ret) 997 return ret; 998 999 ret = smu_fini_power(smu); 1000 if (ret) { 1001 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1002 return ret; 1003 } 1004 1005 ret = smu_fini_smc_tables(smu); 1006 if (ret) { 1007 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1008 return ret; 1009 } 1010 1011 return 0; 1012 } 1013 1014 static void smu_throttling_logging_work_fn(struct work_struct *work) 1015 { 1016 struct smu_context *smu = container_of(work, struct smu_context, 1017 throttling_logging_work); 1018 1019 smu_log_thermal_throttling(smu); 1020 } 1021 1022 static void smu_interrupt_work_fn(struct work_struct *work) 1023 { 1024 struct smu_context *smu = container_of(work, struct smu_context, 1025 interrupt_work); 1026 1027 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1028 smu->ppt_funcs->interrupt_work(smu); 1029 } 1030 1031 static int smu_sw_init(void *handle) 1032 { 1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1034 struct smu_context *smu = adev->powerplay.pp_handle; 1035 int ret; 1036 1037 smu->pool_size = adev->pm.smu_prv_buffer_size; 1038 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1039 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1040 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1041 1042 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1043 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1044 atomic64_set(&smu->throttle_int_counter, 0); 1045 smu->watermarks_bitmap = 0; 1046 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1047 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1048 1049 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1050 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1051 1052 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1053 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1054 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1055 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1056 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1057 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1058 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1059 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1060 1061 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1062 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1063 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1064 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1065 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1066 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1067 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1068 smu->display_config = &adev->pm.pm_display_cfg; 1069 1070 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1071 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1072 1073 ret = smu_smc_table_sw_init(smu); 1074 if (ret) { 1075 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1076 return ret; 1077 } 1078 1079 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1080 ret = smu_get_vbios_bootup_values(smu); 1081 if (ret) { 1082 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1083 return ret; 1084 } 1085 1086 ret = smu_init_pptable_microcode(smu); 1087 if (ret) { 1088 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1089 return ret; 1090 } 1091 1092 ret = smu_register_irq_handler(smu); 1093 if (ret) { 1094 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1095 return ret; 1096 } 1097 1098 /* If there is no way to query fan control mode, fan control is not supported */ 1099 if (!smu->ppt_funcs->get_fan_control_mode) 1100 smu->adev->pm.no_fan = true; 1101 1102 return 0; 1103 } 1104 1105 static int smu_sw_fini(void *handle) 1106 { 1107 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1108 struct smu_context *smu = adev->powerplay.pp_handle; 1109 int ret; 1110 1111 ret = smu_smc_table_sw_fini(smu); 1112 if (ret) { 1113 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1114 return ret; 1115 } 1116 1117 smu_fini_microcode(smu); 1118 1119 return 0; 1120 } 1121 1122 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1123 { 1124 struct amdgpu_device *adev = smu->adev; 1125 struct smu_temperature_range *range = 1126 &smu->thermal_range; 1127 int ret = 0; 1128 1129 if (!smu->ppt_funcs->get_thermal_temperature_range) 1130 return 0; 1131 1132 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1133 if (ret) 1134 return ret; 1135 1136 adev->pm.dpm.thermal.min_temp = range->min; 1137 adev->pm.dpm.thermal.max_temp = range->max; 1138 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1139 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1140 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1141 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1142 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1143 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1144 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1145 1146 return ret; 1147 } 1148 1149 static int smu_smc_hw_setup(struct smu_context *smu) 1150 { 1151 struct smu_feature *feature = &smu->smu_feature; 1152 struct amdgpu_device *adev = smu->adev; 1153 uint32_t pcie_gen = 0, pcie_width = 0; 1154 uint64_t features_supported; 1155 int ret = 0; 1156 1157 switch (adev->ip_versions[MP1_HWIP][0]) { 1158 case IP_VERSION(11, 0, 7): 1159 case IP_VERSION(11, 0, 11): 1160 case IP_VERSION(11, 5, 0): 1161 case IP_VERSION(11, 0, 12): 1162 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1163 dev_info(adev->dev, "dpm has been enabled\n"); 1164 ret = smu_system_features_control(smu, true); 1165 if (ret) 1166 dev_err(adev->dev, "Failed system features control!\n"); 1167 return ret; 1168 } 1169 break; 1170 default: 1171 break; 1172 } 1173 1174 ret = smu_init_display_count(smu, 0); 1175 if (ret) { 1176 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1177 return ret; 1178 } 1179 1180 ret = smu_set_driver_table_location(smu); 1181 if (ret) { 1182 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1183 return ret; 1184 } 1185 1186 /* 1187 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1188 */ 1189 ret = smu_set_tool_table_location(smu); 1190 if (ret) { 1191 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1192 return ret; 1193 } 1194 1195 /* 1196 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1197 * pool location. 1198 */ 1199 ret = smu_notify_memory_pool_location(smu); 1200 if (ret) { 1201 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1202 return ret; 1203 } 1204 1205 ret = smu_setup_pptable(smu); 1206 if (ret) { 1207 dev_err(adev->dev, "Failed to setup pptable!\n"); 1208 return ret; 1209 } 1210 1211 /* smu_dump_pptable(smu); */ 1212 1213 /* 1214 * With SCPM enabled, PSP is responsible for the PPTable transferring 1215 * (to SMU). Driver involvement is not needed and permitted. 1216 */ 1217 if (!adev->scpm_enabled) { 1218 /* 1219 * Copy pptable bo in the vram to smc with SMU MSGs such as 1220 * SetDriverDramAddr and TransferTableDram2Smu. 1221 */ 1222 ret = smu_write_pptable(smu); 1223 if (ret) { 1224 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1225 return ret; 1226 } 1227 } 1228 1229 /* issue Run*Btc msg */ 1230 ret = smu_run_btc(smu); 1231 if (ret) 1232 return ret; 1233 1234 /* 1235 * With SCPM enabled, these actions(and relevant messages) are 1236 * not needed and permitted. 1237 */ 1238 if (!adev->scpm_enabled) { 1239 ret = smu_feature_set_allowed_mask(smu); 1240 if (ret) { 1241 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1242 return ret; 1243 } 1244 } 1245 1246 ret = smu_system_features_control(smu, true); 1247 if (ret) { 1248 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1249 return ret; 1250 } 1251 1252 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1253 if (ret) { 1254 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1255 return ret; 1256 } 1257 bitmap_copy(feature->supported, 1258 (unsigned long *)&features_supported, 1259 feature->feature_num); 1260 1261 if (!smu_is_dpm_running(smu)) 1262 dev_info(adev->dev, "dpm has been disabled\n"); 1263 1264 /* 1265 * Set initialized values (get from vbios) to dpm tables context such as 1266 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1267 * type of clks. 1268 */ 1269 ret = smu_set_default_dpm_table(smu); 1270 if (ret) { 1271 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1272 return ret; 1273 } 1274 1275 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1276 pcie_gen = 3; 1277 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1278 pcie_gen = 2; 1279 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1280 pcie_gen = 1; 1281 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1282 pcie_gen = 0; 1283 1284 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1285 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1286 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1287 */ 1288 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1289 pcie_width = 6; 1290 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1291 pcie_width = 5; 1292 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1293 pcie_width = 4; 1294 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1295 pcie_width = 3; 1296 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1297 pcie_width = 2; 1298 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1299 pcie_width = 1; 1300 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1301 if (ret) { 1302 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1303 return ret; 1304 } 1305 1306 ret = smu_get_thermal_temperature_range(smu); 1307 if (ret) { 1308 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1309 return ret; 1310 } 1311 1312 ret = smu_enable_thermal_alert(smu); 1313 if (ret) { 1314 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1315 return ret; 1316 } 1317 1318 ret = smu_notify_display_change(smu); 1319 if (ret) { 1320 dev_err(adev->dev, "Failed to notify display change!\n"); 1321 return ret; 1322 } 1323 1324 /* 1325 * Set min deep sleep dce fclk with bootup value from vbios via 1326 * SetMinDeepSleepDcefclk MSG. 1327 */ 1328 ret = smu_set_min_dcef_deep_sleep(smu, 1329 smu->smu_table.boot_values.dcefclk / 100); 1330 1331 return ret; 1332 } 1333 1334 static int smu_start_smc_engine(struct smu_context *smu) 1335 { 1336 struct amdgpu_device *adev = smu->adev; 1337 int ret = 0; 1338 1339 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1340 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1341 if (smu->ppt_funcs->load_microcode) { 1342 ret = smu->ppt_funcs->load_microcode(smu); 1343 if (ret) 1344 return ret; 1345 } 1346 } 1347 } 1348 1349 if (smu->ppt_funcs->check_fw_status) { 1350 ret = smu->ppt_funcs->check_fw_status(smu); 1351 if (ret) { 1352 dev_err(adev->dev, "SMC is not ready\n"); 1353 return ret; 1354 } 1355 } 1356 1357 /* 1358 * Send msg GetDriverIfVersion to check if the return value is equal 1359 * with DRIVER_IF_VERSION of smc header. 1360 */ 1361 ret = smu_check_fw_version(smu); 1362 if (ret) 1363 return ret; 1364 1365 return ret; 1366 } 1367 1368 static int smu_hw_init(void *handle) 1369 { 1370 int ret; 1371 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1372 struct smu_context *smu = adev->powerplay.pp_handle; 1373 1374 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1375 smu->pm_enabled = false; 1376 return 0; 1377 } 1378 1379 ret = smu_start_smc_engine(smu); 1380 if (ret) { 1381 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1382 return ret; 1383 } 1384 1385 if (smu->is_apu) { 1386 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) && 1387 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1388 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 1389 if (ret) { 1390 dev_err(adev->dev, "Failed to Enable gfx imu!\n"); 1391 return ret; 1392 } 1393 } 1394 1395 smu_dpm_set_vcn_enable(smu, true); 1396 smu_dpm_set_jpeg_enable(smu, true); 1397 smu_set_gfx_cgpg(smu, true); 1398 } 1399 1400 if (!smu->pm_enabled) 1401 return 0; 1402 1403 ret = smu_get_driver_allowed_feature_mask(smu); 1404 if (ret) 1405 return ret; 1406 1407 ret = smu_smc_hw_setup(smu); 1408 if (ret) { 1409 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1410 return ret; 1411 } 1412 1413 /* 1414 * Move maximum sustainable clock retrieving here considering 1415 * 1. It is not needed on resume(from S3). 1416 * 2. DAL settings come between .hw_init and .late_init of SMU. 1417 * And DAL needs to know the maximum sustainable clocks. Thus 1418 * it cannot be put in .late_init(). 1419 */ 1420 ret = smu_init_max_sustainable_clocks(smu); 1421 if (ret) { 1422 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1423 return ret; 1424 } 1425 1426 adev->pm.dpm_enabled = true; 1427 1428 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1429 1430 return 0; 1431 } 1432 1433 static int smu_disable_dpms(struct smu_context *smu) 1434 { 1435 struct amdgpu_device *adev = smu->adev; 1436 int ret = 0; 1437 bool use_baco = !smu->is_apu && 1438 ((amdgpu_in_reset(adev) && 1439 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1440 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1441 1442 /* 1443 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1444 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1445 */ 1446 switch (adev->ip_versions[MP1_HWIP][0]) { 1447 case IP_VERSION(13, 0, 0): 1448 case IP_VERSION(13, 0, 7): 1449 case IP_VERSION(13, 0, 10): 1450 return 0; 1451 default: 1452 break; 1453 } 1454 1455 /* 1456 * For custom pptable uploading, skip the DPM features 1457 * disable process on Navi1x ASICs. 1458 * - As the gfx related features are under control of 1459 * RLC on those ASICs. RLC reinitialization will be 1460 * needed to reenable them. That will cost much more 1461 * efforts. 1462 * 1463 * - SMU firmware can handle the DPM reenablement 1464 * properly. 1465 */ 1466 if (smu->uploading_custom_pp_table) { 1467 switch (adev->ip_versions[MP1_HWIP][0]) { 1468 case IP_VERSION(11, 0, 0): 1469 case IP_VERSION(11, 0, 5): 1470 case IP_VERSION(11, 0, 9): 1471 case IP_VERSION(11, 0, 7): 1472 case IP_VERSION(11, 0, 11): 1473 case IP_VERSION(11, 5, 0): 1474 case IP_VERSION(11, 0, 12): 1475 case IP_VERSION(11, 0, 13): 1476 return 0; 1477 default: 1478 break; 1479 } 1480 } 1481 1482 /* 1483 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1484 * on BACO in. Driver involvement is unnecessary. 1485 */ 1486 if (use_baco) { 1487 switch (adev->ip_versions[MP1_HWIP][0]) { 1488 case IP_VERSION(11, 0, 7): 1489 case IP_VERSION(11, 0, 0): 1490 case IP_VERSION(11, 0, 5): 1491 case IP_VERSION(11, 0, 9): 1492 case IP_VERSION(13, 0, 7): 1493 return 0; 1494 default: 1495 break; 1496 } 1497 } 1498 1499 /* 1500 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1501 * for gpu reset case. Driver involvement is unnecessary. 1502 */ 1503 if (amdgpu_in_reset(adev)) { 1504 switch (adev->ip_versions[MP1_HWIP][0]) { 1505 case IP_VERSION(13, 0, 4): 1506 case IP_VERSION(13, 0, 11): 1507 return 0; 1508 default: 1509 break; 1510 } 1511 } 1512 1513 /* 1514 * For gpu reset, runpm and hibernation through BACO, 1515 * BACO feature has to be kept enabled. 1516 */ 1517 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1518 ret = smu_disable_all_features_with_exception(smu, 1519 SMU_FEATURE_BACO_BIT); 1520 if (ret) 1521 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1522 } else { 1523 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1524 if (!adev->scpm_enabled) { 1525 ret = smu_system_features_control(smu, false); 1526 if (ret) 1527 dev_err(adev->dev, "Failed to disable smu features.\n"); 1528 } 1529 } 1530 1531 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1532 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1533 adev->gfx.rlc.funcs->stop(adev); 1534 1535 return ret; 1536 } 1537 1538 static int smu_smc_hw_cleanup(struct smu_context *smu) 1539 { 1540 struct amdgpu_device *adev = smu->adev; 1541 int ret = 0; 1542 1543 cancel_work_sync(&smu->throttling_logging_work); 1544 cancel_work_sync(&smu->interrupt_work); 1545 1546 ret = smu_disable_thermal_alert(smu); 1547 if (ret) { 1548 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1549 return ret; 1550 } 1551 1552 ret = smu_disable_dpms(smu); 1553 if (ret) { 1554 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1555 return ret; 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int smu_hw_fini(void *handle) 1562 { 1563 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1564 struct smu_context *smu = adev->powerplay.pp_handle; 1565 1566 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1567 return 0; 1568 1569 smu_dpm_set_vcn_enable(smu, false); 1570 smu_dpm_set_jpeg_enable(smu, false); 1571 1572 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1573 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1574 1575 if (!smu->pm_enabled) 1576 return 0; 1577 1578 adev->pm.dpm_enabled = false; 1579 1580 return smu_smc_hw_cleanup(smu); 1581 } 1582 1583 static void smu_late_fini(void *handle) 1584 { 1585 struct amdgpu_device *adev = handle; 1586 struct smu_context *smu = adev->powerplay.pp_handle; 1587 1588 kfree(smu); 1589 } 1590 1591 static int smu_reset(struct smu_context *smu) 1592 { 1593 struct amdgpu_device *adev = smu->adev; 1594 int ret; 1595 1596 ret = smu_hw_fini(adev); 1597 if (ret) 1598 return ret; 1599 1600 ret = smu_hw_init(adev); 1601 if (ret) 1602 return ret; 1603 1604 ret = smu_late_init(adev); 1605 if (ret) 1606 return ret; 1607 1608 return 0; 1609 } 1610 1611 static int smu_suspend(void *handle) 1612 { 1613 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1614 struct smu_context *smu = adev->powerplay.pp_handle; 1615 int ret; 1616 uint64_t count; 1617 1618 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1619 return 0; 1620 1621 if (!smu->pm_enabled) 1622 return 0; 1623 1624 adev->pm.dpm_enabled = false; 1625 1626 ret = smu_smc_hw_cleanup(smu); 1627 if (ret) 1628 return ret; 1629 1630 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1631 1632 smu_set_gfx_cgpg(smu, false); 1633 1634 /* 1635 * pwfw resets entrycount when device is suspended, so we save the 1636 * last value to be used when we resume to keep it consistent 1637 */ 1638 ret = smu_get_entrycount_gfxoff(smu, &count); 1639 if (!ret) 1640 adev->gfx.gfx_off_entrycount = count; 1641 1642 return 0; 1643 } 1644 1645 static int smu_resume(void *handle) 1646 { 1647 int ret; 1648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1649 struct smu_context *smu = adev->powerplay.pp_handle; 1650 1651 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1652 return 0; 1653 1654 if (!smu->pm_enabled) 1655 return 0; 1656 1657 dev_info(adev->dev, "SMU is resuming...\n"); 1658 1659 ret = smu_start_smc_engine(smu); 1660 if (ret) { 1661 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1662 return ret; 1663 } 1664 1665 ret = smu_smc_hw_setup(smu); 1666 if (ret) { 1667 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1668 return ret; 1669 } 1670 1671 smu_set_gfx_cgpg(smu, true); 1672 1673 smu->disable_uclk_switch = 0; 1674 1675 adev->pm.dpm_enabled = true; 1676 1677 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1678 1679 return 0; 1680 } 1681 1682 static int smu_display_configuration_change(void *handle, 1683 const struct amd_pp_display_configuration *display_config) 1684 { 1685 struct smu_context *smu = handle; 1686 int index = 0; 1687 int num_of_active_display = 0; 1688 1689 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1690 return -EOPNOTSUPP; 1691 1692 if (!display_config) 1693 return -EINVAL; 1694 1695 smu_set_min_dcef_deep_sleep(smu, 1696 display_config->min_dcef_deep_sleep_set_clk / 100); 1697 1698 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1699 if (display_config->displays[index].controller_id != 0) 1700 num_of_active_display++; 1701 } 1702 1703 return 0; 1704 } 1705 1706 static int smu_set_clockgating_state(void *handle, 1707 enum amd_clockgating_state state) 1708 { 1709 return 0; 1710 } 1711 1712 static int smu_set_powergating_state(void *handle, 1713 enum amd_powergating_state state) 1714 { 1715 return 0; 1716 } 1717 1718 static int smu_enable_umd_pstate(void *handle, 1719 enum amd_dpm_forced_level *level) 1720 { 1721 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1722 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1723 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1724 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1725 1726 struct smu_context *smu = (struct smu_context*)(handle); 1727 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1728 1729 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1730 return -EINVAL; 1731 1732 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1733 /* enter umd pstate, save current level, disable gfx cg*/ 1734 if (*level & profile_mode_mask) { 1735 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1736 smu_gpo_control(smu, false); 1737 smu_gfx_ulv_control(smu, false); 1738 smu_deep_sleep_control(smu, false); 1739 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1740 } 1741 } else { 1742 /* exit umd pstate, restore level, enable gfx cg*/ 1743 if (!(*level & profile_mode_mask)) { 1744 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1745 *level = smu_dpm_ctx->saved_dpm_level; 1746 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1747 smu_deep_sleep_control(smu, true); 1748 smu_gfx_ulv_control(smu, true); 1749 smu_gpo_control(smu, true); 1750 } 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int smu_bump_power_profile_mode(struct smu_context *smu, 1757 long *param, 1758 uint32_t param_size) 1759 { 1760 int ret = 0; 1761 1762 if (smu->ppt_funcs->set_power_profile_mode) 1763 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1764 1765 return ret; 1766 } 1767 1768 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1769 enum amd_dpm_forced_level level, 1770 bool skip_display_settings) 1771 { 1772 int ret = 0; 1773 int index = 0; 1774 long workload; 1775 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1776 1777 if (!skip_display_settings) { 1778 ret = smu_display_config_changed(smu); 1779 if (ret) { 1780 dev_err(smu->adev->dev, "Failed to change display config!"); 1781 return ret; 1782 } 1783 } 1784 1785 ret = smu_apply_clocks_adjust_rules(smu); 1786 if (ret) { 1787 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1788 return ret; 1789 } 1790 1791 if (!skip_display_settings) { 1792 ret = smu_notify_smc_display_config(smu); 1793 if (ret) { 1794 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1795 return ret; 1796 } 1797 } 1798 1799 if (smu_dpm_ctx->dpm_level != level) { 1800 ret = smu_asic_set_performance_level(smu, level); 1801 if (ret) { 1802 dev_err(smu->adev->dev, "Failed to set performance level!"); 1803 return ret; 1804 } 1805 1806 /* update the saved copy */ 1807 smu_dpm_ctx->dpm_level = level; 1808 } 1809 1810 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1811 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1812 index = fls(smu->workload_mask); 1813 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1814 workload = smu->workload_setting[index]; 1815 1816 if (smu->power_profile_mode != workload) 1817 smu_bump_power_profile_mode(smu, &workload, 0); 1818 } 1819 1820 return ret; 1821 } 1822 1823 static int smu_handle_task(struct smu_context *smu, 1824 enum amd_dpm_forced_level level, 1825 enum amd_pp_task task_id) 1826 { 1827 int ret = 0; 1828 1829 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1830 return -EOPNOTSUPP; 1831 1832 switch (task_id) { 1833 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1834 ret = smu_pre_display_config_changed(smu); 1835 if (ret) 1836 return ret; 1837 ret = smu_adjust_power_state_dynamic(smu, level, false); 1838 break; 1839 case AMD_PP_TASK_COMPLETE_INIT: 1840 case AMD_PP_TASK_READJUST_POWER_STATE: 1841 ret = smu_adjust_power_state_dynamic(smu, level, true); 1842 break; 1843 default: 1844 break; 1845 } 1846 1847 return ret; 1848 } 1849 1850 static int smu_handle_dpm_task(void *handle, 1851 enum amd_pp_task task_id, 1852 enum amd_pm_state_type *user_state) 1853 { 1854 struct smu_context *smu = handle; 1855 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1856 1857 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1858 1859 } 1860 1861 static int smu_switch_power_profile(void *handle, 1862 enum PP_SMC_POWER_PROFILE type, 1863 bool en) 1864 { 1865 struct smu_context *smu = handle; 1866 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1867 long workload; 1868 uint32_t index; 1869 1870 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1871 return -EOPNOTSUPP; 1872 1873 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1874 return -EINVAL; 1875 1876 if (!en) { 1877 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1878 index = fls(smu->workload_mask); 1879 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1880 workload = smu->workload_setting[index]; 1881 } else { 1882 smu->workload_mask |= (1 << smu->workload_prority[type]); 1883 index = fls(smu->workload_mask); 1884 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1885 workload = smu->workload_setting[index]; 1886 } 1887 1888 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1889 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1890 smu_bump_power_profile_mode(smu, &workload, 0); 1891 1892 return 0; 1893 } 1894 1895 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1896 { 1897 struct smu_context *smu = handle; 1898 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1899 1900 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1901 return -EOPNOTSUPP; 1902 1903 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1904 return -EINVAL; 1905 1906 return smu_dpm_ctx->dpm_level; 1907 } 1908 1909 static int smu_force_performance_level(void *handle, 1910 enum amd_dpm_forced_level level) 1911 { 1912 struct smu_context *smu = handle; 1913 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1914 int ret = 0; 1915 1916 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1917 return -EOPNOTSUPP; 1918 1919 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1920 return -EINVAL; 1921 1922 ret = smu_enable_umd_pstate(smu, &level); 1923 if (ret) 1924 return ret; 1925 1926 ret = smu_handle_task(smu, level, 1927 AMD_PP_TASK_READJUST_POWER_STATE); 1928 1929 /* reset user dpm clock state */ 1930 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1931 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1932 smu->user_dpm_profile.clk_dependency = 0; 1933 } 1934 1935 return ret; 1936 } 1937 1938 static int smu_set_display_count(void *handle, uint32_t count) 1939 { 1940 struct smu_context *smu = handle; 1941 1942 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1943 return -EOPNOTSUPP; 1944 1945 return smu_init_display_count(smu, count); 1946 } 1947 1948 static int smu_force_smuclk_levels(struct smu_context *smu, 1949 enum smu_clk_type clk_type, 1950 uint32_t mask) 1951 { 1952 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1953 int ret = 0; 1954 1955 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1956 return -EOPNOTSUPP; 1957 1958 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1959 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1960 return -EINVAL; 1961 } 1962 1963 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1964 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1965 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1966 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1967 smu_set_user_clk_dependencies(smu, clk_type); 1968 } 1969 } 1970 1971 return ret; 1972 } 1973 1974 static int smu_force_ppclk_levels(void *handle, 1975 enum pp_clock_type type, 1976 uint32_t mask) 1977 { 1978 struct smu_context *smu = handle; 1979 enum smu_clk_type clk_type; 1980 1981 switch (type) { 1982 case PP_SCLK: 1983 clk_type = SMU_SCLK; break; 1984 case PP_MCLK: 1985 clk_type = SMU_MCLK; break; 1986 case PP_PCIE: 1987 clk_type = SMU_PCIE; break; 1988 case PP_SOCCLK: 1989 clk_type = SMU_SOCCLK; break; 1990 case PP_FCLK: 1991 clk_type = SMU_FCLK; break; 1992 case PP_DCEFCLK: 1993 clk_type = SMU_DCEFCLK; break; 1994 case PP_VCLK: 1995 clk_type = SMU_VCLK; break; 1996 case PP_DCLK: 1997 clk_type = SMU_DCLK; break; 1998 case OD_SCLK: 1999 clk_type = SMU_OD_SCLK; break; 2000 case OD_MCLK: 2001 clk_type = SMU_OD_MCLK; break; 2002 case OD_VDDC_CURVE: 2003 clk_type = SMU_OD_VDDC_CURVE; break; 2004 case OD_RANGE: 2005 clk_type = SMU_OD_RANGE; break; 2006 default: 2007 return -EINVAL; 2008 } 2009 2010 return smu_force_smuclk_levels(smu, clk_type, mask); 2011 } 2012 2013 /* 2014 * On system suspending or resetting, the dpm_enabled 2015 * flag will be cleared. So that those SMU services which 2016 * are not supported will be gated. 2017 * However, the mp1 state setting should still be granted 2018 * even if the dpm_enabled cleared. 2019 */ 2020 static int smu_set_mp1_state(void *handle, 2021 enum pp_mp1_state mp1_state) 2022 { 2023 struct smu_context *smu = handle; 2024 int ret = 0; 2025 2026 if (!smu->pm_enabled) 2027 return -EOPNOTSUPP; 2028 2029 if (smu->ppt_funcs && 2030 smu->ppt_funcs->set_mp1_state) 2031 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2032 2033 return ret; 2034 } 2035 2036 static int smu_set_df_cstate(void *handle, 2037 enum pp_df_cstate state) 2038 { 2039 struct smu_context *smu = handle; 2040 int ret = 0; 2041 2042 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2043 return -EOPNOTSUPP; 2044 2045 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2046 return 0; 2047 2048 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2049 if (ret) 2050 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2051 2052 return ret; 2053 } 2054 2055 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2056 { 2057 int ret = 0; 2058 2059 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2060 return -EOPNOTSUPP; 2061 2062 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2063 return 0; 2064 2065 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2066 if (ret) 2067 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2068 2069 return ret; 2070 } 2071 2072 int smu_write_watermarks_table(struct smu_context *smu) 2073 { 2074 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2075 return -EOPNOTSUPP; 2076 2077 return smu_set_watermarks_table(smu, NULL); 2078 } 2079 2080 static int smu_set_watermarks_for_clock_ranges(void *handle, 2081 struct pp_smu_wm_range_sets *clock_ranges) 2082 { 2083 struct smu_context *smu = handle; 2084 2085 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2086 return -EOPNOTSUPP; 2087 2088 if (smu->disable_watermark) 2089 return 0; 2090 2091 return smu_set_watermarks_table(smu, clock_ranges); 2092 } 2093 2094 int smu_set_ac_dc(struct smu_context *smu) 2095 { 2096 int ret = 0; 2097 2098 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2099 return -EOPNOTSUPP; 2100 2101 /* controlled by firmware */ 2102 if (smu->dc_controlled_by_gpio) 2103 return 0; 2104 2105 ret = smu_set_power_source(smu, 2106 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2107 SMU_POWER_SOURCE_DC); 2108 if (ret) 2109 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2110 smu->adev->pm.ac_power ? "AC" : "DC"); 2111 2112 return ret; 2113 } 2114 2115 const struct amd_ip_funcs smu_ip_funcs = { 2116 .name = "smu", 2117 .early_init = smu_early_init, 2118 .late_init = smu_late_init, 2119 .sw_init = smu_sw_init, 2120 .sw_fini = smu_sw_fini, 2121 .hw_init = smu_hw_init, 2122 .hw_fini = smu_hw_fini, 2123 .late_fini = smu_late_fini, 2124 .suspend = smu_suspend, 2125 .resume = smu_resume, 2126 .is_idle = NULL, 2127 .check_soft_reset = NULL, 2128 .wait_for_idle = NULL, 2129 .soft_reset = NULL, 2130 .set_clockgating_state = smu_set_clockgating_state, 2131 .set_powergating_state = smu_set_powergating_state, 2132 }; 2133 2134 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2135 { 2136 .type = AMD_IP_BLOCK_TYPE_SMC, 2137 .major = 11, 2138 .minor = 0, 2139 .rev = 0, 2140 .funcs = &smu_ip_funcs, 2141 }; 2142 2143 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2144 { 2145 .type = AMD_IP_BLOCK_TYPE_SMC, 2146 .major = 12, 2147 .minor = 0, 2148 .rev = 0, 2149 .funcs = &smu_ip_funcs, 2150 }; 2151 2152 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2153 { 2154 .type = AMD_IP_BLOCK_TYPE_SMC, 2155 .major = 13, 2156 .minor = 0, 2157 .rev = 0, 2158 .funcs = &smu_ip_funcs, 2159 }; 2160 2161 static int smu_load_microcode(void *handle) 2162 { 2163 struct smu_context *smu = handle; 2164 struct amdgpu_device *adev = smu->adev; 2165 int ret = 0; 2166 2167 if (!smu->pm_enabled) 2168 return -EOPNOTSUPP; 2169 2170 /* This should be used for non PSP loading */ 2171 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2172 return 0; 2173 2174 if (smu->ppt_funcs->load_microcode) { 2175 ret = smu->ppt_funcs->load_microcode(smu); 2176 if (ret) { 2177 dev_err(adev->dev, "Load microcode failed\n"); 2178 return ret; 2179 } 2180 } 2181 2182 if (smu->ppt_funcs->check_fw_status) { 2183 ret = smu->ppt_funcs->check_fw_status(smu); 2184 if (ret) { 2185 dev_err(adev->dev, "SMC is not ready\n"); 2186 return ret; 2187 } 2188 } 2189 2190 return ret; 2191 } 2192 2193 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2194 { 2195 int ret = 0; 2196 2197 if (smu->ppt_funcs->set_gfx_cgpg) 2198 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2199 2200 return ret; 2201 } 2202 2203 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2204 { 2205 struct smu_context *smu = handle; 2206 int ret = 0; 2207 2208 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2209 return -EOPNOTSUPP; 2210 2211 if (!smu->ppt_funcs->set_fan_speed_rpm) 2212 return -EOPNOTSUPP; 2213 2214 if (speed == U32_MAX) 2215 return -EINVAL; 2216 2217 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2218 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2219 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2220 smu->user_dpm_profile.fan_speed_rpm = speed; 2221 2222 /* Override custom PWM setting as they cannot co-exist */ 2223 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2224 smu->user_dpm_profile.fan_speed_pwm = 0; 2225 } 2226 2227 return ret; 2228 } 2229 2230 /** 2231 * smu_get_power_limit - Request one of the SMU Power Limits 2232 * 2233 * @handle: pointer to smu context 2234 * @limit: requested limit is written back to this variable 2235 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2236 * @pp_power_type: &pp_power_type type of power 2237 * Return: 0 on success, <0 on error 2238 * 2239 */ 2240 int smu_get_power_limit(void *handle, 2241 uint32_t *limit, 2242 enum pp_power_limit_level pp_limit_level, 2243 enum pp_power_type pp_power_type) 2244 { 2245 struct smu_context *smu = handle; 2246 struct amdgpu_device *adev = smu->adev; 2247 enum smu_ppt_limit_level limit_level; 2248 uint32_t limit_type; 2249 int ret = 0; 2250 2251 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2252 return -EOPNOTSUPP; 2253 2254 switch(pp_power_type) { 2255 case PP_PWR_TYPE_SUSTAINED: 2256 limit_type = SMU_DEFAULT_PPT_LIMIT; 2257 break; 2258 case PP_PWR_TYPE_FAST: 2259 limit_type = SMU_FAST_PPT_LIMIT; 2260 break; 2261 default: 2262 return -EOPNOTSUPP; 2263 break; 2264 } 2265 2266 switch(pp_limit_level){ 2267 case PP_PWR_LIMIT_CURRENT: 2268 limit_level = SMU_PPT_LIMIT_CURRENT; 2269 break; 2270 case PP_PWR_LIMIT_DEFAULT: 2271 limit_level = SMU_PPT_LIMIT_DEFAULT; 2272 break; 2273 case PP_PWR_LIMIT_MAX: 2274 limit_level = SMU_PPT_LIMIT_MAX; 2275 break; 2276 case PP_PWR_LIMIT_MIN: 2277 default: 2278 return -EOPNOTSUPP; 2279 break; 2280 } 2281 2282 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2283 if (smu->ppt_funcs->get_ppt_limit) 2284 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2285 } else { 2286 switch (limit_level) { 2287 case SMU_PPT_LIMIT_CURRENT: 2288 switch (adev->ip_versions[MP1_HWIP][0]) { 2289 case IP_VERSION(13, 0, 2): 2290 case IP_VERSION(11, 0, 7): 2291 case IP_VERSION(11, 0, 11): 2292 case IP_VERSION(11, 0, 12): 2293 case IP_VERSION(11, 0, 13): 2294 ret = smu_get_asic_power_limits(smu, 2295 &smu->current_power_limit, 2296 NULL, 2297 NULL); 2298 break; 2299 default: 2300 break; 2301 } 2302 *limit = smu->current_power_limit; 2303 break; 2304 case SMU_PPT_LIMIT_DEFAULT: 2305 *limit = smu->default_power_limit; 2306 break; 2307 case SMU_PPT_LIMIT_MAX: 2308 *limit = smu->max_power_limit; 2309 break; 2310 default: 2311 break; 2312 } 2313 } 2314 2315 return ret; 2316 } 2317 2318 static int smu_set_power_limit(void *handle, uint32_t limit) 2319 { 2320 struct smu_context *smu = handle; 2321 uint32_t limit_type = limit >> 24; 2322 int ret = 0; 2323 2324 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2325 return -EOPNOTSUPP; 2326 2327 limit &= (1<<24)-1; 2328 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2329 if (smu->ppt_funcs->set_power_limit) 2330 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2331 2332 if (limit > smu->max_power_limit) { 2333 dev_err(smu->adev->dev, 2334 "New power limit (%d) is over the max allowed %d\n", 2335 limit, smu->max_power_limit); 2336 return -EINVAL; 2337 } 2338 2339 if (!limit) 2340 limit = smu->current_power_limit; 2341 2342 if (smu->ppt_funcs->set_power_limit) { 2343 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2344 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2345 smu->user_dpm_profile.power_limit = limit; 2346 } 2347 2348 return ret; 2349 } 2350 2351 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2352 { 2353 int ret = 0; 2354 2355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2356 return -EOPNOTSUPP; 2357 2358 if (smu->ppt_funcs->print_clk_levels) 2359 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2360 2361 return ret; 2362 } 2363 2364 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2365 { 2366 enum smu_clk_type clk_type; 2367 2368 switch (type) { 2369 case PP_SCLK: 2370 clk_type = SMU_SCLK; break; 2371 case PP_MCLK: 2372 clk_type = SMU_MCLK; break; 2373 case PP_PCIE: 2374 clk_type = SMU_PCIE; break; 2375 case PP_SOCCLK: 2376 clk_type = SMU_SOCCLK; break; 2377 case PP_FCLK: 2378 clk_type = SMU_FCLK; break; 2379 case PP_DCEFCLK: 2380 clk_type = SMU_DCEFCLK; break; 2381 case PP_VCLK: 2382 clk_type = SMU_VCLK; break; 2383 case PP_DCLK: 2384 clk_type = SMU_DCLK; break; 2385 case OD_SCLK: 2386 clk_type = SMU_OD_SCLK; break; 2387 case OD_MCLK: 2388 clk_type = SMU_OD_MCLK; break; 2389 case OD_VDDC_CURVE: 2390 clk_type = SMU_OD_VDDC_CURVE; break; 2391 case OD_RANGE: 2392 clk_type = SMU_OD_RANGE; break; 2393 case OD_VDDGFX_OFFSET: 2394 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2395 case OD_CCLK: 2396 clk_type = SMU_OD_CCLK; break; 2397 default: 2398 clk_type = SMU_CLK_COUNT; break; 2399 } 2400 2401 return clk_type; 2402 } 2403 2404 static int smu_print_ppclk_levels(void *handle, 2405 enum pp_clock_type type, 2406 char *buf) 2407 { 2408 struct smu_context *smu = handle; 2409 enum smu_clk_type clk_type; 2410 2411 clk_type = smu_convert_to_smuclk(type); 2412 if (clk_type == SMU_CLK_COUNT) 2413 return -EINVAL; 2414 2415 return smu_print_smuclk_levels(smu, clk_type, buf); 2416 } 2417 2418 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2419 { 2420 struct smu_context *smu = handle; 2421 enum smu_clk_type clk_type; 2422 2423 clk_type = smu_convert_to_smuclk(type); 2424 if (clk_type == SMU_CLK_COUNT) 2425 return -EINVAL; 2426 2427 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2428 return -EOPNOTSUPP; 2429 2430 if (!smu->ppt_funcs->emit_clk_levels) 2431 return -ENOENT; 2432 2433 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2434 2435 } 2436 2437 static int smu_od_edit_dpm_table(void *handle, 2438 enum PP_OD_DPM_TABLE_COMMAND type, 2439 long *input, uint32_t size) 2440 { 2441 struct smu_context *smu = handle; 2442 int ret = 0; 2443 2444 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2445 return -EOPNOTSUPP; 2446 2447 if (smu->ppt_funcs->od_edit_dpm_table) { 2448 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2449 } 2450 2451 return ret; 2452 } 2453 2454 static int smu_read_sensor(void *handle, 2455 int sensor, 2456 void *data, 2457 int *size_arg) 2458 { 2459 struct smu_context *smu = handle; 2460 struct smu_umd_pstate_table *pstate_table = 2461 &smu->pstate_table; 2462 int ret = 0; 2463 uint32_t *size, size_val; 2464 2465 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2466 return -EOPNOTSUPP; 2467 2468 if (!data || !size_arg) 2469 return -EINVAL; 2470 2471 size_val = *size_arg; 2472 size = &size_val; 2473 2474 if (smu->ppt_funcs->read_sensor) 2475 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2476 goto unlock; 2477 2478 switch (sensor) { 2479 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2480 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2481 *size = 4; 2482 break; 2483 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2484 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2485 *size = 4; 2486 break; 2487 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2488 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2489 *size = 4; 2490 break; 2491 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2492 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2493 *size = 4; 2494 break; 2495 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2496 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2497 *size = 8; 2498 break; 2499 case AMDGPU_PP_SENSOR_UVD_POWER: 2500 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2501 *size = 4; 2502 break; 2503 case AMDGPU_PP_SENSOR_VCE_POWER: 2504 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2505 *size = 4; 2506 break; 2507 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2508 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2509 *size = 4; 2510 break; 2511 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2512 *(uint32_t *)data = 0; 2513 *size = 4; 2514 break; 2515 default: 2516 *size = 0; 2517 ret = -EOPNOTSUPP; 2518 break; 2519 } 2520 2521 unlock: 2522 // assign uint32_t to int 2523 *size_arg = size_val; 2524 2525 return ret; 2526 } 2527 2528 static int smu_get_power_profile_mode(void *handle, char *buf) 2529 { 2530 struct smu_context *smu = handle; 2531 2532 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2533 !smu->ppt_funcs->get_power_profile_mode) 2534 return -EOPNOTSUPP; 2535 if (!buf) 2536 return -EINVAL; 2537 2538 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2539 } 2540 2541 static int smu_set_power_profile_mode(void *handle, 2542 long *param, 2543 uint32_t param_size) 2544 { 2545 struct smu_context *smu = handle; 2546 2547 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2548 !smu->ppt_funcs->set_power_profile_mode) 2549 return -EOPNOTSUPP; 2550 2551 return smu_bump_power_profile_mode(smu, param, param_size); 2552 } 2553 2554 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2555 { 2556 struct smu_context *smu = handle; 2557 2558 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2559 return -EOPNOTSUPP; 2560 2561 if (!smu->ppt_funcs->get_fan_control_mode) 2562 return -EOPNOTSUPP; 2563 2564 if (!fan_mode) 2565 return -EINVAL; 2566 2567 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2568 2569 return 0; 2570 } 2571 2572 static int smu_set_fan_control_mode(void *handle, u32 value) 2573 { 2574 struct smu_context *smu = handle; 2575 int ret = 0; 2576 2577 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2578 return -EOPNOTSUPP; 2579 2580 if (!smu->ppt_funcs->set_fan_control_mode) 2581 return -EOPNOTSUPP; 2582 2583 if (value == U32_MAX) 2584 return -EINVAL; 2585 2586 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2587 if (ret) 2588 goto out; 2589 2590 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2591 smu->user_dpm_profile.fan_mode = value; 2592 2593 /* reset user dpm fan speed */ 2594 if (value != AMD_FAN_CTRL_MANUAL) { 2595 smu->user_dpm_profile.fan_speed_pwm = 0; 2596 smu->user_dpm_profile.fan_speed_rpm = 0; 2597 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2598 } 2599 } 2600 2601 out: 2602 return ret; 2603 } 2604 2605 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2606 { 2607 struct smu_context *smu = handle; 2608 int ret = 0; 2609 2610 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2611 return -EOPNOTSUPP; 2612 2613 if (!smu->ppt_funcs->get_fan_speed_pwm) 2614 return -EOPNOTSUPP; 2615 2616 if (!speed) 2617 return -EINVAL; 2618 2619 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2620 2621 return ret; 2622 } 2623 2624 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2625 { 2626 struct smu_context *smu = handle; 2627 int ret = 0; 2628 2629 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2630 return -EOPNOTSUPP; 2631 2632 if (!smu->ppt_funcs->set_fan_speed_pwm) 2633 return -EOPNOTSUPP; 2634 2635 if (speed == U32_MAX) 2636 return -EINVAL; 2637 2638 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2639 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2640 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2641 smu->user_dpm_profile.fan_speed_pwm = speed; 2642 2643 /* Override custom RPM setting as they cannot co-exist */ 2644 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2645 smu->user_dpm_profile.fan_speed_rpm = 0; 2646 } 2647 2648 return ret; 2649 } 2650 2651 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2652 { 2653 struct smu_context *smu = handle; 2654 int ret = 0; 2655 2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2657 return -EOPNOTSUPP; 2658 2659 if (!smu->ppt_funcs->get_fan_speed_rpm) 2660 return -EOPNOTSUPP; 2661 2662 if (!speed) 2663 return -EINVAL; 2664 2665 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2666 2667 return ret; 2668 } 2669 2670 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2671 { 2672 struct smu_context *smu = handle; 2673 2674 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2675 return -EOPNOTSUPP; 2676 2677 return smu_set_min_dcef_deep_sleep(smu, clk); 2678 } 2679 2680 static int smu_get_clock_by_type_with_latency(void *handle, 2681 enum amd_pp_clock_type type, 2682 struct pp_clock_levels_with_latency *clocks) 2683 { 2684 struct smu_context *smu = handle; 2685 enum smu_clk_type clk_type; 2686 int ret = 0; 2687 2688 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2689 return -EOPNOTSUPP; 2690 2691 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2692 switch (type) { 2693 case amd_pp_sys_clock: 2694 clk_type = SMU_GFXCLK; 2695 break; 2696 case amd_pp_mem_clock: 2697 clk_type = SMU_MCLK; 2698 break; 2699 case amd_pp_dcef_clock: 2700 clk_type = SMU_DCEFCLK; 2701 break; 2702 case amd_pp_disp_clock: 2703 clk_type = SMU_DISPCLK; 2704 break; 2705 default: 2706 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2707 return -EINVAL; 2708 } 2709 2710 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2711 } 2712 2713 return ret; 2714 } 2715 2716 static int smu_display_clock_voltage_request(void *handle, 2717 struct pp_display_clock_request *clock_req) 2718 { 2719 struct smu_context *smu = handle; 2720 int ret = 0; 2721 2722 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2723 return -EOPNOTSUPP; 2724 2725 if (smu->ppt_funcs->display_clock_voltage_request) 2726 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2727 2728 return ret; 2729 } 2730 2731 2732 static int smu_display_disable_memory_clock_switch(void *handle, 2733 bool disable_memory_clock_switch) 2734 { 2735 struct smu_context *smu = handle; 2736 int ret = -EINVAL; 2737 2738 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2739 return -EOPNOTSUPP; 2740 2741 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2742 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2743 2744 return ret; 2745 } 2746 2747 static int smu_set_xgmi_pstate(void *handle, 2748 uint32_t pstate) 2749 { 2750 struct smu_context *smu = handle; 2751 int ret = 0; 2752 2753 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2754 return -EOPNOTSUPP; 2755 2756 if (smu->ppt_funcs->set_xgmi_pstate) 2757 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2758 2759 if(ret) 2760 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2761 2762 return ret; 2763 } 2764 2765 static int smu_get_baco_capability(void *handle, bool *cap) 2766 { 2767 struct smu_context *smu = handle; 2768 2769 *cap = false; 2770 2771 if (!smu->pm_enabled) 2772 return 0; 2773 2774 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2775 *cap = smu->ppt_funcs->baco_is_support(smu); 2776 2777 return 0; 2778 } 2779 2780 static int smu_baco_set_state(void *handle, int state) 2781 { 2782 struct smu_context *smu = handle; 2783 int ret = 0; 2784 2785 if (!smu->pm_enabled) 2786 return -EOPNOTSUPP; 2787 2788 if (state == 0) { 2789 if (smu->ppt_funcs->baco_exit) 2790 ret = smu->ppt_funcs->baco_exit(smu); 2791 } else if (state == 1) { 2792 if (smu->ppt_funcs->baco_enter) 2793 ret = smu->ppt_funcs->baco_enter(smu); 2794 } else { 2795 return -EINVAL; 2796 } 2797 2798 if (ret) 2799 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2800 (state)?"enter":"exit"); 2801 2802 return ret; 2803 } 2804 2805 bool smu_mode1_reset_is_support(struct smu_context *smu) 2806 { 2807 bool ret = false; 2808 2809 if (!smu->pm_enabled) 2810 return false; 2811 2812 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2813 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2814 2815 return ret; 2816 } 2817 2818 bool smu_mode2_reset_is_support(struct smu_context *smu) 2819 { 2820 bool ret = false; 2821 2822 if (!smu->pm_enabled) 2823 return false; 2824 2825 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2826 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2827 2828 return ret; 2829 } 2830 2831 int smu_mode1_reset(struct smu_context *smu) 2832 { 2833 int ret = 0; 2834 2835 if (!smu->pm_enabled) 2836 return -EOPNOTSUPP; 2837 2838 if (smu->ppt_funcs->mode1_reset) 2839 ret = smu->ppt_funcs->mode1_reset(smu); 2840 2841 return ret; 2842 } 2843 2844 static int smu_mode2_reset(void *handle) 2845 { 2846 struct smu_context *smu = handle; 2847 int ret = 0; 2848 2849 if (!smu->pm_enabled) 2850 return -EOPNOTSUPP; 2851 2852 if (smu->ppt_funcs->mode2_reset) 2853 ret = smu->ppt_funcs->mode2_reset(smu); 2854 2855 if (ret) 2856 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2857 2858 return ret; 2859 } 2860 2861 static int smu_enable_gfx_features(void *handle) 2862 { 2863 struct smu_context *smu = handle; 2864 int ret = 0; 2865 2866 if (!smu->pm_enabled) 2867 return -EOPNOTSUPP; 2868 2869 if (smu->ppt_funcs->enable_gfx_features) 2870 ret = smu->ppt_funcs->enable_gfx_features(smu); 2871 2872 if (ret) 2873 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 2874 2875 return ret; 2876 } 2877 2878 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2879 struct pp_smu_nv_clock_table *max_clocks) 2880 { 2881 struct smu_context *smu = handle; 2882 int ret = 0; 2883 2884 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2885 return -EOPNOTSUPP; 2886 2887 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2888 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2889 2890 return ret; 2891 } 2892 2893 static int smu_get_uclk_dpm_states(void *handle, 2894 unsigned int *clock_values_in_khz, 2895 unsigned int *num_states) 2896 { 2897 struct smu_context *smu = handle; 2898 int ret = 0; 2899 2900 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2901 return -EOPNOTSUPP; 2902 2903 if (smu->ppt_funcs->get_uclk_dpm_states) 2904 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2905 2906 return ret; 2907 } 2908 2909 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2910 { 2911 struct smu_context *smu = handle; 2912 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2913 2914 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2915 return -EOPNOTSUPP; 2916 2917 if (smu->ppt_funcs->get_current_power_state) 2918 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2919 2920 return pm_state; 2921 } 2922 2923 static int smu_get_dpm_clock_table(void *handle, 2924 struct dpm_clocks *clock_table) 2925 { 2926 struct smu_context *smu = handle; 2927 int ret = 0; 2928 2929 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2930 return -EOPNOTSUPP; 2931 2932 if (smu->ppt_funcs->get_dpm_clock_table) 2933 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2934 2935 return ret; 2936 } 2937 2938 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2939 { 2940 struct smu_context *smu = handle; 2941 2942 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2943 return -EOPNOTSUPP; 2944 2945 if (!smu->ppt_funcs->get_gpu_metrics) 2946 return -EOPNOTSUPP; 2947 2948 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2949 } 2950 2951 static int smu_enable_mgpu_fan_boost(void *handle) 2952 { 2953 struct smu_context *smu = handle; 2954 int ret = 0; 2955 2956 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2957 return -EOPNOTSUPP; 2958 2959 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2960 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2961 2962 return ret; 2963 } 2964 2965 static int smu_gfx_state_change_set(void *handle, 2966 uint32_t state) 2967 { 2968 struct smu_context *smu = handle; 2969 int ret = 0; 2970 2971 if (smu->ppt_funcs->gfx_state_change_set) 2972 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2973 2974 return ret; 2975 } 2976 2977 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2978 { 2979 int ret = 0; 2980 2981 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2982 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2983 2984 return ret; 2985 } 2986 2987 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2988 { 2989 int ret = -EOPNOTSUPP; 2990 2991 if (smu->ppt_funcs && 2992 smu->ppt_funcs->get_ecc_info) 2993 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2994 2995 return ret; 2996 2997 } 2998 2999 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3000 { 3001 struct smu_context *smu = handle; 3002 struct smu_table_context *smu_table = &smu->smu_table; 3003 struct smu_table *memory_pool = &smu_table->memory_pool; 3004 3005 if (!addr || !size) 3006 return -EINVAL; 3007 3008 *addr = NULL; 3009 *size = 0; 3010 if (memory_pool->bo) { 3011 *addr = memory_pool->cpu_addr; 3012 *size = memory_pool->size; 3013 } 3014 3015 return 0; 3016 } 3017 3018 static const struct amd_pm_funcs swsmu_pm_funcs = { 3019 /* export for sysfs */ 3020 .set_fan_control_mode = smu_set_fan_control_mode, 3021 .get_fan_control_mode = smu_get_fan_control_mode, 3022 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3023 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3024 .force_clock_level = smu_force_ppclk_levels, 3025 .print_clock_levels = smu_print_ppclk_levels, 3026 .emit_clock_levels = smu_emit_ppclk_levels, 3027 .force_performance_level = smu_force_performance_level, 3028 .read_sensor = smu_read_sensor, 3029 .get_performance_level = smu_get_performance_level, 3030 .get_current_power_state = smu_get_current_power_state, 3031 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3032 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3033 .get_pp_num_states = smu_get_power_num_states, 3034 .get_pp_table = smu_sys_get_pp_table, 3035 .set_pp_table = smu_sys_set_pp_table, 3036 .switch_power_profile = smu_switch_power_profile, 3037 /* export to amdgpu */ 3038 .dispatch_tasks = smu_handle_dpm_task, 3039 .load_firmware = smu_load_microcode, 3040 .set_powergating_by_smu = smu_dpm_set_power_gate, 3041 .set_power_limit = smu_set_power_limit, 3042 .get_power_limit = smu_get_power_limit, 3043 .get_power_profile_mode = smu_get_power_profile_mode, 3044 .set_power_profile_mode = smu_set_power_profile_mode, 3045 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3046 .set_mp1_state = smu_set_mp1_state, 3047 .gfx_state_change_set = smu_gfx_state_change_set, 3048 /* export to DC */ 3049 .get_sclk = smu_get_sclk, 3050 .get_mclk = smu_get_mclk, 3051 .display_configuration_change = smu_display_configuration_change, 3052 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3053 .display_clock_voltage_request = smu_display_clock_voltage_request, 3054 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3055 .set_active_display_count = smu_set_display_count, 3056 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3057 .get_asic_baco_capability = smu_get_baco_capability, 3058 .set_asic_baco_state = smu_baco_set_state, 3059 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3060 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3061 .asic_reset_mode_2 = smu_mode2_reset, 3062 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3063 .set_df_cstate = smu_set_df_cstate, 3064 .set_xgmi_pstate = smu_set_xgmi_pstate, 3065 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3066 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3067 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3068 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3069 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3070 .get_dpm_clock_table = smu_get_dpm_clock_table, 3071 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3072 }; 3073 3074 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3075 uint64_t event_arg) 3076 { 3077 int ret = -EINVAL; 3078 3079 if (smu->ppt_funcs->wait_for_event) 3080 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3081 3082 return ret; 3083 } 3084 3085 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3086 { 3087 3088 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3089 return -EOPNOTSUPP; 3090 3091 /* Confirm the buffer allocated is of correct size */ 3092 if (size != smu->stb_context.stb_buf_size) 3093 return -EINVAL; 3094 3095 /* 3096 * No need to lock smu mutex as we access STB directly through MMIO 3097 * and not going through SMU messaging route (for now at least). 3098 * For registers access rely on implementation internal locking. 3099 */ 3100 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3101 } 3102 3103 #if defined(CONFIG_DEBUG_FS) 3104 3105 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3106 { 3107 struct amdgpu_device *adev = filp->f_inode->i_private; 3108 struct smu_context *smu = adev->powerplay.pp_handle; 3109 unsigned char *buf; 3110 int r; 3111 3112 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3113 if (!buf) 3114 return -ENOMEM; 3115 3116 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3117 if (r) 3118 goto out; 3119 3120 filp->private_data = buf; 3121 3122 return 0; 3123 3124 out: 3125 kvfree(buf); 3126 return r; 3127 } 3128 3129 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3130 loff_t *pos) 3131 { 3132 struct amdgpu_device *adev = filp->f_inode->i_private; 3133 struct smu_context *smu = adev->powerplay.pp_handle; 3134 3135 3136 if (!filp->private_data) 3137 return -EINVAL; 3138 3139 return simple_read_from_buffer(buf, 3140 size, 3141 pos, filp->private_data, 3142 smu->stb_context.stb_buf_size); 3143 } 3144 3145 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3146 { 3147 kvfree(filp->private_data); 3148 filp->private_data = NULL; 3149 3150 return 0; 3151 } 3152 3153 /* 3154 * We have to define not only read method but also 3155 * open and release because .read takes up to PAGE_SIZE 3156 * data each time so and so is invoked multiple times. 3157 * We allocate the STB buffer in .open and release it 3158 * in .release 3159 */ 3160 static const struct file_operations smu_stb_debugfs_fops = { 3161 .owner = THIS_MODULE, 3162 .open = smu_stb_debugfs_open, 3163 .read = smu_stb_debugfs_read, 3164 .release = smu_stb_debugfs_release, 3165 .llseek = default_llseek, 3166 }; 3167 3168 #endif 3169 3170 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3171 { 3172 #if defined(CONFIG_DEBUG_FS) 3173 3174 struct smu_context *smu = adev->powerplay.pp_handle; 3175 3176 if (!smu || (!smu->stb_context.stb_buf_size)) 3177 return; 3178 3179 debugfs_create_file_size("amdgpu_smu_stb_dump", 3180 S_IRUSR, 3181 adev_to_drm(adev)->primary->debugfs_root, 3182 adev, 3183 &smu_stb_debugfs_fops, 3184 smu->stb_context.stb_buf_size); 3185 #endif 3186 } 3187 3188 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3189 { 3190 int ret = 0; 3191 3192 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3193 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3194 3195 return ret; 3196 } 3197 3198 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3199 { 3200 int ret = 0; 3201 3202 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3203 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3204 3205 return ret; 3206 } 3207