1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "cyan_skillfish_ppt.h" 40 #include "smu_v13_0_0_ppt.h" 41 #include "smu_v13_0_4_ppt.h" 42 #include "smu_v13_0_5_ppt.h" 43 #include "smu_v13_0_7_ppt.h" 44 #include "amd_pcie.h" 45 46 /* 47 * DO NOT use these for err/warn/info/debug messages. 48 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 49 * They are more MGPU friendly. 50 */ 51 #undef pr_err 52 #undef pr_warn 53 #undef pr_info 54 #undef pr_debug 55 56 static const struct amd_pm_funcs swsmu_pm_funcs; 57 static int smu_force_smuclk_levels(struct smu_context *smu, 58 enum smu_clk_type clk_type, 59 uint32_t mask); 60 static int smu_handle_task(struct smu_context *smu, 61 enum amd_dpm_forced_level level, 62 enum amd_pp_task task_id); 63 static int smu_reset(struct smu_context *smu); 64 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 65 static int smu_set_fan_control_mode(void *handle, u32 value); 66 static int smu_set_power_limit(void *handle, uint32_t limit); 67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 70 71 static int smu_sys_get_pp_feature_mask(void *handle, 72 char *buf) 73 { 74 struct smu_context *smu = handle; 75 76 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 77 return -EOPNOTSUPP; 78 79 return smu_get_pp_feature_mask(smu, buf); 80 } 81 82 static int smu_sys_set_pp_feature_mask(void *handle, 83 uint64_t new_mask) 84 { 85 struct smu_context *smu = handle; 86 87 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 88 return -EOPNOTSUPP; 89 90 return smu_set_pp_feature_mask(smu, new_mask); 91 } 92 93 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 94 { 95 if (!smu->ppt_funcs->set_gfx_off_residency) 96 return -EINVAL; 97 98 return smu_set_gfx_off_residency(smu, value); 99 } 100 101 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 102 { 103 if (!smu->ppt_funcs->get_gfx_off_residency) 104 return -EINVAL; 105 106 return smu_get_gfx_off_residency(smu, value); 107 } 108 109 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 110 { 111 if (!smu->ppt_funcs->get_gfx_off_entrycount) 112 return -EINVAL; 113 114 return smu_get_gfx_off_entrycount(smu, value); 115 } 116 117 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 118 { 119 if (!smu->ppt_funcs->get_gfx_off_status) 120 return -EINVAL; 121 122 *value = smu_get_gfx_off_status(smu); 123 124 return 0; 125 } 126 127 int smu_set_soft_freq_range(struct smu_context *smu, 128 enum smu_clk_type clk_type, 129 uint32_t min, 130 uint32_t max) 131 { 132 int ret = 0; 133 134 if (smu->ppt_funcs->set_soft_freq_limited_range) 135 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 136 clk_type, 137 min, 138 max); 139 140 return ret; 141 } 142 143 int smu_get_dpm_freq_range(struct smu_context *smu, 144 enum smu_clk_type clk_type, 145 uint32_t *min, 146 uint32_t *max) 147 { 148 int ret = -ENOTSUPP; 149 150 if (!min && !max) 151 return -EINVAL; 152 153 if (smu->ppt_funcs->get_dpm_ultimate_freq) 154 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 155 clk_type, 156 min, 157 max); 158 159 return ret; 160 } 161 162 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 163 { 164 if (!smu->ppt_funcs || !smu->ppt_funcs->set_gfx_power_up_by_imu) 165 return -EOPNOTSUPP; 166 167 return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 168 } 169 170 static u32 smu_get_mclk(void *handle, bool low) 171 { 172 struct smu_context *smu = handle; 173 uint32_t clk_freq; 174 int ret = 0; 175 176 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 177 low ? &clk_freq : NULL, 178 !low ? &clk_freq : NULL); 179 if (ret) 180 return 0; 181 return clk_freq * 100; 182 } 183 184 static u32 smu_get_sclk(void *handle, bool low) 185 { 186 struct smu_context *smu = handle; 187 uint32_t clk_freq; 188 int ret = 0; 189 190 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 191 low ? &clk_freq : NULL, 192 !low ? &clk_freq : NULL); 193 if (ret) 194 return 0; 195 return clk_freq * 100; 196 } 197 198 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 199 bool enable) 200 { 201 struct smu_power_context *smu_power = &smu->smu_power; 202 struct smu_power_gate *power_gate = &smu_power->power_gate; 203 int ret = 0; 204 205 if (!smu->ppt_funcs->dpm_set_vcn_enable) 206 return 0; 207 208 if (atomic_read(&power_gate->vcn_gated) ^ enable) 209 return 0; 210 211 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 212 if (!ret) 213 atomic_set(&power_gate->vcn_gated, !enable); 214 215 return ret; 216 } 217 218 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 219 bool enable) 220 { 221 struct smu_power_context *smu_power = &smu->smu_power; 222 struct smu_power_gate *power_gate = &smu_power->power_gate; 223 int ret = 0; 224 225 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 226 return 0; 227 228 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 229 return 0; 230 231 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 232 if (!ret) 233 atomic_set(&power_gate->jpeg_gated, !enable); 234 235 return ret; 236 } 237 238 /** 239 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 240 * 241 * @handle: smu_context pointer 242 * @block_type: the IP block to power gate/ungate 243 * @gate: to power gate if true, ungate otherwise 244 * 245 * This API uses no smu->mutex lock protection due to: 246 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 247 * This is guarded to be race condition free by the caller. 248 * 2. Or get called on user setting request of power_dpm_force_performance_level. 249 * Under this case, the smu->mutex lock protection is already enforced on 250 * the parent API smu_force_performance_level of the call path. 251 */ 252 static int smu_dpm_set_power_gate(void *handle, 253 uint32_t block_type, 254 bool gate) 255 { 256 struct smu_context *smu = handle; 257 int ret = 0; 258 259 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 260 dev_WARN(smu->adev->dev, 261 "SMU uninitialized but power %s requested for %u!\n", 262 gate ? "gate" : "ungate", block_type); 263 return -EOPNOTSUPP; 264 } 265 266 switch (block_type) { 267 /* 268 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 269 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 270 */ 271 case AMD_IP_BLOCK_TYPE_UVD: 272 case AMD_IP_BLOCK_TYPE_VCN: 273 ret = smu_dpm_set_vcn_enable(smu, !gate); 274 if (ret) 275 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 276 gate ? "gate" : "ungate"); 277 break; 278 case AMD_IP_BLOCK_TYPE_GFX: 279 ret = smu_gfx_off_control(smu, gate); 280 if (ret) 281 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 282 gate ? "enable" : "disable"); 283 break; 284 case AMD_IP_BLOCK_TYPE_SDMA: 285 ret = smu_powergate_sdma(smu, gate); 286 if (ret) 287 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 288 gate ? "gate" : "ungate"); 289 break; 290 case AMD_IP_BLOCK_TYPE_JPEG: 291 ret = smu_dpm_set_jpeg_enable(smu, !gate); 292 if (ret) 293 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 294 gate ? "gate" : "ungate"); 295 break; 296 default: 297 dev_err(smu->adev->dev, "Unsupported block type!\n"); 298 return -EINVAL; 299 } 300 301 return ret; 302 } 303 304 /** 305 * smu_set_user_clk_dependencies - set user profile clock dependencies 306 * 307 * @smu: smu_context pointer 308 * @clk: enum smu_clk_type type 309 * 310 * Enable/Disable the clock dependency for the @clk type. 311 */ 312 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 313 { 314 if (smu->adev->in_suspend) 315 return; 316 317 if (clk == SMU_MCLK) { 318 smu->user_dpm_profile.clk_dependency = 0; 319 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 320 } else if (clk == SMU_FCLK) { 321 /* MCLK takes precedence over FCLK */ 322 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 323 return; 324 325 smu->user_dpm_profile.clk_dependency = 0; 326 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 327 } else if (clk == SMU_SOCCLK) { 328 /* MCLK takes precedence over SOCCLK */ 329 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 330 return; 331 332 smu->user_dpm_profile.clk_dependency = 0; 333 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 334 } else 335 /* Add clk dependencies here, if any */ 336 return; 337 } 338 339 /** 340 * smu_restore_dpm_user_profile - reinstate user dpm profile 341 * 342 * @smu: smu_context pointer 343 * 344 * Restore the saved user power configurations include power limit, 345 * clock frequencies, fan control mode and fan speed. 346 */ 347 static void smu_restore_dpm_user_profile(struct smu_context *smu) 348 { 349 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 350 int ret = 0; 351 352 if (!smu->adev->in_suspend) 353 return; 354 355 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 356 return; 357 358 /* Enable restore flag */ 359 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 360 361 /* set the user dpm power limit */ 362 if (smu->user_dpm_profile.power_limit) { 363 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 364 if (ret) 365 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 366 } 367 368 /* set the user dpm clock configurations */ 369 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 370 enum smu_clk_type clk_type; 371 372 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 373 /* 374 * Iterate over smu clk type and force the saved user clk 375 * configs, skip if clock dependency is enabled 376 */ 377 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 378 smu->user_dpm_profile.clk_mask[clk_type]) { 379 ret = smu_force_smuclk_levels(smu, clk_type, 380 smu->user_dpm_profile.clk_mask[clk_type]); 381 if (ret) 382 dev_err(smu->adev->dev, 383 "Failed to set clock type = %d\n", clk_type); 384 } 385 } 386 } 387 388 /* set the user dpm fan configurations */ 389 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 390 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 391 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 392 if (ret != -EOPNOTSUPP) { 393 smu->user_dpm_profile.fan_speed_pwm = 0; 394 smu->user_dpm_profile.fan_speed_rpm = 0; 395 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 396 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 397 } 398 399 if (smu->user_dpm_profile.fan_speed_pwm) { 400 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 401 if (ret != -EOPNOTSUPP) 402 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 403 } 404 405 if (smu->user_dpm_profile.fan_speed_rpm) { 406 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 407 if (ret != -EOPNOTSUPP) 408 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 409 } 410 } 411 412 /* Restore user customized OD settings */ 413 if (smu->user_dpm_profile.user_od) { 414 if (smu->ppt_funcs->restore_user_od_settings) { 415 ret = smu->ppt_funcs->restore_user_od_settings(smu); 416 if (ret) 417 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 418 } 419 } 420 421 /* Disable restore flag */ 422 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 423 } 424 425 static int smu_get_power_num_states(void *handle, 426 struct pp_states_info *state_info) 427 { 428 if (!state_info) 429 return -EINVAL; 430 431 /* not support power state */ 432 memset(state_info, 0, sizeof(struct pp_states_info)); 433 state_info->nums = 1; 434 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 435 436 return 0; 437 } 438 439 bool is_support_sw_smu(struct amdgpu_device *adev) 440 { 441 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 442 if (adev->asic_type == CHIP_VEGA20) 443 return false; 444 445 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 446 return true; 447 448 return false; 449 } 450 451 bool is_support_cclk_dpm(struct amdgpu_device *adev) 452 { 453 struct smu_context *smu = adev->powerplay.pp_handle; 454 455 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 456 return false; 457 458 return true; 459 } 460 461 462 static int smu_sys_get_pp_table(void *handle, 463 char **table) 464 { 465 struct smu_context *smu = handle; 466 struct smu_table_context *smu_table = &smu->smu_table; 467 468 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 469 return -EOPNOTSUPP; 470 471 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 472 return -EINVAL; 473 474 if (smu_table->hardcode_pptable) 475 *table = smu_table->hardcode_pptable; 476 else 477 *table = smu_table->power_play_table; 478 479 return smu_table->power_play_table_size; 480 } 481 482 static int smu_sys_set_pp_table(void *handle, 483 const char *buf, 484 size_t size) 485 { 486 struct smu_context *smu = handle; 487 struct smu_table_context *smu_table = &smu->smu_table; 488 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 489 int ret = 0; 490 491 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 492 return -EOPNOTSUPP; 493 494 if (header->usStructureSize != size) { 495 dev_err(smu->adev->dev, "pp table size not matched !\n"); 496 return -EIO; 497 } 498 499 if (!smu_table->hardcode_pptable) { 500 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 501 if (!smu_table->hardcode_pptable) 502 return -ENOMEM; 503 } 504 505 memcpy(smu_table->hardcode_pptable, buf, size); 506 smu_table->power_play_table = smu_table->hardcode_pptable; 507 smu_table->power_play_table_size = size; 508 509 /* 510 * Special hw_fini action(for Navi1x, the DPMs disablement will be 511 * skipped) may be needed for custom pptable uploading. 512 */ 513 smu->uploading_custom_pp_table = true; 514 515 ret = smu_reset(smu); 516 if (ret) 517 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 518 519 smu->uploading_custom_pp_table = false; 520 521 return ret; 522 } 523 524 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 525 { 526 struct smu_feature *feature = &smu->smu_feature; 527 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 528 int ret = 0; 529 530 /* 531 * With SCPM enabled, the allowed featuremasks setting(via 532 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 533 * That means there is no way to let PMFW knows the settings below. 534 * Thus, we just assume all the features are allowed under 535 * such scenario. 536 */ 537 if (smu->adev->scpm_enabled) { 538 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 539 return 0; 540 } 541 542 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 543 544 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 545 SMU_FEATURE_MAX/32); 546 if (ret) 547 return ret; 548 549 bitmap_or(feature->allowed, feature->allowed, 550 (unsigned long *)allowed_feature_mask, 551 feature->feature_num); 552 553 return ret; 554 } 555 556 static int smu_set_funcs(struct amdgpu_device *adev) 557 { 558 struct smu_context *smu = adev->powerplay.pp_handle; 559 560 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 561 smu->od_enabled = true; 562 563 switch (adev->ip_versions[MP1_HWIP][0]) { 564 case IP_VERSION(11, 0, 0): 565 case IP_VERSION(11, 0, 5): 566 case IP_VERSION(11, 0, 9): 567 navi10_set_ppt_funcs(smu); 568 break; 569 case IP_VERSION(11, 0, 7): 570 case IP_VERSION(11, 0, 11): 571 case IP_VERSION(11, 0, 12): 572 case IP_VERSION(11, 0, 13): 573 sienna_cichlid_set_ppt_funcs(smu); 574 break; 575 case IP_VERSION(12, 0, 0): 576 case IP_VERSION(12, 0, 1): 577 renoir_set_ppt_funcs(smu); 578 break; 579 case IP_VERSION(11, 5, 0): 580 vangogh_set_ppt_funcs(smu); 581 break; 582 case IP_VERSION(13, 0, 1): 583 case IP_VERSION(13, 0, 3): 584 case IP_VERSION(13, 0, 8): 585 yellow_carp_set_ppt_funcs(smu); 586 break; 587 case IP_VERSION(13, 0, 4): 588 case IP_VERSION(13, 0, 11): 589 smu_v13_0_4_set_ppt_funcs(smu); 590 break; 591 case IP_VERSION(13, 0, 5): 592 smu_v13_0_5_set_ppt_funcs(smu); 593 break; 594 case IP_VERSION(11, 0, 8): 595 cyan_skillfish_set_ppt_funcs(smu); 596 break; 597 case IP_VERSION(11, 0, 2): 598 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 599 arcturus_set_ppt_funcs(smu); 600 /* OD is not supported on Arcturus */ 601 smu->od_enabled =false; 602 break; 603 case IP_VERSION(13, 0, 2): 604 aldebaran_set_ppt_funcs(smu); 605 /* Enable pp_od_clk_voltage node */ 606 smu->od_enabled = true; 607 break; 608 case IP_VERSION(13, 0, 0): 609 case IP_VERSION(13, 0, 10): 610 smu_v13_0_0_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(13, 0, 7): 613 smu_v13_0_7_set_ppt_funcs(smu); 614 break; 615 default: 616 return -EINVAL; 617 } 618 619 return 0; 620 } 621 622 static int smu_early_init(void *handle) 623 { 624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 625 struct smu_context *smu; 626 int r; 627 628 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 629 if (!smu) 630 return -ENOMEM; 631 632 smu->adev = adev; 633 smu->pm_enabled = !!amdgpu_dpm; 634 smu->is_apu = false; 635 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 636 smu->smu_baco.platform_support = false; 637 smu->user_dpm_profile.fan_mode = -1; 638 639 mutex_init(&smu->message_lock); 640 641 adev->powerplay.pp_handle = smu; 642 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 643 644 r = smu_set_funcs(adev); 645 if (r) 646 return r; 647 return smu_init_microcode(smu); 648 } 649 650 static int smu_set_default_dpm_table(struct smu_context *smu) 651 { 652 struct smu_power_context *smu_power = &smu->smu_power; 653 struct smu_power_gate *power_gate = &smu_power->power_gate; 654 int vcn_gate, jpeg_gate; 655 int ret = 0; 656 657 if (!smu->ppt_funcs->set_default_dpm_table) 658 return 0; 659 660 vcn_gate = atomic_read(&power_gate->vcn_gated); 661 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 662 663 ret = smu_dpm_set_vcn_enable(smu, true); 664 if (ret) 665 return ret; 666 667 ret = smu_dpm_set_jpeg_enable(smu, true); 668 if (ret) 669 goto err_out; 670 671 ret = smu->ppt_funcs->set_default_dpm_table(smu); 672 if (ret) 673 dev_err(smu->adev->dev, 674 "Failed to setup default dpm clock tables!\n"); 675 676 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 677 err_out: 678 smu_dpm_set_vcn_enable(smu, !vcn_gate); 679 return ret; 680 } 681 682 static int smu_apply_default_config_table_settings(struct smu_context *smu) 683 { 684 struct amdgpu_device *adev = smu->adev; 685 int ret = 0; 686 687 ret = smu_get_default_config_table_settings(smu, 688 &adev->pm.config_table); 689 if (ret) 690 return ret; 691 692 return smu_set_config_table(smu, &adev->pm.config_table); 693 } 694 695 static int smu_late_init(void *handle) 696 { 697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 698 struct smu_context *smu = adev->powerplay.pp_handle; 699 int ret = 0; 700 701 smu_set_fine_grain_gfx_freq_parameters(smu); 702 703 if (!smu->pm_enabled) 704 return 0; 705 706 ret = smu_post_init(smu); 707 if (ret) { 708 dev_err(adev->dev, "Failed to post smu init!\n"); 709 return ret; 710 } 711 712 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 713 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 714 return 0; 715 716 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 717 ret = smu_set_default_od_settings(smu); 718 if (ret) { 719 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 720 return ret; 721 } 722 } 723 724 ret = smu_populate_umd_state_clk(smu); 725 if (ret) { 726 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 727 return ret; 728 } 729 730 ret = smu_get_asic_power_limits(smu, 731 &smu->current_power_limit, 732 &smu->default_power_limit, 733 &smu->max_power_limit); 734 if (ret) { 735 dev_err(adev->dev, "Failed to get asic power limits!\n"); 736 return ret; 737 } 738 739 if (!amdgpu_sriov_vf(adev)) 740 smu_get_unique_id(smu); 741 742 smu_get_fan_parameters(smu); 743 744 smu_handle_task(smu, 745 smu->smu_dpm.dpm_level, 746 AMD_PP_TASK_COMPLETE_INIT); 747 748 ret = smu_apply_default_config_table_settings(smu); 749 if (ret && (ret != -EOPNOTSUPP)) { 750 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 751 return ret; 752 } 753 754 smu_restore_dpm_user_profile(smu); 755 756 return 0; 757 } 758 759 static int smu_init_fb_allocations(struct smu_context *smu) 760 { 761 struct amdgpu_device *adev = smu->adev; 762 struct smu_table_context *smu_table = &smu->smu_table; 763 struct smu_table *tables = smu_table->tables; 764 struct smu_table *driver_table = &(smu_table->driver_table); 765 uint32_t max_table_size = 0; 766 int ret, i; 767 768 /* VRAM allocation for tool table */ 769 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 770 ret = amdgpu_bo_create_kernel(adev, 771 tables[SMU_TABLE_PMSTATUSLOG].size, 772 tables[SMU_TABLE_PMSTATUSLOG].align, 773 tables[SMU_TABLE_PMSTATUSLOG].domain, 774 &tables[SMU_TABLE_PMSTATUSLOG].bo, 775 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 776 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 777 if (ret) { 778 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 779 return ret; 780 } 781 } 782 783 /* VRAM allocation for driver table */ 784 for (i = 0; i < SMU_TABLE_COUNT; i++) { 785 if (tables[i].size == 0) 786 continue; 787 788 if (i == SMU_TABLE_PMSTATUSLOG) 789 continue; 790 791 if (max_table_size < tables[i].size) 792 max_table_size = tables[i].size; 793 } 794 795 driver_table->size = max_table_size; 796 driver_table->align = PAGE_SIZE; 797 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 798 799 ret = amdgpu_bo_create_kernel(adev, 800 driver_table->size, 801 driver_table->align, 802 driver_table->domain, 803 &driver_table->bo, 804 &driver_table->mc_address, 805 &driver_table->cpu_addr); 806 if (ret) { 807 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 808 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 809 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 810 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 811 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 812 } 813 814 return ret; 815 } 816 817 static int smu_fini_fb_allocations(struct smu_context *smu) 818 { 819 struct smu_table_context *smu_table = &smu->smu_table; 820 struct smu_table *tables = smu_table->tables; 821 struct smu_table *driver_table = &(smu_table->driver_table); 822 823 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 824 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 825 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 826 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 827 828 amdgpu_bo_free_kernel(&driver_table->bo, 829 &driver_table->mc_address, 830 &driver_table->cpu_addr); 831 832 return 0; 833 } 834 835 /** 836 * smu_alloc_memory_pool - allocate memory pool in the system memory 837 * 838 * @smu: amdgpu_device pointer 839 * 840 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 841 * and DramLogSetDramAddr can notify it changed. 842 * 843 * Returns 0 on success, error on failure. 844 */ 845 static int smu_alloc_memory_pool(struct smu_context *smu) 846 { 847 struct amdgpu_device *adev = smu->adev; 848 struct smu_table_context *smu_table = &smu->smu_table; 849 struct smu_table *memory_pool = &smu_table->memory_pool; 850 uint64_t pool_size = smu->pool_size; 851 int ret = 0; 852 853 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 854 return ret; 855 856 memory_pool->size = pool_size; 857 memory_pool->align = PAGE_SIZE; 858 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 859 860 switch (pool_size) { 861 case SMU_MEMORY_POOL_SIZE_256_MB: 862 case SMU_MEMORY_POOL_SIZE_512_MB: 863 case SMU_MEMORY_POOL_SIZE_1_GB: 864 case SMU_MEMORY_POOL_SIZE_2_GB: 865 ret = amdgpu_bo_create_kernel(adev, 866 memory_pool->size, 867 memory_pool->align, 868 memory_pool->domain, 869 &memory_pool->bo, 870 &memory_pool->mc_address, 871 &memory_pool->cpu_addr); 872 if (ret) 873 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 874 break; 875 default: 876 break; 877 } 878 879 return ret; 880 } 881 882 static int smu_free_memory_pool(struct smu_context *smu) 883 { 884 struct smu_table_context *smu_table = &smu->smu_table; 885 struct smu_table *memory_pool = &smu_table->memory_pool; 886 887 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 888 return 0; 889 890 amdgpu_bo_free_kernel(&memory_pool->bo, 891 &memory_pool->mc_address, 892 &memory_pool->cpu_addr); 893 894 memset(memory_pool, 0, sizeof(struct smu_table)); 895 896 return 0; 897 } 898 899 static int smu_alloc_dummy_read_table(struct smu_context *smu) 900 { 901 struct smu_table_context *smu_table = &smu->smu_table; 902 struct smu_table *dummy_read_1_table = 903 &smu_table->dummy_read_1_table; 904 struct amdgpu_device *adev = smu->adev; 905 int ret = 0; 906 907 dummy_read_1_table->size = 0x40000; 908 dummy_read_1_table->align = PAGE_SIZE; 909 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 910 911 ret = amdgpu_bo_create_kernel(adev, 912 dummy_read_1_table->size, 913 dummy_read_1_table->align, 914 dummy_read_1_table->domain, 915 &dummy_read_1_table->bo, 916 &dummy_read_1_table->mc_address, 917 &dummy_read_1_table->cpu_addr); 918 if (ret) 919 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 920 921 return ret; 922 } 923 924 static void smu_free_dummy_read_table(struct smu_context *smu) 925 { 926 struct smu_table_context *smu_table = &smu->smu_table; 927 struct smu_table *dummy_read_1_table = 928 &smu_table->dummy_read_1_table; 929 930 931 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 932 &dummy_read_1_table->mc_address, 933 &dummy_read_1_table->cpu_addr); 934 935 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 936 } 937 938 static int smu_smc_table_sw_init(struct smu_context *smu) 939 { 940 int ret; 941 942 /** 943 * Create smu_table structure, and init smc tables such as 944 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 945 */ 946 ret = smu_init_smc_tables(smu); 947 if (ret) { 948 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 949 return ret; 950 } 951 952 /** 953 * Create smu_power_context structure, and allocate smu_dpm_context and 954 * context size to fill the smu_power_context data. 955 */ 956 ret = smu_init_power(smu); 957 if (ret) { 958 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 959 return ret; 960 } 961 962 /* 963 * allocate vram bos to store smc table contents. 964 */ 965 ret = smu_init_fb_allocations(smu); 966 if (ret) 967 return ret; 968 969 ret = smu_alloc_memory_pool(smu); 970 if (ret) 971 return ret; 972 973 ret = smu_alloc_dummy_read_table(smu); 974 if (ret) 975 return ret; 976 977 ret = smu_i2c_init(smu); 978 if (ret) 979 return ret; 980 981 return 0; 982 } 983 984 static int smu_smc_table_sw_fini(struct smu_context *smu) 985 { 986 int ret; 987 988 smu_i2c_fini(smu); 989 990 smu_free_dummy_read_table(smu); 991 992 ret = smu_free_memory_pool(smu); 993 if (ret) 994 return ret; 995 996 ret = smu_fini_fb_allocations(smu); 997 if (ret) 998 return ret; 999 1000 ret = smu_fini_power(smu); 1001 if (ret) { 1002 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1003 return ret; 1004 } 1005 1006 ret = smu_fini_smc_tables(smu); 1007 if (ret) { 1008 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1009 return ret; 1010 } 1011 1012 return 0; 1013 } 1014 1015 static void smu_throttling_logging_work_fn(struct work_struct *work) 1016 { 1017 struct smu_context *smu = container_of(work, struct smu_context, 1018 throttling_logging_work); 1019 1020 smu_log_thermal_throttling(smu); 1021 } 1022 1023 static void smu_interrupt_work_fn(struct work_struct *work) 1024 { 1025 struct smu_context *smu = container_of(work, struct smu_context, 1026 interrupt_work); 1027 1028 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1029 smu->ppt_funcs->interrupt_work(smu); 1030 } 1031 1032 static int smu_sw_init(void *handle) 1033 { 1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1035 struct smu_context *smu = adev->powerplay.pp_handle; 1036 int ret; 1037 1038 smu->pool_size = adev->pm.smu_prv_buffer_size; 1039 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1040 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1041 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1042 1043 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1044 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1045 atomic64_set(&smu->throttle_int_counter, 0); 1046 smu->watermarks_bitmap = 0; 1047 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1048 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1049 1050 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1051 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1052 1053 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1054 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1055 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1056 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1057 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1058 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1059 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1060 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1061 1062 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1063 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1064 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1065 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1066 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1067 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1068 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1069 smu->display_config = &adev->pm.pm_display_cfg; 1070 1071 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1072 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1073 1074 ret = smu_smc_table_sw_init(smu); 1075 if (ret) { 1076 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1077 return ret; 1078 } 1079 1080 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1081 ret = smu_get_vbios_bootup_values(smu); 1082 if (ret) { 1083 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1084 return ret; 1085 } 1086 1087 ret = smu_init_pptable_microcode(smu); 1088 if (ret) { 1089 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1090 return ret; 1091 } 1092 1093 ret = smu_register_irq_handler(smu); 1094 if (ret) { 1095 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1096 return ret; 1097 } 1098 1099 /* If there is no way to query fan control mode, fan control is not supported */ 1100 if (!smu->ppt_funcs->get_fan_control_mode) 1101 smu->adev->pm.no_fan = true; 1102 1103 return 0; 1104 } 1105 1106 static int smu_sw_fini(void *handle) 1107 { 1108 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1109 struct smu_context *smu = adev->powerplay.pp_handle; 1110 int ret; 1111 1112 ret = smu_smc_table_sw_fini(smu); 1113 if (ret) { 1114 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1115 return ret; 1116 } 1117 1118 smu_fini_microcode(smu); 1119 1120 return 0; 1121 } 1122 1123 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1124 { 1125 struct amdgpu_device *adev = smu->adev; 1126 struct smu_temperature_range *range = 1127 &smu->thermal_range; 1128 int ret = 0; 1129 1130 if (!smu->ppt_funcs->get_thermal_temperature_range) 1131 return 0; 1132 1133 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1134 if (ret) 1135 return ret; 1136 1137 adev->pm.dpm.thermal.min_temp = range->min; 1138 adev->pm.dpm.thermal.max_temp = range->max; 1139 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1140 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1141 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1142 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1143 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1144 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1145 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1146 1147 return ret; 1148 } 1149 1150 static int smu_smc_hw_setup(struct smu_context *smu) 1151 { 1152 struct smu_feature *feature = &smu->smu_feature; 1153 struct amdgpu_device *adev = smu->adev; 1154 uint32_t pcie_gen = 0, pcie_width = 0; 1155 uint64_t features_supported; 1156 int ret = 0; 1157 1158 switch (adev->ip_versions[MP1_HWIP][0]) { 1159 case IP_VERSION(11, 0, 7): 1160 case IP_VERSION(11, 0, 11): 1161 case IP_VERSION(11, 5, 0): 1162 case IP_VERSION(11, 0, 12): 1163 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1164 dev_info(adev->dev, "dpm has been enabled\n"); 1165 ret = smu_system_features_control(smu, true); 1166 if (ret) 1167 dev_err(adev->dev, "Failed system features control!\n"); 1168 return ret; 1169 } 1170 break; 1171 default: 1172 break; 1173 } 1174 1175 ret = smu_init_display_count(smu, 0); 1176 if (ret) { 1177 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1178 return ret; 1179 } 1180 1181 ret = smu_set_driver_table_location(smu); 1182 if (ret) { 1183 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1184 return ret; 1185 } 1186 1187 /* 1188 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1189 */ 1190 ret = smu_set_tool_table_location(smu); 1191 if (ret) { 1192 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1193 return ret; 1194 } 1195 1196 /* 1197 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1198 * pool location. 1199 */ 1200 ret = smu_notify_memory_pool_location(smu); 1201 if (ret) { 1202 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1203 return ret; 1204 } 1205 1206 ret = smu_setup_pptable(smu); 1207 if (ret) { 1208 dev_err(adev->dev, "Failed to setup pptable!\n"); 1209 return ret; 1210 } 1211 1212 /* smu_dump_pptable(smu); */ 1213 1214 /* 1215 * With SCPM enabled, PSP is responsible for the PPTable transferring 1216 * (to SMU). Driver involvement is not needed and permitted. 1217 */ 1218 if (!adev->scpm_enabled) { 1219 /* 1220 * Copy pptable bo in the vram to smc with SMU MSGs such as 1221 * SetDriverDramAddr and TransferTableDram2Smu. 1222 */ 1223 ret = smu_write_pptable(smu); 1224 if (ret) { 1225 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1226 return ret; 1227 } 1228 } 1229 1230 /* issue Run*Btc msg */ 1231 ret = smu_run_btc(smu); 1232 if (ret) 1233 return ret; 1234 1235 /* 1236 * With SCPM enabled, these actions(and relevant messages) are 1237 * not needed and permitted. 1238 */ 1239 if (!adev->scpm_enabled) { 1240 ret = smu_feature_set_allowed_mask(smu); 1241 if (ret) { 1242 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1243 return ret; 1244 } 1245 } 1246 1247 ret = smu_system_features_control(smu, true); 1248 if (ret) { 1249 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1250 return ret; 1251 } 1252 1253 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1254 if (ret) { 1255 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1256 return ret; 1257 } 1258 bitmap_copy(feature->supported, 1259 (unsigned long *)&features_supported, 1260 feature->feature_num); 1261 1262 if (!smu_is_dpm_running(smu)) 1263 dev_info(adev->dev, "dpm has been disabled\n"); 1264 1265 /* 1266 * Set initialized values (get from vbios) to dpm tables context such as 1267 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1268 * type of clks. 1269 */ 1270 ret = smu_set_default_dpm_table(smu); 1271 if (ret) { 1272 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1273 return ret; 1274 } 1275 1276 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1277 pcie_gen = 3; 1278 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1279 pcie_gen = 2; 1280 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1281 pcie_gen = 1; 1282 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1283 pcie_gen = 0; 1284 1285 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1286 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1287 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1288 */ 1289 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1290 pcie_width = 6; 1291 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1292 pcie_width = 5; 1293 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1294 pcie_width = 4; 1295 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1296 pcie_width = 3; 1297 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1298 pcie_width = 2; 1299 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1300 pcie_width = 1; 1301 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1302 if (ret) { 1303 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1304 return ret; 1305 } 1306 1307 ret = smu_get_thermal_temperature_range(smu); 1308 if (ret) { 1309 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1310 return ret; 1311 } 1312 1313 ret = smu_enable_thermal_alert(smu); 1314 if (ret) { 1315 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1316 return ret; 1317 } 1318 1319 ret = smu_notify_display_change(smu); 1320 if (ret) { 1321 dev_err(adev->dev, "Failed to notify display change!\n"); 1322 return ret; 1323 } 1324 1325 /* 1326 * Set min deep sleep dce fclk with bootup value from vbios via 1327 * SetMinDeepSleepDcefclk MSG. 1328 */ 1329 ret = smu_set_min_dcef_deep_sleep(smu, 1330 smu->smu_table.boot_values.dcefclk / 100); 1331 1332 return ret; 1333 } 1334 1335 static int smu_start_smc_engine(struct smu_context *smu) 1336 { 1337 struct amdgpu_device *adev = smu->adev; 1338 int ret = 0; 1339 1340 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1341 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1342 if (smu->ppt_funcs->load_microcode) { 1343 ret = smu->ppt_funcs->load_microcode(smu); 1344 if (ret) 1345 return ret; 1346 } 1347 } 1348 } 1349 1350 if (smu->ppt_funcs->check_fw_status) { 1351 ret = smu->ppt_funcs->check_fw_status(smu); 1352 if (ret) { 1353 dev_err(adev->dev, "SMC is not ready\n"); 1354 return ret; 1355 } 1356 } 1357 1358 /* 1359 * Send msg GetDriverIfVersion to check if the return value is equal 1360 * with DRIVER_IF_VERSION of smc header. 1361 */ 1362 ret = smu_check_fw_version(smu); 1363 if (ret) 1364 return ret; 1365 1366 return ret; 1367 } 1368 1369 static int smu_hw_init(void *handle) 1370 { 1371 int ret; 1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1373 struct smu_context *smu = adev->powerplay.pp_handle; 1374 1375 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1376 smu->pm_enabled = false; 1377 return 0; 1378 } 1379 1380 ret = smu_start_smc_engine(smu); 1381 if (ret) { 1382 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1383 return ret; 1384 } 1385 1386 if (smu->is_apu) { 1387 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) && 1388 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 1389 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 1390 if (ret) { 1391 dev_err(adev->dev, "Failed to Enable gfx imu!\n"); 1392 return ret; 1393 } 1394 } 1395 1396 smu_dpm_set_vcn_enable(smu, true); 1397 smu_dpm_set_jpeg_enable(smu, true); 1398 smu_set_gfx_cgpg(smu, true); 1399 } 1400 1401 if (!smu->pm_enabled) 1402 return 0; 1403 1404 ret = smu_get_driver_allowed_feature_mask(smu); 1405 if (ret) 1406 return ret; 1407 1408 ret = smu_smc_hw_setup(smu); 1409 if (ret) { 1410 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1411 return ret; 1412 } 1413 1414 /* 1415 * Move maximum sustainable clock retrieving here considering 1416 * 1. It is not needed on resume(from S3). 1417 * 2. DAL settings come between .hw_init and .late_init of SMU. 1418 * And DAL needs to know the maximum sustainable clocks. Thus 1419 * it cannot be put in .late_init(). 1420 */ 1421 ret = smu_init_max_sustainable_clocks(smu); 1422 if (ret) { 1423 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1424 return ret; 1425 } 1426 1427 adev->pm.dpm_enabled = true; 1428 1429 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1430 1431 return 0; 1432 } 1433 1434 static int smu_disable_dpms(struct smu_context *smu) 1435 { 1436 struct amdgpu_device *adev = smu->adev; 1437 int ret = 0; 1438 bool use_baco = !smu->is_apu && 1439 ((amdgpu_in_reset(adev) && 1440 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1441 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1442 1443 /* 1444 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1445 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1446 */ 1447 switch (adev->ip_versions[MP1_HWIP][0]) { 1448 case IP_VERSION(13, 0, 0): 1449 case IP_VERSION(13, 0, 7): 1450 case IP_VERSION(13, 0, 10): 1451 return 0; 1452 default: 1453 break; 1454 } 1455 1456 /* 1457 * For custom pptable uploading, skip the DPM features 1458 * disable process on Navi1x ASICs. 1459 * - As the gfx related features are under control of 1460 * RLC on those ASICs. RLC reinitialization will be 1461 * needed to reenable them. That will cost much more 1462 * efforts. 1463 * 1464 * - SMU firmware can handle the DPM reenablement 1465 * properly. 1466 */ 1467 if (smu->uploading_custom_pp_table) { 1468 switch (adev->ip_versions[MP1_HWIP][0]) { 1469 case IP_VERSION(11, 0, 0): 1470 case IP_VERSION(11, 0, 5): 1471 case IP_VERSION(11, 0, 9): 1472 case IP_VERSION(11, 0, 7): 1473 case IP_VERSION(11, 0, 11): 1474 case IP_VERSION(11, 5, 0): 1475 case IP_VERSION(11, 0, 12): 1476 case IP_VERSION(11, 0, 13): 1477 return 0; 1478 default: 1479 break; 1480 } 1481 } 1482 1483 /* 1484 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1485 * on BACO in. Driver involvement is unnecessary. 1486 */ 1487 if (use_baco) { 1488 switch (adev->ip_versions[MP1_HWIP][0]) { 1489 case IP_VERSION(11, 0, 7): 1490 case IP_VERSION(11, 0, 0): 1491 case IP_VERSION(11, 0, 5): 1492 case IP_VERSION(11, 0, 9): 1493 case IP_VERSION(13, 0, 7): 1494 return 0; 1495 default: 1496 break; 1497 } 1498 } 1499 1500 /* 1501 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1502 * for gpu reset case. Driver involvement is unnecessary. 1503 */ 1504 if (amdgpu_in_reset(adev)) { 1505 switch (adev->ip_versions[MP1_HWIP][0]) { 1506 case IP_VERSION(13, 0, 4): 1507 case IP_VERSION(13, 0, 11): 1508 return 0; 1509 default: 1510 break; 1511 } 1512 } 1513 1514 /* 1515 * For gpu reset, runpm and hibernation through BACO, 1516 * BACO feature has to be kept enabled. 1517 */ 1518 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1519 ret = smu_disable_all_features_with_exception(smu, 1520 SMU_FEATURE_BACO_BIT); 1521 if (ret) 1522 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1523 } else { 1524 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1525 if (!adev->scpm_enabled) { 1526 ret = smu_system_features_control(smu, false); 1527 if (ret) 1528 dev_err(adev->dev, "Failed to disable smu features.\n"); 1529 } 1530 } 1531 1532 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1533 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1534 adev->gfx.rlc.funcs->stop(adev); 1535 1536 return ret; 1537 } 1538 1539 static int smu_smc_hw_cleanup(struct smu_context *smu) 1540 { 1541 struct amdgpu_device *adev = smu->adev; 1542 int ret = 0; 1543 1544 cancel_work_sync(&smu->throttling_logging_work); 1545 cancel_work_sync(&smu->interrupt_work); 1546 1547 ret = smu_disable_thermal_alert(smu); 1548 if (ret) { 1549 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1550 return ret; 1551 } 1552 1553 ret = smu_disable_dpms(smu); 1554 if (ret) { 1555 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1556 return ret; 1557 } 1558 1559 return 0; 1560 } 1561 1562 static int smu_hw_fini(void *handle) 1563 { 1564 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1565 struct smu_context *smu = adev->powerplay.pp_handle; 1566 1567 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1568 return 0; 1569 1570 smu_dpm_set_vcn_enable(smu, false); 1571 smu_dpm_set_jpeg_enable(smu, false); 1572 1573 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1574 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1575 1576 if (!smu->pm_enabled) 1577 return 0; 1578 1579 adev->pm.dpm_enabled = false; 1580 1581 return smu_smc_hw_cleanup(smu); 1582 } 1583 1584 static void smu_late_fini(void *handle) 1585 { 1586 struct amdgpu_device *adev = handle; 1587 struct smu_context *smu = adev->powerplay.pp_handle; 1588 1589 kfree(smu); 1590 } 1591 1592 static int smu_reset(struct smu_context *smu) 1593 { 1594 struct amdgpu_device *adev = smu->adev; 1595 int ret; 1596 1597 ret = smu_hw_fini(adev); 1598 if (ret) 1599 return ret; 1600 1601 ret = smu_hw_init(adev); 1602 if (ret) 1603 return ret; 1604 1605 ret = smu_late_init(adev); 1606 if (ret) 1607 return ret; 1608 1609 return 0; 1610 } 1611 1612 static int smu_suspend(void *handle) 1613 { 1614 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1615 struct smu_context *smu = adev->powerplay.pp_handle; 1616 int ret; 1617 uint64_t count; 1618 1619 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1620 return 0; 1621 1622 if (!smu->pm_enabled) 1623 return 0; 1624 1625 adev->pm.dpm_enabled = false; 1626 1627 ret = smu_smc_hw_cleanup(smu); 1628 if (ret) 1629 return ret; 1630 1631 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1632 1633 smu_set_gfx_cgpg(smu, false); 1634 1635 /* 1636 * pwfw resets entrycount when device is suspended, so we save the 1637 * last value to be used when we resume to keep it consistent 1638 */ 1639 ret = smu_get_entrycount_gfxoff(smu, &count); 1640 if (!ret) 1641 adev->gfx.gfx_off_entrycount = count; 1642 1643 return 0; 1644 } 1645 1646 static int smu_resume(void *handle) 1647 { 1648 int ret; 1649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1650 struct smu_context *smu = adev->powerplay.pp_handle; 1651 1652 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1653 return 0; 1654 1655 if (!smu->pm_enabled) 1656 return 0; 1657 1658 dev_info(adev->dev, "SMU is resuming...\n"); 1659 1660 ret = smu_start_smc_engine(smu); 1661 if (ret) { 1662 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1663 return ret; 1664 } 1665 1666 ret = smu_smc_hw_setup(smu); 1667 if (ret) { 1668 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1669 return ret; 1670 } 1671 1672 smu_set_gfx_cgpg(smu, true); 1673 1674 smu->disable_uclk_switch = 0; 1675 1676 adev->pm.dpm_enabled = true; 1677 1678 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1679 1680 return 0; 1681 } 1682 1683 static int smu_display_configuration_change(void *handle, 1684 const struct amd_pp_display_configuration *display_config) 1685 { 1686 struct smu_context *smu = handle; 1687 int index = 0; 1688 int num_of_active_display = 0; 1689 1690 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1691 return -EOPNOTSUPP; 1692 1693 if (!display_config) 1694 return -EINVAL; 1695 1696 smu_set_min_dcef_deep_sleep(smu, 1697 display_config->min_dcef_deep_sleep_set_clk / 100); 1698 1699 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1700 if (display_config->displays[index].controller_id != 0) 1701 num_of_active_display++; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int smu_set_clockgating_state(void *handle, 1708 enum amd_clockgating_state state) 1709 { 1710 return 0; 1711 } 1712 1713 static int smu_set_powergating_state(void *handle, 1714 enum amd_powergating_state state) 1715 { 1716 return 0; 1717 } 1718 1719 static int smu_enable_umd_pstate(void *handle, 1720 enum amd_dpm_forced_level *level) 1721 { 1722 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1723 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1724 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1725 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1726 1727 struct smu_context *smu = (struct smu_context*)(handle); 1728 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1729 1730 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1731 return -EINVAL; 1732 1733 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1734 /* enter umd pstate, save current level, disable gfx cg*/ 1735 if (*level & profile_mode_mask) { 1736 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1737 smu_gpo_control(smu, false); 1738 smu_gfx_ulv_control(smu, false); 1739 smu_deep_sleep_control(smu, false); 1740 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1741 } 1742 } else { 1743 /* exit umd pstate, restore level, enable gfx cg*/ 1744 if (!(*level & profile_mode_mask)) { 1745 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1746 *level = smu_dpm_ctx->saved_dpm_level; 1747 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1748 smu_deep_sleep_control(smu, true); 1749 smu_gfx_ulv_control(smu, true); 1750 smu_gpo_control(smu, true); 1751 } 1752 } 1753 1754 return 0; 1755 } 1756 1757 static int smu_bump_power_profile_mode(struct smu_context *smu, 1758 long *param, 1759 uint32_t param_size) 1760 { 1761 int ret = 0; 1762 1763 if (smu->ppt_funcs->set_power_profile_mode) 1764 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1765 1766 return ret; 1767 } 1768 1769 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1770 enum amd_dpm_forced_level level, 1771 bool skip_display_settings) 1772 { 1773 int ret = 0; 1774 int index = 0; 1775 long workload; 1776 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1777 1778 if (!skip_display_settings) { 1779 ret = smu_display_config_changed(smu); 1780 if (ret) { 1781 dev_err(smu->adev->dev, "Failed to change display config!"); 1782 return ret; 1783 } 1784 } 1785 1786 ret = smu_apply_clocks_adjust_rules(smu); 1787 if (ret) { 1788 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1789 return ret; 1790 } 1791 1792 if (!skip_display_settings) { 1793 ret = smu_notify_smc_display_config(smu); 1794 if (ret) { 1795 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1796 return ret; 1797 } 1798 } 1799 1800 if (smu_dpm_ctx->dpm_level != level) { 1801 ret = smu_asic_set_performance_level(smu, level); 1802 if (ret) { 1803 dev_err(smu->adev->dev, "Failed to set performance level!"); 1804 return ret; 1805 } 1806 1807 /* update the saved copy */ 1808 smu_dpm_ctx->dpm_level = level; 1809 } 1810 1811 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1812 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1813 index = fls(smu->workload_mask); 1814 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1815 workload = smu->workload_setting[index]; 1816 1817 if (smu->power_profile_mode != workload) 1818 smu_bump_power_profile_mode(smu, &workload, 0); 1819 } 1820 1821 return ret; 1822 } 1823 1824 static int smu_handle_task(struct smu_context *smu, 1825 enum amd_dpm_forced_level level, 1826 enum amd_pp_task task_id) 1827 { 1828 int ret = 0; 1829 1830 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1831 return -EOPNOTSUPP; 1832 1833 switch (task_id) { 1834 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1835 ret = smu_pre_display_config_changed(smu); 1836 if (ret) 1837 return ret; 1838 ret = smu_adjust_power_state_dynamic(smu, level, false); 1839 break; 1840 case AMD_PP_TASK_COMPLETE_INIT: 1841 case AMD_PP_TASK_READJUST_POWER_STATE: 1842 ret = smu_adjust_power_state_dynamic(smu, level, true); 1843 break; 1844 default: 1845 break; 1846 } 1847 1848 return ret; 1849 } 1850 1851 static int smu_handle_dpm_task(void *handle, 1852 enum amd_pp_task task_id, 1853 enum amd_pm_state_type *user_state) 1854 { 1855 struct smu_context *smu = handle; 1856 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1857 1858 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1859 1860 } 1861 1862 static int smu_switch_power_profile(void *handle, 1863 enum PP_SMC_POWER_PROFILE type, 1864 bool en) 1865 { 1866 struct smu_context *smu = handle; 1867 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1868 long workload; 1869 uint32_t index; 1870 1871 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1872 return -EOPNOTSUPP; 1873 1874 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1875 return -EINVAL; 1876 1877 if (!en) { 1878 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1879 index = fls(smu->workload_mask); 1880 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1881 workload = smu->workload_setting[index]; 1882 } else { 1883 smu->workload_mask |= (1 << smu->workload_prority[type]); 1884 index = fls(smu->workload_mask); 1885 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1886 workload = smu->workload_setting[index]; 1887 } 1888 1889 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1890 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1891 smu_bump_power_profile_mode(smu, &workload, 0); 1892 1893 return 0; 1894 } 1895 1896 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1897 { 1898 struct smu_context *smu = handle; 1899 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1900 1901 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1902 return -EOPNOTSUPP; 1903 1904 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1905 return -EINVAL; 1906 1907 return smu_dpm_ctx->dpm_level; 1908 } 1909 1910 static int smu_force_performance_level(void *handle, 1911 enum amd_dpm_forced_level level) 1912 { 1913 struct smu_context *smu = handle; 1914 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1915 int ret = 0; 1916 1917 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1918 return -EOPNOTSUPP; 1919 1920 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1921 return -EINVAL; 1922 1923 ret = smu_enable_umd_pstate(smu, &level); 1924 if (ret) 1925 return ret; 1926 1927 ret = smu_handle_task(smu, level, 1928 AMD_PP_TASK_READJUST_POWER_STATE); 1929 1930 /* reset user dpm clock state */ 1931 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1932 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1933 smu->user_dpm_profile.clk_dependency = 0; 1934 } 1935 1936 return ret; 1937 } 1938 1939 static int smu_set_display_count(void *handle, uint32_t count) 1940 { 1941 struct smu_context *smu = handle; 1942 1943 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1944 return -EOPNOTSUPP; 1945 1946 return smu_init_display_count(smu, count); 1947 } 1948 1949 static int smu_force_smuclk_levels(struct smu_context *smu, 1950 enum smu_clk_type clk_type, 1951 uint32_t mask) 1952 { 1953 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1954 int ret = 0; 1955 1956 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1957 return -EOPNOTSUPP; 1958 1959 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1960 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1961 return -EINVAL; 1962 } 1963 1964 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1965 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1966 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1967 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1968 smu_set_user_clk_dependencies(smu, clk_type); 1969 } 1970 } 1971 1972 return ret; 1973 } 1974 1975 static int smu_force_ppclk_levels(void *handle, 1976 enum pp_clock_type type, 1977 uint32_t mask) 1978 { 1979 struct smu_context *smu = handle; 1980 enum smu_clk_type clk_type; 1981 1982 switch (type) { 1983 case PP_SCLK: 1984 clk_type = SMU_SCLK; break; 1985 case PP_MCLK: 1986 clk_type = SMU_MCLK; break; 1987 case PP_PCIE: 1988 clk_type = SMU_PCIE; break; 1989 case PP_SOCCLK: 1990 clk_type = SMU_SOCCLK; break; 1991 case PP_FCLK: 1992 clk_type = SMU_FCLK; break; 1993 case PP_DCEFCLK: 1994 clk_type = SMU_DCEFCLK; break; 1995 case PP_VCLK: 1996 clk_type = SMU_VCLK; break; 1997 case PP_DCLK: 1998 clk_type = SMU_DCLK; break; 1999 case OD_SCLK: 2000 clk_type = SMU_OD_SCLK; break; 2001 case OD_MCLK: 2002 clk_type = SMU_OD_MCLK; break; 2003 case OD_VDDC_CURVE: 2004 clk_type = SMU_OD_VDDC_CURVE; break; 2005 case OD_RANGE: 2006 clk_type = SMU_OD_RANGE; break; 2007 default: 2008 return -EINVAL; 2009 } 2010 2011 return smu_force_smuclk_levels(smu, clk_type, mask); 2012 } 2013 2014 /* 2015 * On system suspending or resetting, the dpm_enabled 2016 * flag will be cleared. So that those SMU services which 2017 * are not supported will be gated. 2018 * However, the mp1 state setting should still be granted 2019 * even if the dpm_enabled cleared. 2020 */ 2021 static int smu_set_mp1_state(void *handle, 2022 enum pp_mp1_state mp1_state) 2023 { 2024 struct smu_context *smu = handle; 2025 int ret = 0; 2026 2027 if (!smu->pm_enabled) 2028 return -EOPNOTSUPP; 2029 2030 if (smu->ppt_funcs && 2031 smu->ppt_funcs->set_mp1_state) 2032 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2033 2034 return ret; 2035 } 2036 2037 static int smu_set_df_cstate(void *handle, 2038 enum pp_df_cstate state) 2039 { 2040 struct smu_context *smu = handle; 2041 int ret = 0; 2042 2043 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2044 return -EOPNOTSUPP; 2045 2046 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2047 return 0; 2048 2049 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2050 if (ret) 2051 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2052 2053 return ret; 2054 } 2055 2056 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2057 { 2058 int ret = 0; 2059 2060 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2061 return -EOPNOTSUPP; 2062 2063 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2064 return 0; 2065 2066 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2067 if (ret) 2068 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2069 2070 return ret; 2071 } 2072 2073 int smu_write_watermarks_table(struct smu_context *smu) 2074 { 2075 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2076 return -EOPNOTSUPP; 2077 2078 return smu_set_watermarks_table(smu, NULL); 2079 } 2080 2081 static int smu_set_watermarks_for_clock_ranges(void *handle, 2082 struct pp_smu_wm_range_sets *clock_ranges) 2083 { 2084 struct smu_context *smu = handle; 2085 2086 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2087 return -EOPNOTSUPP; 2088 2089 if (smu->disable_watermark) 2090 return 0; 2091 2092 return smu_set_watermarks_table(smu, clock_ranges); 2093 } 2094 2095 int smu_set_ac_dc(struct smu_context *smu) 2096 { 2097 int ret = 0; 2098 2099 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2100 return -EOPNOTSUPP; 2101 2102 /* controlled by firmware */ 2103 if (smu->dc_controlled_by_gpio) 2104 return 0; 2105 2106 ret = smu_set_power_source(smu, 2107 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2108 SMU_POWER_SOURCE_DC); 2109 if (ret) 2110 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2111 smu->adev->pm.ac_power ? "AC" : "DC"); 2112 2113 return ret; 2114 } 2115 2116 const struct amd_ip_funcs smu_ip_funcs = { 2117 .name = "smu", 2118 .early_init = smu_early_init, 2119 .late_init = smu_late_init, 2120 .sw_init = smu_sw_init, 2121 .sw_fini = smu_sw_fini, 2122 .hw_init = smu_hw_init, 2123 .hw_fini = smu_hw_fini, 2124 .late_fini = smu_late_fini, 2125 .suspend = smu_suspend, 2126 .resume = smu_resume, 2127 .is_idle = NULL, 2128 .check_soft_reset = NULL, 2129 .wait_for_idle = NULL, 2130 .soft_reset = NULL, 2131 .set_clockgating_state = smu_set_clockgating_state, 2132 .set_powergating_state = smu_set_powergating_state, 2133 }; 2134 2135 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2136 { 2137 .type = AMD_IP_BLOCK_TYPE_SMC, 2138 .major = 11, 2139 .minor = 0, 2140 .rev = 0, 2141 .funcs = &smu_ip_funcs, 2142 }; 2143 2144 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2145 { 2146 .type = AMD_IP_BLOCK_TYPE_SMC, 2147 .major = 12, 2148 .minor = 0, 2149 .rev = 0, 2150 .funcs = &smu_ip_funcs, 2151 }; 2152 2153 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2154 { 2155 .type = AMD_IP_BLOCK_TYPE_SMC, 2156 .major = 13, 2157 .minor = 0, 2158 .rev = 0, 2159 .funcs = &smu_ip_funcs, 2160 }; 2161 2162 static int smu_load_microcode(void *handle) 2163 { 2164 struct smu_context *smu = handle; 2165 struct amdgpu_device *adev = smu->adev; 2166 int ret = 0; 2167 2168 if (!smu->pm_enabled) 2169 return -EOPNOTSUPP; 2170 2171 /* This should be used for non PSP loading */ 2172 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2173 return 0; 2174 2175 if (smu->ppt_funcs->load_microcode) { 2176 ret = smu->ppt_funcs->load_microcode(smu); 2177 if (ret) { 2178 dev_err(adev->dev, "Load microcode failed\n"); 2179 return ret; 2180 } 2181 } 2182 2183 if (smu->ppt_funcs->check_fw_status) { 2184 ret = smu->ppt_funcs->check_fw_status(smu); 2185 if (ret) { 2186 dev_err(adev->dev, "SMC is not ready\n"); 2187 return ret; 2188 } 2189 } 2190 2191 return ret; 2192 } 2193 2194 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2195 { 2196 int ret = 0; 2197 2198 if (smu->ppt_funcs->set_gfx_cgpg) 2199 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2200 2201 return ret; 2202 } 2203 2204 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2205 { 2206 struct smu_context *smu = handle; 2207 int ret = 0; 2208 2209 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2210 return -EOPNOTSUPP; 2211 2212 if (!smu->ppt_funcs->set_fan_speed_rpm) 2213 return -EOPNOTSUPP; 2214 2215 if (speed == U32_MAX) 2216 return -EINVAL; 2217 2218 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2219 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2220 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2221 smu->user_dpm_profile.fan_speed_rpm = speed; 2222 2223 /* Override custom PWM setting as they cannot co-exist */ 2224 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2225 smu->user_dpm_profile.fan_speed_pwm = 0; 2226 } 2227 2228 return ret; 2229 } 2230 2231 /** 2232 * smu_get_power_limit - Request one of the SMU Power Limits 2233 * 2234 * @handle: pointer to smu context 2235 * @limit: requested limit is written back to this variable 2236 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2237 * @pp_power_type: &pp_power_type type of power 2238 * Return: 0 on success, <0 on error 2239 * 2240 */ 2241 int smu_get_power_limit(void *handle, 2242 uint32_t *limit, 2243 enum pp_power_limit_level pp_limit_level, 2244 enum pp_power_type pp_power_type) 2245 { 2246 struct smu_context *smu = handle; 2247 struct amdgpu_device *adev = smu->adev; 2248 enum smu_ppt_limit_level limit_level; 2249 uint32_t limit_type; 2250 int ret = 0; 2251 2252 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2253 return -EOPNOTSUPP; 2254 2255 switch(pp_power_type) { 2256 case PP_PWR_TYPE_SUSTAINED: 2257 limit_type = SMU_DEFAULT_PPT_LIMIT; 2258 break; 2259 case PP_PWR_TYPE_FAST: 2260 limit_type = SMU_FAST_PPT_LIMIT; 2261 break; 2262 default: 2263 return -EOPNOTSUPP; 2264 break; 2265 } 2266 2267 switch(pp_limit_level){ 2268 case PP_PWR_LIMIT_CURRENT: 2269 limit_level = SMU_PPT_LIMIT_CURRENT; 2270 break; 2271 case PP_PWR_LIMIT_DEFAULT: 2272 limit_level = SMU_PPT_LIMIT_DEFAULT; 2273 break; 2274 case PP_PWR_LIMIT_MAX: 2275 limit_level = SMU_PPT_LIMIT_MAX; 2276 break; 2277 case PP_PWR_LIMIT_MIN: 2278 default: 2279 return -EOPNOTSUPP; 2280 break; 2281 } 2282 2283 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2284 if (smu->ppt_funcs->get_ppt_limit) 2285 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2286 } else { 2287 switch (limit_level) { 2288 case SMU_PPT_LIMIT_CURRENT: 2289 switch (adev->ip_versions[MP1_HWIP][0]) { 2290 case IP_VERSION(13, 0, 2): 2291 case IP_VERSION(11, 0, 7): 2292 case IP_VERSION(11, 0, 11): 2293 case IP_VERSION(11, 0, 12): 2294 case IP_VERSION(11, 0, 13): 2295 ret = smu_get_asic_power_limits(smu, 2296 &smu->current_power_limit, 2297 NULL, 2298 NULL); 2299 break; 2300 default: 2301 break; 2302 } 2303 *limit = smu->current_power_limit; 2304 break; 2305 case SMU_PPT_LIMIT_DEFAULT: 2306 *limit = smu->default_power_limit; 2307 break; 2308 case SMU_PPT_LIMIT_MAX: 2309 *limit = smu->max_power_limit; 2310 break; 2311 default: 2312 break; 2313 } 2314 } 2315 2316 return ret; 2317 } 2318 2319 static int smu_set_power_limit(void *handle, uint32_t limit) 2320 { 2321 struct smu_context *smu = handle; 2322 uint32_t limit_type = limit >> 24; 2323 int ret = 0; 2324 2325 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2326 return -EOPNOTSUPP; 2327 2328 limit &= (1<<24)-1; 2329 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2330 if (smu->ppt_funcs->set_power_limit) 2331 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2332 2333 if (limit > smu->max_power_limit) { 2334 dev_err(smu->adev->dev, 2335 "New power limit (%d) is over the max allowed %d\n", 2336 limit, smu->max_power_limit); 2337 return -EINVAL; 2338 } 2339 2340 if (!limit) 2341 limit = smu->current_power_limit; 2342 2343 if (smu->ppt_funcs->set_power_limit) { 2344 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2345 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2346 smu->user_dpm_profile.power_limit = limit; 2347 } 2348 2349 return ret; 2350 } 2351 2352 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2353 { 2354 int ret = 0; 2355 2356 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2357 return -EOPNOTSUPP; 2358 2359 if (smu->ppt_funcs->print_clk_levels) 2360 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2361 2362 return ret; 2363 } 2364 2365 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2366 { 2367 enum smu_clk_type clk_type; 2368 2369 switch (type) { 2370 case PP_SCLK: 2371 clk_type = SMU_SCLK; break; 2372 case PP_MCLK: 2373 clk_type = SMU_MCLK; break; 2374 case PP_PCIE: 2375 clk_type = SMU_PCIE; break; 2376 case PP_SOCCLK: 2377 clk_type = SMU_SOCCLK; break; 2378 case PP_FCLK: 2379 clk_type = SMU_FCLK; break; 2380 case PP_DCEFCLK: 2381 clk_type = SMU_DCEFCLK; break; 2382 case PP_VCLK: 2383 clk_type = SMU_VCLK; break; 2384 case PP_DCLK: 2385 clk_type = SMU_DCLK; break; 2386 case OD_SCLK: 2387 clk_type = SMU_OD_SCLK; break; 2388 case OD_MCLK: 2389 clk_type = SMU_OD_MCLK; break; 2390 case OD_VDDC_CURVE: 2391 clk_type = SMU_OD_VDDC_CURVE; break; 2392 case OD_RANGE: 2393 clk_type = SMU_OD_RANGE; break; 2394 case OD_VDDGFX_OFFSET: 2395 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2396 case OD_CCLK: 2397 clk_type = SMU_OD_CCLK; break; 2398 default: 2399 clk_type = SMU_CLK_COUNT; break; 2400 } 2401 2402 return clk_type; 2403 } 2404 2405 static int smu_print_ppclk_levels(void *handle, 2406 enum pp_clock_type type, 2407 char *buf) 2408 { 2409 struct smu_context *smu = handle; 2410 enum smu_clk_type clk_type; 2411 2412 clk_type = smu_convert_to_smuclk(type); 2413 if (clk_type == SMU_CLK_COUNT) 2414 return -EINVAL; 2415 2416 return smu_print_smuclk_levels(smu, clk_type, buf); 2417 } 2418 2419 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2420 { 2421 struct smu_context *smu = handle; 2422 enum smu_clk_type clk_type; 2423 2424 clk_type = smu_convert_to_smuclk(type); 2425 if (clk_type == SMU_CLK_COUNT) 2426 return -EINVAL; 2427 2428 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2429 return -EOPNOTSUPP; 2430 2431 if (!smu->ppt_funcs->emit_clk_levels) 2432 return -ENOENT; 2433 2434 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2435 2436 } 2437 2438 static int smu_od_edit_dpm_table(void *handle, 2439 enum PP_OD_DPM_TABLE_COMMAND type, 2440 long *input, uint32_t size) 2441 { 2442 struct smu_context *smu = handle; 2443 int ret = 0; 2444 2445 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2446 return -EOPNOTSUPP; 2447 2448 if (smu->ppt_funcs->od_edit_dpm_table) { 2449 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2450 } 2451 2452 return ret; 2453 } 2454 2455 static int smu_read_sensor(void *handle, 2456 int sensor, 2457 void *data, 2458 int *size_arg) 2459 { 2460 struct smu_context *smu = handle; 2461 struct smu_umd_pstate_table *pstate_table = 2462 &smu->pstate_table; 2463 int ret = 0; 2464 uint32_t *size, size_val; 2465 2466 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2467 return -EOPNOTSUPP; 2468 2469 if (!data || !size_arg) 2470 return -EINVAL; 2471 2472 size_val = *size_arg; 2473 size = &size_val; 2474 2475 if (smu->ppt_funcs->read_sensor) 2476 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2477 goto unlock; 2478 2479 switch (sensor) { 2480 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2481 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2482 *size = 4; 2483 break; 2484 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2485 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2486 *size = 4; 2487 break; 2488 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2489 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2490 *size = 4; 2491 break; 2492 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2493 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2494 *size = 4; 2495 break; 2496 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2497 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2498 *size = 8; 2499 break; 2500 case AMDGPU_PP_SENSOR_UVD_POWER: 2501 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2502 *size = 4; 2503 break; 2504 case AMDGPU_PP_SENSOR_VCE_POWER: 2505 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2506 *size = 4; 2507 break; 2508 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2509 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2510 *size = 4; 2511 break; 2512 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2513 *(uint32_t *)data = 0; 2514 *size = 4; 2515 break; 2516 default: 2517 *size = 0; 2518 ret = -EOPNOTSUPP; 2519 break; 2520 } 2521 2522 unlock: 2523 // assign uint32_t to int 2524 *size_arg = size_val; 2525 2526 return ret; 2527 } 2528 2529 static int smu_get_power_profile_mode(void *handle, char *buf) 2530 { 2531 struct smu_context *smu = handle; 2532 2533 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2534 !smu->ppt_funcs->get_power_profile_mode) 2535 return -EOPNOTSUPP; 2536 if (!buf) 2537 return -EINVAL; 2538 2539 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2540 } 2541 2542 static int smu_set_power_profile_mode(void *handle, 2543 long *param, 2544 uint32_t param_size) 2545 { 2546 struct smu_context *smu = handle; 2547 2548 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2549 !smu->ppt_funcs->set_power_profile_mode) 2550 return -EOPNOTSUPP; 2551 2552 return smu_bump_power_profile_mode(smu, param, param_size); 2553 } 2554 2555 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2556 { 2557 struct smu_context *smu = handle; 2558 2559 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2560 return -EOPNOTSUPP; 2561 2562 if (!smu->ppt_funcs->get_fan_control_mode) 2563 return -EOPNOTSUPP; 2564 2565 if (!fan_mode) 2566 return -EINVAL; 2567 2568 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2569 2570 return 0; 2571 } 2572 2573 static int smu_set_fan_control_mode(void *handle, u32 value) 2574 { 2575 struct smu_context *smu = handle; 2576 int ret = 0; 2577 2578 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2579 return -EOPNOTSUPP; 2580 2581 if (!smu->ppt_funcs->set_fan_control_mode) 2582 return -EOPNOTSUPP; 2583 2584 if (value == U32_MAX) 2585 return -EINVAL; 2586 2587 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2588 if (ret) 2589 goto out; 2590 2591 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2592 smu->user_dpm_profile.fan_mode = value; 2593 2594 /* reset user dpm fan speed */ 2595 if (value != AMD_FAN_CTRL_MANUAL) { 2596 smu->user_dpm_profile.fan_speed_pwm = 0; 2597 smu->user_dpm_profile.fan_speed_rpm = 0; 2598 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2599 } 2600 } 2601 2602 out: 2603 return ret; 2604 } 2605 2606 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2607 { 2608 struct smu_context *smu = handle; 2609 int ret = 0; 2610 2611 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2612 return -EOPNOTSUPP; 2613 2614 if (!smu->ppt_funcs->get_fan_speed_pwm) 2615 return -EOPNOTSUPP; 2616 2617 if (!speed) 2618 return -EINVAL; 2619 2620 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2621 2622 return ret; 2623 } 2624 2625 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2626 { 2627 struct smu_context *smu = handle; 2628 int ret = 0; 2629 2630 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2631 return -EOPNOTSUPP; 2632 2633 if (!smu->ppt_funcs->set_fan_speed_pwm) 2634 return -EOPNOTSUPP; 2635 2636 if (speed == U32_MAX) 2637 return -EINVAL; 2638 2639 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2640 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2641 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2642 smu->user_dpm_profile.fan_speed_pwm = speed; 2643 2644 /* Override custom RPM setting as they cannot co-exist */ 2645 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2646 smu->user_dpm_profile.fan_speed_rpm = 0; 2647 } 2648 2649 return ret; 2650 } 2651 2652 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2653 { 2654 struct smu_context *smu = handle; 2655 int ret = 0; 2656 2657 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2658 return -EOPNOTSUPP; 2659 2660 if (!smu->ppt_funcs->get_fan_speed_rpm) 2661 return -EOPNOTSUPP; 2662 2663 if (!speed) 2664 return -EINVAL; 2665 2666 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2667 2668 return ret; 2669 } 2670 2671 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2672 { 2673 struct smu_context *smu = handle; 2674 2675 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2676 return -EOPNOTSUPP; 2677 2678 return smu_set_min_dcef_deep_sleep(smu, clk); 2679 } 2680 2681 static int smu_get_clock_by_type_with_latency(void *handle, 2682 enum amd_pp_clock_type type, 2683 struct pp_clock_levels_with_latency *clocks) 2684 { 2685 struct smu_context *smu = handle; 2686 enum smu_clk_type clk_type; 2687 int ret = 0; 2688 2689 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2690 return -EOPNOTSUPP; 2691 2692 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2693 switch (type) { 2694 case amd_pp_sys_clock: 2695 clk_type = SMU_GFXCLK; 2696 break; 2697 case amd_pp_mem_clock: 2698 clk_type = SMU_MCLK; 2699 break; 2700 case amd_pp_dcef_clock: 2701 clk_type = SMU_DCEFCLK; 2702 break; 2703 case amd_pp_disp_clock: 2704 clk_type = SMU_DISPCLK; 2705 break; 2706 default: 2707 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2708 return -EINVAL; 2709 } 2710 2711 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2712 } 2713 2714 return ret; 2715 } 2716 2717 static int smu_display_clock_voltage_request(void *handle, 2718 struct pp_display_clock_request *clock_req) 2719 { 2720 struct smu_context *smu = handle; 2721 int ret = 0; 2722 2723 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2724 return -EOPNOTSUPP; 2725 2726 if (smu->ppt_funcs->display_clock_voltage_request) 2727 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2728 2729 return ret; 2730 } 2731 2732 2733 static int smu_display_disable_memory_clock_switch(void *handle, 2734 bool disable_memory_clock_switch) 2735 { 2736 struct smu_context *smu = handle; 2737 int ret = -EINVAL; 2738 2739 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2740 return -EOPNOTSUPP; 2741 2742 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2743 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2744 2745 return ret; 2746 } 2747 2748 static int smu_set_xgmi_pstate(void *handle, 2749 uint32_t pstate) 2750 { 2751 struct smu_context *smu = handle; 2752 int ret = 0; 2753 2754 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2755 return -EOPNOTSUPP; 2756 2757 if (smu->ppt_funcs->set_xgmi_pstate) 2758 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2759 2760 if(ret) 2761 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2762 2763 return ret; 2764 } 2765 2766 static int smu_get_baco_capability(void *handle, bool *cap) 2767 { 2768 struct smu_context *smu = handle; 2769 2770 *cap = false; 2771 2772 if (!smu->pm_enabled) 2773 return 0; 2774 2775 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2776 *cap = smu->ppt_funcs->baco_is_support(smu); 2777 2778 return 0; 2779 } 2780 2781 static int smu_baco_set_state(void *handle, int state) 2782 { 2783 struct smu_context *smu = handle; 2784 int ret = 0; 2785 2786 if (!smu->pm_enabled) 2787 return -EOPNOTSUPP; 2788 2789 if (state == 0) { 2790 if (smu->ppt_funcs->baco_exit) 2791 ret = smu->ppt_funcs->baco_exit(smu); 2792 } else if (state == 1) { 2793 if (smu->ppt_funcs->baco_enter) 2794 ret = smu->ppt_funcs->baco_enter(smu); 2795 } else { 2796 return -EINVAL; 2797 } 2798 2799 if (ret) 2800 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2801 (state)?"enter":"exit"); 2802 2803 return ret; 2804 } 2805 2806 bool smu_mode1_reset_is_support(struct smu_context *smu) 2807 { 2808 bool ret = false; 2809 2810 if (!smu->pm_enabled) 2811 return false; 2812 2813 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2814 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2815 2816 return ret; 2817 } 2818 2819 bool smu_mode2_reset_is_support(struct smu_context *smu) 2820 { 2821 bool ret = false; 2822 2823 if (!smu->pm_enabled) 2824 return false; 2825 2826 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2827 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2828 2829 return ret; 2830 } 2831 2832 int smu_mode1_reset(struct smu_context *smu) 2833 { 2834 int ret = 0; 2835 2836 if (!smu->pm_enabled) 2837 return -EOPNOTSUPP; 2838 2839 if (smu->ppt_funcs->mode1_reset) 2840 ret = smu->ppt_funcs->mode1_reset(smu); 2841 2842 return ret; 2843 } 2844 2845 static int smu_mode2_reset(void *handle) 2846 { 2847 struct smu_context *smu = handle; 2848 int ret = 0; 2849 2850 if (!smu->pm_enabled) 2851 return -EOPNOTSUPP; 2852 2853 if (smu->ppt_funcs->mode2_reset) 2854 ret = smu->ppt_funcs->mode2_reset(smu); 2855 2856 if (ret) 2857 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2858 2859 return ret; 2860 } 2861 2862 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2863 struct pp_smu_nv_clock_table *max_clocks) 2864 { 2865 struct smu_context *smu = handle; 2866 int ret = 0; 2867 2868 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2869 return -EOPNOTSUPP; 2870 2871 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2872 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2873 2874 return ret; 2875 } 2876 2877 static int smu_get_uclk_dpm_states(void *handle, 2878 unsigned int *clock_values_in_khz, 2879 unsigned int *num_states) 2880 { 2881 struct smu_context *smu = handle; 2882 int ret = 0; 2883 2884 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2885 return -EOPNOTSUPP; 2886 2887 if (smu->ppt_funcs->get_uclk_dpm_states) 2888 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2889 2890 return ret; 2891 } 2892 2893 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2894 { 2895 struct smu_context *smu = handle; 2896 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2897 2898 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2899 return -EOPNOTSUPP; 2900 2901 if (smu->ppt_funcs->get_current_power_state) 2902 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2903 2904 return pm_state; 2905 } 2906 2907 static int smu_get_dpm_clock_table(void *handle, 2908 struct dpm_clocks *clock_table) 2909 { 2910 struct smu_context *smu = handle; 2911 int ret = 0; 2912 2913 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2914 return -EOPNOTSUPP; 2915 2916 if (smu->ppt_funcs->get_dpm_clock_table) 2917 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2918 2919 return ret; 2920 } 2921 2922 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2923 { 2924 struct smu_context *smu = handle; 2925 2926 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2927 return -EOPNOTSUPP; 2928 2929 if (!smu->ppt_funcs->get_gpu_metrics) 2930 return -EOPNOTSUPP; 2931 2932 return smu->ppt_funcs->get_gpu_metrics(smu, table); 2933 } 2934 2935 static int smu_enable_mgpu_fan_boost(void *handle) 2936 { 2937 struct smu_context *smu = handle; 2938 int ret = 0; 2939 2940 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2941 return -EOPNOTSUPP; 2942 2943 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2944 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2945 2946 return ret; 2947 } 2948 2949 static int smu_gfx_state_change_set(void *handle, 2950 uint32_t state) 2951 { 2952 struct smu_context *smu = handle; 2953 int ret = 0; 2954 2955 if (smu->ppt_funcs->gfx_state_change_set) 2956 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2957 2958 return ret; 2959 } 2960 2961 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 2962 { 2963 int ret = 0; 2964 2965 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 2966 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 2967 2968 return ret; 2969 } 2970 2971 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 2972 { 2973 int ret = -EOPNOTSUPP; 2974 2975 if (smu->ppt_funcs && 2976 smu->ppt_funcs->get_ecc_info) 2977 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 2978 2979 return ret; 2980 2981 } 2982 2983 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 2984 { 2985 struct smu_context *smu = handle; 2986 struct smu_table_context *smu_table = &smu->smu_table; 2987 struct smu_table *memory_pool = &smu_table->memory_pool; 2988 2989 if (!addr || !size) 2990 return -EINVAL; 2991 2992 *addr = NULL; 2993 *size = 0; 2994 if (memory_pool->bo) { 2995 *addr = memory_pool->cpu_addr; 2996 *size = memory_pool->size; 2997 } 2998 2999 return 0; 3000 } 3001 3002 static const struct amd_pm_funcs swsmu_pm_funcs = { 3003 /* export for sysfs */ 3004 .set_fan_control_mode = smu_set_fan_control_mode, 3005 .get_fan_control_mode = smu_get_fan_control_mode, 3006 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3007 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3008 .force_clock_level = smu_force_ppclk_levels, 3009 .print_clock_levels = smu_print_ppclk_levels, 3010 .emit_clock_levels = smu_emit_ppclk_levels, 3011 .force_performance_level = smu_force_performance_level, 3012 .read_sensor = smu_read_sensor, 3013 .get_performance_level = smu_get_performance_level, 3014 .get_current_power_state = smu_get_current_power_state, 3015 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3016 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3017 .get_pp_num_states = smu_get_power_num_states, 3018 .get_pp_table = smu_sys_get_pp_table, 3019 .set_pp_table = smu_sys_set_pp_table, 3020 .switch_power_profile = smu_switch_power_profile, 3021 /* export to amdgpu */ 3022 .dispatch_tasks = smu_handle_dpm_task, 3023 .load_firmware = smu_load_microcode, 3024 .set_powergating_by_smu = smu_dpm_set_power_gate, 3025 .set_power_limit = smu_set_power_limit, 3026 .get_power_limit = smu_get_power_limit, 3027 .get_power_profile_mode = smu_get_power_profile_mode, 3028 .set_power_profile_mode = smu_set_power_profile_mode, 3029 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3030 .set_mp1_state = smu_set_mp1_state, 3031 .gfx_state_change_set = smu_gfx_state_change_set, 3032 /* export to DC */ 3033 .get_sclk = smu_get_sclk, 3034 .get_mclk = smu_get_mclk, 3035 .display_configuration_change = smu_display_configuration_change, 3036 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3037 .display_clock_voltage_request = smu_display_clock_voltage_request, 3038 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3039 .set_active_display_count = smu_set_display_count, 3040 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3041 .get_asic_baco_capability = smu_get_baco_capability, 3042 .set_asic_baco_state = smu_baco_set_state, 3043 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3044 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3045 .asic_reset_mode_2 = smu_mode2_reset, 3046 .set_df_cstate = smu_set_df_cstate, 3047 .set_xgmi_pstate = smu_set_xgmi_pstate, 3048 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3049 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3050 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3051 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3052 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3053 .get_dpm_clock_table = smu_get_dpm_clock_table, 3054 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3055 }; 3056 3057 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3058 uint64_t event_arg) 3059 { 3060 int ret = -EINVAL; 3061 3062 if (smu->ppt_funcs->wait_for_event) 3063 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3064 3065 return ret; 3066 } 3067 3068 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3069 { 3070 3071 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3072 return -EOPNOTSUPP; 3073 3074 /* Confirm the buffer allocated is of correct size */ 3075 if (size != smu->stb_context.stb_buf_size) 3076 return -EINVAL; 3077 3078 /* 3079 * No need to lock smu mutex as we access STB directly through MMIO 3080 * and not going through SMU messaging route (for now at least). 3081 * For registers access rely on implementation internal locking. 3082 */ 3083 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3084 } 3085 3086 #if defined(CONFIG_DEBUG_FS) 3087 3088 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3089 { 3090 struct amdgpu_device *adev = filp->f_inode->i_private; 3091 struct smu_context *smu = adev->powerplay.pp_handle; 3092 unsigned char *buf; 3093 int r; 3094 3095 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3096 if (!buf) 3097 return -ENOMEM; 3098 3099 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3100 if (r) 3101 goto out; 3102 3103 filp->private_data = buf; 3104 3105 return 0; 3106 3107 out: 3108 kvfree(buf); 3109 return r; 3110 } 3111 3112 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3113 loff_t *pos) 3114 { 3115 struct amdgpu_device *adev = filp->f_inode->i_private; 3116 struct smu_context *smu = adev->powerplay.pp_handle; 3117 3118 3119 if (!filp->private_data) 3120 return -EINVAL; 3121 3122 return simple_read_from_buffer(buf, 3123 size, 3124 pos, filp->private_data, 3125 smu->stb_context.stb_buf_size); 3126 } 3127 3128 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3129 { 3130 kvfree(filp->private_data); 3131 filp->private_data = NULL; 3132 3133 return 0; 3134 } 3135 3136 /* 3137 * We have to define not only read method but also 3138 * open and release because .read takes up to PAGE_SIZE 3139 * data each time so and so is invoked multiple times. 3140 * We allocate the STB buffer in .open and release it 3141 * in .release 3142 */ 3143 static const struct file_operations smu_stb_debugfs_fops = { 3144 .owner = THIS_MODULE, 3145 .open = smu_stb_debugfs_open, 3146 .read = smu_stb_debugfs_read, 3147 .release = smu_stb_debugfs_release, 3148 .llseek = default_llseek, 3149 }; 3150 3151 #endif 3152 3153 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3154 { 3155 #if defined(CONFIG_DEBUG_FS) 3156 3157 struct smu_context *smu = adev->powerplay.pp_handle; 3158 3159 if (!smu || (!smu->stb_context.stb_buf_size)) 3160 return; 3161 3162 debugfs_create_file_size("amdgpu_smu_stb_dump", 3163 S_IRUSR, 3164 adev_to_drm(adev)->primary->debugfs_root, 3165 adev, 3166 &smu_stb_debugfs_fops, 3167 smu->stb_context.stb_buf_size); 3168 #endif 3169 } 3170 3171 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3172 { 3173 int ret = 0; 3174 3175 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3176 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3177 3178 return ret; 3179 } 3180 3181 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3182 { 3183 int ret = 0; 3184 3185 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3186 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3187 3188 return ret; 3189 } 3190