1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 #include <linux/power_supply.h> 28 #include <linux/reboot.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_smu.h" 32 #include "smu_internal.h" 33 #include "atom.h" 34 #include "arcturus_ppt.h" 35 #include "navi10_ppt.h" 36 #include "sienna_cichlid_ppt.h" 37 #include "renoir_ppt.h" 38 #include "vangogh_ppt.h" 39 #include "aldebaran_ppt.h" 40 #include "yellow_carp_ppt.h" 41 #include "cyan_skillfish_ppt.h" 42 #include "smu_v13_0_0_ppt.h" 43 #include "smu_v13_0_4_ppt.h" 44 #include "smu_v13_0_5_ppt.h" 45 #include "smu_v13_0_6_ppt.h" 46 #include "smu_v13_0_7_ppt.h" 47 #include "amd_pcie.h" 48 49 /* 50 * DO NOT use these for err/warn/info/debug messages. 51 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 52 * They are more MGPU friendly. 53 */ 54 #undef pr_err 55 #undef pr_warn 56 #undef pr_info 57 #undef pr_debug 58 59 static const struct amd_pm_funcs swsmu_pm_funcs; 60 static int smu_force_smuclk_levels(struct smu_context *smu, 61 enum smu_clk_type clk_type, 62 uint32_t mask); 63 static int smu_handle_task(struct smu_context *smu, 64 enum amd_dpm_forced_level level, 65 enum amd_pp_task task_id); 66 static int smu_reset(struct smu_context *smu); 67 static int smu_set_fan_speed_pwm(void *handle, u32 speed); 68 static int smu_set_fan_control_mode(void *handle, u32 value); 69 static int smu_set_power_limit(void *handle, uint32_t limit); 70 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 71 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 72 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state); 73 74 static int smu_sys_get_pp_feature_mask(void *handle, 75 char *buf) 76 { 77 struct smu_context *smu = handle; 78 79 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 80 return -EOPNOTSUPP; 81 82 return smu_get_pp_feature_mask(smu, buf); 83 } 84 85 static int smu_sys_set_pp_feature_mask(void *handle, 86 uint64_t new_mask) 87 { 88 struct smu_context *smu = handle; 89 90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 91 return -EOPNOTSUPP; 92 93 return smu_set_pp_feature_mask(smu, new_mask); 94 } 95 96 int smu_set_residency_gfxoff(struct smu_context *smu, bool value) 97 { 98 if (!smu->ppt_funcs->set_gfx_off_residency) 99 return -EINVAL; 100 101 return smu_set_gfx_off_residency(smu, value); 102 } 103 104 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value) 105 { 106 if (!smu->ppt_funcs->get_gfx_off_residency) 107 return -EINVAL; 108 109 return smu_get_gfx_off_residency(smu, value); 110 } 111 112 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value) 113 { 114 if (!smu->ppt_funcs->get_gfx_off_entrycount) 115 return -EINVAL; 116 117 return smu_get_gfx_off_entrycount(smu, value); 118 } 119 120 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value) 121 { 122 if (!smu->ppt_funcs->get_gfx_off_status) 123 return -EINVAL; 124 125 *value = smu_get_gfx_off_status(smu); 126 127 return 0; 128 } 129 130 int smu_set_soft_freq_range(struct smu_context *smu, 131 enum smu_clk_type clk_type, 132 uint32_t min, 133 uint32_t max) 134 { 135 int ret = 0; 136 137 if (smu->ppt_funcs->set_soft_freq_limited_range) 138 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 139 clk_type, 140 min, 141 max); 142 143 return ret; 144 } 145 146 int smu_get_dpm_freq_range(struct smu_context *smu, 147 enum smu_clk_type clk_type, 148 uint32_t *min, 149 uint32_t *max) 150 { 151 int ret = -ENOTSUPP; 152 153 if (!min && !max) 154 return -EINVAL; 155 156 if (smu->ppt_funcs->get_dpm_ultimate_freq) 157 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 158 clk_type, 159 min, 160 max); 161 162 return ret; 163 } 164 165 int smu_set_gfx_power_up_by_imu(struct smu_context *smu) 166 { 167 int ret = 0; 168 struct amdgpu_device *adev = smu->adev; 169 170 if (smu->ppt_funcs->set_gfx_power_up_by_imu) { 171 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu); 172 if (ret) 173 dev_err(adev->dev, "Failed to enable gfx imu!\n"); 174 } 175 return ret; 176 } 177 178 static u32 smu_get_mclk(void *handle, bool low) 179 { 180 struct smu_context *smu = handle; 181 uint32_t clk_freq; 182 int ret = 0; 183 184 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 185 low ? &clk_freq : NULL, 186 !low ? &clk_freq : NULL); 187 if (ret) 188 return 0; 189 return clk_freq * 100; 190 } 191 192 static u32 smu_get_sclk(void *handle, bool low) 193 { 194 struct smu_context *smu = handle; 195 uint32_t clk_freq; 196 int ret = 0; 197 198 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 199 low ? &clk_freq : NULL, 200 !low ? &clk_freq : NULL); 201 if (ret) 202 return 0; 203 return clk_freq * 100; 204 } 205 206 static int smu_set_gfx_imu_enable(struct smu_context *smu) 207 { 208 struct amdgpu_device *adev = smu->adev; 209 210 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 211 return 0; 212 213 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix) 214 return 0; 215 216 return smu_set_gfx_power_up_by_imu(smu); 217 } 218 219 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 220 bool enable) 221 { 222 struct smu_power_context *smu_power = &smu->smu_power; 223 struct smu_power_gate *power_gate = &smu_power->power_gate; 224 int ret = 0; 225 226 if (!smu->ppt_funcs->dpm_set_vcn_enable) 227 return 0; 228 229 if (atomic_read(&power_gate->vcn_gated) ^ enable) 230 return 0; 231 232 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 233 if (!ret) 234 atomic_set(&power_gate->vcn_gated, !enable); 235 236 return ret; 237 } 238 239 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 240 bool enable) 241 { 242 struct smu_power_context *smu_power = &smu->smu_power; 243 struct smu_power_gate *power_gate = &smu_power->power_gate; 244 int ret = 0; 245 246 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 247 return 0; 248 249 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 250 return 0; 251 252 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 253 if (!ret) 254 atomic_set(&power_gate->jpeg_gated, !enable); 255 256 return ret; 257 } 258 259 /** 260 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 261 * 262 * @handle: smu_context pointer 263 * @block_type: the IP block to power gate/ungate 264 * @gate: to power gate if true, ungate otherwise 265 * 266 * This API uses no smu->mutex lock protection due to: 267 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 268 * This is guarded to be race condition free by the caller. 269 * 2. Or get called on user setting request of power_dpm_force_performance_level. 270 * Under this case, the smu->mutex lock protection is already enforced on 271 * the parent API smu_force_performance_level of the call path. 272 */ 273 static int smu_dpm_set_power_gate(void *handle, 274 uint32_t block_type, 275 bool gate) 276 { 277 struct smu_context *smu = handle; 278 int ret = 0; 279 280 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) { 281 dev_WARN(smu->adev->dev, 282 "SMU uninitialized but power %s requested for %u!\n", 283 gate ? "gate" : "ungate", block_type); 284 return -EOPNOTSUPP; 285 } 286 287 switch (block_type) { 288 /* 289 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 290 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 291 */ 292 case AMD_IP_BLOCK_TYPE_UVD: 293 case AMD_IP_BLOCK_TYPE_VCN: 294 ret = smu_dpm_set_vcn_enable(smu, !gate); 295 if (ret) 296 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 297 gate ? "gate" : "ungate"); 298 break; 299 case AMD_IP_BLOCK_TYPE_GFX: 300 ret = smu_gfx_off_control(smu, gate); 301 if (ret) 302 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 303 gate ? "enable" : "disable"); 304 break; 305 case AMD_IP_BLOCK_TYPE_SDMA: 306 ret = smu_powergate_sdma(smu, gate); 307 if (ret) 308 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 309 gate ? "gate" : "ungate"); 310 break; 311 case AMD_IP_BLOCK_TYPE_JPEG: 312 ret = smu_dpm_set_jpeg_enable(smu, !gate); 313 if (ret) 314 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 315 gate ? "gate" : "ungate"); 316 break; 317 default: 318 dev_err(smu->adev->dev, "Unsupported block type!\n"); 319 return -EINVAL; 320 } 321 322 return ret; 323 } 324 325 /** 326 * smu_set_user_clk_dependencies - set user profile clock dependencies 327 * 328 * @smu: smu_context pointer 329 * @clk: enum smu_clk_type type 330 * 331 * Enable/Disable the clock dependency for the @clk type. 332 */ 333 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 334 { 335 if (smu->adev->in_suspend) 336 return; 337 338 if (clk == SMU_MCLK) { 339 smu->user_dpm_profile.clk_dependency = 0; 340 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 341 } else if (clk == SMU_FCLK) { 342 /* MCLK takes precedence over FCLK */ 343 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 344 return; 345 346 smu->user_dpm_profile.clk_dependency = 0; 347 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 348 } else if (clk == SMU_SOCCLK) { 349 /* MCLK takes precedence over SOCCLK */ 350 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 351 return; 352 353 smu->user_dpm_profile.clk_dependency = 0; 354 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 355 } else 356 /* Add clk dependencies here, if any */ 357 return; 358 } 359 360 /** 361 * smu_restore_dpm_user_profile - reinstate user dpm profile 362 * 363 * @smu: smu_context pointer 364 * 365 * Restore the saved user power configurations include power limit, 366 * clock frequencies, fan control mode and fan speed. 367 */ 368 static void smu_restore_dpm_user_profile(struct smu_context *smu) 369 { 370 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 371 int ret = 0; 372 373 if (!smu->adev->in_suspend) 374 return; 375 376 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 377 return; 378 379 /* Enable restore flag */ 380 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 381 382 /* set the user dpm power limit */ 383 if (smu->user_dpm_profile.power_limit) { 384 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 385 if (ret) 386 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 387 } 388 389 /* set the user dpm clock configurations */ 390 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 391 enum smu_clk_type clk_type; 392 393 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 394 /* 395 * Iterate over smu clk type and force the saved user clk 396 * configs, skip if clock dependency is enabled 397 */ 398 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 399 smu->user_dpm_profile.clk_mask[clk_type]) { 400 ret = smu_force_smuclk_levels(smu, clk_type, 401 smu->user_dpm_profile.clk_mask[clk_type]); 402 if (ret) 403 dev_err(smu->adev->dev, 404 "Failed to set clock type = %d\n", clk_type); 405 } 406 } 407 } 408 409 /* set the user dpm fan configurations */ 410 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL || 411 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) { 412 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 413 if (ret != -EOPNOTSUPP) { 414 smu->user_dpm_profile.fan_speed_pwm = 0; 415 smu->user_dpm_profile.fan_speed_rpm = 0; 416 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO; 417 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 418 } 419 420 if (smu->user_dpm_profile.fan_speed_pwm) { 421 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm); 422 if (ret != -EOPNOTSUPP) 423 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n"); 424 } 425 426 if (smu->user_dpm_profile.fan_speed_rpm) { 427 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm); 428 if (ret != -EOPNOTSUPP) 429 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n"); 430 } 431 } 432 433 /* Restore user customized OD settings */ 434 if (smu->user_dpm_profile.user_od) { 435 if (smu->ppt_funcs->restore_user_od_settings) { 436 ret = smu->ppt_funcs->restore_user_od_settings(smu); 437 if (ret) 438 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n"); 439 } 440 } 441 442 /* Disable restore flag */ 443 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 444 } 445 446 static int smu_get_power_num_states(void *handle, 447 struct pp_states_info *state_info) 448 { 449 if (!state_info) 450 return -EINVAL; 451 452 /* not support power state */ 453 memset(state_info, 0, sizeof(struct pp_states_info)); 454 state_info->nums = 1; 455 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 456 457 return 0; 458 } 459 460 bool is_support_sw_smu(struct amdgpu_device *adev) 461 { 462 /* vega20 is 11.0.2, but it's supported via the powerplay code */ 463 if (adev->asic_type == CHIP_VEGA20) 464 return false; 465 466 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0)) 467 return true; 468 469 return false; 470 } 471 472 bool is_support_cclk_dpm(struct amdgpu_device *adev) 473 { 474 struct smu_context *smu = adev->powerplay.pp_handle; 475 476 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 477 return false; 478 479 return true; 480 } 481 482 483 static int smu_sys_get_pp_table(void *handle, 484 char **table) 485 { 486 struct smu_context *smu = handle; 487 struct smu_table_context *smu_table = &smu->smu_table; 488 489 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 490 return -EOPNOTSUPP; 491 492 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 493 return -EINVAL; 494 495 if (smu_table->hardcode_pptable) 496 *table = smu_table->hardcode_pptable; 497 else 498 *table = smu_table->power_play_table; 499 500 return smu_table->power_play_table_size; 501 } 502 503 static int smu_sys_set_pp_table(void *handle, 504 const char *buf, 505 size_t size) 506 { 507 struct smu_context *smu = handle; 508 struct smu_table_context *smu_table = &smu->smu_table; 509 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 510 int ret = 0; 511 512 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 513 return -EOPNOTSUPP; 514 515 if (header->usStructureSize != size) { 516 dev_err(smu->adev->dev, "pp table size not matched !\n"); 517 return -EIO; 518 } 519 520 if (!smu_table->hardcode_pptable) { 521 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 522 if (!smu_table->hardcode_pptable) 523 return -ENOMEM; 524 } 525 526 memcpy(smu_table->hardcode_pptable, buf, size); 527 smu_table->power_play_table = smu_table->hardcode_pptable; 528 smu_table->power_play_table_size = size; 529 530 /* 531 * Special hw_fini action(for Navi1x, the DPMs disablement will be 532 * skipped) may be needed for custom pptable uploading. 533 */ 534 smu->uploading_custom_pp_table = true; 535 536 ret = smu_reset(smu); 537 if (ret) 538 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 539 540 smu->uploading_custom_pp_table = false; 541 542 return ret; 543 } 544 545 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 546 { 547 struct smu_feature *feature = &smu->smu_feature; 548 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 549 int ret = 0; 550 551 /* 552 * With SCPM enabled, the allowed featuremasks setting(via 553 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. 554 * That means there is no way to let PMFW knows the settings below. 555 * Thus, we just assume all the features are allowed under 556 * such scenario. 557 */ 558 if (smu->adev->scpm_enabled) { 559 bitmap_fill(feature->allowed, SMU_FEATURE_MAX); 560 return 0; 561 } 562 563 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 564 565 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 566 SMU_FEATURE_MAX/32); 567 if (ret) 568 return ret; 569 570 bitmap_or(feature->allowed, feature->allowed, 571 (unsigned long *)allowed_feature_mask, 572 feature->feature_num); 573 574 return ret; 575 } 576 577 static int smu_set_funcs(struct amdgpu_device *adev) 578 { 579 struct smu_context *smu = adev->powerplay.pp_handle; 580 581 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 582 smu->od_enabled = true; 583 584 switch (adev->ip_versions[MP1_HWIP][0]) { 585 case IP_VERSION(11, 0, 0): 586 case IP_VERSION(11, 0, 5): 587 case IP_VERSION(11, 0, 9): 588 navi10_set_ppt_funcs(smu); 589 break; 590 case IP_VERSION(11, 0, 7): 591 case IP_VERSION(11, 0, 11): 592 case IP_VERSION(11, 0, 12): 593 case IP_VERSION(11, 0, 13): 594 sienna_cichlid_set_ppt_funcs(smu); 595 break; 596 case IP_VERSION(12, 0, 0): 597 case IP_VERSION(12, 0, 1): 598 renoir_set_ppt_funcs(smu); 599 break; 600 case IP_VERSION(11, 5, 0): 601 vangogh_set_ppt_funcs(smu); 602 break; 603 case IP_VERSION(13, 0, 1): 604 case IP_VERSION(13, 0, 3): 605 case IP_VERSION(13, 0, 8): 606 yellow_carp_set_ppt_funcs(smu); 607 break; 608 case IP_VERSION(13, 0, 4): 609 case IP_VERSION(13, 0, 11): 610 smu_v13_0_4_set_ppt_funcs(smu); 611 break; 612 case IP_VERSION(13, 0, 5): 613 smu_v13_0_5_set_ppt_funcs(smu); 614 break; 615 case IP_VERSION(11, 0, 8): 616 cyan_skillfish_set_ppt_funcs(smu); 617 break; 618 case IP_VERSION(11, 0, 2): 619 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 620 arcturus_set_ppt_funcs(smu); 621 /* OD is not supported on Arcturus */ 622 smu->od_enabled = false; 623 break; 624 case IP_VERSION(13, 0, 2): 625 aldebaran_set_ppt_funcs(smu); 626 /* Enable pp_od_clk_voltage node */ 627 smu->od_enabled = true; 628 break; 629 case IP_VERSION(13, 0, 0): 630 case IP_VERSION(13, 0, 10): 631 smu_v13_0_0_set_ppt_funcs(smu); 632 break; 633 case IP_VERSION(13, 0, 6): 634 smu_v13_0_6_set_ppt_funcs(smu); 635 /* Enable pp_od_clk_voltage node */ 636 smu->od_enabled = true; 637 break; 638 case IP_VERSION(13, 0, 7): 639 smu_v13_0_7_set_ppt_funcs(smu); 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 return 0; 646 } 647 648 static int smu_early_init(void *handle) 649 { 650 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 651 struct smu_context *smu; 652 int r; 653 654 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL); 655 if (!smu) 656 return -ENOMEM; 657 658 smu->adev = adev; 659 smu->pm_enabled = !!amdgpu_dpm; 660 smu->is_apu = false; 661 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 662 smu->smu_baco.platform_support = false; 663 smu->user_dpm_profile.fan_mode = -1; 664 665 mutex_init(&smu->message_lock); 666 667 adev->powerplay.pp_handle = smu; 668 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 669 670 r = smu_set_funcs(adev); 671 if (r) 672 return r; 673 return smu_init_microcode(smu); 674 } 675 676 static int smu_set_default_dpm_table(struct smu_context *smu) 677 { 678 struct smu_power_context *smu_power = &smu->smu_power; 679 struct smu_power_gate *power_gate = &smu_power->power_gate; 680 int vcn_gate, jpeg_gate; 681 int ret = 0; 682 683 if (!smu->ppt_funcs->set_default_dpm_table) 684 return 0; 685 686 vcn_gate = atomic_read(&power_gate->vcn_gated); 687 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 688 689 ret = smu_dpm_set_vcn_enable(smu, true); 690 if (ret) 691 return ret; 692 693 ret = smu_dpm_set_jpeg_enable(smu, true); 694 if (ret) 695 goto err_out; 696 697 ret = smu->ppt_funcs->set_default_dpm_table(smu); 698 if (ret) 699 dev_err(smu->adev->dev, 700 "Failed to setup default dpm clock tables!\n"); 701 702 smu_dpm_set_jpeg_enable(smu, !jpeg_gate); 703 err_out: 704 smu_dpm_set_vcn_enable(smu, !vcn_gate); 705 return ret; 706 } 707 708 static int smu_apply_default_config_table_settings(struct smu_context *smu) 709 { 710 struct amdgpu_device *adev = smu->adev; 711 int ret = 0; 712 713 ret = smu_get_default_config_table_settings(smu, 714 &adev->pm.config_table); 715 if (ret) 716 return ret; 717 718 return smu_set_config_table(smu, &adev->pm.config_table); 719 } 720 721 static int smu_late_init(void *handle) 722 { 723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 724 struct smu_context *smu = adev->powerplay.pp_handle; 725 int ret = 0; 726 727 smu_set_fine_grain_gfx_freq_parameters(smu); 728 729 if (!smu->pm_enabled) 730 return 0; 731 732 ret = smu_post_init(smu); 733 if (ret) { 734 dev_err(adev->dev, "Failed to post smu init!\n"); 735 return ret; 736 } 737 738 /* 739 * Explicitly notify PMFW the power mode the system in. Since 740 * the PMFW may boot the ASIC with a different mode. 741 * For those supporting ACDC switch via gpio, PMFW will 742 * handle the switch automatically. Driver involvement 743 * is unnecessary. 744 */ 745 adev->pm.ac_power = power_supply_is_system_supplied() > 0; 746 smu_set_ac_dc(smu); 747 748 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) || 749 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3))) 750 return 0; 751 752 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 753 ret = smu_set_default_od_settings(smu); 754 if (ret) { 755 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 756 return ret; 757 } 758 } 759 760 ret = smu_populate_umd_state_clk(smu); 761 if (ret) { 762 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 763 return ret; 764 } 765 766 ret = smu_get_asic_power_limits(smu, 767 &smu->current_power_limit, 768 &smu->default_power_limit, 769 &smu->max_power_limit); 770 if (ret) { 771 dev_err(adev->dev, "Failed to get asic power limits!\n"); 772 return ret; 773 } 774 775 if (!amdgpu_sriov_vf(adev)) 776 smu_get_unique_id(smu); 777 778 smu_get_fan_parameters(smu); 779 780 smu_handle_task(smu, 781 smu->smu_dpm.dpm_level, 782 AMD_PP_TASK_COMPLETE_INIT); 783 784 ret = smu_apply_default_config_table_settings(smu); 785 if (ret && (ret != -EOPNOTSUPP)) { 786 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n"); 787 return ret; 788 } 789 790 smu_restore_dpm_user_profile(smu); 791 792 return 0; 793 } 794 795 static int smu_init_fb_allocations(struct smu_context *smu) 796 { 797 struct amdgpu_device *adev = smu->adev; 798 struct smu_table_context *smu_table = &smu->smu_table; 799 struct smu_table *tables = smu_table->tables; 800 struct smu_table *driver_table = &(smu_table->driver_table); 801 uint32_t max_table_size = 0; 802 int ret, i; 803 804 /* VRAM allocation for tool table */ 805 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 806 ret = amdgpu_bo_create_kernel(adev, 807 tables[SMU_TABLE_PMSTATUSLOG].size, 808 tables[SMU_TABLE_PMSTATUSLOG].align, 809 tables[SMU_TABLE_PMSTATUSLOG].domain, 810 &tables[SMU_TABLE_PMSTATUSLOG].bo, 811 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 812 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 813 if (ret) { 814 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 815 return ret; 816 } 817 } 818 819 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; 820 /* VRAM allocation for driver table */ 821 for (i = 0; i < SMU_TABLE_COUNT; i++) { 822 if (tables[i].size == 0) 823 continue; 824 825 /* If one of the tables has VRAM domain restriction, keep it in 826 * VRAM 827 */ 828 if ((tables[i].domain & 829 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) == 830 AMDGPU_GEM_DOMAIN_VRAM) 831 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 832 833 if (i == SMU_TABLE_PMSTATUSLOG) 834 continue; 835 836 if (max_table_size < tables[i].size) 837 max_table_size = tables[i].size; 838 } 839 840 driver_table->size = max_table_size; 841 driver_table->align = PAGE_SIZE; 842 843 ret = amdgpu_bo_create_kernel(adev, 844 driver_table->size, 845 driver_table->align, 846 driver_table->domain, 847 &driver_table->bo, 848 &driver_table->mc_address, 849 &driver_table->cpu_addr); 850 if (ret) { 851 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 852 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 853 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 854 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 855 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 856 } 857 858 return ret; 859 } 860 861 static int smu_fini_fb_allocations(struct smu_context *smu) 862 { 863 struct smu_table_context *smu_table = &smu->smu_table; 864 struct smu_table *tables = smu_table->tables; 865 struct smu_table *driver_table = &(smu_table->driver_table); 866 867 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 868 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 869 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 870 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 871 872 amdgpu_bo_free_kernel(&driver_table->bo, 873 &driver_table->mc_address, 874 &driver_table->cpu_addr); 875 876 return 0; 877 } 878 879 /** 880 * smu_alloc_memory_pool - allocate memory pool in the system memory 881 * 882 * @smu: amdgpu_device pointer 883 * 884 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 885 * and DramLogSetDramAddr can notify it changed. 886 * 887 * Returns 0 on success, error on failure. 888 */ 889 static int smu_alloc_memory_pool(struct smu_context *smu) 890 { 891 struct amdgpu_device *adev = smu->adev; 892 struct smu_table_context *smu_table = &smu->smu_table; 893 struct smu_table *memory_pool = &smu_table->memory_pool; 894 uint64_t pool_size = smu->pool_size; 895 int ret = 0; 896 897 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 898 return ret; 899 900 memory_pool->size = pool_size; 901 memory_pool->align = PAGE_SIZE; 902 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 903 904 switch (pool_size) { 905 case SMU_MEMORY_POOL_SIZE_256_MB: 906 case SMU_MEMORY_POOL_SIZE_512_MB: 907 case SMU_MEMORY_POOL_SIZE_1_GB: 908 case SMU_MEMORY_POOL_SIZE_2_GB: 909 ret = amdgpu_bo_create_kernel(adev, 910 memory_pool->size, 911 memory_pool->align, 912 memory_pool->domain, 913 &memory_pool->bo, 914 &memory_pool->mc_address, 915 &memory_pool->cpu_addr); 916 if (ret) 917 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 918 break; 919 default: 920 break; 921 } 922 923 return ret; 924 } 925 926 static int smu_free_memory_pool(struct smu_context *smu) 927 { 928 struct smu_table_context *smu_table = &smu->smu_table; 929 struct smu_table *memory_pool = &smu_table->memory_pool; 930 931 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 932 return 0; 933 934 amdgpu_bo_free_kernel(&memory_pool->bo, 935 &memory_pool->mc_address, 936 &memory_pool->cpu_addr); 937 938 memset(memory_pool, 0, sizeof(struct smu_table)); 939 940 return 0; 941 } 942 943 static int smu_alloc_dummy_read_table(struct smu_context *smu) 944 { 945 struct smu_table_context *smu_table = &smu->smu_table; 946 struct smu_table *dummy_read_1_table = 947 &smu_table->dummy_read_1_table; 948 struct amdgpu_device *adev = smu->adev; 949 int ret = 0; 950 951 if (!dummy_read_1_table->size) 952 return 0; 953 954 ret = amdgpu_bo_create_kernel(adev, 955 dummy_read_1_table->size, 956 dummy_read_1_table->align, 957 dummy_read_1_table->domain, 958 &dummy_read_1_table->bo, 959 &dummy_read_1_table->mc_address, 960 &dummy_read_1_table->cpu_addr); 961 if (ret) 962 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 963 964 return ret; 965 } 966 967 static void smu_free_dummy_read_table(struct smu_context *smu) 968 { 969 struct smu_table_context *smu_table = &smu->smu_table; 970 struct smu_table *dummy_read_1_table = 971 &smu_table->dummy_read_1_table; 972 973 974 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 975 &dummy_read_1_table->mc_address, 976 &dummy_read_1_table->cpu_addr); 977 978 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 979 } 980 981 static int smu_smc_table_sw_init(struct smu_context *smu) 982 { 983 int ret; 984 985 /** 986 * Create smu_table structure, and init smc tables such as 987 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 988 */ 989 ret = smu_init_smc_tables(smu); 990 if (ret) { 991 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 992 return ret; 993 } 994 995 /** 996 * Create smu_power_context structure, and allocate smu_dpm_context and 997 * context size to fill the smu_power_context data. 998 */ 999 ret = smu_init_power(smu); 1000 if (ret) { 1001 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 1002 return ret; 1003 } 1004 1005 /* 1006 * allocate vram bos to store smc table contents. 1007 */ 1008 ret = smu_init_fb_allocations(smu); 1009 if (ret) 1010 return ret; 1011 1012 ret = smu_alloc_memory_pool(smu); 1013 if (ret) 1014 return ret; 1015 1016 ret = smu_alloc_dummy_read_table(smu); 1017 if (ret) 1018 return ret; 1019 1020 ret = smu_i2c_init(smu); 1021 if (ret) 1022 return ret; 1023 1024 return 0; 1025 } 1026 1027 static int smu_smc_table_sw_fini(struct smu_context *smu) 1028 { 1029 int ret; 1030 1031 smu_i2c_fini(smu); 1032 1033 smu_free_dummy_read_table(smu); 1034 1035 ret = smu_free_memory_pool(smu); 1036 if (ret) 1037 return ret; 1038 1039 ret = smu_fini_fb_allocations(smu); 1040 if (ret) 1041 return ret; 1042 1043 ret = smu_fini_power(smu); 1044 if (ret) { 1045 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 1046 return ret; 1047 } 1048 1049 ret = smu_fini_smc_tables(smu); 1050 if (ret) { 1051 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 1052 return ret; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static void smu_throttling_logging_work_fn(struct work_struct *work) 1059 { 1060 struct smu_context *smu = container_of(work, struct smu_context, 1061 throttling_logging_work); 1062 1063 smu_log_thermal_throttling(smu); 1064 } 1065 1066 static void smu_interrupt_work_fn(struct work_struct *work) 1067 { 1068 struct smu_context *smu = container_of(work, struct smu_context, 1069 interrupt_work); 1070 1071 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 1072 smu->ppt_funcs->interrupt_work(smu); 1073 } 1074 1075 static void smu_swctf_delayed_work_handler(struct work_struct *work) 1076 { 1077 struct smu_context *smu = 1078 container_of(work, struct smu_context, swctf_delayed_work.work); 1079 struct smu_temperature_range *range = 1080 &smu->thermal_range; 1081 struct amdgpu_device *adev = smu->adev; 1082 uint32_t hotspot_tmp, size; 1083 1084 /* 1085 * If the hotspot temperature is confirmed as below SW CTF setting point 1086 * after the delay enforced, nothing will be done. 1087 * Otherwise, a graceful shutdown will be performed to prevent further damage. 1088 */ 1089 if (range->software_shutdown_temp && 1090 smu->ppt_funcs->read_sensor && 1091 !smu->ppt_funcs->read_sensor(smu, 1092 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 1093 &hotspot_tmp, 1094 &size) && 1095 hotspot_tmp / 1000 < range->software_shutdown_temp) 1096 return; 1097 1098 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n"); 1099 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n"); 1100 orderly_poweroff(true); 1101 } 1102 1103 static int smu_sw_init(void *handle) 1104 { 1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1106 struct smu_context *smu = adev->powerplay.pp_handle; 1107 int ret; 1108 1109 smu->pool_size = adev->pm.smu_prv_buffer_size; 1110 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1111 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1112 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1113 1114 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1115 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1116 atomic64_set(&smu->throttle_int_counter, 0); 1117 smu->watermarks_bitmap = 0; 1118 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1119 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1120 1121 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1122 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1123 1124 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1125 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1126 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1127 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1128 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1129 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1130 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1131 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1132 1133 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1134 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1135 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1136 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1137 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1138 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1139 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1140 smu->display_config = &adev->pm.pm_display_cfg; 1141 1142 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1143 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1144 1145 INIT_DELAYED_WORK(&smu->swctf_delayed_work, 1146 smu_swctf_delayed_work_handler); 1147 1148 ret = smu_smc_table_sw_init(smu); 1149 if (ret) { 1150 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1151 return ret; 1152 } 1153 1154 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1155 ret = smu_get_vbios_bootup_values(smu); 1156 if (ret) { 1157 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1158 return ret; 1159 } 1160 1161 ret = smu_init_pptable_microcode(smu); 1162 if (ret) { 1163 dev_err(adev->dev, "Failed to setup pptable firmware!\n"); 1164 return ret; 1165 } 1166 1167 ret = smu_register_irq_handler(smu); 1168 if (ret) { 1169 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1170 return ret; 1171 } 1172 1173 /* If there is no way to query fan control mode, fan control is not supported */ 1174 if (!smu->ppt_funcs->get_fan_control_mode) 1175 smu->adev->pm.no_fan = true; 1176 1177 return 0; 1178 } 1179 1180 static int smu_sw_fini(void *handle) 1181 { 1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1183 struct smu_context *smu = adev->powerplay.pp_handle; 1184 int ret; 1185 1186 ret = smu_smc_table_sw_fini(smu); 1187 if (ret) { 1188 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1189 return ret; 1190 } 1191 1192 smu_fini_microcode(smu); 1193 1194 return 0; 1195 } 1196 1197 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1198 { 1199 struct amdgpu_device *adev = smu->adev; 1200 struct smu_temperature_range *range = 1201 &smu->thermal_range; 1202 int ret = 0; 1203 1204 if (!smu->ppt_funcs->get_thermal_temperature_range) 1205 return 0; 1206 1207 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1208 if (ret) 1209 return ret; 1210 1211 adev->pm.dpm.thermal.min_temp = range->min; 1212 adev->pm.dpm.thermal.max_temp = range->max; 1213 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1214 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1215 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1216 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1217 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1218 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1219 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1220 1221 return ret; 1222 } 1223 1224 static int smu_smc_hw_setup(struct smu_context *smu) 1225 { 1226 struct smu_feature *feature = &smu->smu_feature; 1227 struct amdgpu_device *adev = smu->adev; 1228 uint8_t pcie_gen = 0, pcie_width = 0; 1229 uint64_t features_supported; 1230 int ret = 0; 1231 1232 switch (adev->ip_versions[MP1_HWIP][0]) { 1233 case IP_VERSION(11, 0, 7): 1234 case IP_VERSION(11, 0, 11): 1235 case IP_VERSION(11, 5, 0): 1236 case IP_VERSION(11, 0, 12): 1237 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1238 dev_info(adev->dev, "dpm has been enabled\n"); 1239 ret = smu_system_features_control(smu, true); 1240 if (ret) 1241 dev_err(adev->dev, "Failed system features control!\n"); 1242 return ret; 1243 } 1244 break; 1245 default: 1246 break; 1247 } 1248 1249 ret = smu_init_display_count(smu, 0); 1250 if (ret) { 1251 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1252 return ret; 1253 } 1254 1255 ret = smu_set_driver_table_location(smu); 1256 if (ret) { 1257 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1258 return ret; 1259 } 1260 1261 /* 1262 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1263 */ 1264 ret = smu_set_tool_table_location(smu); 1265 if (ret) { 1266 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1267 return ret; 1268 } 1269 1270 /* 1271 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1272 * pool location. 1273 */ 1274 ret = smu_notify_memory_pool_location(smu); 1275 if (ret) { 1276 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1277 return ret; 1278 } 1279 1280 /* 1281 * It is assumed the pptable used before runpm is same as 1282 * the one used afterwards. Thus, we can reuse the stored 1283 * copy and do not need to resetup the pptable again. 1284 */ 1285 if (!adev->in_runpm) { 1286 ret = smu_setup_pptable(smu); 1287 if (ret) { 1288 dev_err(adev->dev, "Failed to setup pptable!\n"); 1289 return ret; 1290 } 1291 } 1292 1293 /* smu_dump_pptable(smu); */ 1294 1295 /* 1296 * With SCPM enabled, PSP is responsible for the PPTable transferring 1297 * (to SMU). Driver involvement is not needed and permitted. 1298 */ 1299 if (!adev->scpm_enabled) { 1300 /* 1301 * Copy pptable bo in the vram to smc with SMU MSGs such as 1302 * SetDriverDramAddr and TransferTableDram2Smu. 1303 */ 1304 ret = smu_write_pptable(smu); 1305 if (ret) { 1306 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1307 return ret; 1308 } 1309 } 1310 1311 /* issue Run*Btc msg */ 1312 ret = smu_run_btc(smu); 1313 if (ret) 1314 return ret; 1315 1316 /* 1317 * With SCPM enabled, these actions(and relevant messages) are 1318 * not needed and permitted. 1319 */ 1320 if (!adev->scpm_enabled) { 1321 ret = smu_feature_set_allowed_mask(smu); 1322 if (ret) { 1323 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1324 return ret; 1325 } 1326 } 1327 1328 ret = smu_system_features_control(smu, true); 1329 if (ret) { 1330 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1331 return ret; 1332 } 1333 1334 ret = smu_feature_get_enabled_mask(smu, &features_supported); 1335 if (ret) { 1336 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); 1337 return ret; 1338 } 1339 bitmap_copy(feature->supported, 1340 (unsigned long *)&features_supported, 1341 feature->feature_num); 1342 1343 if (!smu_is_dpm_running(smu)) 1344 dev_info(adev->dev, "dpm has been disabled\n"); 1345 1346 /* 1347 * Set initialized values (get from vbios) to dpm tables context such as 1348 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1349 * type of clks. 1350 */ 1351 ret = smu_set_default_dpm_table(smu); 1352 if (ret) { 1353 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1354 return ret; 1355 } 1356 1357 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1358 pcie_gen = 3; 1359 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1360 pcie_gen = 2; 1361 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1362 pcie_gen = 1; 1363 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1364 pcie_gen = 0; 1365 1366 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1367 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1368 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1369 */ 1370 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1371 pcie_width = 6; 1372 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1373 pcie_width = 5; 1374 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1375 pcie_width = 4; 1376 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1377 pcie_width = 3; 1378 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1379 pcie_width = 2; 1380 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1381 pcie_width = 1; 1382 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1383 if (ret) { 1384 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1385 return ret; 1386 } 1387 1388 ret = smu_get_thermal_temperature_range(smu); 1389 if (ret) { 1390 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1391 return ret; 1392 } 1393 1394 ret = smu_enable_thermal_alert(smu); 1395 if (ret) { 1396 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1397 return ret; 1398 } 1399 1400 ret = smu_notify_display_change(smu); 1401 if (ret) { 1402 dev_err(adev->dev, "Failed to notify display change!\n"); 1403 return ret; 1404 } 1405 1406 /* 1407 * Set min deep sleep dce fclk with bootup value from vbios via 1408 * SetMinDeepSleepDcefclk MSG. 1409 */ 1410 ret = smu_set_min_dcef_deep_sleep(smu, 1411 smu->smu_table.boot_values.dcefclk / 100); 1412 1413 return ret; 1414 } 1415 1416 static int smu_start_smc_engine(struct smu_context *smu) 1417 { 1418 struct amdgpu_device *adev = smu->adev; 1419 int ret = 0; 1420 1421 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1422 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) { 1423 if (smu->ppt_funcs->load_microcode) { 1424 ret = smu->ppt_funcs->load_microcode(smu); 1425 if (ret) 1426 return ret; 1427 } 1428 } 1429 } 1430 1431 if (smu->ppt_funcs->check_fw_status) { 1432 ret = smu->ppt_funcs->check_fw_status(smu); 1433 if (ret) { 1434 dev_err(adev->dev, "SMC is not ready\n"); 1435 return ret; 1436 } 1437 } 1438 1439 /* 1440 * Send msg GetDriverIfVersion to check if the return value is equal 1441 * with DRIVER_IF_VERSION of smc header. 1442 */ 1443 ret = smu_check_fw_version(smu); 1444 if (ret) 1445 return ret; 1446 1447 return ret; 1448 } 1449 1450 static int smu_hw_init(void *handle) 1451 { 1452 int ret; 1453 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1454 struct smu_context *smu = adev->powerplay.pp_handle; 1455 1456 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1457 smu->pm_enabled = false; 1458 return 0; 1459 } 1460 1461 ret = smu_start_smc_engine(smu); 1462 if (ret) { 1463 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1464 return ret; 1465 } 1466 1467 if (smu->is_apu) { 1468 ret = smu_set_gfx_imu_enable(smu); 1469 if (ret) 1470 return ret; 1471 smu_dpm_set_vcn_enable(smu, true); 1472 smu_dpm_set_jpeg_enable(smu, true); 1473 smu_set_gfx_cgpg(smu, true); 1474 } 1475 1476 if (!smu->pm_enabled) 1477 return 0; 1478 1479 ret = smu_get_driver_allowed_feature_mask(smu); 1480 if (ret) 1481 return ret; 1482 1483 ret = smu_smc_hw_setup(smu); 1484 if (ret) { 1485 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1486 return ret; 1487 } 1488 1489 /* 1490 * Move maximum sustainable clock retrieving here considering 1491 * 1. It is not needed on resume(from S3). 1492 * 2. DAL settings come between .hw_init and .late_init of SMU. 1493 * And DAL needs to know the maximum sustainable clocks. Thus 1494 * it cannot be put in .late_init(). 1495 */ 1496 ret = smu_init_max_sustainable_clocks(smu); 1497 if (ret) { 1498 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1499 return ret; 1500 } 1501 1502 adev->pm.dpm_enabled = true; 1503 1504 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1505 1506 return 0; 1507 } 1508 1509 static int smu_disable_dpms(struct smu_context *smu) 1510 { 1511 struct amdgpu_device *adev = smu->adev; 1512 int ret = 0; 1513 bool use_baco = !smu->is_apu && 1514 ((amdgpu_in_reset(adev) && 1515 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1516 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1517 1518 /* 1519 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others) 1520 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues. 1521 */ 1522 switch (adev->ip_versions[MP1_HWIP][0]) { 1523 case IP_VERSION(13, 0, 0): 1524 case IP_VERSION(13, 0, 7): 1525 case IP_VERSION(13, 0, 10): 1526 return 0; 1527 default: 1528 break; 1529 } 1530 1531 /* 1532 * For custom pptable uploading, skip the DPM features 1533 * disable process on Navi1x ASICs. 1534 * - As the gfx related features are under control of 1535 * RLC on those ASICs. RLC reinitialization will be 1536 * needed to reenable them. That will cost much more 1537 * efforts. 1538 * 1539 * - SMU firmware can handle the DPM reenablement 1540 * properly. 1541 */ 1542 if (smu->uploading_custom_pp_table) { 1543 switch (adev->ip_versions[MP1_HWIP][0]) { 1544 case IP_VERSION(11, 0, 0): 1545 case IP_VERSION(11, 0, 5): 1546 case IP_VERSION(11, 0, 9): 1547 case IP_VERSION(11, 0, 7): 1548 case IP_VERSION(11, 0, 11): 1549 case IP_VERSION(11, 5, 0): 1550 case IP_VERSION(11, 0, 12): 1551 case IP_VERSION(11, 0, 13): 1552 return 0; 1553 default: 1554 break; 1555 } 1556 } 1557 1558 /* 1559 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1560 * on BACO in. Driver involvement is unnecessary. 1561 */ 1562 if (use_baco) { 1563 switch (adev->ip_versions[MP1_HWIP][0]) { 1564 case IP_VERSION(11, 0, 7): 1565 case IP_VERSION(11, 0, 0): 1566 case IP_VERSION(11, 0, 5): 1567 case IP_VERSION(11, 0, 9): 1568 case IP_VERSION(13, 0, 7): 1569 return 0; 1570 default: 1571 break; 1572 } 1573 } 1574 1575 /* 1576 * For SMU 13.0.4/11, PMFW will handle the features disablement properly 1577 * for gpu reset and S0i3 cases. Driver involvement is unnecessary. 1578 */ 1579 if (amdgpu_in_reset(adev) || adev->in_s0ix) { 1580 switch (adev->ip_versions[MP1_HWIP][0]) { 1581 case IP_VERSION(13, 0, 4): 1582 case IP_VERSION(13, 0, 11): 1583 return 0; 1584 default: 1585 break; 1586 } 1587 } 1588 1589 /* 1590 * For gpu reset, runpm and hibernation through BACO, 1591 * BACO feature has to be kept enabled. 1592 */ 1593 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1594 ret = smu_disable_all_features_with_exception(smu, 1595 SMU_FEATURE_BACO_BIT); 1596 if (ret) 1597 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1598 } else { 1599 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */ 1600 if (!adev->scpm_enabled) { 1601 ret = smu_system_features_control(smu, false); 1602 if (ret) 1603 dev_err(adev->dev, "Failed to disable smu features.\n"); 1604 } 1605 } 1606 1607 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) && 1608 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop) 1609 adev->gfx.rlc.funcs->stop(adev); 1610 1611 return ret; 1612 } 1613 1614 static int smu_smc_hw_cleanup(struct smu_context *smu) 1615 { 1616 struct amdgpu_device *adev = smu->adev; 1617 int ret = 0; 1618 1619 cancel_work_sync(&smu->throttling_logging_work); 1620 cancel_work_sync(&smu->interrupt_work); 1621 1622 ret = smu_disable_thermal_alert(smu); 1623 if (ret) { 1624 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1625 return ret; 1626 } 1627 1628 cancel_delayed_work_sync(&smu->swctf_delayed_work); 1629 1630 ret = smu_disable_dpms(smu); 1631 if (ret) { 1632 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1633 return ret; 1634 } 1635 1636 return 0; 1637 } 1638 1639 static int smu_hw_fini(void *handle) 1640 { 1641 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1642 struct smu_context *smu = adev->powerplay.pp_handle; 1643 1644 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1645 return 0; 1646 1647 smu_dpm_set_vcn_enable(smu, false); 1648 smu_dpm_set_jpeg_enable(smu, false); 1649 1650 adev->vcn.cur_state = AMD_PG_STATE_GATE; 1651 adev->jpeg.cur_state = AMD_PG_STATE_GATE; 1652 1653 if (!smu->pm_enabled) 1654 return 0; 1655 1656 adev->pm.dpm_enabled = false; 1657 1658 return smu_smc_hw_cleanup(smu); 1659 } 1660 1661 static void smu_late_fini(void *handle) 1662 { 1663 struct amdgpu_device *adev = handle; 1664 struct smu_context *smu = adev->powerplay.pp_handle; 1665 1666 kfree(smu); 1667 } 1668 1669 static int smu_reset(struct smu_context *smu) 1670 { 1671 struct amdgpu_device *adev = smu->adev; 1672 int ret; 1673 1674 ret = smu_hw_fini(adev); 1675 if (ret) 1676 return ret; 1677 1678 ret = smu_hw_init(adev); 1679 if (ret) 1680 return ret; 1681 1682 ret = smu_late_init(adev); 1683 if (ret) 1684 return ret; 1685 1686 return 0; 1687 } 1688 1689 static int smu_suspend(void *handle) 1690 { 1691 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1692 struct smu_context *smu = adev->powerplay.pp_handle; 1693 int ret; 1694 uint64_t count; 1695 1696 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1697 return 0; 1698 1699 if (!smu->pm_enabled) 1700 return 0; 1701 1702 adev->pm.dpm_enabled = false; 1703 1704 ret = smu_smc_hw_cleanup(smu); 1705 if (ret) 1706 return ret; 1707 1708 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1709 1710 smu_set_gfx_cgpg(smu, false); 1711 1712 /* 1713 * pwfw resets entrycount when device is suspended, so we save the 1714 * last value to be used when we resume to keep it consistent 1715 */ 1716 ret = smu_get_entrycount_gfxoff(smu, &count); 1717 if (!ret) 1718 adev->gfx.gfx_off_entrycount = count; 1719 1720 return 0; 1721 } 1722 1723 static int smu_resume(void *handle) 1724 { 1725 int ret; 1726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1727 struct smu_context *smu = adev->powerplay.pp_handle; 1728 1729 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1730 return 0; 1731 1732 if (!smu->pm_enabled) 1733 return 0; 1734 1735 dev_info(adev->dev, "SMU is resuming...\n"); 1736 1737 ret = smu_start_smc_engine(smu); 1738 if (ret) { 1739 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1740 return ret; 1741 } 1742 1743 ret = smu_smc_hw_setup(smu); 1744 if (ret) { 1745 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1746 return ret; 1747 } 1748 1749 ret = smu_set_gfx_imu_enable(smu); 1750 if (ret) 1751 return ret; 1752 1753 smu_set_gfx_cgpg(smu, true); 1754 1755 smu->disable_uclk_switch = 0; 1756 1757 adev->pm.dpm_enabled = true; 1758 1759 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1760 1761 return 0; 1762 } 1763 1764 static int smu_display_configuration_change(void *handle, 1765 const struct amd_pp_display_configuration *display_config) 1766 { 1767 struct smu_context *smu = handle; 1768 1769 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1770 return -EOPNOTSUPP; 1771 1772 if (!display_config) 1773 return -EINVAL; 1774 1775 smu_set_min_dcef_deep_sleep(smu, 1776 display_config->min_dcef_deep_sleep_set_clk / 100); 1777 1778 return 0; 1779 } 1780 1781 static int smu_set_clockgating_state(void *handle, 1782 enum amd_clockgating_state state) 1783 { 1784 return 0; 1785 } 1786 1787 static int smu_set_powergating_state(void *handle, 1788 enum amd_powergating_state state) 1789 { 1790 return 0; 1791 } 1792 1793 static int smu_enable_umd_pstate(void *handle, 1794 enum amd_dpm_forced_level *level) 1795 { 1796 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1797 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1798 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1799 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1800 1801 struct smu_context *smu = (struct smu_context*)(handle); 1802 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1803 1804 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1805 return -EINVAL; 1806 1807 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1808 /* enter umd pstate, save current level, disable gfx cg*/ 1809 if (*level & profile_mode_mask) { 1810 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1811 smu_gpo_control(smu, false); 1812 smu_gfx_ulv_control(smu, false); 1813 smu_deep_sleep_control(smu, false); 1814 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1815 } 1816 } else { 1817 /* exit umd pstate, restore level, enable gfx cg*/ 1818 if (!(*level & profile_mode_mask)) { 1819 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1820 *level = smu_dpm_ctx->saved_dpm_level; 1821 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1822 smu_deep_sleep_control(smu, true); 1823 smu_gfx_ulv_control(smu, true); 1824 smu_gpo_control(smu, true); 1825 } 1826 } 1827 1828 return 0; 1829 } 1830 1831 static int smu_bump_power_profile_mode(struct smu_context *smu, 1832 long *param, 1833 uint32_t param_size) 1834 { 1835 int ret = 0; 1836 1837 if (smu->ppt_funcs->set_power_profile_mode) 1838 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1839 1840 return ret; 1841 } 1842 1843 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1844 enum amd_dpm_forced_level level, 1845 bool skip_display_settings, 1846 bool force_update) 1847 { 1848 int ret = 0; 1849 int index = 0; 1850 long workload[1]; 1851 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1852 1853 if (!skip_display_settings) { 1854 ret = smu_display_config_changed(smu); 1855 if (ret) { 1856 dev_err(smu->adev->dev, "Failed to change display config!"); 1857 return ret; 1858 } 1859 } 1860 1861 ret = smu_apply_clocks_adjust_rules(smu); 1862 if (ret) { 1863 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1864 return ret; 1865 } 1866 1867 if (!skip_display_settings) { 1868 ret = smu_notify_smc_display_config(smu); 1869 if (ret) { 1870 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1871 return ret; 1872 } 1873 } 1874 1875 if (force_update || smu_dpm_ctx->dpm_level != level) { 1876 ret = smu_asic_set_performance_level(smu, level); 1877 if (ret) { 1878 dev_err(smu->adev->dev, "Failed to set performance level!"); 1879 return ret; 1880 } 1881 1882 /* update the saved copy */ 1883 smu_dpm_ctx->dpm_level = level; 1884 } 1885 1886 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1887 index = fls(smu->workload_mask); 1888 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1889 workload[0] = smu->workload_setting[index]; 1890 1891 if (force_update || smu->power_profile_mode != workload[0]) 1892 smu_bump_power_profile_mode(smu, workload, 0); 1893 } 1894 1895 return ret; 1896 } 1897 1898 static int smu_handle_task(struct smu_context *smu, 1899 enum amd_dpm_forced_level level, 1900 enum amd_pp_task task_id) 1901 { 1902 int ret = 0; 1903 1904 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1905 return -EOPNOTSUPP; 1906 1907 switch (task_id) { 1908 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1909 ret = smu_pre_display_config_changed(smu); 1910 if (ret) 1911 return ret; 1912 ret = smu_adjust_power_state_dynamic(smu, level, false, false); 1913 break; 1914 case AMD_PP_TASK_COMPLETE_INIT: 1915 ret = smu_adjust_power_state_dynamic(smu, level, true, true); 1916 break; 1917 case AMD_PP_TASK_READJUST_POWER_STATE: 1918 ret = smu_adjust_power_state_dynamic(smu, level, true, false); 1919 break; 1920 default: 1921 break; 1922 } 1923 1924 return ret; 1925 } 1926 1927 static int smu_handle_dpm_task(void *handle, 1928 enum amd_pp_task task_id, 1929 enum amd_pm_state_type *user_state) 1930 { 1931 struct smu_context *smu = handle; 1932 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1933 1934 return smu_handle_task(smu, smu_dpm->dpm_level, task_id); 1935 1936 } 1937 1938 static int smu_switch_power_profile(void *handle, 1939 enum PP_SMC_POWER_PROFILE type, 1940 bool en) 1941 { 1942 struct smu_context *smu = handle; 1943 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1944 long workload[1]; 1945 uint32_t index; 1946 1947 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1948 return -EOPNOTSUPP; 1949 1950 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1951 return -EINVAL; 1952 1953 if (!en) { 1954 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1955 index = fls(smu->workload_mask); 1956 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1957 workload[0] = smu->workload_setting[index]; 1958 } else { 1959 smu->workload_mask |= (1 << smu->workload_prority[type]); 1960 index = fls(smu->workload_mask); 1961 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1962 workload[0] = smu->workload_setting[index]; 1963 } 1964 1965 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1966 smu_bump_power_profile_mode(smu, workload, 0); 1967 1968 return 0; 1969 } 1970 1971 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1972 { 1973 struct smu_context *smu = handle; 1974 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1975 1976 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1977 return -EOPNOTSUPP; 1978 1979 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1980 return -EINVAL; 1981 1982 return smu_dpm_ctx->dpm_level; 1983 } 1984 1985 static int smu_force_performance_level(void *handle, 1986 enum amd_dpm_forced_level level) 1987 { 1988 struct smu_context *smu = handle; 1989 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1990 int ret = 0; 1991 1992 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1993 return -EOPNOTSUPP; 1994 1995 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1996 return -EINVAL; 1997 1998 ret = smu_enable_umd_pstate(smu, &level); 1999 if (ret) 2000 return ret; 2001 2002 ret = smu_handle_task(smu, level, 2003 AMD_PP_TASK_READJUST_POWER_STATE); 2004 2005 /* reset user dpm clock state */ 2006 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2007 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 2008 smu->user_dpm_profile.clk_dependency = 0; 2009 } 2010 2011 return ret; 2012 } 2013 2014 static int smu_set_display_count(void *handle, uint32_t count) 2015 { 2016 struct smu_context *smu = handle; 2017 2018 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2019 return -EOPNOTSUPP; 2020 2021 return smu_init_display_count(smu, count); 2022 } 2023 2024 static int smu_force_smuclk_levels(struct smu_context *smu, 2025 enum smu_clk_type clk_type, 2026 uint32_t mask) 2027 { 2028 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 2029 int ret = 0; 2030 2031 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2032 return -EOPNOTSUPP; 2033 2034 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 2035 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 2036 return -EINVAL; 2037 } 2038 2039 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 2040 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 2041 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2042 smu->user_dpm_profile.clk_mask[clk_type] = mask; 2043 smu_set_user_clk_dependencies(smu, clk_type); 2044 } 2045 } 2046 2047 return ret; 2048 } 2049 2050 static int smu_force_ppclk_levels(void *handle, 2051 enum pp_clock_type type, 2052 uint32_t mask) 2053 { 2054 struct smu_context *smu = handle; 2055 enum smu_clk_type clk_type; 2056 2057 switch (type) { 2058 case PP_SCLK: 2059 clk_type = SMU_SCLK; break; 2060 case PP_MCLK: 2061 clk_type = SMU_MCLK; break; 2062 case PP_PCIE: 2063 clk_type = SMU_PCIE; break; 2064 case PP_SOCCLK: 2065 clk_type = SMU_SOCCLK; break; 2066 case PP_FCLK: 2067 clk_type = SMU_FCLK; break; 2068 case PP_DCEFCLK: 2069 clk_type = SMU_DCEFCLK; break; 2070 case PP_VCLK: 2071 clk_type = SMU_VCLK; break; 2072 case PP_VCLK1: 2073 clk_type = SMU_VCLK1; break; 2074 case PP_DCLK: 2075 clk_type = SMU_DCLK; break; 2076 case PP_DCLK1: 2077 clk_type = SMU_DCLK1; break; 2078 case OD_SCLK: 2079 clk_type = SMU_OD_SCLK; break; 2080 case OD_MCLK: 2081 clk_type = SMU_OD_MCLK; break; 2082 case OD_VDDC_CURVE: 2083 clk_type = SMU_OD_VDDC_CURVE; break; 2084 case OD_RANGE: 2085 clk_type = SMU_OD_RANGE; break; 2086 default: 2087 return -EINVAL; 2088 } 2089 2090 return smu_force_smuclk_levels(smu, clk_type, mask); 2091 } 2092 2093 /* 2094 * On system suspending or resetting, the dpm_enabled 2095 * flag will be cleared. So that those SMU services which 2096 * are not supported will be gated. 2097 * However, the mp1 state setting should still be granted 2098 * even if the dpm_enabled cleared. 2099 */ 2100 static int smu_set_mp1_state(void *handle, 2101 enum pp_mp1_state mp1_state) 2102 { 2103 struct smu_context *smu = handle; 2104 int ret = 0; 2105 2106 if (!smu->pm_enabled) 2107 return -EOPNOTSUPP; 2108 2109 if (smu->ppt_funcs && 2110 smu->ppt_funcs->set_mp1_state) 2111 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 2112 2113 return ret; 2114 } 2115 2116 static int smu_set_df_cstate(void *handle, 2117 enum pp_df_cstate state) 2118 { 2119 struct smu_context *smu = handle; 2120 int ret = 0; 2121 2122 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2123 return -EOPNOTSUPP; 2124 2125 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 2126 return 0; 2127 2128 ret = smu->ppt_funcs->set_df_cstate(smu, state); 2129 if (ret) 2130 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 2131 2132 return ret; 2133 } 2134 2135 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 2136 { 2137 int ret = 0; 2138 2139 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2140 return -EOPNOTSUPP; 2141 2142 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 2143 return 0; 2144 2145 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2146 if (ret) 2147 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2148 2149 return ret; 2150 } 2151 2152 int smu_write_watermarks_table(struct smu_context *smu) 2153 { 2154 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2155 return -EOPNOTSUPP; 2156 2157 return smu_set_watermarks_table(smu, NULL); 2158 } 2159 2160 static int smu_set_watermarks_for_clock_ranges(void *handle, 2161 struct pp_smu_wm_range_sets *clock_ranges) 2162 { 2163 struct smu_context *smu = handle; 2164 2165 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2166 return -EOPNOTSUPP; 2167 2168 if (smu->disable_watermark) 2169 return 0; 2170 2171 return smu_set_watermarks_table(smu, clock_ranges); 2172 } 2173 2174 int smu_set_ac_dc(struct smu_context *smu) 2175 { 2176 int ret = 0; 2177 2178 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2179 return -EOPNOTSUPP; 2180 2181 /* controlled by firmware */ 2182 if (smu->dc_controlled_by_gpio) 2183 return 0; 2184 2185 ret = smu_set_power_source(smu, 2186 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2187 SMU_POWER_SOURCE_DC); 2188 if (ret) 2189 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2190 smu->adev->pm.ac_power ? "AC" : "DC"); 2191 2192 return ret; 2193 } 2194 2195 const struct amd_ip_funcs smu_ip_funcs = { 2196 .name = "smu", 2197 .early_init = smu_early_init, 2198 .late_init = smu_late_init, 2199 .sw_init = smu_sw_init, 2200 .sw_fini = smu_sw_fini, 2201 .hw_init = smu_hw_init, 2202 .hw_fini = smu_hw_fini, 2203 .late_fini = smu_late_fini, 2204 .suspend = smu_suspend, 2205 .resume = smu_resume, 2206 .is_idle = NULL, 2207 .check_soft_reset = NULL, 2208 .wait_for_idle = NULL, 2209 .soft_reset = NULL, 2210 .set_clockgating_state = smu_set_clockgating_state, 2211 .set_powergating_state = smu_set_powergating_state, 2212 }; 2213 2214 const struct amdgpu_ip_block_version smu_v11_0_ip_block = { 2215 .type = AMD_IP_BLOCK_TYPE_SMC, 2216 .major = 11, 2217 .minor = 0, 2218 .rev = 0, 2219 .funcs = &smu_ip_funcs, 2220 }; 2221 2222 const struct amdgpu_ip_block_version smu_v12_0_ip_block = { 2223 .type = AMD_IP_BLOCK_TYPE_SMC, 2224 .major = 12, 2225 .minor = 0, 2226 .rev = 0, 2227 .funcs = &smu_ip_funcs, 2228 }; 2229 2230 const struct amdgpu_ip_block_version smu_v13_0_ip_block = { 2231 .type = AMD_IP_BLOCK_TYPE_SMC, 2232 .major = 13, 2233 .minor = 0, 2234 .rev = 0, 2235 .funcs = &smu_ip_funcs, 2236 }; 2237 2238 static int smu_load_microcode(void *handle) 2239 { 2240 struct smu_context *smu = handle; 2241 struct amdgpu_device *adev = smu->adev; 2242 int ret = 0; 2243 2244 if (!smu->pm_enabled) 2245 return -EOPNOTSUPP; 2246 2247 /* This should be used for non PSP loading */ 2248 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2249 return 0; 2250 2251 if (smu->ppt_funcs->load_microcode) { 2252 ret = smu->ppt_funcs->load_microcode(smu); 2253 if (ret) { 2254 dev_err(adev->dev, "Load microcode failed\n"); 2255 return ret; 2256 } 2257 } 2258 2259 if (smu->ppt_funcs->check_fw_status) { 2260 ret = smu->ppt_funcs->check_fw_status(smu); 2261 if (ret) { 2262 dev_err(adev->dev, "SMC is not ready\n"); 2263 return ret; 2264 } 2265 } 2266 2267 return ret; 2268 } 2269 2270 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2271 { 2272 int ret = 0; 2273 2274 if (smu->ppt_funcs->set_gfx_cgpg) 2275 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2276 2277 return ret; 2278 } 2279 2280 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2281 { 2282 struct smu_context *smu = handle; 2283 int ret = 0; 2284 2285 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2286 return -EOPNOTSUPP; 2287 2288 if (!smu->ppt_funcs->set_fan_speed_rpm) 2289 return -EOPNOTSUPP; 2290 2291 if (speed == U32_MAX) 2292 return -EINVAL; 2293 2294 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 2295 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2296 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM; 2297 smu->user_dpm_profile.fan_speed_rpm = speed; 2298 2299 /* Override custom PWM setting as they cannot co-exist */ 2300 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM; 2301 smu->user_dpm_profile.fan_speed_pwm = 0; 2302 } 2303 2304 return ret; 2305 } 2306 2307 /** 2308 * smu_get_power_limit - Request one of the SMU Power Limits 2309 * 2310 * @handle: pointer to smu context 2311 * @limit: requested limit is written back to this variable 2312 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2313 * @pp_power_type: &pp_power_type type of power 2314 * Return: 0 on success, <0 on error 2315 * 2316 */ 2317 int smu_get_power_limit(void *handle, 2318 uint32_t *limit, 2319 enum pp_power_limit_level pp_limit_level, 2320 enum pp_power_type pp_power_type) 2321 { 2322 struct smu_context *smu = handle; 2323 struct amdgpu_device *adev = smu->adev; 2324 enum smu_ppt_limit_level limit_level; 2325 uint32_t limit_type; 2326 int ret = 0; 2327 2328 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2329 return -EOPNOTSUPP; 2330 2331 switch (pp_power_type) { 2332 case PP_PWR_TYPE_SUSTAINED: 2333 limit_type = SMU_DEFAULT_PPT_LIMIT; 2334 break; 2335 case PP_PWR_TYPE_FAST: 2336 limit_type = SMU_FAST_PPT_LIMIT; 2337 break; 2338 default: 2339 return -EOPNOTSUPP; 2340 break; 2341 } 2342 2343 switch (pp_limit_level) { 2344 case PP_PWR_LIMIT_CURRENT: 2345 limit_level = SMU_PPT_LIMIT_CURRENT; 2346 break; 2347 case PP_PWR_LIMIT_DEFAULT: 2348 limit_level = SMU_PPT_LIMIT_DEFAULT; 2349 break; 2350 case PP_PWR_LIMIT_MAX: 2351 limit_level = SMU_PPT_LIMIT_MAX; 2352 break; 2353 case PP_PWR_LIMIT_MIN: 2354 default: 2355 return -EOPNOTSUPP; 2356 break; 2357 } 2358 2359 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2360 if (smu->ppt_funcs->get_ppt_limit) 2361 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2362 } else { 2363 switch (limit_level) { 2364 case SMU_PPT_LIMIT_CURRENT: 2365 switch (adev->ip_versions[MP1_HWIP][0]) { 2366 case IP_VERSION(13, 0, 2): 2367 case IP_VERSION(11, 0, 7): 2368 case IP_VERSION(11, 0, 11): 2369 case IP_VERSION(11, 0, 12): 2370 case IP_VERSION(11, 0, 13): 2371 ret = smu_get_asic_power_limits(smu, 2372 &smu->current_power_limit, 2373 NULL, 2374 NULL); 2375 break; 2376 default: 2377 break; 2378 } 2379 *limit = smu->current_power_limit; 2380 break; 2381 case SMU_PPT_LIMIT_DEFAULT: 2382 *limit = smu->default_power_limit; 2383 break; 2384 case SMU_PPT_LIMIT_MAX: 2385 *limit = smu->max_power_limit; 2386 break; 2387 default: 2388 break; 2389 } 2390 } 2391 2392 return ret; 2393 } 2394 2395 static int smu_set_power_limit(void *handle, uint32_t limit) 2396 { 2397 struct smu_context *smu = handle; 2398 uint32_t limit_type = limit >> 24; 2399 int ret = 0; 2400 2401 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2402 return -EOPNOTSUPP; 2403 2404 limit &= (1<<24)-1; 2405 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2406 if (smu->ppt_funcs->set_power_limit) 2407 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2408 2409 if (limit > smu->max_power_limit) { 2410 dev_err(smu->adev->dev, 2411 "New power limit (%d) is over the max allowed %d\n", 2412 limit, smu->max_power_limit); 2413 return -EINVAL; 2414 } 2415 2416 if (!limit) 2417 limit = smu->current_power_limit; 2418 2419 if (smu->ppt_funcs->set_power_limit) { 2420 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit); 2421 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2422 smu->user_dpm_profile.power_limit = limit; 2423 } 2424 2425 return ret; 2426 } 2427 2428 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2429 { 2430 int ret = 0; 2431 2432 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2433 return -EOPNOTSUPP; 2434 2435 if (smu->ppt_funcs->print_clk_levels) 2436 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2437 2438 return ret; 2439 } 2440 2441 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) 2442 { 2443 enum smu_clk_type clk_type; 2444 2445 switch (type) { 2446 case PP_SCLK: 2447 clk_type = SMU_SCLK; break; 2448 case PP_MCLK: 2449 clk_type = SMU_MCLK; break; 2450 case PP_PCIE: 2451 clk_type = SMU_PCIE; break; 2452 case PP_SOCCLK: 2453 clk_type = SMU_SOCCLK; break; 2454 case PP_FCLK: 2455 clk_type = SMU_FCLK; break; 2456 case PP_DCEFCLK: 2457 clk_type = SMU_DCEFCLK; break; 2458 case PP_VCLK: 2459 clk_type = SMU_VCLK; break; 2460 case PP_VCLK1: 2461 clk_type = SMU_VCLK1; break; 2462 case PP_DCLK: 2463 clk_type = SMU_DCLK; break; 2464 case PP_DCLK1: 2465 clk_type = SMU_DCLK1; break; 2466 case OD_SCLK: 2467 clk_type = SMU_OD_SCLK; break; 2468 case OD_MCLK: 2469 clk_type = SMU_OD_MCLK; break; 2470 case OD_VDDC_CURVE: 2471 clk_type = SMU_OD_VDDC_CURVE; break; 2472 case OD_RANGE: 2473 clk_type = SMU_OD_RANGE; break; 2474 case OD_VDDGFX_OFFSET: 2475 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2476 case OD_CCLK: 2477 clk_type = SMU_OD_CCLK; break; 2478 default: 2479 clk_type = SMU_CLK_COUNT; break; 2480 } 2481 2482 return clk_type; 2483 } 2484 2485 static int smu_print_ppclk_levels(void *handle, 2486 enum pp_clock_type type, 2487 char *buf) 2488 { 2489 struct smu_context *smu = handle; 2490 enum smu_clk_type clk_type; 2491 2492 clk_type = smu_convert_to_smuclk(type); 2493 if (clk_type == SMU_CLK_COUNT) 2494 return -EINVAL; 2495 2496 return smu_print_smuclk_levels(smu, clk_type, buf); 2497 } 2498 2499 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) 2500 { 2501 struct smu_context *smu = handle; 2502 enum smu_clk_type clk_type; 2503 2504 clk_type = smu_convert_to_smuclk(type); 2505 if (clk_type == SMU_CLK_COUNT) 2506 return -EINVAL; 2507 2508 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2509 return -EOPNOTSUPP; 2510 2511 if (!smu->ppt_funcs->emit_clk_levels) 2512 return -ENOENT; 2513 2514 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset); 2515 2516 } 2517 2518 static int smu_od_edit_dpm_table(void *handle, 2519 enum PP_OD_DPM_TABLE_COMMAND type, 2520 long *input, uint32_t size) 2521 { 2522 struct smu_context *smu = handle; 2523 int ret = 0; 2524 2525 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2526 return -EOPNOTSUPP; 2527 2528 if (smu->ppt_funcs->od_edit_dpm_table) { 2529 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2530 } 2531 2532 return ret; 2533 } 2534 2535 static int smu_read_sensor(void *handle, 2536 int sensor, 2537 void *data, 2538 int *size_arg) 2539 { 2540 struct smu_context *smu = handle; 2541 struct smu_umd_pstate_table *pstate_table = 2542 &smu->pstate_table; 2543 int ret = 0; 2544 uint32_t *size, size_val; 2545 2546 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2547 return -EOPNOTSUPP; 2548 2549 if (!data || !size_arg) 2550 return -EINVAL; 2551 2552 size_val = *size_arg; 2553 size = &size_val; 2554 2555 if (smu->ppt_funcs->read_sensor) 2556 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2557 goto unlock; 2558 2559 switch (sensor) { 2560 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2561 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2562 *size = 4; 2563 break; 2564 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2565 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2566 *size = 4; 2567 break; 2568 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK: 2569 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100; 2570 *size = 4; 2571 break; 2572 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK: 2573 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; 2574 *size = 4; 2575 break; 2576 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2577 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); 2578 *size = 8; 2579 break; 2580 case AMDGPU_PP_SENSOR_UVD_POWER: 2581 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2582 *size = 4; 2583 break; 2584 case AMDGPU_PP_SENSOR_VCE_POWER: 2585 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2586 *size = 4; 2587 break; 2588 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2589 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1; 2590 *size = 4; 2591 break; 2592 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2593 *(uint32_t *)data = 0; 2594 *size = 4; 2595 break; 2596 default: 2597 *size = 0; 2598 ret = -EOPNOTSUPP; 2599 break; 2600 } 2601 2602 unlock: 2603 // assign uint32_t to int 2604 *size_arg = size_val; 2605 2606 return ret; 2607 } 2608 2609 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit) 2610 { 2611 int ret = -EINVAL; 2612 struct smu_context *smu = handle; 2613 2614 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit) 2615 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit); 2616 2617 return ret; 2618 } 2619 2620 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit) 2621 { 2622 int ret = -EINVAL; 2623 struct smu_context *smu = handle; 2624 2625 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit) 2626 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit); 2627 2628 return ret; 2629 } 2630 2631 static int smu_get_power_profile_mode(void *handle, char *buf) 2632 { 2633 struct smu_context *smu = handle; 2634 2635 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2636 !smu->ppt_funcs->get_power_profile_mode) 2637 return -EOPNOTSUPP; 2638 if (!buf) 2639 return -EINVAL; 2640 2641 return smu->ppt_funcs->get_power_profile_mode(smu, buf); 2642 } 2643 2644 static int smu_set_power_profile_mode(void *handle, 2645 long *param, 2646 uint32_t param_size) 2647 { 2648 struct smu_context *smu = handle; 2649 2650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || 2651 !smu->ppt_funcs->set_power_profile_mode) 2652 return -EOPNOTSUPP; 2653 2654 return smu_bump_power_profile_mode(smu, param, param_size); 2655 } 2656 2657 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) 2658 { 2659 struct smu_context *smu = handle; 2660 2661 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2662 return -EOPNOTSUPP; 2663 2664 if (!smu->ppt_funcs->get_fan_control_mode) 2665 return -EOPNOTSUPP; 2666 2667 if (!fan_mode) 2668 return -EINVAL; 2669 2670 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu); 2671 2672 return 0; 2673 } 2674 2675 static int smu_set_fan_control_mode(void *handle, u32 value) 2676 { 2677 struct smu_context *smu = handle; 2678 int ret = 0; 2679 2680 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2681 return -EOPNOTSUPP; 2682 2683 if (!smu->ppt_funcs->set_fan_control_mode) 2684 return -EOPNOTSUPP; 2685 2686 if (value == U32_MAX) 2687 return -EINVAL; 2688 2689 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2690 if (ret) 2691 goto out; 2692 2693 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2694 smu->user_dpm_profile.fan_mode = value; 2695 2696 /* reset user dpm fan speed */ 2697 if (value != AMD_FAN_CTRL_MANUAL) { 2698 smu->user_dpm_profile.fan_speed_pwm = 0; 2699 smu->user_dpm_profile.fan_speed_rpm = 0; 2700 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM); 2701 } 2702 } 2703 2704 out: 2705 return ret; 2706 } 2707 2708 static int smu_get_fan_speed_pwm(void *handle, u32 *speed) 2709 { 2710 struct smu_context *smu = handle; 2711 int ret = 0; 2712 2713 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2714 return -EOPNOTSUPP; 2715 2716 if (!smu->ppt_funcs->get_fan_speed_pwm) 2717 return -EOPNOTSUPP; 2718 2719 if (!speed) 2720 return -EINVAL; 2721 2722 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed); 2723 2724 return ret; 2725 } 2726 2727 static int smu_set_fan_speed_pwm(void *handle, u32 speed) 2728 { 2729 struct smu_context *smu = handle; 2730 int ret = 0; 2731 2732 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2733 return -EOPNOTSUPP; 2734 2735 if (!smu->ppt_funcs->set_fan_speed_pwm) 2736 return -EOPNOTSUPP; 2737 2738 if (speed == U32_MAX) 2739 return -EINVAL; 2740 2741 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed); 2742 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 2743 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM; 2744 smu->user_dpm_profile.fan_speed_pwm = speed; 2745 2746 /* Override custom RPM setting as they cannot co-exist */ 2747 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM; 2748 smu->user_dpm_profile.fan_speed_rpm = 0; 2749 } 2750 2751 return ret; 2752 } 2753 2754 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2755 { 2756 struct smu_context *smu = handle; 2757 int ret = 0; 2758 2759 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2760 return -EOPNOTSUPP; 2761 2762 if (!smu->ppt_funcs->get_fan_speed_rpm) 2763 return -EOPNOTSUPP; 2764 2765 if (!speed) 2766 return -EINVAL; 2767 2768 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2769 2770 return ret; 2771 } 2772 2773 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2774 { 2775 struct smu_context *smu = handle; 2776 2777 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2778 return -EOPNOTSUPP; 2779 2780 return smu_set_min_dcef_deep_sleep(smu, clk); 2781 } 2782 2783 static int smu_get_clock_by_type_with_latency(void *handle, 2784 enum amd_pp_clock_type type, 2785 struct pp_clock_levels_with_latency *clocks) 2786 { 2787 struct smu_context *smu = handle; 2788 enum smu_clk_type clk_type; 2789 int ret = 0; 2790 2791 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2792 return -EOPNOTSUPP; 2793 2794 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2795 switch (type) { 2796 case amd_pp_sys_clock: 2797 clk_type = SMU_GFXCLK; 2798 break; 2799 case amd_pp_mem_clock: 2800 clk_type = SMU_MCLK; 2801 break; 2802 case amd_pp_dcef_clock: 2803 clk_type = SMU_DCEFCLK; 2804 break; 2805 case amd_pp_disp_clock: 2806 clk_type = SMU_DISPCLK; 2807 break; 2808 default: 2809 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2810 return -EINVAL; 2811 } 2812 2813 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2814 } 2815 2816 return ret; 2817 } 2818 2819 static int smu_display_clock_voltage_request(void *handle, 2820 struct pp_display_clock_request *clock_req) 2821 { 2822 struct smu_context *smu = handle; 2823 int ret = 0; 2824 2825 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2826 return -EOPNOTSUPP; 2827 2828 if (smu->ppt_funcs->display_clock_voltage_request) 2829 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2830 2831 return ret; 2832 } 2833 2834 2835 static int smu_display_disable_memory_clock_switch(void *handle, 2836 bool disable_memory_clock_switch) 2837 { 2838 struct smu_context *smu = handle; 2839 int ret = -EINVAL; 2840 2841 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2842 return -EOPNOTSUPP; 2843 2844 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2845 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2846 2847 return ret; 2848 } 2849 2850 static int smu_set_xgmi_pstate(void *handle, 2851 uint32_t pstate) 2852 { 2853 struct smu_context *smu = handle; 2854 int ret = 0; 2855 2856 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2857 return -EOPNOTSUPP; 2858 2859 if (smu->ppt_funcs->set_xgmi_pstate) 2860 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2861 2862 if (ret) 2863 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2864 2865 return ret; 2866 } 2867 2868 static int smu_get_baco_capability(void *handle, bool *cap) 2869 { 2870 struct smu_context *smu = handle; 2871 2872 *cap = false; 2873 2874 if (!smu->pm_enabled) 2875 return 0; 2876 2877 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2878 *cap = smu->ppt_funcs->baco_is_support(smu); 2879 2880 return 0; 2881 } 2882 2883 static int smu_baco_set_state(void *handle, int state) 2884 { 2885 struct smu_context *smu = handle; 2886 int ret = 0; 2887 2888 if (!smu->pm_enabled) 2889 return -EOPNOTSUPP; 2890 2891 if (state == 0) { 2892 if (smu->ppt_funcs->baco_exit) 2893 ret = smu->ppt_funcs->baco_exit(smu); 2894 } else if (state == 1) { 2895 if (smu->ppt_funcs->baco_enter) 2896 ret = smu->ppt_funcs->baco_enter(smu); 2897 } else { 2898 return -EINVAL; 2899 } 2900 2901 if (ret) 2902 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2903 (state)?"enter":"exit"); 2904 2905 return ret; 2906 } 2907 2908 bool smu_mode1_reset_is_support(struct smu_context *smu) 2909 { 2910 bool ret = false; 2911 2912 if (!smu->pm_enabled) 2913 return false; 2914 2915 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2916 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2917 2918 return ret; 2919 } 2920 2921 bool smu_mode2_reset_is_support(struct smu_context *smu) 2922 { 2923 bool ret = false; 2924 2925 if (!smu->pm_enabled) 2926 return false; 2927 2928 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2929 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2930 2931 return ret; 2932 } 2933 2934 int smu_mode1_reset(struct smu_context *smu) 2935 { 2936 int ret = 0; 2937 2938 if (!smu->pm_enabled) 2939 return -EOPNOTSUPP; 2940 2941 if (smu->ppt_funcs->mode1_reset) 2942 ret = smu->ppt_funcs->mode1_reset(smu); 2943 2944 return ret; 2945 } 2946 2947 static int smu_mode2_reset(void *handle) 2948 { 2949 struct smu_context *smu = handle; 2950 int ret = 0; 2951 2952 if (!smu->pm_enabled) 2953 return -EOPNOTSUPP; 2954 2955 if (smu->ppt_funcs->mode2_reset) 2956 ret = smu->ppt_funcs->mode2_reset(smu); 2957 2958 if (ret) 2959 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2960 2961 return ret; 2962 } 2963 2964 static int smu_enable_gfx_features(void *handle) 2965 { 2966 struct smu_context *smu = handle; 2967 int ret = 0; 2968 2969 if (!smu->pm_enabled) 2970 return -EOPNOTSUPP; 2971 2972 if (smu->ppt_funcs->enable_gfx_features) 2973 ret = smu->ppt_funcs->enable_gfx_features(smu); 2974 2975 if (ret) 2976 dev_err(smu->adev->dev, "enable gfx features failed!\n"); 2977 2978 return ret; 2979 } 2980 2981 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2982 struct pp_smu_nv_clock_table *max_clocks) 2983 { 2984 struct smu_context *smu = handle; 2985 int ret = 0; 2986 2987 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2988 return -EOPNOTSUPP; 2989 2990 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2991 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2992 2993 return ret; 2994 } 2995 2996 static int smu_get_uclk_dpm_states(void *handle, 2997 unsigned int *clock_values_in_khz, 2998 unsigned int *num_states) 2999 { 3000 struct smu_context *smu = handle; 3001 int ret = 0; 3002 3003 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3004 return -EOPNOTSUPP; 3005 3006 if (smu->ppt_funcs->get_uclk_dpm_states) 3007 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 3008 3009 return ret; 3010 } 3011 3012 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 3013 { 3014 struct smu_context *smu = handle; 3015 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 3016 3017 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3018 return -EOPNOTSUPP; 3019 3020 if (smu->ppt_funcs->get_current_power_state) 3021 pm_state = smu->ppt_funcs->get_current_power_state(smu); 3022 3023 return pm_state; 3024 } 3025 3026 static int smu_get_dpm_clock_table(void *handle, 3027 struct dpm_clocks *clock_table) 3028 { 3029 struct smu_context *smu = handle; 3030 int ret = 0; 3031 3032 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3033 return -EOPNOTSUPP; 3034 3035 if (smu->ppt_funcs->get_dpm_clock_table) 3036 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 3037 3038 return ret; 3039 } 3040 3041 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 3042 { 3043 struct smu_context *smu = handle; 3044 3045 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3046 return -EOPNOTSUPP; 3047 3048 if (!smu->ppt_funcs->get_gpu_metrics) 3049 return -EOPNOTSUPP; 3050 3051 return smu->ppt_funcs->get_gpu_metrics(smu, table); 3052 } 3053 3054 static int smu_enable_mgpu_fan_boost(void *handle) 3055 { 3056 struct smu_context *smu = handle; 3057 int ret = 0; 3058 3059 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 3060 return -EOPNOTSUPP; 3061 3062 if (smu->ppt_funcs->enable_mgpu_fan_boost) 3063 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 3064 3065 return ret; 3066 } 3067 3068 static int smu_gfx_state_change_set(void *handle, 3069 uint32_t state) 3070 { 3071 struct smu_context *smu = handle; 3072 int ret = 0; 3073 3074 if (smu->ppt_funcs->gfx_state_change_set) 3075 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 3076 3077 return ret; 3078 } 3079 3080 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable) 3081 { 3082 int ret = 0; 3083 3084 if (smu->ppt_funcs->smu_handle_passthrough_sbr) 3085 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable); 3086 3087 return ret; 3088 } 3089 3090 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc) 3091 { 3092 int ret = -EOPNOTSUPP; 3093 3094 if (smu->ppt_funcs && 3095 smu->ppt_funcs->get_ecc_info) 3096 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc); 3097 3098 return ret; 3099 3100 } 3101 3102 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3103 { 3104 struct smu_context *smu = handle; 3105 struct smu_table_context *smu_table = &smu->smu_table; 3106 struct smu_table *memory_pool = &smu_table->memory_pool; 3107 3108 if (!addr || !size) 3109 return -EINVAL; 3110 3111 *addr = NULL; 3112 *size = 0; 3113 if (memory_pool->bo) { 3114 *addr = memory_pool->cpu_addr; 3115 *size = memory_pool->size; 3116 } 3117 3118 return 0; 3119 } 3120 3121 static const struct amd_pm_funcs swsmu_pm_funcs = { 3122 /* export for sysfs */ 3123 .set_fan_control_mode = smu_set_fan_control_mode, 3124 .get_fan_control_mode = smu_get_fan_control_mode, 3125 .set_fan_speed_pwm = smu_set_fan_speed_pwm, 3126 .get_fan_speed_pwm = smu_get_fan_speed_pwm, 3127 .force_clock_level = smu_force_ppclk_levels, 3128 .print_clock_levels = smu_print_ppclk_levels, 3129 .emit_clock_levels = smu_emit_ppclk_levels, 3130 .force_performance_level = smu_force_performance_level, 3131 .read_sensor = smu_read_sensor, 3132 .get_apu_thermal_limit = smu_get_apu_thermal_limit, 3133 .set_apu_thermal_limit = smu_set_apu_thermal_limit, 3134 .get_performance_level = smu_get_performance_level, 3135 .get_current_power_state = smu_get_current_power_state, 3136 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3137 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3138 .get_pp_num_states = smu_get_power_num_states, 3139 .get_pp_table = smu_sys_get_pp_table, 3140 .set_pp_table = smu_sys_set_pp_table, 3141 .switch_power_profile = smu_switch_power_profile, 3142 /* export to amdgpu */ 3143 .dispatch_tasks = smu_handle_dpm_task, 3144 .load_firmware = smu_load_microcode, 3145 .set_powergating_by_smu = smu_dpm_set_power_gate, 3146 .set_power_limit = smu_set_power_limit, 3147 .get_power_limit = smu_get_power_limit, 3148 .get_power_profile_mode = smu_get_power_profile_mode, 3149 .set_power_profile_mode = smu_set_power_profile_mode, 3150 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3151 .set_mp1_state = smu_set_mp1_state, 3152 .gfx_state_change_set = smu_gfx_state_change_set, 3153 /* export to DC */ 3154 .get_sclk = smu_get_sclk, 3155 .get_mclk = smu_get_mclk, 3156 .display_configuration_change = smu_display_configuration_change, 3157 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3158 .display_clock_voltage_request = smu_display_clock_voltage_request, 3159 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3160 .set_active_display_count = smu_set_display_count, 3161 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3162 .get_asic_baco_capability = smu_get_baco_capability, 3163 .set_asic_baco_state = smu_baco_set_state, 3164 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3165 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3166 .asic_reset_mode_2 = smu_mode2_reset, 3167 .asic_reset_enable_gfx_features = smu_enable_gfx_features, 3168 .set_df_cstate = smu_set_df_cstate, 3169 .set_xgmi_pstate = smu_set_xgmi_pstate, 3170 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3171 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3172 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3173 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3174 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3175 .get_dpm_clock_table = smu_get_dpm_clock_table, 3176 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3177 }; 3178 3179 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event, 3180 uint64_t event_arg) 3181 { 3182 int ret = -EINVAL; 3183 3184 if (smu->ppt_funcs->wait_for_event) 3185 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3186 3187 return ret; 3188 } 3189 3190 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size) 3191 { 3192 3193 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled) 3194 return -EOPNOTSUPP; 3195 3196 /* Confirm the buffer allocated is of correct size */ 3197 if (size != smu->stb_context.stb_buf_size) 3198 return -EINVAL; 3199 3200 /* 3201 * No need to lock smu mutex as we access STB directly through MMIO 3202 * and not going through SMU messaging route (for now at least). 3203 * For registers access rely on implementation internal locking. 3204 */ 3205 return smu->ppt_funcs->stb_collect_info(smu, buf, size); 3206 } 3207 3208 #if defined(CONFIG_DEBUG_FS) 3209 3210 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp) 3211 { 3212 struct amdgpu_device *adev = filp->f_inode->i_private; 3213 struct smu_context *smu = adev->powerplay.pp_handle; 3214 unsigned char *buf; 3215 int r; 3216 3217 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL); 3218 if (!buf) 3219 return -ENOMEM; 3220 3221 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size); 3222 if (r) 3223 goto out; 3224 3225 filp->private_data = buf; 3226 3227 return 0; 3228 3229 out: 3230 kvfree(buf); 3231 return r; 3232 } 3233 3234 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size, 3235 loff_t *pos) 3236 { 3237 struct amdgpu_device *adev = filp->f_inode->i_private; 3238 struct smu_context *smu = adev->powerplay.pp_handle; 3239 3240 3241 if (!filp->private_data) 3242 return -EINVAL; 3243 3244 return simple_read_from_buffer(buf, 3245 size, 3246 pos, filp->private_data, 3247 smu->stb_context.stb_buf_size); 3248 } 3249 3250 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp) 3251 { 3252 kvfree(filp->private_data); 3253 filp->private_data = NULL; 3254 3255 return 0; 3256 } 3257 3258 /* 3259 * We have to define not only read method but also 3260 * open and release because .read takes up to PAGE_SIZE 3261 * data each time so and so is invoked multiple times. 3262 * We allocate the STB buffer in .open and release it 3263 * in .release 3264 */ 3265 static const struct file_operations smu_stb_debugfs_fops = { 3266 .owner = THIS_MODULE, 3267 .open = smu_stb_debugfs_open, 3268 .read = smu_stb_debugfs_read, 3269 .release = smu_stb_debugfs_release, 3270 .llseek = default_llseek, 3271 }; 3272 3273 #endif 3274 3275 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev) 3276 { 3277 #if defined(CONFIG_DEBUG_FS) 3278 3279 struct smu_context *smu = adev->powerplay.pp_handle; 3280 3281 if (!smu || (!smu->stb_context.stb_buf_size)) 3282 return; 3283 3284 debugfs_create_file_size("amdgpu_smu_stb_dump", 3285 S_IRUSR, 3286 adev_to_drm(adev)->primary->debugfs_root, 3287 adev, 3288 &smu_stb_debugfs_fops, 3289 smu->stb_context.stb_buf_size); 3290 #endif 3291 } 3292 3293 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size) 3294 { 3295 int ret = 0; 3296 3297 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num) 3298 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size); 3299 3300 return ret; 3301 } 3302 3303 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size) 3304 { 3305 int ret = 0; 3306 3307 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag) 3308 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size); 3309 3310 return ret; 3311 } 3312