1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "amd_pcie.h" 37 38 /* 39 * DO NOT use these for err/warn/info/debug messages. 40 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 41 * They are more MGPU friendly. 42 */ 43 #undef pr_err 44 #undef pr_warn 45 #undef pr_info 46 #undef pr_debug 47 48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf) 49 { 50 size_t size = 0; 51 52 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 53 return -EOPNOTSUPP; 54 55 mutex_lock(&smu->mutex); 56 57 size = smu_get_pp_feature_mask(smu, buf); 58 59 mutex_unlock(&smu->mutex); 60 61 return size; 62 } 63 64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) 65 { 66 int ret = 0; 67 68 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 69 return -EOPNOTSUPP; 70 71 mutex_lock(&smu->mutex); 72 73 ret = smu_set_pp_feature_mask(smu, new_mask); 74 75 mutex_unlock(&smu->mutex); 76 77 return ret; 78 } 79 80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 81 { 82 int ret = 0; 83 struct smu_context *smu = &adev->smu; 84 85 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 86 *value = smu_get_gfx_off_status(smu); 87 else 88 ret = -EINVAL; 89 90 return ret; 91 } 92 93 int smu_set_soft_freq_range(struct smu_context *smu, 94 enum smu_clk_type clk_type, 95 uint32_t min, 96 uint32_t max) 97 { 98 int ret = 0; 99 100 mutex_lock(&smu->mutex); 101 102 if (smu->ppt_funcs->set_soft_freq_limited_range) 103 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 104 clk_type, 105 min, 106 max); 107 108 mutex_unlock(&smu->mutex); 109 110 return ret; 111 } 112 113 int smu_get_dpm_freq_range(struct smu_context *smu, 114 enum smu_clk_type clk_type, 115 uint32_t *min, 116 uint32_t *max) 117 { 118 int ret = 0; 119 120 if (!min && !max) 121 return -EINVAL; 122 123 mutex_lock(&smu->mutex); 124 125 if (smu->ppt_funcs->get_dpm_ultimate_freq) 126 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 127 clk_type, 128 min, 129 max); 130 131 mutex_unlock(&smu->mutex); 132 133 return ret; 134 } 135 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 137 bool enable) 138 { 139 struct smu_power_context *smu_power = &smu->smu_power; 140 struct smu_power_gate *power_gate = &smu_power->power_gate; 141 int ret = 0; 142 143 if (!smu->ppt_funcs->dpm_set_vcn_enable) 144 return 0; 145 146 if (atomic_read(&power_gate->vcn_gated) ^ enable) 147 return 0; 148 149 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 150 if (!ret) 151 atomic_set(&power_gate->vcn_gated, !enable); 152 153 return ret; 154 } 155 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 157 bool enable) 158 { 159 struct smu_power_context *smu_power = &smu->smu_power; 160 struct smu_power_gate *power_gate = &smu_power->power_gate; 161 int ret = 0; 162 163 mutex_lock(&power_gate->vcn_gate_lock); 164 165 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 166 167 mutex_unlock(&power_gate->vcn_gate_lock); 168 169 return ret; 170 } 171 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 173 bool enable) 174 { 175 struct smu_power_context *smu_power = &smu->smu_power; 176 struct smu_power_gate *power_gate = &smu_power->power_gate; 177 int ret = 0; 178 179 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 180 return 0; 181 182 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 183 return 0; 184 185 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 186 if (!ret) 187 atomic_set(&power_gate->jpeg_gated, !enable); 188 189 return ret; 190 } 191 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 193 bool enable) 194 { 195 struct smu_power_context *smu_power = &smu->smu_power; 196 struct smu_power_gate *power_gate = &smu_power->power_gate; 197 int ret = 0; 198 199 mutex_lock(&power_gate->jpeg_gate_lock); 200 201 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 202 203 mutex_unlock(&power_gate->jpeg_gate_lock); 204 205 return ret; 206 } 207 208 /** 209 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 210 * 211 * @smu: smu_context pointer 212 * @block_type: the IP block to power gate/ungate 213 * @gate: to power gate if true, ungate otherwise 214 * 215 * This API uses no smu->mutex lock protection due to: 216 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 217 * This is guarded to be race condition free by the caller. 218 * 2. Or get called on user setting request of power_dpm_force_performance_level. 219 * Under this case, the smu->mutex lock protection is already enforced on 220 * the parent API smu_force_performance_level of the call path. 221 */ 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, 223 bool gate) 224 { 225 int ret = 0; 226 227 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 228 return -EOPNOTSUPP; 229 230 switch (block_type) { 231 /* 232 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 233 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 234 */ 235 case AMD_IP_BLOCK_TYPE_UVD: 236 case AMD_IP_BLOCK_TYPE_VCN: 237 ret = smu_dpm_set_vcn_enable(smu, !gate); 238 if (ret) 239 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 240 gate ? "gate" : "ungate"); 241 break; 242 case AMD_IP_BLOCK_TYPE_GFX: 243 ret = smu_gfx_off_control(smu, gate); 244 if (ret) 245 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 246 gate ? "enable" : "disable"); 247 break; 248 case AMD_IP_BLOCK_TYPE_SDMA: 249 ret = smu_powergate_sdma(smu, gate); 250 if (ret) 251 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 252 gate ? "gate" : "ungate"); 253 break; 254 case AMD_IP_BLOCK_TYPE_JPEG: 255 ret = smu_dpm_set_jpeg_enable(smu, !gate); 256 if (ret) 257 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 258 gate ? "gate" : "ungate"); 259 break; 260 default: 261 dev_err(smu->adev->dev, "Unsupported block type!\n"); 262 return -EINVAL; 263 } 264 265 return ret; 266 } 267 268 int smu_get_power_num_states(struct smu_context *smu, 269 struct pp_states_info *state_info) 270 { 271 if (!state_info) 272 return -EINVAL; 273 274 /* not support power state */ 275 memset(state_info, 0, sizeof(struct pp_states_info)); 276 state_info->nums = 1; 277 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 278 279 return 0; 280 } 281 282 bool is_support_sw_smu(struct amdgpu_device *adev) 283 { 284 if (adev->asic_type >= CHIP_ARCTURUS) 285 return true; 286 287 return false; 288 } 289 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table) 291 { 292 struct smu_table_context *smu_table = &smu->smu_table; 293 uint32_t powerplay_table_size; 294 295 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 296 return -EOPNOTSUPP; 297 298 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 299 return -EINVAL; 300 301 mutex_lock(&smu->mutex); 302 303 if (smu_table->hardcode_pptable) 304 *table = smu_table->hardcode_pptable; 305 else 306 *table = smu_table->power_play_table; 307 308 powerplay_table_size = smu_table->power_play_table_size; 309 310 mutex_unlock(&smu->mutex); 311 312 return powerplay_table_size; 313 } 314 315 int smu_sys_set_pp_table(struct smu_context *smu, void *buf, size_t size) 316 { 317 struct smu_table_context *smu_table = &smu->smu_table; 318 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 319 int ret = 0; 320 321 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 322 return -EOPNOTSUPP; 323 324 if (header->usStructureSize != size) { 325 dev_err(smu->adev->dev, "pp table size not matched !\n"); 326 return -EIO; 327 } 328 329 mutex_lock(&smu->mutex); 330 if (!smu_table->hardcode_pptable) 331 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 332 if (!smu_table->hardcode_pptable) { 333 ret = -ENOMEM; 334 goto failed; 335 } 336 337 memcpy(smu_table->hardcode_pptable, buf, size); 338 smu_table->power_play_table = smu_table->hardcode_pptable; 339 smu_table->power_play_table_size = size; 340 341 /* 342 * Special hw_fini action(for Navi1x, the DPMs disablement will be 343 * skipped) may be needed for custom pptable uploading. 344 */ 345 smu->uploading_custom_pp_table = true; 346 347 ret = smu_reset(smu); 348 if (ret) 349 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 350 351 smu->uploading_custom_pp_table = false; 352 353 failed: 354 mutex_unlock(&smu->mutex); 355 return ret; 356 } 357 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 359 { 360 struct smu_feature *feature = &smu->smu_feature; 361 int ret = 0; 362 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 363 364 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 365 366 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 367 SMU_FEATURE_MAX/32); 368 if (ret) 369 return ret; 370 371 bitmap_or(feature->allowed, feature->allowed, 372 (unsigned long *)allowed_feature_mask, 373 feature->feature_num); 374 375 return ret; 376 } 377 378 static int smu_set_funcs(struct amdgpu_device *adev) 379 { 380 struct smu_context *smu = &adev->smu; 381 382 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 383 smu->od_enabled = true; 384 385 switch (adev->asic_type) { 386 case CHIP_NAVI10: 387 case CHIP_NAVI14: 388 case CHIP_NAVI12: 389 navi10_set_ppt_funcs(smu); 390 break; 391 case CHIP_ARCTURUS: 392 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 393 arcturus_set_ppt_funcs(smu); 394 /* OD is not supported on Arcturus */ 395 smu->od_enabled =false; 396 break; 397 case CHIP_SIENNA_CICHLID: 398 case CHIP_NAVY_FLOUNDER: 399 sienna_cichlid_set_ppt_funcs(smu); 400 break; 401 case CHIP_RENOIR: 402 renoir_set_ppt_funcs(smu); 403 break; 404 default: 405 return -EINVAL; 406 } 407 408 return 0; 409 } 410 411 static int smu_early_init(void *handle) 412 { 413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 414 struct smu_context *smu = &adev->smu; 415 416 smu->adev = adev; 417 smu->pm_enabled = !!amdgpu_dpm; 418 smu->is_apu = false; 419 mutex_init(&smu->mutex); 420 421 return smu_set_funcs(adev); 422 } 423 424 static int smu_set_default_dpm_table(struct smu_context *smu) 425 { 426 struct smu_power_context *smu_power = &smu->smu_power; 427 struct smu_power_gate *power_gate = &smu_power->power_gate; 428 int vcn_gate, jpeg_gate; 429 int ret = 0; 430 431 if (!smu->ppt_funcs->set_default_dpm_table) 432 return 0; 433 434 mutex_lock(&power_gate->vcn_gate_lock); 435 mutex_lock(&power_gate->jpeg_gate_lock); 436 437 vcn_gate = atomic_read(&power_gate->vcn_gated); 438 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 439 440 ret = smu_dpm_set_vcn_enable_locked(smu, true); 441 if (ret) 442 goto err0_out; 443 444 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 445 if (ret) 446 goto err1_out; 447 448 ret = smu->ppt_funcs->set_default_dpm_table(smu); 449 if (ret) 450 dev_err(smu->adev->dev, 451 "Failed to setup default dpm clock tables!\n"); 452 453 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 454 err1_out: 455 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 456 err0_out: 457 mutex_unlock(&power_gate->jpeg_gate_lock); 458 mutex_unlock(&power_gate->vcn_gate_lock); 459 460 return ret; 461 } 462 463 static int smu_late_init(void *handle) 464 { 465 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 466 struct smu_context *smu = &adev->smu; 467 int ret = 0; 468 469 if (!smu->pm_enabled) 470 return 0; 471 472 ret = smu_post_init(smu); 473 if (ret) { 474 dev_err(adev->dev, "Failed to post smu init!\n"); 475 return ret; 476 } 477 478 ret = smu_set_default_od_settings(smu); 479 if (ret) { 480 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 481 return ret; 482 } 483 484 /* 485 * Set initialized values (get from vbios) to dpm tables context such as 486 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 487 * type of clks. 488 */ 489 ret = smu_set_default_dpm_table(smu); 490 if (ret) { 491 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 492 return ret; 493 } 494 495 ret = smu_populate_umd_state_clk(smu); 496 if (ret) { 497 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 498 return ret; 499 } 500 501 ret = smu_get_asic_power_limits(smu); 502 if (ret) { 503 dev_err(adev->dev, "Failed to get asic power limits!\n"); 504 return ret; 505 } 506 507 smu_get_unique_id(smu); 508 509 smu_get_fan_parameters(smu); 510 511 smu_handle_task(&adev->smu, 512 smu->smu_dpm.dpm_level, 513 AMD_PP_TASK_COMPLETE_INIT, 514 false); 515 516 return 0; 517 } 518 519 static int smu_init_fb_allocations(struct smu_context *smu) 520 { 521 struct amdgpu_device *adev = smu->adev; 522 struct smu_table_context *smu_table = &smu->smu_table; 523 struct smu_table *tables = smu_table->tables; 524 struct smu_table *driver_table = &(smu_table->driver_table); 525 uint32_t max_table_size = 0; 526 int ret, i; 527 528 /* VRAM allocation for tool table */ 529 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 530 ret = amdgpu_bo_create_kernel(adev, 531 tables[SMU_TABLE_PMSTATUSLOG].size, 532 tables[SMU_TABLE_PMSTATUSLOG].align, 533 tables[SMU_TABLE_PMSTATUSLOG].domain, 534 &tables[SMU_TABLE_PMSTATUSLOG].bo, 535 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 536 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 537 if (ret) { 538 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 539 return ret; 540 } 541 } 542 543 /* VRAM allocation for driver table */ 544 for (i = 0; i < SMU_TABLE_COUNT; i++) { 545 if (tables[i].size == 0) 546 continue; 547 548 if (i == SMU_TABLE_PMSTATUSLOG) 549 continue; 550 551 if (max_table_size < tables[i].size) 552 max_table_size = tables[i].size; 553 } 554 555 driver_table->size = max_table_size; 556 driver_table->align = PAGE_SIZE; 557 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 558 559 ret = amdgpu_bo_create_kernel(adev, 560 driver_table->size, 561 driver_table->align, 562 driver_table->domain, 563 &driver_table->bo, 564 &driver_table->mc_address, 565 &driver_table->cpu_addr); 566 if (ret) { 567 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 568 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 569 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 570 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 571 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 572 } 573 574 return ret; 575 } 576 577 static int smu_fini_fb_allocations(struct smu_context *smu) 578 { 579 struct smu_table_context *smu_table = &smu->smu_table; 580 struct smu_table *tables = smu_table->tables; 581 struct smu_table *driver_table = &(smu_table->driver_table); 582 583 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 584 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 585 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 586 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 587 588 amdgpu_bo_free_kernel(&driver_table->bo, 589 &driver_table->mc_address, 590 &driver_table->cpu_addr); 591 592 return 0; 593 } 594 595 /** 596 * smu_alloc_memory_pool - allocate memory pool in the system memory 597 * 598 * @smu: amdgpu_device pointer 599 * 600 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 601 * and DramLogSetDramAddr can notify it changed. 602 * 603 * Returns 0 on success, error on failure. 604 */ 605 static int smu_alloc_memory_pool(struct smu_context *smu) 606 { 607 struct amdgpu_device *adev = smu->adev; 608 struct smu_table_context *smu_table = &smu->smu_table; 609 struct smu_table *memory_pool = &smu_table->memory_pool; 610 uint64_t pool_size = smu->pool_size; 611 int ret = 0; 612 613 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 614 return ret; 615 616 memory_pool->size = pool_size; 617 memory_pool->align = PAGE_SIZE; 618 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 619 620 switch (pool_size) { 621 case SMU_MEMORY_POOL_SIZE_256_MB: 622 case SMU_MEMORY_POOL_SIZE_512_MB: 623 case SMU_MEMORY_POOL_SIZE_1_GB: 624 case SMU_MEMORY_POOL_SIZE_2_GB: 625 ret = amdgpu_bo_create_kernel(adev, 626 memory_pool->size, 627 memory_pool->align, 628 memory_pool->domain, 629 &memory_pool->bo, 630 &memory_pool->mc_address, 631 &memory_pool->cpu_addr); 632 if (ret) 633 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 634 break; 635 default: 636 break; 637 } 638 639 return ret; 640 } 641 642 static int smu_free_memory_pool(struct smu_context *smu) 643 { 644 struct smu_table_context *smu_table = &smu->smu_table; 645 struct smu_table *memory_pool = &smu_table->memory_pool; 646 647 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 648 return 0; 649 650 amdgpu_bo_free_kernel(&memory_pool->bo, 651 &memory_pool->mc_address, 652 &memory_pool->cpu_addr); 653 654 memset(memory_pool, 0, sizeof(struct smu_table)); 655 656 return 0; 657 } 658 659 static int smu_alloc_dummy_read_table(struct smu_context *smu) 660 { 661 struct smu_table_context *smu_table = &smu->smu_table; 662 struct smu_table *dummy_read_1_table = 663 &smu_table->dummy_read_1_table; 664 struct amdgpu_device *adev = smu->adev; 665 int ret = 0; 666 667 dummy_read_1_table->size = 0x40000; 668 dummy_read_1_table->align = PAGE_SIZE; 669 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 670 671 ret = amdgpu_bo_create_kernel(adev, 672 dummy_read_1_table->size, 673 dummy_read_1_table->align, 674 dummy_read_1_table->domain, 675 &dummy_read_1_table->bo, 676 &dummy_read_1_table->mc_address, 677 &dummy_read_1_table->cpu_addr); 678 if (ret) 679 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 680 681 return ret; 682 } 683 684 static void smu_free_dummy_read_table(struct smu_context *smu) 685 { 686 struct smu_table_context *smu_table = &smu->smu_table; 687 struct smu_table *dummy_read_1_table = 688 &smu_table->dummy_read_1_table; 689 690 691 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 692 &dummy_read_1_table->mc_address, 693 &dummy_read_1_table->cpu_addr); 694 695 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 696 } 697 698 static int smu_smc_table_sw_init(struct smu_context *smu) 699 { 700 int ret; 701 702 /** 703 * Create smu_table structure, and init smc tables such as 704 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 705 */ 706 ret = smu_init_smc_tables(smu); 707 if (ret) { 708 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 709 return ret; 710 } 711 712 /** 713 * Create smu_power_context structure, and allocate smu_dpm_context and 714 * context size to fill the smu_power_context data. 715 */ 716 ret = smu_init_power(smu); 717 if (ret) { 718 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 719 return ret; 720 } 721 722 /* 723 * allocate vram bos to store smc table contents. 724 */ 725 ret = smu_init_fb_allocations(smu); 726 if (ret) 727 return ret; 728 729 ret = smu_alloc_memory_pool(smu); 730 if (ret) 731 return ret; 732 733 ret = smu_alloc_dummy_read_table(smu); 734 if (ret) 735 return ret; 736 737 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 738 if (ret) 739 return ret; 740 741 return 0; 742 } 743 744 static int smu_smc_table_sw_fini(struct smu_context *smu) 745 { 746 int ret; 747 748 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 749 750 smu_free_dummy_read_table(smu); 751 752 ret = smu_free_memory_pool(smu); 753 if (ret) 754 return ret; 755 756 ret = smu_fini_fb_allocations(smu); 757 if (ret) 758 return ret; 759 760 ret = smu_fini_power(smu); 761 if (ret) { 762 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 763 return ret; 764 } 765 766 ret = smu_fini_smc_tables(smu); 767 if (ret) { 768 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 769 return ret; 770 } 771 772 return 0; 773 } 774 775 static void smu_throttling_logging_work_fn(struct work_struct *work) 776 { 777 struct smu_context *smu = container_of(work, struct smu_context, 778 throttling_logging_work); 779 780 smu_log_thermal_throttling(smu); 781 } 782 783 static void smu_interrupt_work_fn(struct work_struct *work) 784 { 785 struct smu_context *smu = container_of(work, struct smu_context, 786 interrupt_work); 787 788 mutex_lock(&smu->mutex); 789 790 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 791 smu->ppt_funcs->interrupt_work(smu); 792 793 mutex_unlock(&smu->mutex); 794 } 795 796 static int smu_sw_init(void *handle) 797 { 798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 799 struct smu_context *smu = &adev->smu; 800 int ret; 801 802 smu->pool_size = adev->pm.smu_prv_buffer_size; 803 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 804 mutex_init(&smu->smu_feature.mutex); 805 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 806 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 807 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 808 809 mutex_init(&smu->smu_baco.mutex); 810 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 811 smu->smu_baco.platform_support = false; 812 813 mutex_init(&smu->sensor_lock); 814 mutex_init(&smu->metrics_lock); 815 mutex_init(&smu->message_lock); 816 817 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 818 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 819 atomic64_set(&smu->throttle_int_counter, 0); 820 smu->watermarks_bitmap = 0; 821 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 822 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 823 824 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 825 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 826 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 827 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 828 829 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 830 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 831 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 832 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 833 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 834 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 835 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 836 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 837 838 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 839 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 840 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 841 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 842 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 843 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 844 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 845 smu->display_config = &adev->pm.pm_display_cfg; 846 847 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 848 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 849 850 if (!amdgpu_sriov_vf(adev)) { 851 ret = smu_init_microcode(smu); 852 if (ret) { 853 dev_err(adev->dev, "Failed to load smu firmware!\n"); 854 return ret; 855 } 856 } 857 858 ret = smu_smc_table_sw_init(smu); 859 if (ret) { 860 dev_err(adev->dev, "Failed to sw init smc table!\n"); 861 return ret; 862 } 863 864 ret = smu_register_irq_handler(smu); 865 if (ret) { 866 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 867 return ret; 868 } 869 870 return 0; 871 } 872 873 static int smu_sw_fini(void *handle) 874 { 875 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 876 struct smu_context *smu = &adev->smu; 877 int ret; 878 879 ret = smu_smc_table_sw_fini(smu); 880 if (ret) { 881 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 882 return ret; 883 } 884 885 smu_fini_microcode(smu); 886 887 return 0; 888 } 889 890 static int smu_get_thermal_temperature_range(struct smu_context *smu) 891 { 892 struct amdgpu_device *adev = smu->adev; 893 struct smu_temperature_range *range = 894 &smu->thermal_range; 895 int ret = 0; 896 897 if (!smu->ppt_funcs->get_thermal_temperature_range) 898 return 0; 899 900 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 901 if (ret) 902 return ret; 903 904 adev->pm.dpm.thermal.min_temp = range->min; 905 adev->pm.dpm.thermal.max_temp = range->max; 906 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 907 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 908 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 909 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 910 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 911 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 912 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 913 914 return ret; 915 } 916 917 static int smu_smc_hw_setup(struct smu_context *smu) 918 { 919 struct amdgpu_device *adev = smu->adev; 920 uint32_t pcie_gen = 0, pcie_width = 0; 921 int ret; 922 923 if (adev->in_suspend && smu_is_dpm_running(smu)) { 924 dev_info(adev->dev, "dpm has been enabled\n"); 925 return 0; 926 } 927 928 ret = smu_init_display_count(smu, 0); 929 if (ret) { 930 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 931 return ret; 932 } 933 934 ret = smu_set_driver_table_location(smu); 935 if (ret) { 936 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 937 return ret; 938 } 939 940 /* 941 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 942 */ 943 ret = smu_set_tool_table_location(smu); 944 if (ret) { 945 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 946 return ret; 947 } 948 949 /* 950 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 951 * pool location. 952 */ 953 ret = smu_notify_memory_pool_location(smu); 954 if (ret) { 955 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 956 return ret; 957 } 958 959 /* smu_dump_pptable(smu); */ 960 /* 961 * Copy pptable bo in the vram to smc with SMU MSGs such as 962 * SetDriverDramAddr and TransferTableDram2Smu. 963 */ 964 ret = smu_write_pptable(smu); 965 if (ret) { 966 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 967 return ret; 968 } 969 970 /* issue Run*Btc msg */ 971 ret = smu_run_btc(smu); 972 if (ret) 973 return ret; 974 975 ret = smu_feature_set_allowed_mask(smu); 976 if (ret) { 977 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 978 return ret; 979 } 980 981 ret = smu_system_features_control(smu, true); 982 if (ret) { 983 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 984 return ret; 985 } 986 987 if (!smu_is_dpm_running(smu)) 988 dev_info(adev->dev, "dpm has been disabled\n"); 989 990 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 991 pcie_gen = 3; 992 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 993 pcie_gen = 2; 994 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 995 pcie_gen = 1; 996 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 997 pcie_gen = 0; 998 999 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1000 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1001 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1002 */ 1003 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1004 pcie_width = 6; 1005 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1006 pcie_width = 5; 1007 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1008 pcie_width = 4; 1009 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1010 pcie_width = 3; 1011 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1012 pcie_width = 2; 1013 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1014 pcie_width = 1; 1015 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1016 if (ret) { 1017 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1018 return ret; 1019 } 1020 1021 ret = smu_get_thermal_temperature_range(smu); 1022 if (ret) { 1023 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1024 return ret; 1025 } 1026 1027 ret = smu_enable_thermal_alert(smu); 1028 if (ret) { 1029 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1030 return ret; 1031 } 1032 1033 ret = smu_notify_display_change(smu); 1034 if (ret) 1035 return ret; 1036 1037 /* 1038 * Set min deep sleep dce fclk with bootup value from vbios via 1039 * SetMinDeepSleepDcefclk MSG. 1040 */ 1041 ret = smu_set_min_dcef_deep_sleep(smu, 1042 smu->smu_table.boot_values.dcefclk / 100); 1043 if (ret) 1044 return ret; 1045 1046 return ret; 1047 } 1048 1049 static int smu_start_smc_engine(struct smu_context *smu) 1050 { 1051 struct amdgpu_device *adev = smu->adev; 1052 int ret = 0; 1053 1054 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1055 if (adev->asic_type < CHIP_NAVI10) { 1056 if (smu->ppt_funcs->load_microcode) { 1057 ret = smu->ppt_funcs->load_microcode(smu); 1058 if (ret) 1059 return ret; 1060 } 1061 } 1062 } 1063 1064 if (smu->ppt_funcs->check_fw_status) { 1065 ret = smu->ppt_funcs->check_fw_status(smu); 1066 if (ret) { 1067 dev_err(adev->dev, "SMC is not ready\n"); 1068 return ret; 1069 } 1070 } 1071 1072 /* 1073 * Send msg GetDriverIfVersion to check if the return value is equal 1074 * with DRIVER_IF_VERSION of smc header. 1075 */ 1076 ret = smu_check_fw_version(smu); 1077 if (ret) 1078 return ret; 1079 1080 return ret; 1081 } 1082 1083 static int smu_hw_init(void *handle) 1084 { 1085 int ret; 1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1087 struct smu_context *smu = &adev->smu; 1088 1089 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1090 smu->pm_enabled = false; 1091 return 0; 1092 } 1093 1094 ret = smu_start_smc_engine(smu); 1095 if (ret) { 1096 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1097 return ret; 1098 } 1099 1100 if (smu->is_apu) { 1101 smu_powergate_sdma(&adev->smu, false); 1102 smu_dpm_set_vcn_enable(smu, true); 1103 smu_dpm_set_jpeg_enable(smu, true); 1104 smu_set_gfx_cgpg(&adev->smu, true); 1105 } 1106 1107 if (!smu->pm_enabled) 1108 return 0; 1109 1110 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1111 ret = smu_get_vbios_bootup_values(smu); 1112 if (ret) { 1113 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1114 return ret; 1115 } 1116 1117 ret = smu_setup_pptable(smu); 1118 if (ret) { 1119 dev_err(adev->dev, "Failed to setup pptable!\n"); 1120 return ret; 1121 } 1122 1123 ret = smu_get_driver_allowed_feature_mask(smu); 1124 if (ret) 1125 return ret; 1126 1127 ret = smu_smc_hw_setup(smu); 1128 if (ret) { 1129 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1130 return ret; 1131 } 1132 1133 /* 1134 * Move maximum sustainable clock retrieving here considering 1135 * 1. It is not needed on resume(from S3). 1136 * 2. DAL settings come between .hw_init and .late_init of SMU. 1137 * And DAL needs to know the maximum sustainable clocks. Thus 1138 * it cannot be put in .late_init(). 1139 */ 1140 ret = smu_init_max_sustainable_clocks(smu); 1141 if (ret) { 1142 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1143 return ret; 1144 } 1145 1146 adev->pm.dpm_enabled = true; 1147 1148 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1149 1150 return 0; 1151 } 1152 1153 static int smu_disable_dpms(struct smu_context *smu) 1154 { 1155 struct amdgpu_device *adev = smu->adev; 1156 int ret = 0; 1157 bool use_baco = !smu->is_apu && 1158 ((amdgpu_in_reset(adev) && 1159 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1160 ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev))); 1161 1162 /* 1163 * For custom pptable uploading, skip the DPM features 1164 * disable process on Navi1x ASICs. 1165 * - As the gfx related features are under control of 1166 * RLC on those ASICs. RLC reinitialization will be 1167 * needed to reenable them. That will cost much more 1168 * efforts. 1169 * 1170 * - SMU firmware can handle the DPM reenablement 1171 * properly. 1172 */ 1173 if (smu->uploading_custom_pp_table && 1174 (adev->asic_type >= CHIP_NAVI10) && 1175 (adev->asic_type <= CHIP_NAVY_FLOUNDER)) 1176 return 0; 1177 1178 /* 1179 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1180 * on BACO in. Driver involvement is unnecessary. 1181 */ 1182 if ((adev->asic_type == CHIP_SIENNA_CICHLID) && 1183 use_baco) 1184 return 0; 1185 1186 /* 1187 * For gpu reset, runpm and hibernation through BACO, 1188 * BACO feature has to be kept enabled. 1189 */ 1190 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1191 ret = smu_disable_all_features_with_exception(smu, 1192 SMU_FEATURE_BACO_BIT); 1193 if (ret) 1194 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1195 } else { 1196 ret = smu_system_features_control(smu, false); 1197 if (ret) 1198 dev_err(adev->dev, "Failed to disable smu features.\n"); 1199 } 1200 1201 if (adev->asic_type >= CHIP_NAVI10 && 1202 adev->gfx.rlc.funcs->stop) 1203 adev->gfx.rlc.funcs->stop(adev); 1204 1205 return ret; 1206 } 1207 1208 static int smu_smc_hw_cleanup(struct smu_context *smu) 1209 { 1210 struct amdgpu_device *adev = smu->adev; 1211 int ret = 0; 1212 1213 cancel_work_sync(&smu->throttling_logging_work); 1214 cancel_work_sync(&smu->interrupt_work); 1215 1216 ret = smu_disable_thermal_alert(smu); 1217 if (ret) { 1218 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1219 return ret; 1220 } 1221 1222 ret = smu_disable_dpms(smu); 1223 if (ret) { 1224 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1225 return ret; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static int smu_hw_fini(void *handle) 1232 { 1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1234 struct smu_context *smu = &adev->smu; 1235 1236 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1237 return 0; 1238 1239 if (smu->is_apu) { 1240 smu_powergate_sdma(&adev->smu, true); 1241 smu_dpm_set_vcn_enable(smu, false); 1242 smu_dpm_set_jpeg_enable(smu, false); 1243 } 1244 1245 if (!smu->pm_enabled) 1246 return 0; 1247 1248 adev->pm.dpm_enabled = false; 1249 1250 return smu_smc_hw_cleanup(smu); 1251 } 1252 1253 int smu_reset(struct smu_context *smu) 1254 { 1255 struct amdgpu_device *adev = smu->adev; 1256 int ret; 1257 1258 amdgpu_gfx_off_ctrl(smu->adev, false); 1259 1260 ret = smu_hw_fini(adev); 1261 if (ret) 1262 return ret; 1263 1264 ret = smu_hw_init(adev); 1265 if (ret) 1266 return ret; 1267 1268 ret = smu_late_init(adev); 1269 if (ret) 1270 return ret; 1271 1272 amdgpu_gfx_off_ctrl(smu->adev, true); 1273 1274 return 0; 1275 } 1276 1277 static int smu_suspend(void *handle) 1278 { 1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1280 struct smu_context *smu = &adev->smu; 1281 int ret; 1282 1283 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1284 return 0; 1285 1286 if (!smu->pm_enabled) 1287 return 0; 1288 1289 adev->pm.dpm_enabled = false; 1290 1291 ret = smu_smc_hw_cleanup(smu); 1292 if (ret) 1293 return ret; 1294 1295 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1296 1297 if (smu->is_apu) 1298 smu_set_gfx_cgpg(&adev->smu, false); 1299 1300 return 0; 1301 } 1302 1303 static int smu_resume(void *handle) 1304 { 1305 int ret; 1306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1307 struct smu_context *smu = &adev->smu; 1308 1309 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1310 return 0; 1311 1312 if (!smu->pm_enabled) 1313 return 0; 1314 1315 dev_info(adev->dev, "SMU is resuming...\n"); 1316 1317 ret = smu_start_smc_engine(smu); 1318 if (ret) { 1319 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1320 return ret; 1321 } 1322 1323 ret = smu_smc_hw_setup(smu); 1324 if (ret) { 1325 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1326 return ret; 1327 } 1328 1329 if (smu->is_apu) 1330 smu_set_gfx_cgpg(&adev->smu, true); 1331 1332 smu->disable_uclk_switch = 0; 1333 1334 adev->pm.dpm_enabled = true; 1335 1336 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1337 1338 return 0; 1339 } 1340 1341 int smu_display_configuration_change(struct smu_context *smu, 1342 const struct amd_pp_display_configuration *display_config) 1343 { 1344 int index = 0; 1345 int num_of_active_display = 0; 1346 1347 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1348 return -EOPNOTSUPP; 1349 1350 if (!display_config) 1351 return -EINVAL; 1352 1353 mutex_lock(&smu->mutex); 1354 1355 smu_set_min_dcef_deep_sleep(smu, 1356 display_config->min_dcef_deep_sleep_set_clk / 100); 1357 1358 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1359 if (display_config->displays[index].controller_id != 0) 1360 num_of_active_display++; 1361 } 1362 1363 smu_set_active_display_count(smu, num_of_active_display); 1364 1365 smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time, 1366 display_config->cpu_cc6_disable, 1367 display_config->cpu_pstate_disable, 1368 display_config->nb_pstate_switch_disable); 1369 1370 mutex_unlock(&smu->mutex); 1371 1372 return 0; 1373 } 1374 1375 static int smu_get_clock_info(struct smu_context *smu, 1376 struct smu_clock_info *clk_info, 1377 enum smu_perf_level_designation designation) 1378 { 1379 int ret; 1380 struct smu_performance_level level = {0}; 1381 1382 if (!clk_info) 1383 return -EINVAL; 1384 1385 ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level); 1386 if (ret) 1387 return -EINVAL; 1388 1389 clk_info->min_mem_clk = level.memory_clock; 1390 clk_info->min_eng_clk = level.core_clock; 1391 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width; 1392 1393 ret = smu_get_perf_level(smu, designation, &level); 1394 if (ret) 1395 return -EINVAL; 1396 1397 clk_info->min_mem_clk = level.memory_clock; 1398 clk_info->min_eng_clk = level.core_clock; 1399 clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width; 1400 1401 return 0; 1402 } 1403 1404 int smu_get_current_clocks(struct smu_context *smu, 1405 struct amd_pp_clock_info *clocks) 1406 { 1407 struct amd_pp_simple_clock_info simple_clocks = {0}; 1408 struct smu_clock_info hw_clocks; 1409 int ret = 0; 1410 1411 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1412 return -EOPNOTSUPP; 1413 1414 mutex_lock(&smu->mutex); 1415 1416 smu_get_dal_power_level(smu, &simple_clocks); 1417 1418 if (smu->support_power_containment) 1419 ret = smu_get_clock_info(smu, &hw_clocks, 1420 PERF_LEVEL_POWER_CONTAINMENT); 1421 else 1422 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY); 1423 1424 if (ret) { 1425 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n"); 1426 goto failed; 1427 } 1428 1429 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1430 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1431 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1432 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1433 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1434 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1435 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1436 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1437 1438 if (simple_clocks.level == 0) 1439 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; 1440 else 1441 clocks->max_clocks_state = simple_clocks.level; 1442 1443 if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) { 1444 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1445 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1446 } 1447 1448 failed: 1449 mutex_unlock(&smu->mutex); 1450 return ret; 1451 } 1452 1453 static int smu_set_clockgating_state(void *handle, 1454 enum amd_clockgating_state state) 1455 { 1456 return 0; 1457 } 1458 1459 static int smu_set_powergating_state(void *handle, 1460 enum amd_powergating_state state) 1461 { 1462 return 0; 1463 } 1464 1465 static int smu_enable_umd_pstate(void *handle, 1466 enum amd_dpm_forced_level *level) 1467 { 1468 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1469 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1470 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1471 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1472 1473 struct smu_context *smu = (struct smu_context*)(handle); 1474 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1475 1476 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1477 return -EINVAL; 1478 1479 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1480 /* enter umd pstate, save current level, disable gfx cg*/ 1481 if (*level & profile_mode_mask) { 1482 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1483 smu_dpm_ctx->enable_umd_pstate = true; 1484 amdgpu_device_ip_set_powergating_state(smu->adev, 1485 AMD_IP_BLOCK_TYPE_GFX, 1486 AMD_PG_STATE_UNGATE); 1487 amdgpu_device_ip_set_clockgating_state(smu->adev, 1488 AMD_IP_BLOCK_TYPE_GFX, 1489 AMD_CG_STATE_UNGATE); 1490 smu_gfx_ulv_control(smu, false); 1491 smu_deep_sleep_control(smu, false); 1492 } 1493 } else { 1494 /* exit umd pstate, restore level, enable gfx cg*/ 1495 if (!(*level & profile_mode_mask)) { 1496 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1497 *level = smu_dpm_ctx->saved_dpm_level; 1498 smu_dpm_ctx->enable_umd_pstate = false; 1499 smu_deep_sleep_control(smu, true); 1500 smu_gfx_ulv_control(smu, true); 1501 amdgpu_device_ip_set_clockgating_state(smu->adev, 1502 AMD_IP_BLOCK_TYPE_GFX, 1503 AMD_CG_STATE_GATE); 1504 amdgpu_device_ip_set_powergating_state(smu->adev, 1505 AMD_IP_BLOCK_TYPE_GFX, 1506 AMD_PG_STATE_GATE); 1507 } 1508 } 1509 1510 return 0; 1511 } 1512 1513 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1514 enum amd_dpm_forced_level level, 1515 bool skip_display_settings) 1516 { 1517 int ret = 0; 1518 int index = 0; 1519 long workload; 1520 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1521 1522 if (!skip_display_settings) { 1523 ret = smu_display_config_changed(smu); 1524 if (ret) { 1525 dev_err(smu->adev->dev, "Failed to change display config!"); 1526 return ret; 1527 } 1528 } 1529 1530 ret = smu_apply_clocks_adjust_rules(smu); 1531 if (ret) { 1532 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1533 return ret; 1534 } 1535 1536 if (!skip_display_settings) { 1537 ret = smu_notify_smc_display_config(smu); 1538 if (ret) { 1539 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1540 return ret; 1541 } 1542 } 1543 1544 if (smu_dpm_ctx->dpm_level != level) { 1545 ret = smu_asic_set_performance_level(smu, level); 1546 if (ret) { 1547 dev_err(smu->adev->dev, "Failed to set performance level!"); 1548 return ret; 1549 } 1550 1551 /* update the saved copy */ 1552 smu_dpm_ctx->dpm_level = level; 1553 } 1554 1555 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1556 index = fls(smu->workload_mask); 1557 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1558 workload = smu->workload_setting[index]; 1559 1560 if (smu->power_profile_mode != workload) 1561 smu_set_power_profile_mode(smu, &workload, 0, false); 1562 } 1563 1564 return ret; 1565 } 1566 1567 int smu_handle_task(struct smu_context *smu, 1568 enum amd_dpm_forced_level level, 1569 enum amd_pp_task task_id, 1570 bool lock_needed) 1571 { 1572 int ret = 0; 1573 1574 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1575 return -EOPNOTSUPP; 1576 1577 if (lock_needed) 1578 mutex_lock(&smu->mutex); 1579 1580 switch (task_id) { 1581 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1582 ret = smu_pre_display_config_changed(smu); 1583 if (ret) 1584 goto out; 1585 ret = smu_set_cpu_power_state(smu); 1586 if (ret) 1587 goto out; 1588 ret = smu_adjust_power_state_dynamic(smu, level, false); 1589 break; 1590 case AMD_PP_TASK_COMPLETE_INIT: 1591 case AMD_PP_TASK_READJUST_POWER_STATE: 1592 ret = smu_adjust_power_state_dynamic(smu, level, true); 1593 break; 1594 default: 1595 break; 1596 } 1597 1598 out: 1599 if (lock_needed) 1600 mutex_unlock(&smu->mutex); 1601 1602 return ret; 1603 } 1604 1605 int smu_switch_power_profile(struct smu_context *smu, 1606 enum PP_SMC_POWER_PROFILE type, 1607 bool en) 1608 { 1609 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1610 long workload; 1611 uint32_t index; 1612 1613 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1614 return -EOPNOTSUPP; 1615 1616 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1617 return -EINVAL; 1618 1619 mutex_lock(&smu->mutex); 1620 1621 if (!en) { 1622 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1623 index = fls(smu->workload_mask); 1624 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1625 workload = smu->workload_setting[index]; 1626 } else { 1627 smu->workload_mask |= (1 << smu->workload_prority[type]); 1628 index = fls(smu->workload_mask); 1629 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1630 workload = smu->workload_setting[index]; 1631 } 1632 1633 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 1634 smu_set_power_profile_mode(smu, &workload, 0, false); 1635 1636 mutex_unlock(&smu->mutex); 1637 1638 return 0; 1639 } 1640 1641 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu) 1642 { 1643 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1644 enum amd_dpm_forced_level level; 1645 1646 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1647 return -EOPNOTSUPP; 1648 1649 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1650 return -EINVAL; 1651 1652 mutex_lock(&(smu->mutex)); 1653 level = smu_dpm_ctx->dpm_level; 1654 mutex_unlock(&(smu->mutex)); 1655 1656 return level; 1657 } 1658 1659 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level) 1660 { 1661 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1662 int ret = 0; 1663 1664 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1665 return -EOPNOTSUPP; 1666 1667 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1668 return -EINVAL; 1669 1670 mutex_lock(&smu->mutex); 1671 1672 ret = smu_enable_umd_pstate(smu, &level); 1673 if (ret) { 1674 mutex_unlock(&smu->mutex); 1675 return ret; 1676 } 1677 1678 ret = smu_handle_task(smu, level, 1679 AMD_PP_TASK_READJUST_POWER_STATE, 1680 false); 1681 1682 mutex_unlock(&smu->mutex); 1683 1684 return ret; 1685 } 1686 1687 int smu_set_display_count(struct smu_context *smu, uint32_t count) 1688 { 1689 int ret = 0; 1690 1691 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1692 return -EOPNOTSUPP; 1693 1694 mutex_lock(&smu->mutex); 1695 ret = smu_init_display_count(smu, count); 1696 mutex_unlock(&smu->mutex); 1697 1698 return ret; 1699 } 1700 1701 int smu_force_clk_levels(struct smu_context *smu, 1702 enum smu_clk_type clk_type, 1703 uint32_t mask) 1704 { 1705 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1706 int ret = 0; 1707 1708 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1709 return -EOPNOTSUPP; 1710 1711 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1712 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1713 return -EINVAL; 1714 } 1715 1716 mutex_lock(&smu->mutex); 1717 1718 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) 1719 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1720 1721 mutex_unlock(&smu->mutex); 1722 1723 return ret; 1724 } 1725 1726 /* 1727 * On system suspending or resetting, the dpm_enabled 1728 * flag will be cleared. So that those SMU services which 1729 * are not supported will be gated. 1730 * However, the mp1 state setting should still be granted 1731 * even if the dpm_enabled cleared. 1732 */ 1733 int smu_set_mp1_state(struct smu_context *smu, 1734 enum pp_mp1_state mp1_state) 1735 { 1736 uint16_t msg; 1737 int ret; 1738 1739 if (!smu->pm_enabled) 1740 return -EOPNOTSUPP; 1741 1742 mutex_lock(&smu->mutex); 1743 1744 switch (mp1_state) { 1745 case PP_MP1_STATE_SHUTDOWN: 1746 msg = SMU_MSG_PrepareMp1ForShutdown; 1747 break; 1748 case PP_MP1_STATE_UNLOAD: 1749 msg = SMU_MSG_PrepareMp1ForUnload; 1750 break; 1751 case PP_MP1_STATE_RESET: 1752 msg = SMU_MSG_PrepareMp1ForReset; 1753 break; 1754 case PP_MP1_STATE_NONE: 1755 default: 1756 mutex_unlock(&smu->mutex); 1757 return 0; 1758 } 1759 1760 ret = smu_send_smc_msg(smu, msg, NULL); 1761 /* some asics may not support those messages */ 1762 if (ret == -EINVAL) 1763 ret = 0; 1764 if (ret) 1765 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); 1766 1767 mutex_unlock(&smu->mutex); 1768 1769 return ret; 1770 } 1771 1772 int smu_set_df_cstate(struct smu_context *smu, 1773 enum pp_df_cstate state) 1774 { 1775 int ret = 0; 1776 1777 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1778 return -EOPNOTSUPP; 1779 1780 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1781 return 0; 1782 1783 mutex_lock(&smu->mutex); 1784 1785 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1786 if (ret) 1787 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1788 1789 mutex_unlock(&smu->mutex); 1790 1791 return ret; 1792 } 1793 1794 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1795 { 1796 int ret = 0; 1797 1798 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1799 return -EOPNOTSUPP; 1800 1801 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1802 return 0; 1803 1804 mutex_lock(&smu->mutex); 1805 1806 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 1807 if (ret) 1808 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 1809 1810 mutex_unlock(&smu->mutex); 1811 1812 return ret; 1813 } 1814 1815 int smu_write_watermarks_table(struct smu_context *smu) 1816 { 1817 int ret = 0; 1818 1819 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1820 return -EOPNOTSUPP; 1821 1822 mutex_lock(&smu->mutex); 1823 1824 ret = smu_set_watermarks_table(smu, NULL); 1825 1826 mutex_unlock(&smu->mutex); 1827 1828 return ret; 1829 } 1830 1831 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu, 1832 struct pp_smu_wm_range_sets *clock_ranges) 1833 { 1834 int ret = 0; 1835 1836 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1837 return -EOPNOTSUPP; 1838 1839 if (smu->disable_watermark) 1840 return 0; 1841 1842 mutex_lock(&smu->mutex); 1843 1844 ret = smu_set_watermarks_table(smu, clock_ranges); 1845 1846 mutex_unlock(&smu->mutex); 1847 1848 return ret; 1849 } 1850 1851 int smu_set_ac_dc(struct smu_context *smu) 1852 { 1853 int ret = 0; 1854 1855 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1856 return -EOPNOTSUPP; 1857 1858 /* controlled by firmware */ 1859 if (smu->dc_controlled_by_gpio) 1860 return 0; 1861 1862 mutex_lock(&smu->mutex); 1863 ret = smu_set_power_source(smu, 1864 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 1865 SMU_POWER_SOURCE_DC); 1866 if (ret) 1867 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 1868 smu->adev->pm.ac_power ? "AC" : "DC"); 1869 mutex_unlock(&smu->mutex); 1870 1871 return ret; 1872 } 1873 1874 const struct amd_ip_funcs smu_ip_funcs = { 1875 .name = "smu", 1876 .early_init = smu_early_init, 1877 .late_init = smu_late_init, 1878 .sw_init = smu_sw_init, 1879 .sw_fini = smu_sw_fini, 1880 .hw_init = smu_hw_init, 1881 .hw_fini = smu_hw_fini, 1882 .suspend = smu_suspend, 1883 .resume = smu_resume, 1884 .is_idle = NULL, 1885 .check_soft_reset = NULL, 1886 .wait_for_idle = NULL, 1887 .soft_reset = NULL, 1888 .set_clockgating_state = smu_set_clockgating_state, 1889 .set_powergating_state = smu_set_powergating_state, 1890 .enable_umd_pstate = smu_enable_umd_pstate, 1891 }; 1892 1893 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 1894 { 1895 .type = AMD_IP_BLOCK_TYPE_SMC, 1896 .major = 11, 1897 .minor = 0, 1898 .rev = 0, 1899 .funcs = &smu_ip_funcs, 1900 }; 1901 1902 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 1903 { 1904 .type = AMD_IP_BLOCK_TYPE_SMC, 1905 .major = 12, 1906 .minor = 0, 1907 .rev = 0, 1908 .funcs = &smu_ip_funcs, 1909 }; 1910 1911 int smu_load_microcode(struct smu_context *smu) 1912 { 1913 int ret = 0; 1914 1915 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1916 return -EOPNOTSUPP; 1917 1918 mutex_lock(&smu->mutex); 1919 1920 if (smu->ppt_funcs->load_microcode) 1921 ret = smu->ppt_funcs->load_microcode(smu); 1922 1923 mutex_unlock(&smu->mutex); 1924 1925 return ret; 1926 } 1927 1928 int smu_check_fw_status(struct smu_context *smu) 1929 { 1930 int ret = 0; 1931 1932 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1933 return -EOPNOTSUPP; 1934 1935 mutex_lock(&smu->mutex); 1936 1937 if (smu->ppt_funcs->check_fw_status) 1938 ret = smu->ppt_funcs->check_fw_status(smu); 1939 1940 mutex_unlock(&smu->mutex); 1941 1942 return ret; 1943 } 1944 1945 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 1946 { 1947 int ret = 0; 1948 1949 mutex_lock(&smu->mutex); 1950 1951 if (smu->ppt_funcs->set_gfx_cgpg) 1952 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 1953 1954 mutex_unlock(&smu->mutex); 1955 1956 return ret; 1957 } 1958 1959 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed) 1960 { 1961 int ret = 0; 1962 1963 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1964 return -EOPNOTSUPP; 1965 1966 mutex_lock(&smu->mutex); 1967 1968 if (smu->ppt_funcs->set_fan_speed_rpm) 1969 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed); 1970 1971 mutex_unlock(&smu->mutex); 1972 1973 return ret; 1974 } 1975 1976 int smu_get_power_limit(struct smu_context *smu, 1977 uint32_t *limit, 1978 bool max_setting) 1979 { 1980 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1981 return -EOPNOTSUPP; 1982 1983 mutex_lock(&smu->mutex); 1984 1985 *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit); 1986 1987 mutex_unlock(&smu->mutex); 1988 1989 return 0; 1990 } 1991 1992 int smu_set_power_limit(struct smu_context *smu, uint32_t limit) 1993 { 1994 int ret = 0; 1995 1996 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1997 return -EOPNOTSUPP; 1998 1999 mutex_lock(&smu->mutex); 2000 2001 if (limit > smu->max_power_limit) { 2002 dev_err(smu->adev->dev, 2003 "New power limit (%d) is over the max allowed %d\n", 2004 limit, smu->max_power_limit); 2005 goto out; 2006 } 2007 2008 if (!limit) 2009 limit = smu->current_power_limit; 2010 2011 if (smu->ppt_funcs->set_power_limit) 2012 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2013 2014 out: 2015 mutex_unlock(&smu->mutex); 2016 2017 return ret; 2018 } 2019 2020 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2021 { 2022 int ret = 0; 2023 2024 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2025 return -EOPNOTSUPP; 2026 2027 mutex_lock(&smu->mutex); 2028 2029 if (smu->ppt_funcs->print_clk_levels) 2030 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2031 2032 mutex_unlock(&smu->mutex); 2033 2034 return ret; 2035 } 2036 2037 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type) 2038 { 2039 int ret = 0; 2040 2041 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2042 return -EOPNOTSUPP; 2043 2044 mutex_lock(&smu->mutex); 2045 2046 if (smu->ppt_funcs->get_od_percentage) 2047 ret = smu->ppt_funcs->get_od_percentage(smu, type); 2048 2049 mutex_unlock(&smu->mutex); 2050 2051 return ret; 2052 } 2053 2054 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value) 2055 { 2056 int ret = 0; 2057 2058 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2059 return -EOPNOTSUPP; 2060 2061 mutex_lock(&smu->mutex); 2062 2063 if (smu->ppt_funcs->set_od_percentage) 2064 ret = smu->ppt_funcs->set_od_percentage(smu, type, value); 2065 2066 mutex_unlock(&smu->mutex); 2067 2068 return ret; 2069 } 2070 2071 int smu_od_edit_dpm_table(struct smu_context *smu, 2072 enum PP_OD_DPM_TABLE_COMMAND type, 2073 long *input, uint32_t size) 2074 { 2075 int ret = 0; 2076 2077 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2078 return -EOPNOTSUPP; 2079 2080 mutex_lock(&smu->mutex); 2081 2082 if (smu->ppt_funcs->od_edit_dpm_table) { 2083 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2084 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE)) 2085 ret = smu_handle_task(smu, 2086 smu->smu_dpm.dpm_level, 2087 AMD_PP_TASK_READJUST_POWER_STATE, 2088 false); 2089 } 2090 2091 mutex_unlock(&smu->mutex); 2092 2093 return ret; 2094 } 2095 2096 int smu_read_sensor(struct smu_context *smu, 2097 enum amd_pp_sensors sensor, 2098 void *data, uint32_t *size) 2099 { 2100 struct smu_umd_pstate_table *pstate_table = 2101 &smu->pstate_table; 2102 int ret = 0; 2103 2104 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2105 return -EOPNOTSUPP; 2106 2107 if (!data || !size) 2108 return -EINVAL; 2109 2110 mutex_lock(&smu->mutex); 2111 2112 if (smu->ppt_funcs->read_sensor) 2113 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2114 goto unlock; 2115 2116 switch (sensor) { 2117 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2118 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2119 *size = 4; 2120 break; 2121 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2122 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2123 *size = 4; 2124 break; 2125 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2126 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2127 *size = 8; 2128 break; 2129 case AMDGPU_PP_SENSOR_UVD_POWER: 2130 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2131 *size = 4; 2132 break; 2133 case AMDGPU_PP_SENSOR_VCE_POWER: 2134 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2135 *size = 4; 2136 break; 2137 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2138 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2139 *size = 4; 2140 break; 2141 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2142 *(uint32_t *)data = 0; 2143 *size = 4; 2144 break; 2145 default: 2146 *size = 0; 2147 ret = -EOPNOTSUPP; 2148 break; 2149 } 2150 2151 unlock: 2152 mutex_unlock(&smu->mutex); 2153 2154 return ret; 2155 } 2156 2157 int smu_get_power_profile_mode(struct smu_context *smu, char *buf) 2158 { 2159 int ret = 0; 2160 2161 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2162 return -EOPNOTSUPP; 2163 2164 mutex_lock(&smu->mutex); 2165 2166 if (smu->ppt_funcs->get_power_profile_mode) 2167 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2168 2169 mutex_unlock(&smu->mutex); 2170 2171 return ret; 2172 } 2173 2174 int smu_set_power_profile_mode(struct smu_context *smu, 2175 long *param, 2176 uint32_t param_size, 2177 bool lock_needed) 2178 { 2179 int ret = 0; 2180 2181 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2182 return -EOPNOTSUPP; 2183 2184 if (lock_needed) 2185 mutex_lock(&smu->mutex); 2186 2187 if (smu->ppt_funcs->set_power_profile_mode) 2188 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 2189 2190 if (lock_needed) 2191 mutex_unlock(&smu->mutex); 2192 2193 return ret; 2194 } 2195 2196 2197 int smu_get_fan_control_mode(struct smu_context *smu) 2198 { 2199 int ret = 0; 2200 2201 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2202 return -EOPNOTSUPP; 2203 2204 mutex_lock(&smu->mutex); 2205 2206 if (smu->ppt_funcs->get_fan_control_mode) 2207 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2208 2209 mutex_unlock(&smu->mutex); 2210 2211 return ret; 2212 } 2213 2214 int smu_set_fan_control_mode(struct smu_context *smu, int value) 2215 { 2216 int ret = 0; 2217 2218 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2219 return -EOPNOTSUPP; 2220 2221 mutex_lock(&smu->mutex); 2222 2223 if (smu->ppt_funcs->set_fan_control_mode) 2224 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2225 2226 mutex_unlock(&smu->mutex); 2227 2228 return ret; 2229 } 2230 2231 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed) 2232 { 2233 int ret = 0; 2234 uint32_t percent; 2235 uint32_t current_rpm; 2236 2237 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2238 return -EOPNOTSUPP; 2239 2240 mutex_lock(&smu->mutex); 2241 2242 if (smu->ppt_funcs->get_fan_speed_rpm) { 2243 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, ¤t_rpm); 2244 if (!ret) { 2245 percent = current_rpm * 100 / smu->fan_max_rpm; 2246 *speed = percent > 100 ? 100 : percent; 2247 } 2248 } 2249 2250 mutex_unlock(&smu->mutex); 2251 2252 2253 return ret; 2254 } 2255 2256 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) 2257 { 2258 int ret = 0; 2259 uint32_t rpm; 2260 2261 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2262 return -EOPNOTSUPP; 2263 2264 mutex_lock(&smu->mutex); 2265 2266 if (smu->ppt_funcs->set_fan_speed_rpm) { 2267 if (speed > 100) 2268 speed = 100; 2269 rpm = speed * smu->fan_max_rpm / 100; 2270 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, rpm); 2271 } 2272 2273 mutex_unlock(&smu->mutex); 2274 2275 return ret; 2276 } 2277 2278 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed) 2279 { 2280 int ret = 0; 2281 2282 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2283 return -EOPNOTSUPP; 2284 2285 mutex_lock(&smu->mutex); 2286 2287 if (smu->ppt_funcs->get_fan_speed_rpm) 2288 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed); 2289 2290 mutex_unlock(&smu->mutex); 2291 2292 return ret; 2293 } 2294 2295 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk) 2296 { 2297 int ret = 0; 2298 2299 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2300 return -EOPNOTSUPP; 2301 2302 mutex_lock(&smu->mutex); 2303 2304 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2305 2306 mutex_unlock(&smu->mutex); 2307 2308 return ret; 2309 } 2310 2311 int smu_get_clock_by_type(struct smu_context *smu, 2312 enum amd_pp_clock_type type, 2313 struct amd_pp_clocks *clocks) 2314 { 2315 int ret = 0; 2316 2317 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2318 return -EOPNOTSUPP; 2319 2320 mutex_lock(&smu->mutex); 2321 2322 if (smu->ppt_funcs->get_clock_by_type) 2323 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks); 2324 2325 mutex_unlock(&smu->mutex); 2326 2327 return ret; 2328 } 2329 2330 int smu_get_max_high_clocks(struct smu_context *smu, 2331 struct amd_pp_simple_clock_info *clocks) 2332 { 2333 int ret = 0; 2334 2335 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2336 return -EOPNOTSUPP; 2337 2338 mutex_lock(&smu->mutex); 2339 2340 if (smu->ppt_funcs->get_max_high_clocks) 2341 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks); 2342 2343 mutex_unlock(&smu->mutex); 2344 2345 return ret; 2346 } 2347 2348 int smu_get_clock_by_type_with_latency(struct smu_context *smu, 2349 enum smu_clk_type clk_type, 2350 struct pp_clock_levels_with_latency *clocks) 2351 { 2352 int ret = 0; 2353 2354 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2355 return -EOPNOTSUPP; 2356 2357 mutex_lock(&smu->mutex); 2358 2359 if (smu->ppt_funcs->get_clock_by_type_with_latency) 2360 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2361 2362 mutex_unlock(&smu->mutex); 2363 2364 return ret; 2365 } 2366 2367 int smu_get_clock_by_type_with_voltage(struct smu_context *smu, 2368 enum amd_pp_clock_type type, 2369 struct pp_clock_levels_with_voltage *clocks) 2370 { 2371 int ret = 0; 2372 2373 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2374 return -EOPNOTSUPP; 2375 2376 mutex_lock(&smu->mutex); 2377 2378 if (smu->ppt_funcs->get_clock_by_type_with_voltage) 2379 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks); 2380 2381 mutex_unlock(&smu->mutex); 2382 2383 return ret; 2384 } 2385 2386 2387 int smu_display_clock_voltage_request(struct smu_context *smu, 2388 struct pp_display_clock_request *clock_req) 2389 { 2390 int ret = 0; 2391 2392 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2393 return -EOPNOTSUPP; 2394 2395 mutex_lock(&smu->mutex); 2396 2397 if (smu->ppt_funcs->display_clock_voltage_request) 2398 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2399 2400 mutex_unlock(&smu->mutex); 2401 2402 return ret; 2403 } 2404 2405 2406 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch) 2407 { 2408 int ret = -EINVAL; 2409 2410 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2411 return -EOPNOTSUPP; 2412 2413 mutex_lock(&smu->mutex); 2414 2415 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2416 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2417 2418 mutex_unlock(&smu->mutex); 2419 2420 return ret; 2421 } 2422 2423 int smu_notify_smu_enable_pwe(struct smu_context *smu) 2424 { 2425 int ret = 0; 2426 2427 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2428 return -EOPNOTSUPP; 2429 2430 mutex_lock(&smu->mutex); 2431 2432 if (smu->ppt_funcs->notify_smu_enable_pwe) 2433 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu); 2434 2435 mutex_unlock(&smu->mutex); 2436 2437 return ret; 2438 } 2439 2440 int smu_set_xgmi_pstate(struct smu_context *smu, 2441 uint32_t pstate) 2442 { 2443 int ret = 0; 2444 2445 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2446 return -EOPNOTSUPP; 2447 2448 mutex_lock(&smu->mutex); 2449 2450 if (smu->ppt_funcs->set_xgmi_pstate) 2451 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2452 2453 mutex_unlock(&smu->mutex); 2454 2455 if(ret) 2456 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2457 2458 return ret; 2459 } 2460 2461 int smu_set_azalia_d3_pme(struct smu_context *smu) 2462 { 2463 int ret = 0; 2464 2465 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2466 return -EOPNOTSUPP; 2467 2468 mutex_lock(&smu->mutex); 2469 2470 if (smu->ppt_funcs->set_azalia_d3_pme) 2471 ret = smu->ppt_funcs->set_azalia_d3_pme(smu); 2472 2473 mutex_unlock(&smu->mutex); 2474 2475 return ret; 2476 } 2477 2478 /* 2479 * On system suspending or resetting, the dpm_enabled 2480 * flag will be cleared. So that those SMU services which 2481 * are not supported will be gated. 2482 * 2483 * However, the baco/mode1 reset should still be granted 2484 * as they are still supported and necessary. 2485 */ 2486 bool smu_baco_is_support(struct smu_context *smu) 2487 { 2488 bool ret = false; 2489 2490 if (!smu->pm_enabled) 2491 return false; 2492 2493 mutex_lock(&smu->mutex); 2494 2495 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2496 ret = smu->ppt_funcs->baco_is_support(smu); 2497 2498 mutex_unlock(&smu->mutex); 2499 2500 return ret; 2501 } 2502 2503 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state) 2504 { 2505 if (smu->ppt_funcs->baco_get_state) 2506 return -EINVAL; 2507 2508 mutex_lock(&smu->mutex); 2509 *state = smu->ppt_funcs->baco_get_state(smu); 2510 mutex_unlock(&smu->mutex); 2511 2512 return 0; 2513 } 2514 2515 int smu_baco_enter(struct smu_context *smu) 2516 { 2517 int ret = 0; 2518 2519 if (!smu->pm_enabled) 2520 return -EOPNOTSUPP; 2521 2522 mutex_lock(&smu->mutex); 2523 2524 if (smu->ppt_funcs->baco_enter) 2525 ret = smu->ppt_funcs->baco_enter(smu); 2526 2527 mutex_unlock(&smu->mutex); 2528 2529 if (ret) 2530 dev_err(smu->adev->dev, "Failed to enter BACO state!\n"); 2531 2532 return ret; 2533 } 2534 2535 int smu_baco_exit(struct smu_context *smu) 2536 { 2537 int ret = 0; 2538 2539 if (!smu->pm_enabled) 2540 return -EOPNOTSUPP; 2541 2542 mutex_lock(&smu->mutex); 2543 2544 if (smu->ppt_funcs->baco_exit) 2545 ret = smu->ppt_funcs->baco_exit(smu); 2546 2547 mutex_unlock(&smu->mutex); 2548 2549 if (ret) 2550 dev_err(smu->adev->dev, "Failed to exit BACO state!\n"); 2551 2552 return ret; 2553 } 2554 2555 bool smu_mode1_reset_is_support(struct smu_context *smu) 2556 { 2557 bool ret = false; 2558 2559 if (!smu->pm_enabled) 2560 return false; 2561 2562 mutex_lock(&smu->mutex); 2563 2564 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2565 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2566 2567 mutex_unlock(&smu->mutex); 2568 2569 return ret; 2570 } 2571 2572 int smu_mode1_reset(struct smu_context *smu) 2573 { 2574 int ret = 0; 2575 2576 if (!smu->pm_enabled) 2577 return -EOPNOTSUPP; 2578 2579 mutex_lock(&smu->mutex); 2580 2581 if (smu->ppt_funcs->mode1_reset) 2582 ret = smu->ppt_funcs->mode1_reset(smu); 2583 2584 mutex_unlock(&smu->mutex); 2585 2586 return ret; 2587 } 2588 2589 int smu_mode2_reset(struct smu_context *smu) 2590 { 2591 int ret = 0; 2592 2593 if (!smu->pm_enabled) 2594 return -EOPNOTSUPP; 2595 2596 mutex_lock(&smu->mutex); 2597 2598 if (smu->ppt_funcs->mode2_reset) 2599 ret = smu->ppt_funcs->mode2_reset(smu); 2600 2601 mutex_unlock(&smu->mutex); 2602 2603 if (ret) 2604 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2605 2606 return ret; 2607 } 2608 2609 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu, 2610 struct pp_smu_nv_clock_table *max_clocks) 2611 { 2612 int ret = 0; 2613 2614 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2615 return -EOPNOTSUPP; 2616 2617 mutex_lock(&smu->mutex); 2618 2619 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2620 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2621 2622 mutex_unlock(&smu->mutex); 2623 2624 return ret; 2625 } 2626 2627 int smu_get_uclk_dpm_states(struct smu_context *smu, 2628 unsigned int *clock_values_in_khz, 2629 unsigned int *num_states) 2630 { 2631 int ret = 0; 2632 2633 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2634 return -EOPNOTSUPP; 2635 2636 mutex_lock(&smu->mutex); 2637 2638 if (smu->ppt_funcs->get_uclk_dpm_states) 2639 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2640 2641 mutex_unlock(&smu->mutex); 2642 2643 return ret; 2644 } 2645 2646 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu) 2647 { 2648 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2649 2650 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2651 return -EOPNOTSUPP; 2652 2653 mutex_lock(&smu->mutex); 2654 2655 if (smu->ppt_funcs->get_current_power_state) 2656 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2657 2658 mutex_unlock(&smu->mutex); 2659 2660 return pm_state; 2661 } 2662 2663 int smu_get_dpm_clock_table(struct smu_context *smu, 2664 struct dpm_clocks *clock_table) 2665 { 2666 int ret = 0; 2667 2668 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2669 return -EOPNOTSUPP; 2670 2671 mutex_lock(&smu->mutex); 2672 2673 if (smu->ppt_funcs->get_dpm_clock_table) 2674 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2675 2676 mutex_unlock(&smu->mutex); 2677 2678 return ret; 2679 } 2680 2681 ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, 2682 void **table) 2683 { 2684 ssize_t size; 2685 2686 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2687 return -EOPNOTSUPP; 2688 2689 if (!smu->ppt_funcs->get_gpu_metrics) 2690 return -EOPNOTSUPP; 2691 2692 mutex_lock(&smu->mutex); 2693 2694 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2695 2696 mutex_unlock(&smu->mutex); 2697 2698 return size; 2699 } 2700 2701 int smu_enable_mgpu_fan_boost(struct smu_context *smu) 2702 { 2703 int ret = 0; 2704 2705 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2706 return -EOPNOTSUPP; 2707 2708 mutex_lock(&smu->mutex); 2709 2710 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2711 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2712 2713 mutex_unlock(&smu->mutex); 2714 2715 return ret; 2716 } 2717