1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define SWSMU_CODE_LAYER_L1 24 25 #include <linux/firmware.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_smu.h" 30 #include "smu_internal.h" 31 #include "atom.h" 32 #include "arcturus_ppt.h" 33 #include "navi10_ppt.h" 34 #include "sienna_cichlid_ppt.h" 35 #include "renoir_ppt.h" 36 #include "vangogh_ppt.h" 37 #include "aldebaran_ppt.h" 38 #include "yellow_carp_ppt.h" 39 #include "amd_pcie.h" 40 41 /* 42 * DO NOT use these for err/warn/info/debug messages. 43 * Use dev_err, dev_warn, dev_info and dev_dbg instead. 44 * They are more MGPU friendly. 45 */ 46 #undef pr_err 47 #undef pr_warn 48 #undef pr_info 49 #undef pr_debug 50 51 static const struct amd_pm_funcs swsmu_pm_funcs; 52 static int smu_force_smuclk_levels(struct smu_context *smu, 53 enum smu_clk_type clk_type, 54 uint32_t mask); 55 static int smu_handle_task(struct smu_context *smu, 56 enum amd_dpm_forced_level level, 57 enum amd_pp_task task_id, 58 bool lock_needed); 59 static int smu_reset(struct smu_context *smu); 60 static int smu_set_fan_speed_percent(void *handle, u32 speed); 61 static int smu_set_fan_control_mode(struct smu_context *smu, int value); 62 static int smu_set_power_limit(void *handle, uint32_t limit); 63 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed); 64 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled); 65 66 static int smu_sys_get_pp_feature_mask(void *handle, 67 char *buf) 68 { 69 struct smu_context *smu = handle; 70 int size = 0; 71 72 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 73 return -EOPNOTSUPP; 74 75 mutex_lock(&smu->mutex); 76 77 size = smu_get_pp_feature_mask(smu, buf); 78 79 mutex_unlock(&smu->mutex); 80 81 return size; 82 } 83 84 static int smu_sys_set_pp_feature_mask(void *handle, 85 uint64_t new_mask) 86 { 87 struct smu_context *smu = handle; 88 int ret = 0; 89 90 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 91 return -EOPNOTSUPP; 92 93 mutex_lock(&smu->mutex); 94 95 ret = smu_set_pp_feature_mask(smu, new_mask); 96 97 mutex_unlock(&smu->mutex); 98 99 return ret; 100 } 101 102 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) 103 { 104 int ret = 0; 105 struct smu_context *smu = &adev->smu; 106 107 if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status) 108 *value = smu_get_gfx_off_status(smu); 109 else 110 ret = -EINVAL; 111 112 return ret; 113 } 114 115 int smu_set_soft_freq_range(struct smu_context *smu, 116 enum smu_clk_type clk_type, 117 uint32_t min, 118 uint32_t max) 119 { 120 int ret = 0; 121 122 mutex_lock(&smu->mutex); 123 124 if (smu->ppt_funcs->set_soft_freq_limited_range) 125 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu, 126 clk_type, 127 min, 128 max); 129 130 mutex_unlock(&smu->mutex); 131 132 return ret; 133 } 134 135 int smu_get_dpm_freq_range(struct smu_context *smu, 136 enum smu_clk_type clk_type, 137 uint32_t *min, 138 uint32_t *max) 139 { 140 int ret = 0; 141 142 if (!min && !max) 143 return -EINVAL; 144 145 mutex_lock(&smu->mutex); 146 147 if (smu->ppt_funcs->get_dpm_ultimate_freq) 148 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu, 149 clk_type, 150 min, 151 max); 152 153 mutex_unlock(&smu->mutex); 154 155 return ret; 156 } 157 158 static u32 smu_get_mclk(void *handle, bool low) 159 { 160 struct smu_context *smu = handle; 161 uint32_t clk_freq; 162 int ret = 0; 163 164 ret = smu_get_dpm_freq_range(smu, SMU_UCLK, 165 low ? &clk_freq : NULL, 166 !low ? &clk_freq : NULL); 167 if (ret) 168 return 0; 169 return clk_freq * 100; 170 } 171 172 static u32 smu_get_sclk(void *handle, bool low) 173 { 174 struct smu_context *smu = handle; 175 uint32_t clk_freq; 176 int ret = 0; 177 178 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK, 179 low ? &clk_freq : NULL, 180 !low ? &clk_freq : NULL); 181 if (ret) 182 return 0; 183 return clk_freq * 100; 184 } 185 186 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu, 187 bool enable) 188 { 189 struct smu_power_context *smu_power = &smu->smu_power; 190 struct smu_power_gate *power_gate = &smu_power->power_gate; 191 int ret = 0; 192 193 if (!smu->ppt_funcs->dpm_set_vcn_enable) 194 return 0; 195 196 if (atomic_read(&power_gate->vcn_gated) ^ enable) 197 return 0; 198 199 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable); 200 if (!ret) 201 atomic_set(&power_gate->vcn_gated, !enable); 202 203 return ret; 204 } 205 206 static int smu_dpm_set_vcn_enable(struct smu_context *smu, 207 bool enable) 208 { 209 struct smu_power_context *smu_power = &smu->smu_power; 210 struct smu_power_gate *power_gate = &smu_power->power_gate; 211 int ret = 0; 212 213 mutex_lock(&power_gate->vcn_gate_lock); 214 215 ret = smu_dpm_set_vcn_enable_locked(smu, enable); 216 217 mutex_unlock(&power_gate->vcn_gate_lock); 218 219 return ret; 220 } 221 222 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu, 223 bool enable) 224 { 225 struct smu_power_context *smu_power = &smu->smu_power; 226 struct smu_power_gate *power_gate = &smu_power->power_gate; 227 int ret = 0; 228 229 if (!smu->ppt_funcs->dpm_set_jpeg_enable) 230 return 0; 231 232 if (atomic_read(&power_gate->jpeg_gated) ^ enable) 233 return 0; 234 235 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable); 236 if (!ret) 237 atomic_set(&power_gate->jpeg_gated, !enable); 238 239 return ret; 240 } 241 242 static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 243 bool enable) 244 { 245 struct smu_power_context *smu_power = &smu->smu_power; 246 struct smu_power_gate *power_gate = &smu_power->power_gate; 247 int ret = 0; 248 249 mutex_lock(&power_gate->jpeg_gate_lock); 250 251 ret = smu_dpm_set_jpeg_enable_locked(smu, enable); 252 253 mutex_unlock(&power_gate->jpeg_gate_lock); 254 255 return ret; 256 } 257 258 /** 259 * smu_dpm_set_power_gate - power gate/ungate the specific IP block 260 * 261 * @handle: smu_context pointer 262 * @block_type: the IP block to power gate/ungate 263 * @gate: to power gate if true, ungate otherwise 264 * 265 * This API uses no smu->mutex lock protection due to: 266 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce). 267 * This is guarded to be race condition free by the caller. 268 * 2. Or get called on user setting request of power_dpm_force_performance_level. 269 * Under this case, the smu->mutex lock protection is already enforced on 270 * the parent API smu_force_performance_level of the call path. 271 */ 272 static int smu_dpm_set_power_gate(void *handle, 273 uint32_t block_type, 274 bool gate) 275 { 276 struct smu_context *smu = handle; 277 int ret = 0; 278 279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 280 return -EOPNOTSUPP; 281 282 switch (block_type) { 283 /* 284 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses 285 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept. 286 */ 287 case AMD_IP_BLOCK_TYPE_UVD: 288 case AMD_IP_BLOCK_TYPE_VCN: 289 ret = smu_dpm_set_vcn_enable(smu, !gate); 290 if (ret) 291 dev_err(smu->adev->dev, "Failed to power %s VCN!\n", 292 gate ? "gate" : "ungate"); 293 break; 294 case AMD_IP_BLOCK_TYPE_GFX: 295 ret = smu_gfx_off_control(smu, gate); 296 if (ret) 297 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n", 298 gate ? "enable" : "disable"); 299 break; 300 case AMD_IP_BLOCK_TYPE_SDMA: 301 ret = smu_powergate_sdma(smu, gate); 302 if (ret) 303 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n", 304 gate ? "gate" : "ungate"); 305 break; 306 case AMD_IP_BLOCK_TYPE_JPEG: 307 ret = smu_dpm_set_jpeg_enable(smu, !gate); 308 if (ret) 309 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n", 310 gate ? "gate" : "ungate"); 311 break; 312 default: 313 dev_err(smu->adev->dev, "Unsupported block type!\n"); 314 return -EINVAL; 315 } 316 317 return ret; 318 } 319 320 /** 321 * smu_set_user_clk_dependencies - set user profile clock dependencies 322 * 323 * @smu: smu_context pointer 324 * @clk: enum smu_clk_type type 325 * 326 * Enable/Disable the clock dependency for the @clk type. 327 */ 328 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk) 329 { 330 if (smu->adev->in_suspend) 331 return; 332 333 if (clk == SMU_MCLK) { 334 smu->user_dpm_profile.clk_dependency = 0; 335 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK); 336 } else if (clk == SMU_FCLK) { 337 /* MCLK takes precedence over FCLK */ 338 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 339 return; 340 341 smu->user_dpm_profile.clk_dependency = 0; 342 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK); 343 } else if (clk == SMU_SOCCLK) { 344 /* MCLK takes precedence over SOCCLK */ 345 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK))) 346 return; 347 348 smu->user_dpm_profile.clk_dependency = 0; 349 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK); 350 } else 351 /* Add clk dependencies here, if any */ 352 return; 353 } 354 355 /** 356 * smu_restore_dpm_user_profile - reinstate user dpm profile 357 * 358 * @smu: smu_context pointer 359 * 360 * Restore the saved user power configurations include power limit, 361 * clock frequencies, fan control mode and fan speed. 362 */ 363 static void smu_restore_dpm_user_profile(struct smu_context *smu) 364 { 365 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 366 int ret = 0; 367 368 if (!smu->adev->in_suspend) 369 return; 370 371 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 372 return; 373 374 /* Enable restore flag */ 375 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE; 376 377 /* set the user dpm power limit */ 378 if (smu->user_dpm_profile.power_limit) { 379 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit); 380 if (ret) 381 dev_err(smu->adev->dev, "Failed to set power limit value\n"); 382 } 383 384 /* set the user dpm clock configurations */ 385 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { 386 enum smu_clk_type clk_type; 387 388 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { 389 /* 390 * Iterate over smu clk type and force the saved user clk 391 * configs, skip if clock dependency is enabled 392 */ 393 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) && 394 smu->user_dpm_profile.clk_mask[clk_type]) { 395 ret = smu_force_smuclk_levels(smu, clk_type, 396 smu->user_dpm_profile.clk_mask[clk_type]); 397 if (ret) 398 dev_err(smu->adev->dev, 399 "Failed to set clock type = %d\n", clk_type); 400 } 401 } 402 } 403 404 /* set the user dpm fan configurations */ 405 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL) { 406 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode); 407 if (ret) { 408 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n"); 409 return; 410 } 411 412 if (!ret && smu->user_dpm_profile.fan_speed_percent) { 413 ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent); 414 if (ret) 415 dev_err(smu->adev->dev, "Failed to set manual fan speed\n"); 416 } 417 } 418 419 /* Disable restore flag */ 420 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE; 421 } 422 423 static int smu_get_power_num_states(void *handle, 424 struct pp_states_info *state_info) 425 { 426 if (!state_info) 427 return -EINVAL; 428 429 /* not support power state */ 430 memset(state_info, 0, sizeof(struct pp_states_info)); 431 state_info->nums = 1; 432 state_info->states[0] = POWER_STATE_TYPE_DEFAULT; 433 434 return 0; 435 } 436 437 bool is_support_sw_smu(struct amdgpu_device *adev) 438 { 439 if (adev->asic_type >= CHIP_ARCTURUS) 440 return true; 441 442 return false; 443 } 444 445 bool is_support_cclk_dpm(struct amdgpu_device *adev) 446 { 447 struct smu_context *smu = &adev->smu; 448 449 if (!is_support_sw_smu(adev)) 450 return false; 451 452 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT)) 453 return false; 454 455 return true; 456 } 457 458 459 static int smu_sys_get_pp_table(void *handle, 460 char **table) 461 { 462 struct smu_context *smu = handle; 463 struct smu_table_context *smu_table = &smu->smu_table; 464 uint32_t powerplay_table_size; 465 466 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 467 return -EOPNOTSUPP; 468 469 if (!smu_table->power_play_table && !smu_table->hardcode_pptable) 470 return -EINVAL; 471 472 mutex_lock(&smu->mutex); 473 474 if (smu_table->hardcode_pptable) 475 *table = smu_table->hardcode_pptable; 476 else 477 *table = smu_table->power_play_table; 478 479 powerplay_table_size = smu_table->power_play_table_size; 480 481 mutex_unlock(&smu->mutex); 482 483 return powerplay_table_size; 484 } 485 486 static int smu_sys_set_pp_table(void *handle, 487 const char *buf, 488 size_t size) 489 { 490 struct smu_context *smu = handle; 491 struct smu_table_context *smu_table = &smu->smu_table; 492 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf; 493 int ret = 0; 494 495 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 496 return -EOPNOTSUPP; 497 498 if (header->usStructureSize != size) { 499 dev_err(smu->adev->dev, "pp table size not matched !\n"); 500 return -EIO; 501 } 502 503 mutex_lock(&smu->mutex); 504 if (!smu_table->hardcode_pptable) 505 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL); 506 if (!smu_table->hardcode_pptable) { 507 ret = -ENOMEM; 508 goto failed; 509 } 510 511 memcpy(smu_table->hardcode_pptable, buf, size); 512 smu_table->power_play_table = smu_table->hardcode_pptable; 513 smu_table->power_play_table_size = size; 514 515 /* 516 * Special hw_fini action(for Navi1x, the DPMs disablement will be 517 * skipped) may be needed for custom pptable uploading. 518 */ 519 smu->uploading_custom_pp_table = true; 520 521 ret = smu_reset(smu); 522 if (ret) 523 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret); 524 525 smu->uploading_custom_pp_table = false; 526 527 failed: 528 mutex_unlock(&smu->mutex); 529 return ret; 530 } 531 532 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) 533 { 534 struct smu_feature *feature = &smu->smu_feature; 535 int ret = 0; 536 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; 537 538 bitmap_zero(feature->allowed, SMU_FEATURE_MAX); 539 540 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, 541 SMU_FEATURE_MAX/32); 542 if (ret) 543 return ret; 544 545 bitmap_or(feature->allowed, feature->allowed, 546 (unsigned long *)allowed_feature_mask, 547 feature->feature_num); 548 549 return ret; 550 } 551 552 static int smu_set_funcs(struct amdgpu_device *adev) 553 { 554 struct smu_context *smu = &adev->smu; 555 556 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK) 557 smu->od_enabled = true; 558 559 switch (adev->asic_type) { 560 case CHIP_NAVI10: 561 case CHIP_NAVI14: 562 case CHIP_NAVI12: 563 navi10_set_ppt_funcs(smu); 564 break; 565 case CHIP_ARCTURUS: 566 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 567 arcturus_set_ppt_funcs(smu); 568 /* OD is not supported on Arcturus */ 569 smu->od_enabled =false; 570 break; 571 case CHIP_SIENNA_CICHLID: 572 case CHIP_NAVY_FLOUNDER: 573 case CHIP_DIMGREY_CAVEFISH: 574 case CHIP_BEIGE_GOBY: 575 sienna_cichlid_set_ppt_funcs(smu); 576 break; 577 case CHIP_ALDEBARAN: 578 aldebaran_set_ppt_funcs(smu); 579 /* Enable pp_od_clk_voltage node */ 580 smu->od_enabled = true; 581 break; 582 case CHIP_RENOIR: 583 renoir_set_ppt_funcs(smu); 584 break; 585 case CHIP_VANGOGH: 586 vangogh_set_ppt_funcs(smu); 587 break; 588 case CHIP_YELLOW_CARP: 589 yellow_carp_set_ppt_funcs(smu); 590 break; 591 default: 592 return -EINVAL; 593 } 594 595 return 0; 596 } 597 598 static int smu_early_init(void *handle) 599 { 600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 601 struct smu_context *smu = &adev->smu; 602 603 smu->adev = adev; 604 smu->pm_enabled = !!amdgpu_dpm; 605 smu->is_apu = false; 606 mutex_init(&smu->mutex); 607 mutex_init(&smu->smu_baco.mutex); 608 smu->smu_baco.state = SMU_BACO_STATE_EXIT; 609 smu->smu_baco.platform_support = false; 610 611 adev->powerplay.pp_handle = smu; 612 adev->powerplay.pp_funcs = &swsmu_pm_funcs; 613 614 return smu_set_funcs(adev); 615 } 616 617 static int smu_set_default_dpm_table(struct smu_context *smu) 618 { 619 struct smu_power_context *smu_power = &smu->smu_power; 620 struct smu_power_gate *power_gate = &smu_power->power_gate; 621 int vcn_gate, jpeg_gate; 622 int ret = 0; 623 624 if (!smu->ppt_funcs->set_default_dpm_table) 625 return 0; 626 627 mutex_lock(&power_gate->vcn_gate_lock); 628 mutex_lock(&power_gate->jpeg_gate_lock); 629 630 vcn_gate = atomic_read(&power_gate->vcn_gated); 631 jpeg_gate = atomic_read(&power_gate->jpeg_gated); 632 633 ret = smu_dpm_set_vcn_enable_locked(smu, true); 634 if (ret) 635 goto err0_out; 636 637 ret = smu_dpm_set_jpeg_enable_locked(smu, true); 638 if (ret) 639 goto err1_out; 640 641 ret = smu->ppt_funcs->set_default_dpm_table(smu); 642 if (ret) 643 dev_err(smu->adev->dev, 644 "Failed to setup default dpm clock tables!\n"); 645 646 smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate); 647 err1_out: 648 smu_dpm_set_vcn_enable_locked(smu, !vcn_gate); 649 err0_out: 650 mutex_unlock(&power_gate->jpeg_gate_lock); 651 mutex_unlock(&power_gate->vcn_gate_lock); 652 653 return ret; 654 } 655 656 657 static int smu_late_init(void *handle) 658 { 659 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 660 struct smu_context *smu = &adev->smu; 661 int ret = 0; 662 663 smu_set_fine_grain_gfx_freq_parameters(smu); 664 665 if (!smu->pm_enabled) 666 return 0; 667 668 ret = smu_post_init(smu); 669 if (ret) { 670 dev_err(adev->dev, "Failed to post smu init!\n"); 671 return ret; 672 } 673 674 if (adev->asic_type == CHIP_YELLOW_CARP) 675 return 0; 676 677 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) { 678 ret = smu_set_default_od_settings(smu); 679 if (ret) { 680 dev_err(adev->dev, "Failed to setup default OD settings!\n"); 681 return ret; 682 } 683 } 684 685 ret = smu_populate_umd_state_clk(smu); 686 if (ret) { 687 dev_err(adev->dev, "Failed to populate UMD state clocks!\n"); 688 return ret; 689 } 690 691 ret = smu_get_asic_power_limits(smu, 692 &smu->current_power_limit, 693 &smu->default_power_limit, 694 &smu->max_power_limit); 695 if (ret) { 696 dev_err(adev->dev, "Failed to get asic power limits!\n"); 697 return ret; 698 } 699 700 if (!amdgpu_sriov_vf(adev)) 701 smu_get_unique_id(smu); 702 703 smu_get_fan_parameters(smu); 704 705 smu_handle_task(&adev->smu, 706 smu->smu_dpm.dpm_level, 707 AMD_PP_TASK_COMPLETE_INIT, 708 false); 709 710 smu_restore_dpm_user_profile(smu); 711 712 return 0; 713 } 714 715 static int smu_init_fb_allocations(struct smu_context *smu) 716 { 717 struct amdgpu_device *adev = smu->adev; 718 struct smu_table_context *smu_table = &smu->smu_table; 719 struct smu_table *tables = smu_table->tables; 720 struct smu_table *driver_table = &(smu_table->driver_table); 721 uint32_t max_table_size = 0; 722 int ret, i; 723 724 /* VRAM allocation for tool table */ 725 if (tables[SMU_TABLE_PMSTATUSLOG].size) { 726 ret = amdgpu_bo_create_kernel(adev, 727 tables[SMU_TABLE_PMSTATUSLOG].size, 728 tables[SMU_TABLE_PMSTATUSLOG].align, 729 tables[SMU_TABLE_PMSTATUSLOG].domain, 730 &tables[SMU_TABLE_PMSTATUSLOG].bo, 731 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 732 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 733 if (ret) { 734 dev_err(adev->dev, "VRAM allocation for tool table failed!\n"); 735 return ret; 736 } 737 } 738 739 /* VRAM allocation for driver table */ 740 for (i = 0; i < SMU_TABLE_COUNT; i++) { 741 if (tables[i].size == 0) 742 continue; 743 744 if (i == SMU_TABLE_PMSTATUSLOG) 745 continue; 746 747 if (max_table_size < tables[i].size) 748 max_table_size = tables[i].size; 749 } 750 751 driver_table->size = max_table_size; 752 driver_table->align = PAGE_SIZE; 753 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 754 755 ret = amdgpu_bo_create_kernel(adev, 756 driver_table->size, 757 driver_table->align, 758 driver_table->domain, 759 &driver_table->bo, 760 &driver_table->mc_address, 761 &driver_table->cpu_addr); 762 if (ret) { 763 dev_err(adev->dev, "VRAM allocation for driver table failed!\n"); 764 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 765 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 766 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 767 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 768 } 769 770 return ret; 771 } 772 773 static int smu_fini_fb_allocations(struct smu_context *smu) 774 { 775 struct smu_table_context *smu_table = &smu->smu_table; 776 struct smu_table *tables = smu_table->tables; 777 struct smu_table *driver_table = &(smu_table->driver_table); 778 779 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address) 780 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo, 781 &tables[SMU_TABLE_PMSTATUSLOG].mc_address, 782 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr); 783 784 amdgpu_bo_free_kernel(&driver_table->bo, 785 &driver_table->mc_address, 786 &driver_table->cpu_addr); 787 788 return 0; 789 } 790 791 /** 792 * smu_alloc_memory_pool - allocate memory pool in the system memory 793 * 794 * @smu: amdgpu_device pointer 795 * 796 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr 797 * and DramLogSetDramAddr can notify it changed. 798 * 799 * Returns 0 on success, error on failure. 800 */ 801 static int smu_alloc_memory_pool(struct smu_context *smu) 802 { 803 struct amdgpu_device *adev = smu->adev; 804 struct smu_table_context *smu_table = &smu->smu_table; 805 struct smu_table *memory_pool = &smu_table->memory_pool; 806 uint64_t pool_size = smu->pool_size; 807 int ret = 0; 808 809 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO) 810 return ret; 811 812 memory_pool->size = pool_size; 813 memory_pool->align = PAGE_SIZE; 814 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT; 815 816 switch (pool_size) { 817 case SMU_MEMORY_POOL_SIZE_256_MB: 818 case SMU_MEMORY_POOL_SIZE_512_MB: 819 case SMU_MEMORY_POOL_SIZE_1_GB: 820 case SMU_MEMORY_POOL_SIZE_2_GB: 821 ret = amdgpu_bo_create_kernel(adev, 822 memory_pool->size, 823 memory_pool->align, 824 memory_pool->domain, 825 &memory_pool->bo, 826 &memory_pool->mc_address, 827 &memory_pool->cpu_addr); 828 if (ret) 829 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n"); 830 break; 831 default: 832 break; 833 } 834 835 return ret; 836 } 837 838 static int smu_free_memory_pool(struct smu_context *smu) 839 { 840 struct smu_table_context *smu_table = &smu->smu_table; 841 struct smu_table *memory_pool = &smu_table->memory_pool; 842 843 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO) 844 return 0; 845 846 amdgpu_bo_free_kernel(&memory_pool->bo, 847 &memory_pool->mc_address, 848 &memory_pool->cpu_addr); 849 850 memset(memory_pool, 0, sizeof(struct smu_table)); 851 852 return 0; 853 } 854 855 static int smu_alloc_dummy_read_table(struct smu_context *smu) 856 { 857 struct smu_table_context *smu_table = &smu->smu_table; 858 struct smu_table *dummy_read_1_table = 859 &smu_table->dummy_read_1_table; 860 struct amdgpu_device *adev = smu->adev; 861 int ret = 0; 862 863 dummy_read_1_table->size = 0x40000; 864 dummy_read_1_table->align = PAGE_SIZE; 865 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM; 866 867 ret = amdgpu_bo_create_kernel(adev, 868 dummy_read_1_table->size, 869 dummy_read_1_table->align, 870 dummy_read_1_table->domain, 871 &dummy_read_1_table->bo, 872 &dummy_read_1_table->mc_address, 873 &dummy_read_1_table->cpu_addr); 874 if (ret) 875 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n"); 876 877 return ret; 878 } 879 880 static void smu_free_dummy_read_table(struct smu_context *smu) 881 { 882 struct smu_table_context *smu_table = &smu->smu_table; 883 struct smu_table *dummy_read_1_table = 884 &smu_table->dummy_read_1_table; 885 886 887 amdgpu_bo_free_kernel(&dummy_read_1_table->bo, 888 &dummy_read_1_table->mc_address, 889 &dummy_read_1_table->cpu_addr); 890 891 memset(dummy_read_1_table, 0, sizeof(struct smu_table)); 892 } 893 894 static int smu_smc_table_sw_init(struct smu_context *smu) 895 { 896 int ret; 897 898 /** 899 * Create smu_table structure, and init smc tables such as 900 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc. 901 */ 902 ret = smu_init_smc_tables(smu); 903 if (ret) { 904 dev_err(smu->adev->dev, "Failed to init smc tables!\n"); 905 return ret; 906 } 907 908 /** 909 * Create smu_power_context structure, and allocate smu_dpm_context and 910 * context size to fill the smu_power_context data. 911 */ 912 ret = smu_init_power(smu); 913 if (ret) { 914 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n"); 915 return ret; 916 } 917 918 /* 919 * allocate vram bos to store smc table contents. 920 */ 921 ret = smu_init_fb_allocations(smu); 922 if (ret) 923 return ret; 924 925 ret = smu_alloc_memory_pool(smu); 926 if (ret) 927 return ret; 928 929 ret = smu_alloc_dummy_read_table(smu); 930 if (ret) 931 return ret; 932 933 ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c); 934 if (ret) 935 return ret; 936 937 return 0; 938 } 939 940 static int smu_smc_table_sw_fini(struct smu_context *smu) 941 { 942 int ret; 943 944 smu_i2c_fini(smu, &smu->adev->pm.smu_i2c); 945 946 smu_free_dummy_read_table(smu); 947 948 ret = smu_free_memory_pool(smu); 949 if (ret) 950 return ret; 951 952 ret = smu_fini_fb_allocations(smu); 953 if (ret) 954 return ret; 955 956 ret = smu_fini_power(smu); 957 if (ret) { 958 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n"); 959 return ret; 960 } 961 962 ret = smu_fini_smc_tables(smu); 963 if (ret) { 964 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n"); 965 return ret; 966 } 967 968 return 0; 969 } 970 971 static void smu_throttling_logging_work_fn(struct work_struct *work) 972 { 973 struct smu_context *smu = container_of(work, struct smu_context, 974 throttling_logging_work); 975 976 smu_log_thermal_throttling(smu); 977 } 978 979 static void smu_interrupt_work_fn(struct work_struct *work) 980 { 981 struct smu_context *smu = container_of(work, struct smu_context, 982 interrupt_work); 983 984 mutex_lock(&smu->mutex); 985 986 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work) 987 smu->ppt_funcs->interrupt_work(smu); 988 989 mutex_unlock(&smu->mutex); 990 } 991 992 static int smu_sw_init(void *handle) 993 { 994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 995 struct smu_context *smu = &adev->smu; 996 int ret; 997 998 smu->pool_size = adev->pm.smu_prv_buffer_size; 999 smu->smu_feature.feature_num = SMU_FEATURE_MAX; 1000 mutex_init(&smu->smu_feature.mutex); 1001 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); 1002 bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX); 1003 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); 1004 1005 mutex_init(&smu->sensor_lock); 1006 mutex_init(&smu->metrics_lock); 1007 mutex_init(&smu->message_lock); 1008 1009 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); 1010 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); 1011 atomic64_set(&smu->throttle_int_counter, 0); 1012 smu->watermarks_bitmap = 0; 1013 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1014 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1015 1016 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1); 1017 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1); 1018 mutex_init(&smu->smu_power.power_gate.vcn_gate_lock); 1019 mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock); 1020 1021 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 1022 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; 1023 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; 1024 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; 1025 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3; 1026 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; 1027 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; 1028 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; 1029 1030 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 1031 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1032 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING; 1033 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO; 1034 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR; 1035 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE; 1036 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM; 1037 smu->display_config = &adev->pm.pm_display_cfg; 1038 1039 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1040 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; 1041 1042 ret = smu_init_microcode(smu); 1043 if (ret) { 1044 dev_err(adev->dev, "Failed to load smu firmware!\n"); 1045 return ret; 1046 } 1047 1048 ret = smu_smc_table_sw_init(smu); 1049 if (ret) { 1050 dev_err(adev->dev, "Failed to sw init smc table!\n"); 1051 return ret; 1052 } 1053 1054 ret = smu_register_irq_handler(smu); 1055 if (ret) { 1056 dev_err(adev->dev, "Failed to register smc irq handler!\n"); 1057 return ret; 1058 } 1059 1060 /* If there is no way to query fan control mode, fan control is not supported */ 1061 if (!smu->ppt_funcs->get_fan_control_mode) 1062 smu->adev->pm.no_fan = true; 1063 1064 return 0; 1065 } 1066 1067 static int smu_sw_fini(void *handle) 1068 { 1069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1070 struct smu_context *smu = &adev->smu; 1071 int ret; 1072 1073 ret = smu_smc_table_sw_fini(smu); 1074 if (ret) { 1075 dev_err(adev->dev, "Failed to sw fini smc table!\n"); 1076 return ret; 1077 } 1078 1079 smu_fini_microcode(smu); 1080 1081 return 0; 1082 } 1083 1084 static int smu_get_thermal_temperature_range(struct smu_context *smu) 1085 { 1086 struct amdgpu_device *adev = smu->adev; 1087 struct smu_temperature_range *range = 1088 &smu->thermal_range; 1089 int ret = 0; 1090 1091 if (!smu->ppt_funcs->get_thermal_temperature_range) 1092 return 0; 1093 1094 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range); 1095 if (ret) 1096 return ret; 1097 1098 adev->pm.dpm.thermal.min_temp = range->min; 1099 adev->pm.dpm.thermal.max_temp = range->max; 1100 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max; 1101 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min; 1102 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max; 1103 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max; 1104 adev->pm.dpm.thermal.min_mem_temp = range->mem_min; 1105 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max; 1106 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max; 1107 1108 return ret; 1109 } 1110 1111 static int smu_smc_hw_setup(struct smu_context *smu) 1112 { 1113 struct amdgpu_device *adev = smu->adev; 1114 uint32_t pcie_gen = 0, pcie_width = 0; 1115 int ret = 0; 1116 1117 if (adev->in_suspend && smu_is_dpm_running(smu)) { 1118 dev_info(adev->dev, "dpm has been enabled\n"); 1119 /* this is needed specifically */ 1120 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) && 1121 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1122 ret = smu_system_features_control(smu, true); 1123 return ret; 1124 } 1125 1126 ret = smu_init_display_count(smu, 0); 1127 if (ret) { 1128 dev_info(adev->dev, "Failed to pre-set display count as 0!\n"); 1129 return ret; 1130 } 1131 1132 ret = smu_set_driver_table_location(smu); 1133 if (ret) { 1134 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n"); 1135 return ret; 1136 } 1137 1138 /* 1139 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools. 1140 */ 1141 ret = smu_set_tool_table_location(smu); 1142 if (ret) { 1143 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n"); 1144 return ret; 1145 } 1146 1147 /* 1148 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify 1149 * pool location. 1150 */ 1151 ret = smu_notify_memory_pool_location(smu); 1152 if (ret) { 1153 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n"); 1154 return ret; 1155 } 1156 1157 /* smu_dump_pptable(smu); */ 1158 /* 1159 * Copy pptable bo in the vram to smc with SMU MSGs such as 1160 * SetDriverDramAddr and TransferTableDram2Smu. 1161 */ 1162 ret = smu_write_pptable(smu); 1163 if (ret) { 1164 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n"); 1165 return ret; 1166 } 1167 1168 /* issue Run*Btc msg */ 1169 ret = smu_run_btc(smu); 1170 if (ret) 1171 return ret; 1172 1173 ret = smu_feature_set_allowed_mask(smu); 1174 if (ret) { 1175 dev_err(adev->dev, "Failed to set driver allowed features mask!\n"); 1176 return ret; 1177 } 1178 1179 ret = smu_system_features_control(smu, true); 1180 if (ret) { 1181 dev_err(adev->dev, "Failed to enable requested dpm features!\n"); 1182 return ret; 1183 } 1184 1185 if (!smu_is_dpm_running(smu)) 1186 dev_info(adev->dev, "dpm has been disabled\n"); 1187 1188 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1189 pcie_gen = 3; 1190 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1191 pcie_gen = 2; 1192 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1193 pcie_gen = 1; 1194 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1195 pcie_gen = 0; 1196 1197 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 1198 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 1199 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 1200 */ 1201 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1202 pcie_width = 6; 1203 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1204 pcie_width = 5; 1205 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1206 pcie_width = 4; 1207 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1208 pcie_width = 3; 1209 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1210 pcie_width = 2; 1211 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1212 pcie_width = 1; 1213 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width); 1214 if (ret) { 1215 dev_err(adev->dev, "Attempt to override pcie params failed!\n"); 1216 return ret; 1217 } 1218 1219 ret = smu_get_thermal_temperature_range(smu); 1220 if (ret) { 1221 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n"); 1222 return ret; 1223 } 1224 1225 ret = smu_enable_thermal_alert(smu); 1226 if (ret) { 1227 dev_err(adev->dev, "Failed to enable thermal alert!\n"); 1228 return ret; 1229 } 1230 1231 /* 1232 * Set initialized values (get from vbios) to dpm tables context such as 1233 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each 1234 * type of clks. 1235 */ 1236 ret = smu_set_default_dpm_table(smu); 1237 if (ret) { 1238 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n"); 1239 return ret; 1240 } 1241 1242 ret = smu_notify_display_change(smu); 1243 if (ret) 1244 return ret; 1245 1246 /* 1247 * Set min deep sleep dce fclk with bootup value from vbios via 1248 * SetMinDeepSleepDcefclk MSG. 1249 */ 1250 ret = smu_set_min_dcef_deep_sleep(smu, 1251 smu->smu_table.boot_values.dcefclk / 100); 1252 if (ret) 1253 return ret; 1254 1255 return ret; 1256 } 1257 1258 static int smu_start_smc_engine(struct smu_context *smu) 1259 { 1260 struct amdgpu_device *adev = smu->adev; 1261 int ret = 0; 1262 1263 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1264 if (adev->asic_type < CHIP_NAVI10) { 1265 if (smu->ppt_funcs->load_microcode) { 1266 ret = smu->ppt_funcs->load_microcode(smu); 1267 if (ret) 1268 return ret; 1269 } 1270 } 1271 } 1272 1273 if (smu->ppt_funcs->check_fw_status) { 1274 ret = smu->ppt_funcs->check_fw_status(smu); 1275 if (ret) { 1276 dev_err(adev->dev, "SMC is not ready\n"); 1277 return ret; 1278 } 1279 } 1280 1281 /* 1282 * Send msg GetDriverIfVersion to check if the return value is equal 1283 * with DRIVER_IF_VERSION of smc header. 1284 */ 1285 ret = smu_check_fw_version(smu); 1286 if (ret) 1287 return ret; 1288 1289 return ret; 1290 } 1291 1292 static int smu_hw_init(void *handle) 1293 { 1294 int ret; 1295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1296 struct smu_context *smu = &adev->smu; 1297 1298 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 1299 smu->pm_enabled = false; 1300 return 0; 1301 } 1302 1303 ret = smu_start_smc_engine(smu); 1304 if (ret) { 1305 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1306 return ret; 1307 } 1308 1309 if (smu->is_apu) { 1310 smu_powergate_sdma(&adev->smu, false); 1311 smu_dpm_set_vcn_enable(smu, true); 1312 smu_dpm_set_jpeg_enable(smu, true); 1313 smu_set_gfx_cgpg(&adev->smu, true); 1314 } 1315 1316 if (!smu->pm_enabled) 1317 return 0; 1318 1319 /* get boot_values from vbios to set revision, gfxclk, and etc. */ 1320 ret = smu_get_vbios_bootup_values(smu); 1321 if (ret) { 1322 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n"); 1323 return ret; 1324 } 1325 1326 ret = smu_setup_pptable(smu); 1327 if (ret) { 1328 dev_err(adev->dev, "Failed to setup pptable!\n"); 1329 return ret; 1330 } 1331 1332 ret = smu_get_driver_allowed_feature_mask(smu); 1333 if (ret) 1334 return ret; 1335 1336 ret = smu_smc_hw_setup(smu); 1337 if (ret) { 1338 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1339 return ret; 1340 } 1341 1342 /* 1343 * Move maximum sustainable clock retrieving here considering 1344 * 1. It is not needed on resume(from S3). 1345 * 2. DAL settings come between .hw_init and .late_init of SMU. 1346 * And DAL needs to know the maximum sustainable clocks. Thus 1347 * it cannot be put in .late_init(). 1348 */ 1349 ret = smu_init_max_sustainable_clocks(smu); 1350 if (ret) { 1351 dev_err(adev->dev, "Failed to init max sustainable clocks!\n"); 1352 return ret; 1353 } 1354 1355 adev->pm.dpm_enabled = true; 1356 1357 dev_info(adev->dev, "SMU is initialized successfully!\n"); 1358 1359 return 0; 1360 } 1361 1362 static int smu_disable_dpms(struct smu_context *smu) 1363 { 1364 struct amdgpu_device *adev = smu->adev; 1365 int ret = 0; 1366 bool use_baco = !smu->is_apu && 1367 ((amdgpu_in_reset(adev) && 1368 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 1369 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev))); 1370 1371 /* 1372 * For custom pptable uploading, skip the DPM features 1373 * disable process on Navi1x ASICs. 1374 * - As the gfx related features are under control of 1375 * RLC on those ASICs. RLC reinitialization will be 1376 * needed to reenable them. That will cost much more 1377 * efforts. 1378 * 1379 * - SMU firmware can handle the DPM reenablement 1380 * properly. 1381 */ 1382 if (smu->uploading_custom_pp_table && 1383 (adev->asic_type >= CHIP_NAVI10) && 1384 (adev->asic_type <= CHIP_DIMGREY_CAVEFISH)) 1385 return smu_disable_all_features_with_exception(smu, 1386 true, 1387 SMU_FEATURE_COUNT); 1388 1389 /* 1390 * For Sienna_Cichlid, PMFW will handle the features disablement properly 1391 * on BACO in. Driver involvement is unnecessary. 1392 */ 1393 if (((adev->asic_type == CHIP_SIENNA_CICHLID) || 1394 ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) && 1395 use_baco) 1396 return smu_disable_all_features_with_exception(smu, 1397 true, 1398 SMU_FEATURE_BACO_BIT); 1399 1400 /* 1401 * For gpu reset, runpm and hibernation through BACO, 1402 * BACO feature has to be kept enabled. 1403 */ 1404 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) { 1405 ret = smu_disable_all_features_with_exception(smu, 1406 false, 1407 SMU_FEATURE_BACO_BIT); 1408 if (ret) 1409 dev_err(adev->dev, "Failed to disable smu features except BACO.\n"); 1410 } else { 1411 ret = smu_system_features_control(smu, false); 1412 if (ret) 1413 dev_err(adev->dev, "Failed to disable smu features.\n"); 1414 } 1415 1416 if (adev->asic_type >= CHIP_NAVI10 && 1417 adev->gfx.rlc.funcs->stop) 1418 adev->gfx.rlc.funcs->stop(adev); 1419 1420 return ret; 1421 } 1422 1423 static int smu_smc_hw_cleanup(struct smu_context *smu) 1424 { 1425 struct amdgpu_device *adev = smu->adev; 1426 int ret = 0; 1427 1428 cancel_work_sync(&smu->throttling_logging_work); 1429 cancel_work_sync(&smu->interrupt_work); 1430 1431 ret = smu_disable_thermal_alert(smu); 1432 if (ret) { 1433 dev_err(adev->dev, "Fail to disable thermal alert!\n"); 1434 return ret; 1435 } 1436 1437 ret = smu_disable_dpms(smu); 1438 if (ret) { 1439 dev_err(adev->dev, "Fail to disable dpm features!\n"); 1440 return ret; 1441 } 1442 1443 return 0; 1444 } 1445 1446 static int smu_hw_fini(void *handle) 1447 { 1448 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1449 struct smu_context *smu = &adev->smu; 1450 1451 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1452 return 0; 1453 1454 if (smu->is_apu) { 1455 smu_powergate_sdma(&adev->smu, true); 1456 smu_dpm_set_vcn_enable(smu, false); 1457 smu_dpm_set_jpeg_enable(smu, false); 1458 } 1459 1460 if (!smu->pm_enabled) 1461 return 0; 1462 1463 adev->pm.dpm_enabled = false; 1464 1465 return smu_smc_hw_cleanup(smu); 1466 } 1467 1468 static int smu_reset(struct smu_context *smu) 1469 { 1470 struct amdgpu_device *adev = smu->adev; 1471 int ret; 1472 1473 amdgpu_gfx_off_ctrl(smu->adev, false); 1474 1475 ret = smu_hw_fini(adev); 1476 if (ret) 1477 return ret; 1478 1479 ret = smu_hw_init(adev); 1480 if (ret) 1481 return ret; 1482 1483 ret = smu_late_init(adev); 1484 if (ret) 1485 return ret; 1486 1487 amdgpu_gfx_off_ctrl(smu->adev, true); 1488 1489 return 0; 1490 } 1491 1492 static int smu_suspend(void *handle) 1493 { 1494 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1495 struct smu_context *smu = &adev->smu; 1496 int ret; 1497 1498 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1499 return 0; 1500 1501 if (!smu->pm_enabled) 1502 return 0; 1503 1504 adev->pm.dpm_enabled = false; 1505 1506 ret = smu_smc_hw_cleanup(smu); 1507 if (ret) 1508 return ret; 1509 1510 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED); 1511 1512 /* skip CGPG when in S0ix */ 1513 if (smu->is_apu && !adev->in_s0ix) 1514 smu_set_gfx_cgpg(&adev->smu, false); 1515 1516 return 0; 1517 } 1518 1519 static int smu_resume(void *handle) 1520 { 1521 int ret; 1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1523 struct smu_context *smu = &adev->smu; 1524 1525 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) 1526 return 0; 1527 1528 if (!smu->pm_enabled) 1529 return 0; 1530 1531 dev_info(adev->dev, "SMU is resuming...\n"); 1532 1533 ret = smu_start_smc_engine(smu); 1534 if (ret) { 1535 dev_err(adev->dev, "SMC engine is not correctly up!\n"); 1536 return ret; 1537 } 1538 1539 ret = smu_smc_hw_setup(smu); 1540 if (ret) { 1541 dev_err(adev->dev, "Failed to setup smc hw!\n"); 1542 return ret; 1543 } 1544 1545 if (smu->is_apu) 1546 smu_set_gfx_cgpg(&adev->smu, true); 1547 1548 smu->disable_uclk_switch = 0; 1549 1550 adev->pm.dpm_enabled = true; 1551 1552 dev_info(adev->dev, "SMU is resumed successfully!\n"); 1553 1554 return 0; 1555 } 1556 1557 static int smu_display_configuration_change(void *handle, 1558 const struct amd_pp_display_configuration *display_config) 1559 { 1560 struct smu_context *smu = handle; 1561 int index = 0; 1562 int num_of_active_display = 0; 1563 1564 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1565 return -EOPNOTSUPP; 1566 1567 if (!display_config) 1568 return -EINVAL; 1569 1570 mutex_lock(&smu->mutex); 1571 1572 smu_set_min_dcef_deep_sleep(smu, 1573 display_config->min_dcef_deep_sleep_set_clk / 100); 1574 1575 for (index = 0; index < display_config->num_path_including_non_display; index++) { 1576 if (display_config->displays[index].controller_id != 0) 1577 num_of_active_display++; 1578 } 1579 1580 mutex_unlock(&smu->mutex); 1581 1582 return 0; 1583 } 1584 1585 static int smu_set_clockgating_state(void *handle, 1586 enum amd_clockgating_state state) 1587 { 1588 return 0; 1589 } 1590 1591 static int smu_set_powergating_state(void *handle, 1592 enum amd_powergating_state state) 1593 { 1594 return 0; 1595 } 1596 1597 static int smu_enable_umd_pstate(void *handle, 1598 enum amd_dpm_forced_level *level) 1599 { 1600 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 1601 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 1602 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 1603 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 1604 1605 struct smu_context *smu = (struct smu_context*)(handle); 1606 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1607 1608 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1609 return -EINVAL; 1610 1611 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) { 1612 /* enter umd pstate, save current level, disable gfx cg*/ 1613 if (*level & profile_mode_mask) { 1614 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level; 1615 smu_dpm_ctx->enable_umd_pstate = true; 1616 smu_gpo_control(smu, false); 1617 amdgpu_device_ip_set_powergating_state(smu->adev, 1618 AMD_IP_BLOCK_TYPE_GFX, 1619 AMD_PG_STATE_UNGATE); 1620 amdgpu_device_ip_set_clockgating_state(smu->adev, 1621 AMD_IP_BLOCK_TYPE_GFX, 1622 AMD_CG_STATE_UNGATE); 1623 smu_gfx_ulv_control(smu, false); 1624 smu_deep_sleep_control(smu, false); 1625 amdgpu_asic_update_umd_stable_pstate(smu->adev, true); 1626 } 1627 } else { 1628 /* exit umd pstate, restore level, enable gfx cg*/ 1629 if (!(*level & profile_mode_mask)) { 1630 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 1631 *level = smu_dpm_ctx->saved_dpm_level; 1632 smu_dpm_ctx->enable_umd_pstate = false; 1633 amdgpu_asic_update_umd_stable_pstate(smu->adev, false); 1634 smu_deep_sleep_control(smu, true); 1635 smu_gfx_ulv_control(smu, true); 1636 amdgpu_device_ip_set_clockgating_state(smu->adev, 1637 AMD_IP_BLOCK_TYPE_GFX, 1638 AMD_CG_STATE_GATE); 1639 amdgpu_device_ip_set_powergating_state(smu->adev, 1640 AMD_IP_BLOCK_TYPE_GFX, 1641 AMD_PG_STATE_GATE); 1642 smu_gpo_control(smu, true); 1643 } 1644 } 1645 1646 return 0; 1647 } 1648 1649 static int smu_bump_power_profile_mode(struct smu_context *smu, 1650 long *param, 1651 uint32_t param_size) 1652 { 1653 int ret = 0; 1654 1655 if (smu->ppt_funcs->set_power_profile_mode) 1656 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size); 1657 1658 return ret; 1659 } 1660 1661 static int smu_adjust_power_state_dynamic(struct smu_context *smu, 1662 enum amd_dpm_forced_level level, 1663 bool skip_display_settings) 1664 { 1665 int ret = 0; 1666 int index = 0; 1667 long workload; 1668 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1669 1670 if (!skip_display_settings) { 1671 ret = smu_display_config_changed(smu); 1672 if (ret) { 1673 dev_err(smu->adev->dev, "Failed to change display config!"); 1674 return ret; 1675 } 1676 } 1677 1678 ret = smu_apply_clocks_adjust_rules(smu); 1679 if (ret) { 1680 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!"); 1681 return ret; 1682 } 1683 1684 if (!skip_display_settings) { 1685 ret = smu_notify_smc_display_config(smu); 1686 if (ret) { 1687 dev_err(smu->adev->dev, "Failed to notify smc display config!"); 1688 return ret; 1689 } 1690 } 1691 1692 if (smu_dpm_ctx->dpm_level != level) { 1693 ret = smu_asic_set_performance_level(smu, level); 1694 if (ret) { 1695 dev_err(smu->adev->dev, "Failed to set performance level!"); 1696 return ret; 1697 } 1698 1699 /* update the saved copy */ 1700 smu_dpm_ctx->dpm_level = level; 1701 } 1702 1703 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1704 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { 1705 index = fls(smu->workload_mask); 1706 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1707 workload = smu->workload_setting[index]; 1708 1709 if (smu->power_profile_mode != workload) 1710 smu_bump_power_profile_mode(smu, &workload, 0); 1711 } 1712 1713 return ret; 1714 } 1715 1716 static int smu_handle_task(struct smu_context *smu, 1717 enum amd_dpm_forced_level level, 1718 enum amd_pp_task task_id, 1719 bool lock_needed) 1720 { 1721 int ret = 0; 1722 1723 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1724 return -EOPNOTSUPP; 1725 1726 if (lock_needed) 1727 mutex_lock(&smu->mutex); 1728 1729 switch (task_id) { 1730 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE: 1731 ret = smu_pre_display_config_changed(smu); 1732 if (ret) 1733 goto out; 1734 ret = smu_adjust_power_state_dynamic(smu, level, false); 1735 break; 1736 case AMD_PP_TASK_COMPLETE_INIT: 1737 case AMD_PP_TASK_READJUST_POWER_STATE: 1738 ret = smu_adjust_power_state_dynamic(smu, level, true); 1739 break; 1740 default: 1741 break; 1742 } 1743 1744 out: 1745 if (lock_needed) 1746 mutex_unlock(&smu->mutex); 1747 1748 return ret; 1749 } 1750 1751 static int smu_handle_dpm_task(void *handle, 1752 enum amd_pp_task task_id, 1753 enum amd_pm_state_type *user_state) 1754 { 1755 struct smu_context *smu = handle; 1756 struct smu_dpm_context *smu_dpm = &smu->smu_dpm; 1757 1758 return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true); 1759 1760 } 1761 1762 static int smu_switch_power_profile(void *handle, 1763 enum PP_SMC_POWER_PROFILE type, 1764 bool en) 1765 { 1766 struct smu_context *smu = handle; 1767 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1768 long workload; 1769 uint32_t index; 1770 1771 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1772 return -EOPNOTSUPP; 1773 1774 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 1775 return -EINVAL; 1776 1777 mutex_lock(&smu->mutex); 1778 1779 if (!en) { 1780 smu->workload_mask &= ~(1 << smu->workload_prority[type]); 1781 index = fls(smu->workload_mask); 1782 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1783 workload = smu->workload_setting[index]; 1784 } else { 1785 smu->workload_mask |= (1 << smu->workload_prority[type]); 1786 index = fls(smu->workload_mask); 1787 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; 1788 workload = smu->workload_setting[index]; 1789 } 1790 1791 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && 1792 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) 1793 smu_bump_power_profile_mode(smu, &workload, 0); 1794 1795 mutex_unlock(&smu->mutex); 1796 1797 return 0; 1798 } 1799 1800 static enum amd_dpm_forced_level smu_get_performance_level(void *handle) 1801 { 1802 struct smu_context *smu = handle; 1803 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1804 enum amd_dpm_forced_level level; 1805 1806 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1807 return -EOPNOTSUPP; 1808 1809 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1810 return -EINVAL; 1811 1812 mutex_lock(&(smu->mutex)); 1813 level = smu_dpm_ctx->dpm_level; 1814 mutex_unlock(&(smu->mutex)); 1815 1816 return level; 1817 } 1818 1819 static int smu_force_performance_level(void *handle, 1820 enum amd_dpm_forced_level level) 1821 { 1822 struct smu_context *smu = handle; 1823 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1824 int ret = 0; 1825 1826 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1827 return -EOPNOTSUPP; 1828 1829 if (!smu->is_apu && !smu_dpm_ctx->dpm_context) 1830 return -EINVAL; 1831 1832 mutex_lock(&smu->mutex); 1833 1834 ret = smu_enable_umd_pstate(smu, &level); 1835 if (ret) { 1836 mutex_unlock(&smu->mutex); 1837 return ret; 1838 } 1839 1840 ret = smu_handle_task(smu, level, 1841 AMD_PP_TASK_READJUST_POWER_STATE, 1842 false); 1843 1844 mutex_unlock(&smu->mutex); 1845 1846 /* reset user dpm clock state */ 1847 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1848 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); 1849 smu->user_dpm_profile.clk_dependency = 0; 1850 } 1851 1852 return ret; 1853 } 1854 1855 static int smu_set_display_count(void *handle, uint32_t count) 1856 { 1857 struct smu_context *smu = handle; 1858 int ret = 0; 1859 1860 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1861 return -EOPNOTSUPP; 1862 1863 mutex_lock(&smu->mutex); 1864 ret = smu_init_display_count(smu, count); 1865 mutex_unlock(&smu->mutex); 1866 1867 return ret; 1868 } 1869 1870 static int smu_force_smuclk_levels(struct smu_context *smu, 1871 enum smu_clk_type clk_type, 1872 uint32_t mask) 1873 { 1874 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); 1875 int ret = 0; 1876 1877 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1878 return -EOPNOTSUPP; 1879 1880 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 1881 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n"); 1882 return -EINVAL; 1883 } 1884 1885 mutex_lock(&smu->mutex); 1886 1887 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) { 1888 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); 1889 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) { 1890 smu->user_dpm_profile.clk_mask[clk_type] = mask; 1891 smu_set_user_clk_dependencies(smu, clk_type); 1892 } 1893 } 1894 1895 mutex_unlock(&smu->mutex); 1896 1897 return ret; 1898 } 1899 1900 static int smu_force_ppclk_levels(void *handle, 1901 enum pp_clock_type type, 1902 uint32_t mask) 1903 { 1904 struct smu_context *smu = handle; 1905 enum smu_clk_type clk_type; 1906 1907 switch (type) { 1908 case PP_SCLK: 1909 clk_type = SMU_SCLK; break; 1910 case PP_MCLK: 1911 clk_type = SMU_MCLK; break; 1912 case PP_PCIE: 1913 clk_type = SMU_PCIE; break; 1914 case PP_SOCCLK: 1915 clk_type = SMU_SOCCLK; break; 1916 case PP_FCLK: 1917 clk_type = SMU_FCLK; break; 1918 case PP_DCEFCLK: 1919 clk_type = SMU_DCEFCLK; break; 1920 case PP_VCLK: 1921 clk_type = SMU_VCLK; break; 1922 case PP_DCLK: 1923 clk_type = SMU_DCLK; break; 1924 case OD_SCLK: 1925 clk_type = SMU_OD_SCLK; break; 1926 case OD_MCLK: 1927 clk_type = SMU_OD_MCLK; break; 1928 case OD_VDDC_CURVE: 1929 clk_type = SMU_OD_VDDC_CURVE; break; 1930 case OD_RANGE: 1931 clk_type = SMU_OD_RANGE; break; 1932 default: 1933 return -EINVAL; 1934 } 1935 1936 return smu_force_smuclk_levels(smu, clk_type, mask); 1937 } 1938 1939 /* 1940 * On system suspending or resetting, the dpm_enabled 1941 * flag will be cleared. So that those SMU services which 1942 * are not supported will be gated. 1943 * However, the mp1 state setting should still be granted 1944 * even if the dpm_enabled cleared. 1945 */ 1946 static int smu_set_mp1_state(void *handle, 1947 enum pp_mp1_state mp1_state) 1948 { 1949 struct smu_context *smu = handle; 1950 int ret = 0; 1951 1952 if (!smu->pm_enabled) 1953 return -EOPNOTSUPP; 1954 1955 mutex_lock(&smu->mutex); 1956 1957 if (smu->ppt_funcs && 1958 smu->ppt_funcs->set_mp1_state) 1959 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state); 1960 1961 mutex_unlock(&smu->mutex); 1962 1963 return ret; 1964 } 1965 1966 static int smu_set_df_cstate(void *handle, 1967 enum pp_df_cstate state) 1968 { 1969 struct smu_context *smu = handle; 1970 int ret = 0; 1971 1972 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1973 return -EOPNOTSUPP; 1974 1975 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate) 1976 return 0; 1977 1978 mutex_lock(&smu->mutex); 1979 1980 ret = smu->ppt_funcs->set_df_cstate(smu, state); 1981 if (ret) 1982 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n"); 1983 1984 mutex_unlock(&smu->mutex); 1985 1986 return ret; 1987 } 1988 1989 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en) 1990 { 1991 int ret = 0; 1992 1993 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 1994 return -EOPNOTSUPP; 1995 1996 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down) 1997 return 0; 1998 1999 mutex_lock(&smu->mutex); 2000 2001 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en); 2002 if (ret) 2003 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n"); 2004 2005 mutex_unlock(&smu->mutex); 2006 2007 return ret; 2008 } 2009 2010 int smu_write_watermarks_table(struct smu_context *smu) 2011 { 2012 int ret = 0; 2013 2014 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2015 return -EOPNOTSUPP; 2016 2017 mutex_lock(&smu->mutex); 2018 2019 ret = smu_set_watermarks_table(smu, NULL); 2020 2021 mutex_unlock(&smu->mutex); 2022 2023 return ret; 2024 } 2025 2026 static int smu_set_watermarks_for_clock_ranges(void *handle, 2027 struct pp_smu_wm_range_sets *clock_ranges) 2028 { 2029 struct smu_context *smu = handle; 2030 int ret = 0; 2031 2032 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2033 return -EOPNOTSUPP; 2034 2035 if (smu->disable_watermark) 2036 return 0; 2037 2038 mutex_lock(&smu->mutex); 2039 2040 ret = smu_set_watermarks_table(smu, clock_ranges); 2041 2042 mutex_unlock(&smu->mutex); 2043 2044 return ret; 2045 } 2046 2047 int smu_set_ac_dc(struct smu_context *smu) 2048 { 2049 int ret = 0; 2050 2051 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2052 return -EOPNOTSUPP; 2053 2054 /* controlled by firmware */ 2055 if (smu->dc_controlled_by_gpio) 2056 return 0; 2057 2058 mutex_lock(&smu->mutex); 2059 ret = smu_set_power_source(smu, 2060 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC : 2061 SMU_POWER_SOURCE_DC); 2062 if (ret) 2063 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n", 2064 smu->adev->pm.ac_power ? "AC" : "DC"); 2065 mutex_unlock(&smu->mutex); 2066 2067 return ret; 2068 } 2069 2070 const struct amd_ip_funcs smu_ip_funcs = { 2071 .name = "smu", 2072 .early_init = smu_early_init, 2073 .late_init = smu_late_init, 2074 .sw_init = smu_sw_init, 2075 .sw_fini = smu_sw_fini, 2076 .hw_init = smu_hw_init, 2077 .hw_fini = smu_hw_fini, 2078 .suspend = smu_suspend, 2079 .resume = smu_resume, 2080 .is_idle = NULL, 2081 .check_soft_reset = NULL, 2082 .wait_for_idle = NULL, 2083 .soft_reset = NULL, 2084 .set_clockgating_state = smu_set_clockgating_state, 2085 .set_powergating_state = smu_set_powergating_state, 2086 .enable_umd_pstate = smu_enable_umd_pstate, 2087 }; 2088 2089 const struct amdgpu_ip_block_version smu_v11_0_ip_block = 2090 { 2091 .type = AMD_IP_BLOCK_TYPE_SMC, 2092 .major = 11, 2093 .minor = 0, 2094 .rev = 0, 2095 .funcs = &smu_ip_funcs, 2096 }; 2097 2098 const struct amdgpu_ip_block_version smu_v12_0_ip_block = 2099 { 2100 .type = AMD_IP_BLOCK_TYPE_SMC, 2101 .major = 12, 2102 .minor = 0, 2103 .rev = 0, 2104 .funcs = &smu_ip_funcs, 2105 }; 2106 2107 const struct amdgpu_ip_block_version smu_v13_0_ip_block = 2108 { 2109 .type = AMD_IP_BLOCK_TYPE_SMC, 2110 .major = 13, 2111 .minor = 0, 2112 .rev = 0, 2113 .funcs = &smu_ip_funcs, 2114 }; 2115 2116 static int smu_load_microcode(void *handle) 2117 { 2118 struct smu_context *smu = handle; 2119 struct amdgpu_device *adev = smu->adev; 2120 int ret = 0; 2121 2122 if (!smu->pm_enabled) 2123 return -EOPNOTSUPP; 2124 2125 /* This should be used for non PSP loading */ 2126 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2127 return 0; 2128 2129 if (smu->ppt_funcs->load_microcode) { 2130 ret = smu->ppt_funcs->load_microcode(smu); 2131 if (ret) { 2132 dev_err(adev->dev, "Load microcode failed\n"); 2133 return ret; 2134 } 2135 } 2136 2137 if (smu->ppt_funcs->check_fw_status) { 2138 ret = smu->ppt_funcs->check_fw_status(smu); 2139 if (ret) { 2140 dev_err(adev->dev, "SMC is not ready\n"); 2141 return ret; 2142 } 2143 } 2144 2145 return ret; 2146 } 2147 2148 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled) 2149 { 2150 int ret = 0; 2151 2152 mutex_lock(&smu->mutex); 2153 2154 if (smu->ppt_funcs->set_gfx_cgpg) 2155 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled); 2156 2157 mutex_unlock(&smu->mutex); 2158 2159 return ret; 2160 } 2161 2162 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed) 2163 { 2164 struct smu_context *smu = handle; 2165 u32 percent; 2166 int ret = 0; 2167 2168 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2169 return -EOPNOTSUPP; 2170 2171 mutex_lock(&smu->mutex); 2172 2173 if (smu->ppt_funcs->set_fan_speed_percent) { 2174 percent = speed * 100 / smu->fan_max_rpm; 2175 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent); 2176 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2177 smu->user_dpm_profile.fan_speed_percent = percent; 2178 } 2179 2180 mutex_unlock(&smu->mutex); 2181 2182 return ret; 2183 } 2184 2185 /** 2186 * smu_get_power_limit - Request one of the SMU Power Limits 2187 * 2188 * @handle: pointer to smu context 2189 * @limit: requested limit is written back to this variable 2190 * @pp_limit_level: &pp_power_limit_level which limit of the power to return 2191 * @pp_power_type: &pp_power_type type of power 2192 * Return: 0 on success, <0 on error 2193 * 2194 */ 2195 int smu_get_power_limit(void *handle, 2196 uint32_t *limit, 2197 enum pp_power_limit_level pp_limit_level, 2198 enum pp_power_type pp_power_type) 2199 { 2200 struct smu_context *smu = handle; 2201 enum smu_ppt_limit_level limit_level; 2202 uint32_t limit_type; 2203 int ret = 0; 2204 2205 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2206 return -EOPNOTSUPP; 2207 2208 switch(pp_power_type) { 2209 case PP_PWR_TYPE_SUSTAINED: 2210 limit_type = SMU_DEFAULT_PPT_LIMIT; 2211 break; 2212 case PP_PWR_TYPE_FAST: 2213 limit_type = SMU_FAST_PPT_LIMIT; 2214 break; 2215 default: 2216 return -EOPNOTSUPP; 2217 break; 2218 } 2219 2220 switch(pp_limit_level){ 2221 case PP_PWR_LIMIT_CURRENT: 2222 limit_level = SMU_PPT_LIMIT_CURRENT; 2223 break; 2224 case PP_PWR_LIMIT_DEFAULT: 2225 limit_level = SMU_PPT_LIMIT_DEFAULT; 2226 break; 2227 case PP_PWR_LIMIT_MAX: 2228 limit_level = SMU_PPT_LIMIT_MAX; 2229 break; 2230 case PP_PWR_LIMIT_MIN: 2231 default: 2232 return -EOPNOTSUPP; 2233 break; 2234 } 2235 2236 mutex_lock(&smu->mutex); 2237 2238 if (limit_type != SMU_DEFAULT_PPT_LIMIT) { 2239 if (smu->ppt_funcs->get_ppt_limit) 2240 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); 2241 } else { 2242 switch (limit_level) { 2243 case SMU_PPT_LIMIT_CURRENT: 2244 if ((smu->adev->asic_type == CHIP_ALDEBARAN) || 2245 (smu->adev->asic_type == CHIP_SIENNA_CICHLID) || 2246 (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) || 2247 (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) || 2248 (smu->adev->asic_type == CHIP_BEIGE_GOBY)) 2249 ret = smu_get_asic_power_limits(smu, 2250 &smu->current_power_limit, 2251 NULL, 2252 NULL); 2253 *limit = smu->current_power_limit; 2254 break; 2255 case SMU_PPT_LIMIT_DEFAULT: 2256 *limit = smu->default_power_limit; 2257 break; 2258 case SMU_PPT_LIMIT_MAX: 2259 *limit = smu->max_power_limit; 2260 break; 2261 default: 2262 break; 2263 } 2264 } 2265 2266 mutex_unlock(&smu->mutex); 2267 2268 return ret; 2269 } 2270 2271 static int smu_set_power_limit(void *handle, uint32_t limit) 2272 { 2273 struct smu_context *smu = handle; 2274 uint32_t limit_type = limit >> 24; 2275 int ret = 0; 2276 2277 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2278 return -EOPNOTSUPP; 2279 2280 mutex_lock(&smu->mutex); 2281 2282 if (limit_type != SMU_DEFAULT_PPT_LIMIT) 2283 if (smu->ppt_funcs->set_power_limit) { 2284 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2285 goto out; 2286 } 2287 2288 if (limit > smu->max_power_limit) { 2289 dev_err(smu->adev->dev, 2290 "New power limit (%d) is over the max allowed %d\n", 2291 limit, smu->max_power_limit); 2292 ret = -EINVAL; 2293 goto out; 2294 } 2295 2296 if (!limit) 2297 limit = smu->current_power_limit; 2298 2299 if (smu->ppt_funcs->set_power_limit) { 2300 ret = smu->ppt_funcs->set_power_limit(smu, limit); 2301 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2302 smu->user_dpm_profile.power_limit = limit; 2303 } 2304 2305 out: 2306 mutex_unlock(&smu->mutex); 2307 2308 return ret; 2309 } 2310 2311 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) 2312 { 2313 int ret = 0; 2314 2315 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2316 return -EOPNOTSUPP; 2317 2318 mutex_lock(&smu->mutex); 2319 2320 if (smu->ppt_funcs->print_clk_levels) 2321 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); 2322 2323 mutex_unlock(&smu->mutex); 2324 2325 return ret; 2326 } 2327 2328 static int smu_print_ppclk_levels(void *handle, 2329 enum pp_clock_type type, 2330 char *buf) 2331 { 2332 struct smu_context *smu = handle; 2333 enum smu_clk_type clk_type; 2334 2335 switch (type) { 2336 case PP_SCLK: 2337 clk_type = SMU_SCLK; break; 2338 case PP_MCLK: 2339 clk_type = SMU_MCLK; break; 2340 case PP_PCIE: 2341 clk_type = SMU_PCIE; break; 2342 case PP_SOCCLK: 2343 clk_type = SMU_SOCCLK; break; 2344 case PP_FCLK: 2345 clk_type = SMU_FCLK; break; 2346 case PP_DCEFCLK: 2347 clk_type = SMU_DCEFCLK; break; 2348 case PP_VCLK: 2349 clk_type = SMU_VCLK; break; 2350 case PP_DCLK: 2351 clk_type = SMU_DCLK; break; 2352 case OD_SCLK: 2353 clk_type = SMU_OD_SCLK; break; 2354 case OD_MCLK: 2355 clk_type = SMU_OD_MCLK; break; 2356 case OD_VDDC_CURVE: 2357 clk_type = SMU_OD_VDDC_CURVE; break; 2358 case OD_RANGE: 2359 clk_type = SMU_OD_RANGE; break; 2360 case OD_VDDGFX_OFFSET: 2361 clk_type = SMU_OD_VDDGFX_OFFSET; break; 2362 case OD_CCLK: 2363 clk_type = SMU_OD_CCLK; break; 2364 default: 2365 return -EINVAL; 2366 } 2367 2368 return smu_print_smuclk_levels(smu, clk_type, buf); 2369 } 2370 2371 static int smu_od_edit_dpm_table(void *handle, 2372 enum PP_OD_DPM_TABLE_COMMAND type, 2373 long *input, uint32_t size) 2374 { 2375 struct smu_context *smu = handle; 2376 int ret = 0; 2377 2378 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2379 return -EOPNOTSUPP; 2380 2381 mutex_lock(&smu->mutex); 2382 2383 if (smu->ppt_funcs->od_edit_dpm_table) { 2384 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size); 2385 } 2386 2387 mutex_unlock(&smu->mutex); 2388 2389 return ret; 2390 } 2391 2392 static int smu_read_sensor(void *handle, 2393 int sensor, 2394 void *data, 2395 int *size_arg) 2396 { 2397 struct smu_context *smu = handle; 2398 struct smu_umd_pstate_table *pstate_table = 2399 &smu->pstate_table; 2400 int ret = 0; 2401 uint32_t *size, size_val; 2402 2403 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2404 return -EOPNOTSUPP; 2405 2406 if (!data || !size_arg) 2407 return -EINVAL; 2408 2409 size_val = *size_arg; 2410 size = &size_val; 2411 2412 mutex_lock(&smu->mutex); 2413 2414 if (smu->ppt_funcs->read_sensor) 2415 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size)) 2416 goto unlock; 2417 2418 switch (sensor) { 2419 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 2420 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100; 2421 *size = 4; 2422 break; 2423 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 2424 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100; 2425 *size = 4; 2426 break; 2427 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2428 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2); 2429 *size = 8; 2430 break; 2431 case AMDGPU_PP_SENSOR_UVD_POWER: 2432 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; 2433 *size = 4; 2434 break; 2435 case AMDGPU_PP_SENSOR_VCE_POWER: 2436 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0; 2437 *size = 4; 2438 break; 2439 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 2440 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1; 2441 *size = 4; 2442 break; 2443 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 2444 *(uint32_t *)data = 0; 2445 *size = 4; 2446 break; 2447 default: 2448 *size = 0; 2449 ret = -EOPNOTSUPP; 2450 break; 2451 } 2452 2453 unlock: 2454 mutex_unlock(&smu->mutex); 2455 2456 // assign uint32_t to int 2457 *size_arg = size_val; 2458 2459 return ret; 2460 } 2461 2462 static int smu_get_power_profile_mode(void *handle, char *buf) 2463 { 2464 struct smu_context *smu = handle; 2465 int ret = 0; 2466 2467 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2468 return -EOPNOTSUPP; 2469 2470 mutex_lock(&smu->mutex); 2471 2472 if (smu->ppt_funcs->get_power_profile_mode) 2473 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf); 2474 2475 mutex_unlock(&smu->mutex); 2476 2477 return ret; 2478 } 2479 2480 static int smu_set_power_profile_mode(void *handle, 2481 long *param, 2482 uint32_t param_size) 2483 { 2484 struct smu_context *smu = handle; 2485 int ret = 0; 2486 2487 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2488 return -EOPNOTSUPP; 2489 2490 mutex_lock(&smu->mutex); 2491 2492 smu_bump_power_profile_mode(smu, param, param_size); 2493 2494 mutex_unlock(&smu->mutex); 2495 2496 return ret; 2497 } 2498 2499 2500 static u32 smu_get_fan_control_mode(void *handle) 2501 { 2502 struct smu_context *smu = handle; 2503 u32 ret = 0; 2504 2505 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2506 return AMD_FAN_CTRL_NONE; 2507 2508 mutex_lock(&smu->mutex); 2509 2510 if (smu->ppt_funcs->get_fan_control_mode) 2511 ret = smu->ppt_funcs->get_fan_control_mode(smu); 2512 2513 mutex_unlock(&smu->mutex); 2514 2515 return ret; 2516 } 2517 2518 static int smu_set_fan_control_mode(struct smu_context *smu, int value) 2519 { 2520 int ret = 0; 2521 2522 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2523 return -EOPNOTSUPP; 2524 2525 mutex_lock(&smu->mutex); 2526 2527 if (smu->ppt_funcs->set_fan_control_mode) { 2528 ret = smu->ppt_funcs->set_fan_control_mode(smu, value); 2529 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2530 smu->user_dpm_profile.fan_mode = value; 2531 } 2532 2533 mutex_unlock(&smu->mutex); 2534 2535 /* reset user dpm fan speed */ 2536 if (!ret && value != AMD_FAN_CTRL_MANUAL && 2537 !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2538 smu->user_dpm_profile.fan_speed_percent = 0; 2539 2540 return ret; 2541 } 2542 2543 static void smu_pp_set_fan_control_mode(void *handle, u32 value) 2544 { 2545 struct smu_context *smu = handle; 2546 2547 smu_set_fan_control_mode(smu, value); 2548 } 2549 2550 2551 static int smu_get_fan_speed_percent(void *handle, u32 *speed) 2552 { 2553 struct smu_context *smu = handle; 2554 int ret = 0; 2555 uint32_t percent; 2556 2557 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2558 return -EOPNOTSUPP; 2559 2560 mutex_lock(&smu->mutex); 2561 2562 if (smu->ppt_funcs->get_fan_speed_percent) { 2563 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2564 if (!ret) { 2565 *speed = percent > 100 ? 100 : percent; 2566 } 2567 } 2568 2569 mutex_unlock(&smu->mutex); 2570 2571 2572 return ret; 2573 } 2574 2575 static int smu_set_fan_speed_percent(void *handle, u32 speed) 2576 { 2577 struct smu_context *smu = handle; 2578 int ret = 0; 2579 2580 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2581 return -EOPNOTSUPP; 2582 2583 mutex_lock(&smu->mutex); 2584 2585 if (smu->ppt_funcs->set_fan_speed_percent) { 2586 if (speed > 100) 2587 speed = 100; 2588 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed); 2589 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) 2590 smu->user_dpm_profile.fan_speed_percent = speed; 2591 } 2592 2593 mutex_unlock(&smu->mutex); 2594 2595 return ret; 2596 } 2597 2598 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed) 2599 { 2600 struct smu_context *smu = handle; 2601 int ret = 0; 2602 u32 percent; 2603 2604 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2605 return -EOPNOTSUPP; 2606 2607 mutex_lock(&smu->mutex); 2608 2609 if (smu->ppt_funcs->get_fan_speed_percent) { 2610 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent); 2611 *speed = percent * smu->fan_max_rpm / 100; 2612 } 2613 2614 mutex_unlock(&smu->mutex); 2615 2616 return ret; 2617 } 2618 2619 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk) 2620 { 2621 struct smu_context *smu = handle; 2622 int ret = 0; 2623 2624 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2625 return -EOPNOTSUPP; 2626 2627 mutex_lock(&smu->mutex); 2628 2629 ret = smu_set_min_dcef_deep_sleep(smu, clk); 2630 2631 mutex_unlock(&smu->mutex); 2632 2633 return ret; 2634 } 2635 2636 static int smu_get_clock_by_type_with_latency(void *handle, 2637 enum amd_pp_clock_type type, 2638 struct pp_clock_levels_with_latency *clocks) 2639 { 2640 struct smu_context *smu = handle; 2641 enum smu_clk_type clk_type; 2642 int ret = 0; 2643 2644 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2645 return -EOPNOTSUPP; 2646 2647 mutex_lock(&smu->mutex); 2648 2649 if (smu->ppt_funcs->get_clock_by_type_with_latency) { 2650 switch (type) { 2651 case amd_pp_sys_clock: 2652 clk_type = SMU_GFXCLK; 2653 break; 2654 case amd_pp_mem_clock: 2655 clk_type = SMU_MCLK; 2656 break; 2657 case amd_pp_dcef_clock: 2658 clk_type = SMU_DCEFCLK; 2659 break; 2660 case amd_pp_disp_clock: 2661 clk_type = SMU_DISPCLK; 2662 break; 2663 default: 2664 dev_err(smu->adev->dev, "Invalid clock type!\n"); 2665 mutex_unlock(&smu->mutex); 2666 return -EINVAL; 2667 } 2668 2669 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); 2670 } 2671 2672 mutex_unlock(&smu->mutex); 2673 2674 return ret; 2675 } 2676 2677 static int smu_display_clock_voltage_request(void *handle, 2678 struct pp_display_clock_request *clock_req) 2679 { 2680 struct smu_context *smu = handle; 2681 int ret = 0; 2682 2683 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2684 return -EOPNOTSUPP; 2685 2686 mutex_lock(&smu->mutex); 2687 2688 if (smu->ppt_funcs->display_clock_voltage_request) 2689 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req); 2690 2691 mutex_unlock(&smu->mutex); 2692 2693 return ret; 2694 } 2695 2696 2697 static int smu_display_disable_memory_clock_switch(void *handle, 2698 bool disable_memory_clock_switch) 2699 { 2700 struct smu_context *smu = handle; 2701 int ret = -EINVAL; 2702 2703 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2704 return -EOPNOTSUPP; 2705 2706 mutex_lock(&smu->mutex); 2707 2708 if (smu->ppt_funcs->display_disable_memory_clock_switch) 2709 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch); 2710 2711 mutex_unlock(&smu->mutex); 2712 2713 return ret; 2714 } 2715 2716 static int smu_set_xgmi_pstate(void *handle, 2717 uint32_t pstate) 2718 { 2719 struct smu_context *smu = handle; 2720 int ret = 0; 2721 2722 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2723 return -EOPNOTSUPP; 2724 2725 mutex_lock(&smu->mutex); 2726 2727 if (smu->ppt_funcs->set_xgmi_pstate) 2728 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate); 2729 2730 mutex_unlock(&smu->mutex); 2731 2732 if(ret) 2733 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n"); 2734 2735 return ret; 2736 } 2737 2738 static int smu_get_baco_capability(void *handle, bool *cap) 2739 { 2740 struct smu_context *smu = handle; 2741 int ret = 0; 2742 2743 *cap = false; 2744 2745 if (!smu->pm_enabled) 2746 return 0; 2747 2748 mutex_lock(&smu->mutex); 2749 2750 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support) 2751 *cap = smu->ppt_funcs->baco_is_support(smu); 2752 2753 mutex_unlock(&smu->mutex); 2754 2755 return ret; 2756 } 2757 2758 static int smu_baco_set_state(void *handle, int state) 2759 { 2760 struct smu_context *smu = handle; 2761 int ret = 0; 2762 2763 if (!smu->pm_enabled) 2764 return -EOPNOTSUPP; 2765 2766 if (state == 0) { 2767 mutex_lock(&smu->mutex); 2768 2769 if (smu->ppt_funcs->baco_exit) 2770 ret = smu->ppt_funcs->baco_exit(smu); 2771 2772 mutex_unlock(&smu->mutex); 2773 } else if (state == 1) { 2774 mutex_lock(&smu->mutex); 2775 2776 if (smu->ppt_funcs->baco_enter) 2777 ret = smu->ppt_funcs->baco_enter(smu); 2778 2779 mutex_unlock(&smu->mutex); 2780 2781 } else { 2782 return -EINVAL; 2783 } 2784 2785 if (ret) 2786 dev_err(smu->adev->dev, "Failed to %s BACO state!\n", 2787 (state)?"enter":"exit"); 2788 2789 return ret; 2790 } 2791 2792 bool smu_mode1_reset_is_support(struct smu_context *smu) 2793 { 2794 bool ret = false; 2795 2796 if (!smu->pm_enabled) 2797 return false; 2798 2799 mutex_lock(&smu->mutex); 2800 2801 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support) 2802 ret = smu->ppt_funcs->mode1_reset_is_support(smu); 2803 2804 mutex_unlock(&smu->mutex); 2805 2806 return ret; 2807 } 2808 2809 bool smu_mode2_reset_is_support(struct smu_context *smu) 2810 { 2811 bool ret = false; 2812 2813 if (!smu->pm_enabled) 2814 return false; 2815 2816 mutex_lock(&smu->mutex); 2817 2818 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support) 2819 ret = smu->ppt_funcs->mode2_reset_is_support(smu); 2820 2821 mutex_unlock(&smu->mutex); 2822 2823 return ret; 2824 } 2825 2826 int smu_mode1_reset(struct smu_context *smu) 2827 { 2828 int ret = 0; 2829 2830 if (!smu->pm_enabled) 2831 return -EOPNOTSUPP; 2832 2833 mutex_lock(&smu->mutex); 2834 2835 if (smu->ppt_funcs->mode1_reset) 2836 ret = smu->ppt_funcs->mode1_reset(smu); 2837 2838 mutex_unlock(&smu->mutex); 2839 2840 return ret; 2841 } 2842 2843 static int smu_mode2_reset(void *handle) 2844 { 2845 struct smu_context *smu = handle; 2846 int ret = 0; 2847 2848 if (!smu->pm_enabled) 2849 return -EOPNOTSUPP; 2850 2851 mutex_lock(&smu->mutex); 2852 2853 if (smu->ppt_funcs->mode2_reset) 2854 ret = smu->ppt_funcs->mode2_reset(smu); 2855 2856 mutex_unlock(&smu->mutex); 2857 2858 if (ret) 2859 dev_err(smu->adev->dev, "Mode2 reset failed!\n"); 2860 2861 return ret; 2862 } 2863 2864 static int smu_get_max_sustainable_clocks_by_dc(void *handle, 2865 struct pp_smu_nv_clock_table *max_clocks) 2866 { 2867 struct smu_context *smu = handle; 2868 int ret = 0; 2869 2870 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2871 return -EOPNOTSUPP; 2872 2873 mutex_lock(&smu->mutex); 2874 2875 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc) 2876 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks); 2877 2878 mutex_unlock(&smu->mutex); 2879 2880 return ret; 2881 } 2882 2883 static int smu_get_uclk_dpm_states(void *handle, 2884 unsigned int *clock_values_in_khz, 2885 unsigned int *num_states) 2886 { 2887 struct smu_context *smu = handle; 2888 int ret = 0; 2889 2890 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2891 return -EOPNOTSUPP; 2892 2893 mutex_lock(&smu->mutex); 2894 2895 if (smu->ppt_funcs->get_uclk_dpm_states) 2896 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states); 2897 2898 mutex_unlock(&smu->mutex); 2899 2900 return ret; 2901 } 2902 2903 static enum amd_pm_state_type smu_get_current_power_state(void *handle) 2904 { 2905 struct smu_context *smu = handle; 2906 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT; 2907 2908 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2909 return -EOPNOTSUPP; 2910 2911 mutex_lock(&smu->mutex); 2912 2913 if (smu->ppt_funcs->get_current_power_state) 2914 pm_state = smu->ppt_funcs->get_current_power_state(smu); 2915 2916 mutex_unlock(&smu->mutex); 2917 2918 return pm_state; 2919 } 2920 2921 static int smu_get_dpm_clock_table(void *handle, 2922 struct dpm_clocks *clock_table) 2923 { 2924 struct smu_context *smu = handle; 2925 int ret = 0; 2926 2927 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2928 return -EOPNOTSUPP; 2929 2930 mutex_lock(&smu->mutex); 2931 2932 if (smu->ppt_funcs->get_dpm_clock_table) 2933 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table); 2934 2935 mutex_unlock(&smu->mutex); 2936 2937 return ret; 2938 } 2939 2940 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) 2941 { 2942 struct smu_context *smu = handle; 2943 ssize_t size; 2944 2945 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2946 return -EOPNOTSUPP; 2947 2948 if (!smu->ppt_funcs->get_gpu_metrics) 2949 return -EOPNOTSUPP; 2950 2951 mutex_lock(&smu->mutex); 2952 2953 size = smu->ppt_funcs->get_gpu_metrics(smu, table); 2954 2955 mutex_unlock(&smu->mutex); 2956 2957 return size; 2958 } 2959 2960 static int smu_enable_mgpu_fan_boost(void *handle) 2961 { 2962 struct smu_context *smu = handle; 2963 int ret = 0; 2964 2965 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) 2966 return -EOPNOTSUPP; 2967 2968 mutex_lock(&smu->mutex); 2969 2970 if (smu->ppt_funcs->enable_mgpu_fan_boost) 2971 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu); 2972 2973 mutex_unlock(&smu->mutex); 2974 2975 return ret; 2976 } 2977 2978 static int smu_gfx_state_change_set(void *handle, 2979 uint32_t state) 2980 { 2981 struct smu_context *smu = handle; 2982 int ret = 0; 2983 2984 mutex_lock(&smu->mutex); 2985 if (smu->ppt_funcs->gfx_state_change_set) 2986 ret = smu->ppt_funcs->gfx_state_change_set(smu, state); 2987 mutex_unlock(&smu->mutex); 2988 2989 return ret; 2990 } 2991 2992 int smu_set_light_sbr(struct smu_context *smu, bool enable) 2993 { 2994 int ret = 0; 2995 2996 mutex_lock(&smu->mutex); 2997 if (smu->ppt_funcs->set_light_sbr) 2998 ret = smu->ppt_funcs->set_light_sbr(smu, enable); 2999 mutex_unlock(&smu->mutex); 3000 3001 return ret; 3002 } 3003 3004 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size) 3005 { 3006 struct smu_context *smu = handle; 3007 struct smu_table_context *smu_table = &smu->smu_table; 3008 struct smu_table *memory_pool = &smu_table->memory_pool; 3009 3010 if (!addr || !size) 3011 return -EINVAL; 3012 3013 *addr = NULL; 3014 *size = 0; 3015 mutex_lock(&smu->mutex); 3016 if (memory_pool->bo) { 3017 *addr = memory_pool->cpu_addr; 3018 *size = memory_pool->size; 3019 } 3020 mutex_unlock(&smu->mutex); 3021 3022 return 0; 3023 } 3024 3025 static const struct amd_pm_funcs swsmu_pm_funcs = { 3026 /* export for sysfs */ 3027 .set_fan_control_mode = smu_pp_set_fan_control_mode, 3028 .get_fan_control_mode = smu_get_fan_control_mode, 3029 .set_fan_speed_percent = smu_set_fan_speed_percent, 3030 .get_fan_speed_percent = smu_get_fan_speed_percent, 3031 .force_clock_level = smu_force_ppclk_levels, 3032 .print_clock_levels = smu_print_ppclk_levels, 3033 .force_performance_level = smu_force_performance_level, 3034 .read_sensor = smu_read_sensor, 3035 .get_performance_level = smu_get_performance_level, 3036 .get_current_power_state = smu_get_current_power_state, 3037 .get_fan_speed_rpm = smu_get_fan_speed_rpm, 3038 .set_fan_speed_rpm = smu_set_fan_speed_rpm, 3039 .get_pp_num_states = smu_get_power_num_states, 3040 .get_pp_table = smu_sys_get_pp_table, 3041 .set_pp_table = smu_sys_set_pp_table, 3042 .switch_power_profile = smu_switch_power_profile, 3043 /* export to amdgpu */ 3044 .dispatch_tasks = smu_handle_dpm_task, 3045 .load_firmware = smu_load_microcode, 3046 .set_powergating_by_smu = smu_dpm_set_power_gate, 3047 .set_power_limit = smu_set_power_limit, 3048 .get_power_limit = smu_get_power_limit, 3049 .get_power_profile_mode = smu_get_power_profile_mode, 3050 .set_power_profile_mode = smu_set_power_profile_mode, 3051 .odn_edit_dpm_table = smu_od_edit_dpm_table, 3052 .set_mp1_state = smu_set_mp1_state, 3053 .gfx_state_change_set = smu_gfx_state_change_set, 3054 /* export to DC */ 3055 .get_sclk = smu_get_sclk, 3056 .get_mclk = smu_get_mclk, 3057 .display_configuration_change = smu_display_configuration_change, 3058 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency, 3059 .display_clock_voltage_request = smu_display_clock_voltage_request, 3060 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost, 3061 .set_active_display_count = smu_set_display_count, 3062 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk, 3063 .get_asic_baco_capability = smu_get_baco_capability, 3064 .set_asic_baco_state = smu_baco_set_state, 3065 .get_ppfeature_status = smu_sys_get_pp_feature_mask, 3066 .set_ppfeature_status = smu_sys_set_pp_feature_mask, 3067 .asic_reset_mode_2 = smu_mode2_reset, 3068 .set_df_cstate = smu_set_df_cstate, 3069 .set_xgmi_pstate = smu_set_xgmi_pstate, 3070 .get_gpu_metrics = smu_sys_get_gpu_metrics, 3071 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges, 3072 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch, 3073 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc, 3074 .get_uclk_dpm_states = smu_get_uclk_dpm_states, 3075 .get_dpm_clock_table = smu_get_dpm_clock_table, 3076 .get_smu_prv_buf_details = smu_get_prv_buffer_details, 3077 }; 3078 3079 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 3080 uint64_t event_arg) 3081 { 3082 int ret = -EINVAL; 3083 struct smu_context *smu = &adev->smu; 3084 3085 if (smu->ppt_funcs->wait_for_event) { 3086 mutex_lock(&smu->mutex); 3087 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg); 3088 mutex_unlock(&smu->mutex); 3089 } 3090 3091 return ret; 3092 } 3093