1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2017 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan 24e098bc96SEvan Quan #ifndef _VEGAM_SMUMANAGER_H 25e098bc96SEvan Quan #define _VEGAM_SMUMANAGER_H 26e098bc96SEvan Quan 27e098bc96SEvan Quan 28e098bc96SEvan Quan #include <pp_endian.h> 29e098bc96SEvan Quan #include "smu75_discrete.h" 30e098bc96SEvan Quan #include "smu7_smumgr.h" 31e098bc96SEvan Quan 32e098bc96SEvan Quan #define SMC_RAM_END 0x40000 33e098bc96SEvan Quan 34e098bc96SEvan Quan #define DPMTuning_Uphyst_Shift 0 35e098bc96SEvan Quan #define DPMTuning_Downhyst_Shift 8 36e098bc96SEvan Quan #define DPMTuning_Activity_Shift 16 37e098bc96SEvan Quan 38e098bc96SEvan Quan #define GraphicsDPMTuning_VEGAM 0x001e6400 39e098bc96SEvan Quan #define MemoryDPMTuning_VEGAM 0x000f3c0a 40e098bc96SEvan Quan #define SclkDPMTuning_VEGAM 0x002d000a 41e098bc96SEvan Quan #define MclkDPMTuning_VEGAM 0x001f100a 42e098bc96SEvan Quan 43e098bc96SEvan Quan 44e098bc96SEvan Quan struct vegam_pt_defaults { 45e098bc96SEvan Quan uint8_t SviLoadLineEn; 46e098bc96SEvan Quan uint8_t SviLoadLineVddC; 47e098bc96SEvan Quan uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 48e098bc96SEvan Quan uint8_t TDC_MAWt; 49e098bc96SEvan Quan uint8_t TdcWaterfallCtl; 50e098bc96SEvan Quan uint8_t DTEAmbientTempBase; 51e098bc96SEvan Quan 52e098bc96SEvan Quan uint32_t DisplayCac; 53e098bc96SEvan Quan uint32_t BAPM_TEMP_GRADIENT; 54e098bc96SEvan Quan uint16_t BAPMTI_R[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS]; 55e098bc96SEvan Quan uint16_t BAPMTI_RC[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS]; 56e098bc96SEvan Quan }; 57e098bc96SEvan Quan 58e098bc96SEvan Quan struct vegam_range_table { 59e098bc96SEvan Quan uint32_t trans_lower_frequency; /* in 10khz */ 60e098bc96SEvan Quan uint32_t trans_upper_frequency; 61e098bc96SEvan Quan }; 62e098bc96SEvan Quan 63e098bc96SEvan Quan struct vegam_smumgr { 64e098bc96SEvan Quan struct smu7_smumgr smu7_data; 65e098bc96SEvan Quan uint8_t protected_mode; 66e098bc96SEvan Quan SMU75_Discrete_DpmTable smc_state_table; 67e098bc96SEvan Quan struct SMU75_Discrete_Ulv ulv_setting; 68e098bc96SEvan Quan struct SMU75_Discrete_PmFuses power_tune_table; 69e098bc96SEvan Quan struct vegam_range_table range_table[NUM_SCLK_RANGE]; 70e098bc96SEvan Quan const struct vegam_pt_defaults *power_tune_defaults; 71e098bc96SEvan Quan uint32_t bif_sclk_table[SMU75_MAX_LEVELS_LINK]; 72e098bc96SEvan Quan }; 73e098bc96SEvan Quan 74e098bc96SEvan Quan 75e098bc96SEvan Quan #endif 76