1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smumgr.h" 25 #include "vega10_inc.h" 26 #include "soc15_common.h" 27 #include "pp_debug.h" 28 29 30 /* MP Apertures */ 31 #define MP0_Public 0x03800000 32 #define MP0_SRAM 0x03900000 33 #define MP1_Public 0x03b00000 34 #define MP1_SRAM 0x03c00004 35 36 #define smnMP1_FIRMWARE_FLAGS 0x3010028 37 38 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr) 39 { 40 struct amdgpu_device *adev = hwmgr->adev; 41 uint32_t mp1_fw_flags; 42 43 mp1_fw_flags = RREG32_PCIE(MP1_Public | 44 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 45 46 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) 47 return true; 48 49 return false; 50 } 51 52 /* 53 * Check if SMC has responded to previous message. 54 * 55 * @param smumgr the address of the powerplay hardware manager. 56 * @return TRUE SMC has responded, FALSE otherwise. 57 */ 58 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr) 59 { 60 struct amdgpu_device *adev = hwmgr->adev; 61 uint32_t reg; 62 uint32_t ret; 63 64 if (hwmgr->pp_one_vf) { 65 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103); 66 67 ret = phm_wait_for_register_unequal(hwmgr, reg, 68 0, MP1_C2PMSG_103__CONTENT_MASK); 69 70 if (ret) 71 pr_err("No response from smu\n"); 72 73 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); 74 } else { 75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 76 77 ret = phm_wait_for_register_unequal(hwmgr, reg, 78 0, MP1_C2PMSG_90__CONTENT_MASK); 79 80 if (ret) 81 pr_err("No response from smu\n"); 82 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); 83 } 84 } 85 86 /* 87 * Send a message to the SMC, and do not wait for its response. 88 * @param smumgr the address of the powerplay hardware manager. 89 * @param msg the message to send. 90 * @return Always return 0. 91 */ 92 static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, 93 uint16_t msg) 94 { 95 struct amdgpu_device *adev = hwmgr->adev; 96 97 if (hwmgr->pp_one_vf) { 98 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_101, msg); 99 } else { 100 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 101 } 102 103 return 0; 104 } 105 106 /* 107 * Send a message to the SMC, and wait for its response. 108 * @param hwmgr the address of the powerplay hardware manager. 109 * @param msg the message to send. 110 * @return Always return 0. 111 */ 112 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 113 { 114 struct amdgpu_device *adev = hwmgr->adev; 115 uint32_t ret; 116 117 smu9_wait_for_response(hwmgr); 118 119 if (hwmgr->pp_one_vf) 120 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); 121 else 122 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 123 124 smu9_send_msg_to_smc_without_waiting(hwmgr, msg); 125 126 ret = smu9_wait_for_response(hwmgr); 127 if (ret != 1) 128 pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret); 129 130 return 0; 131 } 132 133 /* 134 * Send a message to the SMC with parameter 135 * @param hwmgr: the address of the powerplay hardware manager. 136 * @param msg: the message to send. 137 * @param parameter: the parameter to send 138 * @return Always return 0. 139 */ 140 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 141 uint16_t msg, uint32_t parameter) 142 { 143 struct amdgpu_device *adev = hwmgr->adev; 144 uint32_t ret; 145 146 smu9_wait_for_response(hwmgr); 147 148 if (hwmgr->pp_one_vf) { 149 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); 150 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter); 151 } else { 152 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 153 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); 154 } 155 156 smu9_send_msg_to_smc_without_waiting(hwmgr, msg); 157 158 ret = smu9_wait_for_response(hwmgr); 159 if (ret != 1) 160 pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret); 161 162 return 0; 163 } 164 165 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr) 166 { 167 struct amdgpu_device *adev = hwmgr->adev; 168 169 if (hwmgr->pp_one_vf) 170 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); 171 else 172 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); 173 } 174