1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "smumgr.h" 25 #include "vega10_inc.h" 26 #include "soc15_common.h" 27 #include "pp_debug.h" 28 29 30 /* MP Apertures */ 31 #define MP0_Public 0x03800000 32 #define MP0_SRAM 0x03900000 33 #define MP1_Public 0x03b00000 34 #define MP1_SRAM 0x03c00004 35 36 #define smnMP1_FIRMWARE_FLAGS 0x3010028 37 38 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr) 39 { 40 struct amdgpu_device *adev = hwmgr->adev; 41 uint32_t mp1_fw_flags; 42 43 mp1_fw_flags = RREG32_PCIE(MP1_Public | 44 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); 45 46 if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) 47 return true; 48 49 return false; 50 } 51 52 /* 53 * Check if SMC has responded to previous message. 54 * 55 * @param smumgr the address of the powerplay hardware manager. 56 * @return TRUE SMC has responded, FALSE otherwise. 57 */ 58 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr) 59 { 60 struct amdgpu_device *adev = hwmgr->adev; 61 uint32_t reg; 62 uint32_t ret; 63 64 /* Due to the L1 policy problem under SRIOV, we have to use 65 * mmMP1_SMN_C2PMSG_103 as the driver response register 66 */ 67 if (hwmgr->pp_one_vf) { 68 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_103); 69 70 ret = phm_wait_for_register_unequal(hwmgr, reg, 71 0, MP1_C2PMSG_103__CONTENT_MASK); 72 73 if (ret) 74 pr_err("No response from smu\n"); 75 76 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103); 77 } else { 78 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); 79 80 ret = phm_wait_for_register_unequal(hwmgr, reg, 81 0, MP1_C2PMSG_90__CONTENT_MASK); 82 83 if (ret) 84 pr_err("No response from smu\n"); 85 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); 86 } 87 } 88 89 /* 90 * Send a message to the SMC, and do not wait for its response. 91 * @param smumgr the address of the powerplay hardware manager. 92 * @param msg the message to send. 93 * @return Always return 0. 94 */ 95 static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, 96 uint16_t msg) 97 { 98 struct amdgpu_device *adev = hwmgr->adev; 99 100 if (hwmgr->pp_one_vf) { 101 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_101, msg); 102 } else { 103 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 104 } 105 106 return 0; 107 } 108 109 /* 110 * Send a message to the SMC, and wait for its response. 111 * @param hwmgr the address of the powerplay hardware manager. 112 * @param msg the message to send. 113 * @return Always return 0. 114 */ 115 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) 116 { 117 struct amdgpu_device *adev = hwmgr->adev; 118 uint32_t ret; 119 120 smu9_wait_for_response(hwmgr); 121 122 if (hwmgr->pp_one_vf) 123 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); 124 else 125 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 126 127 smu9_send_msg_to_smc_without_waiting(hwmgr, msg); 128 129 ret = smu9_wait_for_response(hwmgr); 130 if (ret != 1) 131 pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret); 132 133 return 0; 134 } 135 136 /* 137 * Send a message to the SMC with parameter 138 * @param hwmgr: the address of the powerplay hardware manager. 139 * @param msg: the message to send. 140 * @param parameter: the parameter to send 141 * @return Always return 0. 142 */ 143 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 144 uint16_t msg, uint32_t parameter) 145 { 146 struct amdgpu_device *adev = hwmgr->adev; 147 uint32_t ret; 148 149 smu9_wait_for_response(hwmgr); 150 151 /* Due to the L1 policy problem under SRIOV, we have to use 152 * mmMP1_SMN_C2PMSG_101 as the driver message register and 153 * mmMP1_SMN_C2PMSG_102 as the driver parameter register. 154 */ 155 if (hwmgr->pp_one_vf) { 156 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); 157 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter); 158 } else { 159 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 160 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); 161 } 162 163 smu9_send_msg_to_smc_without_waiting(hwmgr, msg); 164 165 ret = smu9_wait_for_response(hwmgr); 166 if (ret != 1) 167 pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret); 168 169 return 0; 170 } 171 172 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr) 173 { 174 struct amdgpu_device *adev = hwmgr->adev; 175 176 if (hwmgr->pp_one_vf) 177 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102); 178 else 179 return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); 180 } 181