1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2015 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan #ifndef _SMU8_SMUMGR_H_ 24e098bc96SEvan Quan #define _SMU8_SMUMGR_H_ 25e098bc96SEvan Quan 26e098bc96SEvan Quan 27e098bc96SEvan Quan #define MAX_NUM_FIRMWARE 8 28e098bc96SEvan Quan #define MAX_NUM_SCRATCH 11 29e098bc96SEvan Quan #define SMU8_SCRATCH_SIZE_NONGFX_CLOCKGATING 1024 30e098bc96SEvan Quan #define SMU8_SCRATCH_SIZE_NONGFX_GOLDENSETTING 2048 31e098bc96SEvan Quan #define SMU8_SCRATCH_SIZE_SDMA_METADATA 1024 32e098bc96SEvan Quan #define SMU8_SCRATCH_SIZE_IH ((2*256+1)*4) 33e098bc96SEvan Quan 34e098bc96SEvan Quan #define SMU_EnabledFeatureScoreboard_SclkDpmOn 0x00200000 35e098bc96SEvan Quan 36e098bc96SEvan Quan enum smu8_scratch_entry { 37e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0, 38e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_SDMA1, 39e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_CP_CE, 40e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_CP_PFP, 41e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_CP_ME, 42e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, 43e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, 44e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG, 45e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_G, 46e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH, 47e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM, 48e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM, 49e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM, 50e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM, 51e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING, 52e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_HALT, 53e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING, 54e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS, 55e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT, 56e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_DATA_ID_SDMA_START, 57e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS, 58e098bc96SEvan Quan SMU8_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE 59e098bc96SEvan Quan }; 60e098bc96SEvan Quan 61e098bc96SEvan Quan struct smu8_buffer_entry { 62e098bc96SEvan Quan uint32_t data_size; 63e098bc96SEvan Quan uint64_t mc_addr; 64e098bc96SEvan Quan void *kaddr; 65e098bc96SEvan Quan enum smu8_scratch_entry firmware_ID; 66e098bc96SEvan Quan struct amdgpu_bo *handle; /* as bo handle used when release bo */ 67e098bc96SEvan Quan }; 68e098bc96SEvan Quan 69e098bc96SEvan Quan struct smu8_register_index_data_pair { 70e098bc96SEvan Quan uint32_t offset; 71e098bc96SEvan Quan uint32_t value; 72e098bc96SEvan Quan }; 73e098bc96SEvan Quan 74e098bc96SEvan Quan struct smu8_ih_meta_data { 75e098bc96SEvan Quan uint32_t command; 76e098bc96SEvan Quan struct smu8_register_index_data_pair register_index_value_pair[1]; 77e098bc96SEvan Quan }; 78e098bc96SEvan Quan 79e098bc96SEvan Quan struct smu8_smumgr { 80e098bc96SEvan Quan uint8_t driver_buffer_length; 81e098bc96SEvan Quan uint8_t scratch_buffer_length; 82e098bc96SEvan Quan uint16_t toc_entry_used_count; 83e098bc96SEvan Quan uint16_t toc_entry_initialize_index; 84e098bc96SEvan Quan uint16_t toc_entry_power_profiling_index; 85e098bc96SEvan Quan uint16_t toc_entry_aram; 86e098bc96SEvan Quan uint16_t toc_entry_ih_register_restore_task_index; 87e098bc96SEvan Quan uint16_t toc_entry_clock_table; 88e098bc96SEvan Quan uint16_t ih_register_restore_task_size; 89e098bc96SEvan Quan uint16_t smu_buffer_used_bytes; 90e098bc96SEvan Quan 91e098bc96SEvan Quan struct smu8_buffer_entry toc_buffer; 92e098bc96SEvan Quan struct smu8_buffer_entry smu_buffer; 93e098bc96SEvan Quan struct smu8_buffer_entry firmware_buffer; 94e098bc96SEvan Quan struct smu8_buffer_entry driver_buffer[MAX_NUM_FIRMWARE]; 95e098bc96SEvan Quan struct smu8_buffer_entry meta_data_buffer[MAX_NUM_FIRMWARE]; 96e098bc96SEvan Quan struct smu8_buffer_entry scratch_buffer[MAX_NUM_SCRATCH]; 97e098bc96SEvan Quan }; 98e098bc96SEvan Quan 99e098bc96SEvan Quan #endif 100