1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/pci.h> 25 26 #include "pp_debug.h" 27 #include "smumgr.h" 28 #include "smu74.h" 29 #include "smu_ucode_xfer_vi.h" 30 #include "polaris10_smumgr.h" 31 #include "smu74_discrete.h" 32 #include "smu/smu_7_1_3_d.h" 33 #include "smu/smu_7_1_3_sh_mask.h" 34 #include "gmc/gmc_8_1_d.h" 35 #include "gmc/gmc_8_1_sh_mask.h" 36 #include "oss/oss_3_0_d.h" 37 #include "gca/gfx_8_0_d.h" 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 #include "ppatomctrl.h" 41 #include "cgs_common.h" 42 #include "smu7_ppsmc.h" 43 #include "smu7_smumgr.h" 44 45 #include "smu7_dyn_defaults.h" 46 47 #include "smu7_hwmgr.h" 48 #include "hardwaremanager.h" 49 #include "atombios.h" 50 #include "pppcielanes.h" 51 52 #include "dce/dce_10_0_d.h" 53 #include "dce/dce_10_0_sh_mask.h" 54 55 #define POLARIS10_SMC_SIZE 0x20000 56 #define POWERTUNE_DEFAULT_SET_MAX 1 57 #define VDDC_VDDCI_DELTA 200 58 #define MC_CG_ARB_FREQ_F1 0x0b 59 60 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { 61 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, 62 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ 63 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, 64 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, 65 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } }, 66 }; 67 68 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { 69 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112}, 70 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160}, 71 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112}, 72 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160}, 73 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112}, 74 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160}, 75 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108}, 76 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} }; 77 78 #define PPPOLARIS10_TARGETACTIVITY_DFLT 50 79 80 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { 81 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */ 82 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */ 83 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } }, 84 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } }, 85 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }, 86 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } }, 87 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } }, 88 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } }, 89 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } }, 90 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } } 91 }; 92 93 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = { 94 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00}; 95 96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr) 97 { 98 int result = 0; 99 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); 100 101 if (0 != smu_data->avfs_btc_param) { 102 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param, 103 NULL)) { 104 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); 105 result = -1; 106 } 107 } 108 if (smu_data->avfs_btc_param > 1) { 109 /* Soft-Reset to reset the engine before loading uCode */ 110 /* halt */ 111 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000); 112 /* reset everything */ 113 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff); 114 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0); 115 } 116 return result; 117 } 118 119 120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) 121 { 122 uint32_t vr_config; 123 uint32_t dpm_table_start; 124 125 uint16_t u16_boot_mvdd; 126 uint32_t graphics_level_address, vr_config_address, graphics_level_size; 127 128 graphics_level_size = sizeof(avfs_graphics_level_polaris10); 129 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); 130 131 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr, 132 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), 133 &dpm_table_start, 0x40000), 134 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", 135 return -1); 136 137 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */ 138 vr_config = 0x01000500; /* Real value:0x50001 */ 139 140 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); 141 142 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address, 143 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), 144 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", 145 return -1); 146 147 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); 148 149 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, 150 (uint8_t *)(&avfs_graphics_level_polaris10), 151 graphics_level_size, 0x40000), 152 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", 153 return -1); 154 155 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); 156 157 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, 158 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), 159 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", 160 return -1); 161 162 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */ 163 164 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); 165 166 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address, 167 (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), 168 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", 169 return -1); 170 171 return 0; 172 } 173 174 175 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr) 176 { 177 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend); 178 179 if (!hwmgr->avfs_supported) 180 return 0; 181 182 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr), 183 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", 184 return -EINVAL); 185 186 if (smu_data->avfs_btc_param > 1) { 187 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); 188 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr), 189 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", 190 return -EINVAL); 191 } 192 193 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr), 194 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", 195 return -EINVAL); 196 197 return 0; 198 } 199 200 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) 201 { 202 int result = 0; 203 204 /* Wait for smc boot up */ 205 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */ 206 207 /* Assert reset */ 208 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 209 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 210 211 result = smu7_upload_smu_firmware_image(hwmgr); 212 if (result != 0) 213 return result; 214 215 /* Clear status */ 216 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0); 217 218 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 219 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 220 221 /* De-assert reset */ 222 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 223 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 224 225 226 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); 227 228 229 /* Call Test SMU message with 0x20000 offset to trigger SMU start */ 230 smu7_send_msg_to_smc_offset(hwmgr); 231 232 /* Wait done bit to be set */ 233 /* Check pass/failed indicator */ 234 235 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0); 236 237 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 238 SMU_STATUS, SMU_PASS)) 239 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1); 240 241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0); 242 243 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 244 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 245 246 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 247 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 248 249 /* Wait for firmware to initialize */ 250 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 251 252 return result; 253 } 254 255 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) 256 { 257 int result = 0; 258 259 /* wait for smc boot up */ 260 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0); 261 262 /* Clear firmware interrupt enable flag */ 263 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */ 264 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 265 ixFIRMWARE_FLAGS, 0); 266 267 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 268 SMC_SYSCON_RESET_CNTL, 269 rst_reg, 1); 270 271 result = smu7_upload_smu_firmware_image(hwmgr); 272 if (result != 0) 273 return result; 274 275 /* Set smc instruct start point at 0x0 */ 276 smu7_program_jump_on_start(hwmgr); 277 278 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 279 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 280 281 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 282 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 283 284 /* Wait for firmware to initialize */ 285 286 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, 287 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 288 289 return result; 290 } 291 292 static int polaris10_start_smu(struct pp_hwmgr *hwmgr) 293 { 294 int result = 0; 295 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 296 297 /* Only start SMC if SMC RAM is not running */ 298 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) { 299 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); 300 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); 301 302 /* Check if SMU is running in protected mode */ 303 if (smu_data->protected_mode == 0) 304 result = polaris10_start_smu_in_non_protection_mode(hwmgr); 305 else 306 result = polaris10_start_smu_in_protection_mode(hwmgr); 307 308 if (result != 0) 309 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); 310 311 polaris10_avfs_event_mgr(hwmgr); 312 } 313 314 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ 315 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), 316 &(smu_data->smu7_data.soft_regs_start), 0x40000); 317 318 result = smu7_request_smu_load_fw(hwmgr); 319 320 return result; 321 } 322 323 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr) 324 { 325 uint32_t efuse; 326 327 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4)); 328 efuse &= 0x00000001; 329 if (efuse) 330 return true; 331 332 return false; 333 } 334 335 static int polaris10_smu_init(struct pp_hwmgr *hwmgr) 336 { 337 struct polaris10_smumgr *smu_data; 338 339 smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL); 340 if (smu_data == NULL) 341 return -ENOMEM; 342 343 hwmgr->smu_backend = smu_data; 344 345 if (smu7_init(hwmgr)) { 346 kfree(smu_data); 347 return -EINVAL; 348 } 349 350 return 0; 351 } 352 353 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, 354 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, 355 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) 356 { 357 uint32_t i; 358 uint16_t vddci; 359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 360 361 *voltage = *mvdd = 0; 362 363 /* clock - voltage dependency table is empty table */ 364 if (dep_table->count == 0) 365 return -EINVAL; 366 367 for (i = 0; i < dep_table->count; i++) { 368 /* find first sclk bigger than request */ 369 if (dep_table->entries[i].clk >= clock) { 370 *voltage |= (dep_table->entries[i].vddc * 371 VOLTAGE_SCALE) << VDDC_SHIFT; 372 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) 373 *voltage |= (data->vbios_boot_state.vddci_bootup_value * 374 VOLTAGE_SCALE) << VDDCI_SHIFT; 375 else if (dep_table->entries[i].vddci) 376 *voltage |= (dep_table->entries[i].vddci * 377 VOLTAGE_SCALE) << VDDCI_SHIFT; 378 else { 379 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), 380 (dep_table->entries[i].vddc - 381 (uint16_t)VDDC_VDDCI_DELTA)); 382 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 383 } 384 385 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) 386 *mvdd = data->vbios_boot_state.mvdd_bootup_value * 387 VOLTAGE_SCALE; 388 else if (dep_table->entries[i].mvdd) 389 *mvdd = (uint32_t) dep_table->entries[i].mvdd * 390 VOLTAGE_SCALE; 391 392 *voltage |= 1 << PHASES_SHIFT; 393 return 0; 394 } 395 } 396 397 /* sclk is bigger than max sclk in the dependence table */ 398 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 399 400 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control) 401 *voltage |= (data->vbios_boot_state.vddci_bootup_value * 402 VOLTAGE_SCALE) << VDDCI_SHIFT; 403 else if (dep_table->entries[i-1].vddci) { 404 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table), 405 (dep_table->entries[i].vddc - 406 (uint16_t)VDDC_VDDCI_DELTA)); 407 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 408 } 409 410 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) 411 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; 412 else if (dep_table->entries[i].mvdd) 413 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; 414 415 return 0; 416 } 417 418 static uint16_t scale_fan_gain_settings(uint16_t raw_setting) 419 { 420 uint32_t tmp; 421 tmp = raw_setting * 4096 / 100; 422 return (uint16_t)tmp; 423 } 424 425 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 426 { 427 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 428 429 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 430 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 431 struct phm_ppt_v1_information *table_info = 432 (struct phm_ppt_v1_information *)(hwmgr->pptable); 433 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; 434 struct pp_advance_fan_control_parameters *fan_table = 435 &hwmgr->thermal_controller.advanceFanControlParameters; 436 int i, j, k; 437 const uint16_t *pdef1; 438 const uint16_t *pdef2; 439 440 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); 441 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128)); 442 443 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, 444 "Target Operating Temp is out of Range!", 445 ); 446 447 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( 448 cac_dtp_table->usTargetOperatingTemp * 256); 449 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( 450 cac_dtp_table->usTemperatureLimitHotspot * 256); 451 table->FanGainEdge = PP_HOST_TO_SMC_US( 452 scale_fan_gain_settings(fan_table->usFanGainEdge)); 453 table->FanGainHotspot = PP_HOST_TO_SMC_US( 454 scale_fan_gain_settings(fan_table->usFanGainHotspot)); 455 456 pdef1 = defaults->BAPMTI_R; 457 pdef2 = defaults->BAPMTI_RC; 458 459 for (i = 0; i < SMU74_DTE_ITERATIONS; i++) { 460 for (j = 0; j < SMU74_DTE_SOURCES; j++) { 461 for (k = 0; k < SMU74_DTE_SINKS; k++) { 462 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1); 463 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2); 464 pdef1++; 465 pdef2++; 466 } 467 } 468 } 469 470 return 0; 471 } 472 473 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) 474 { 475 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 476 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 477 478 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; 479 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; 480 smu_data->power_tune_table.SviLoadLineTrimVddC = 3; 481 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; 482 483 return 0; 484 } 485 486 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) 487 { 488 uint16_t tdc_limit; 489 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 490 struct phm_ppt_v1_information *table_info = 491 (struct phm_ppt_v1_information *)(hwmgr->pptable); 492 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 493 494 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128); 495 smu_data->power_tune_table.TDC_VDDC_PkgLimit = 496 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); 497 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 498 defaults->TDC_VDDC_ThrottleReleaseLimitPerc; 499 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt; 500 501 return 0; 502 } 503 504 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 505 { 506 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 507 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults; 508 uint32_t temp; 509 510 if (smu7_read_smc_sram_dword(hwmgr, 511 fuse_table_offset + 512 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), 513 (uint32_t *)&temp, SMC_RAM_END)) 514 PP_ASSERT_WITH_CODE(false, 515 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!", 516 return -EINVAL); 517 else { 518 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl; 519 smu_data->power_tune_table.LPMLTemperatureMin = 520 (uint8_t)((temp >> 16) & 0xff); 521 smu_data->power_tune_table.LPMLTemperatureMax = 522 (uint8_t)((temp >> 8) & 0xff); 523 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff); 524 } 525 return 0; 526 } 527 528 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) 529 { 530 int i; 531 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 532 533 /* Currently not used. Set all to zero. */ 534 for (i = 0; i < 16; i++) 535 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; 536 537 return 0; 538 } 539 540 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) 541 { 542 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 543 544 /* TO DO move to hwmgr */ 545 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) 546 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) 547 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 548 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity; 549 550 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US( 551 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity); 552 return 0; 553 } 554 555 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) 556 { 557 int i; 558 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 559 560 /* Currently not used. Set all to zero. */ 561 for (i = 0; i < 16; i++) 562 smu_data->power_tune_table.GnbLPML[i] = 0; 563 564 return 0; 565 } 566 567 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 568 { 569 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 570 struct phm_ppt_v1_information *table_info = 571 (struct phm_ppt_v1_information *)(hwmgr->pptable); 572 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 573 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; 574 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; 575 576 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); 577 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); 578 579 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd = 580 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd); 581 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd = 582 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd); 583 584 return 0; 585 } 586 587 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) 588 { 589 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 590 uint32_t pm_fuse_table_offset; 591 592 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 593 PHM_PlatformCaps_PowerContainment)) { 594 if (smu7_read_smc_sram_dword(hwmgr, 595 SMU7_FIRMWARE_HEADER_LOCATION + 596 offsetof(SMU74_Firmware_Header, PmFuseTable), 597 &pm_fuse_table_offset, SMC_RAM_END)) 598 PP_ASSERT_WITH_CODE(false, 599 "Attempt to get pm_fuse_table_offset Failed!", 600 return -EINVAL); 601 602 if (polaris10_populate_svi_load_line(hwmgr)) 603 PP_ASSERT_WITH_CODE(false, 604 "Attempt to populate SviLoadLine Failed!", 605 return -EINVAL); 606 607 if (polaris10_populate_tdc_limit(hwmgr)) 608 PP_ASSERT_WITH_CODE(false, 609 "Attempt to populate TDCLimit Failed!", return -EINVAL); 610 611 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset)) 612 PP_ASSERT_WITH_CODE(false, 613 "Attempt to populate TdcWaterfallCtl, " 614 "LPMLTemperature Min and Max Failed!", 615 return -EINVAL); 616 617 if (0 != polaris10_populate_temperature_scaler(hwmgr)) 618 PP_ASSERT_WITH_CODE(false, 619 "Attempt to populate LPMLTemperatureScaler Failed!", 620 return -EINVAL); 621 622 if (polaris10_populate_fuzzy_fan(hwmgr)) 623 PP_ASSERT_WITH_CODE(false, 624 "Attempt to populate Fuzzy Fan Control parameters Failed!", 625 return -EINVAL); 626 627 if (polaris10_populate_gnb_lpml(hwmgr)) 628 PP_ASSERT_WITH_CODE(false, 629 "Attempt to populate GnbLPML Failed!", 630 return -EINVAL); 631 632 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr)) 633 PP_ASSERT_WITH_CODE(false, 634 "Attempt to populate BapmVddCBaseLeakage Hi and Lo " 635 "Sidd Failed!", return -EINVAL); 636 637 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, 638 (uint8_t *)&smu_data->power_tune_table, 639 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END)) 640 PP_ASSERT_WITH_CODE(false, 641 "Attempt to download PmFuseTable Failed!", 642 return -EINVAL); 643 } 644 return 0; 645 } 646 647 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, 648 SMU74_Discrete_DpmTable *table) 649 { 650 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 651 uint32_t count, level; 652 653 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 654 count = data->mvdd_voltage_table.count; 655 if (count > SMU_MAX_SMIO_LEVELS) 656 count = SMU_MAX_SMIO_LEVELS; 657 for (level = 0; level < count; level++) { 658 table->SmioTable2.Pattern[level].Voltage = 659 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE); 660 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ 661 table->SmioTable2.Pattern[level].Smio = 662 (uint8_t) level; 663 table->Smio[level] |= 664 data->mvdd_voltage_table.entries[level].smio_low; 665 } 666 table->SmioMask2 = data->mvdd_voltage_table.mask_low; 667 668 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count); 669 } 670 671 return 0; 672 } 673 674 static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, 675 struct SMU74_Discrete_DpmTable *table) 676 { 677 uint32_t count, level; 678 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 679 680 count = data->vddc_voltage_table.count; 681 682 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { 683 if (count > SMU_MAX_SMIO_LEVELS) 684 count = SMU_MAX_SMIO_LEVELS; 685 for (level = 0; level < count; ++level) { 686 table->SmioTable1.Pattern[level].Voltage = 687 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE); 688 table->SmioTable1.Pattern[level].Smio = (uint8_t) level; 689 690 table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low; 691 } 692 693 table->SmioMask1 = data->vddc_voltage_table.mask_low; 694 } 695 696 return 0; 697 } 698 699 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, 700 struct SMU74_Discrete_DpmTable *table) 701 { 702 uint32_t count, level; 703 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 704 705 count = data->vddci_voltage_table.count; 706 707 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 708 if (count > SMU_MAX_SMIO_LEVELS) 709 count = SMU_MAX_SMIO_LEVELS; 710 for (level = 0; level < count; ++level) { 711 table->SmioTable1.Pattern[level].Voltage = 712 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE); 713 table->SmioTable1.Pattern[level].Smio = (uint8_t) level; 714 715 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low; 716 } 717 718 table->SmioMask1 = data->vddci_voltage_table.mask_low; 719 } 720 721 return 0; 722 } 723 724 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr, 725 struct SMU74_Discrete_DpmTable *table) 726 { 727 uint32_t count; 728 uint8_t index; 729 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 730 struct phm_ppt_v1_information *table_info = 731 (struct phm_ppt_v1_information *)(hwmgr->pptable); 732 struct phm_ppt_v1_voltage_lookup_table *lookup_table = 733 table_info->vddc_lookup_table; 734 /* tables is already swapped, so in order to use the value from it, 735 * we need to swap it back. 736 * We are populating vddc CAC data to BapmVddc table 737 * in split and merged mode 738 */ 739 for (count = 0; count < lookup_table->count; count++) { 740 index = phm_get_voltage_index(lookup_table, 741 data->vddc_voltage_table.entries[count].value); 742 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low); 743 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid); 744 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high); 745 } 746 747 return 0; 748 } 749 750 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, 751 struct SMU74_Discrete_DpmTable *table) 752 { 753 polaris10_populate_smc_vddc_table(hwmgr, table); 754 polaris10_populate_smc_vddci_table(hwmgr, table); 755 polaris10_populate_smc_mvdd_table(hwmgr, table); 756 polaris10_populate_cac_table(hwmgr, table); 757 758 return 0; 759 } 760 761 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, 762 struct SMU74_Discrete_Ulv *state) 763 { 764 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 765 struct phm_ppt_v1_information *table_info = 766 (struct phm_ppt_v1_information *)(hwmgr->pptable); 767 768 state->CcPwrDynRm = 0; 769 state->CcPwrDynRm1 = 0; 770 771 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; 772 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * 773 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 774 775 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) 776 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3; 777 else 778 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1; 779 780 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); 781 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); 782 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); 783 784 return 0; 785 } 786 787 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr, 788 struct SMU74_Discrete_DpmTable *table) 789 { 790 return polaris10_populate_ulv_level(hwmgr, &table->Ulv); 791 } 792 793 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, 794 struct SMU74_Discrete_DpmTable *table) 795 { 796 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 797 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 798 struct smu7_dpm_table *dpm_table = &data->dpm_table; 799 int i; 800 801 /* Index (dpm_table->pcie_speed_table.count) 802 * is reserved for PCIE boot level. */ 803 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 804 table->LinkLevel[i].PcieGenSpeed = 805 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 806 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( 807 dpm_table->pcie_speed_table.dpm_levels[i].param1); 808 table->LinkLevel[i].EnabledForActivity = 1; 809 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); 810 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); 811 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); 812 } 813 814 smu_data->smc_state_table.LinkLevelCount = 815 (uint8_t)dpm_table->pcie_speed_table.count; 816 817 /* To Do move to hwmgr */ 818 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 819 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 820 821 return 0; 822 } 823 824 825 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr, 826 SMU74_Discrete_DpmTable *table) 827 { 828 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 829 uint32_t i, ref_clk; 830 831 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; 832 833 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 834 835 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { 836 for (i = 0; i < NUM_SCLK_RANGE; i++) { 837 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting; 838 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; 839 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc; 840 841 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper; 842 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower; 843 844 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); 845 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); 846 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); 847 } 848 return; 849 } 850 851 for (i = 0; i < NUM_SCLK_RANGE; i++) { 852 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; 853 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; 854 855 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting; 856 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; 857 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc; 858 859 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper; 860 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower; 861 862 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc); 863 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper); 864 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower); 865 } 866 } 867 868 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, 869 uint32_t clock, SMU_SclkSetting *sclk_setting) 870 { 871 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 872 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 873 struct pp_atomctrl_clock_dividers_ai dividers; 874 uint32_t ref_clock; 875 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq; 876 uint8_t i; 877 int result; 878 uint64_t temp; 879 880 sclk_setting->SclkFrequency = clock; 881 /* get the engine clock dividers for this clock value */ 882 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); 883 if (result == 0) { 884 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; 885 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; 886 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; 887 sclk_setting->PllRange = dividers.ucSclkPllRange; 888 sclk_setting->Sclk_slew_rate = 0x400; 889 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; 890 sclk_setting->Pcc_down_slew_rate = 0xffff; 891 sclk_setting->SSc_En = dividers.ucSscEnable; 892 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; 893 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; 894 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; 895 return result; 896 } 897 898 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 899 900 for (i = 0; i < NUM_SCLK_RANGE; i++) { 901 if (clock > smu_data->range_table[i].trans_lower_frequency 902 && clock <= smu_data->range_table[i].trans_upper_frequency) { 903 sclk_setting->PllRange = i; 904 break; 905 } 906 } 907 908 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); 909 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; 910 temp <<= 0x10; 911 do_div(temp, ref_clock); 912 sclk_setting->Fcw_frac = temp & 0xffff; 913 914 pcc_target_percent = 10; /* Hardcode 10% for now. */ 915 pcc_target_freq = clock - (clock * pcc_target_percent / 100); 916 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); 917 918 ss_target_percent = 2; /* Hardcode 2% for now. */ 919 sclk_setting->SSc_En = 0; 920 if (ss_target_percent) { 921 sclk_setting->SSc_En = 1; 922 ss_target_freq = clock - (clock * ss_target_percent / 100); 923 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); 924 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; 925 temp <<= 0x10; 926 do_div(temp, ref_clock); 927 sclk_setting->Fcw1_frac = temp & 0xffff; 928 } 929 930 return 0; 931 } 932 933 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, 934 uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level) 935 { 936 int result; 937 /* PP_Clocks minClocks; */ 938 uint32_t mvdd; 939 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 940 struct phm_ppt_v1_information *table_info = 941 (struct phm_ppt_v1_information *)(hwmgr->pptable); 942 SMU_SclkSetting curr_sclk_setting = { 0 }; 943 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL; 944 945 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); 946 947 if (hwmgr->od_enabled) 948 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk; 949 else 950 vdd_dep_table = table_info->vdd_dep_on_sclk; 951 952 /* populate graphics levels */ 953 result = polaris10_get_dependency_volt_by_clk(hwmgr, 954 vdd_dep_table, clock, 955 &level->MinVoltage, &mvdd); 956 957 PP_ASSERT_WITH_CODE((0 == result), 958 "can not find VDDC voltage value for " 959 "VDDC engine clock dependency table", 960 return result); 961 level->ActivityLevel = data->current_profile_setting.sclk_activity; 962 963 level->CcPwrDynRm = 0; 964 level->CcPwrDynRm1 = 0; 965 level->EnabledForActivity = 0; 966 level->EnabledForThrottle = 1; 967 level->UpHyst = data->current_profile_setting.sclk_up_hyst; 968 level->DownHyst = data->current_profile_setting.sclk_down_hyst; 969 level->VoltageDownHyst = 0; 970 level->PowerThrottle = 0; 971 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; 972 973 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) 974 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock, 975 hwmgr->display_config->min_core_set_clock_in_sr); 976 977 /* Default to slow, highest DPM level will be 978 * set to PPSMC_DISPLAY_WATERMARK_LOW later. 979 */ 980 if (data->update_up_hyst) 981 level->UpHyst = (uint8_t)data->up_hyst; 982 if (data->update_down_hyst) 983 level->DownHyst = (uint8_t)data->down_hyst; 984 985 level->SclkSetting = curr_sclk_setting; 986 987 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage); 988 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm); 989 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1); 990 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel); 991 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency); 992 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int); 993 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac); 994 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int); 995 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate); 996 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate); 997 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate); 998 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int); 999 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac); 1000 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate); 1001 return 0; 1002 } 1003 1004 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 1005 { 1006 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1007 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1008 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 1009 struct phm_ppt_v1_information *table_info = 1010 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1011 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; 1012 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; 1013 int result = 0; 1014 uint32_t array = smu_data->smu7_data.dpm_table_start + 1015 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); 1016 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) * 1017 SMU74_MAX_LEVELS_GRAPHICS; 1018 struct SMU74_Discrete_GraphicsLevel *levels = 1019 smu_data->smc_state_table.GraphicsLevel; 1020 uint32_t i, max_entry; 1021 uint8_t hightest_pcie_level_enabled = 0, 1022 lowest_pcie_level_enabled = 0, 1023 mid_pcie_level_enabled = 0, 1024 count = 0; 1025 struct amdgpu_device *adev = hwmgr->adev; 1026 pp_atomctrl_clock_dividers_vi dividers; 1027 uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency; 1028 1029 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); 1030 1031 for (i = 0; i < dpm_table->sclk_table.count; i++) { 1032 1033 result = polaris10_populate_single_graphic_level(hwmgr, 1034 dpm_table->sclk_table.dpm_levels[i].value, 1035 &(smu_data->smc_state_table.GraphicsLevel[i])); 1036 if (result) 1037 return result; 1038 1039 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ 1040 if (i > 1) 1041 levels[i].DeepSleepDivId = 0; 1042 } 1043 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1044 PHM_PlatformCaps_SPLLShutdownSupport)) { 1045 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; 1046 if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) { 1047 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1048 dpm_table->sclk_table.dpm_levels[0].value, 1049 ÷rs); 1050 PP_ASSERT_WITH_CODE((0 == result), 1051 "can not find divide id for sclk", 1052 return result); 1053 smum_send_msg_to_smc_with_parameter(hwmgr, 1054 PPSMC_MSG_SetGpuPllDfsForSclk, 1055 dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ? 1056 dividers.pll_post_divider - 1 : dividers.pll_post_divider, 1057 NULL); 1058 } 1059 } 1060 1061 smu_data->smc_state_table.GraphicsDpmLevelCount = 1062 (uint8_t)dpm_table->sclk_table.count; 1063 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = 1064 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 1065 1066 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) 1067 smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity = 1068 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i; 1069 1070 if (pcie_table != NULL) { 1071 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt), 1072 "There must be 1 or more PCIE levels defined in PPTable.", 1073 return -EINVAL); 1074 max_entry = pcie_entry_cnt - 1; 1075 for (i = 0; i < dpm_table->sclk_table.count; i++) 1076 levels[i].pcieDpmLevel = 1077 (uint8_t) ((i < max_entry) ? i : max_entry); 1078 } else { 1079 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && 1080 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & 1081 (1 << (hightest_pcie_level_enabled + 1))) != 0)) 1082 hightest_pcie_level_enabled++; 1083 1084 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && 1085 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & 1086 (1 << lowest_pcie_level_enabled)) == 0)) 1087 lowest_pcie_level_enabled++; 1088 1089 while ((count < hightest_pcie_level_enabled) && 1090 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & 1091 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0)) 1092 count++; 1093 1094 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) < 1095 hightest_pcie_level_enabled ? 1096 (lowest_pcie_level_enabled + 1 + count) : 1097 hightest_pcie_level_enabled; 1098 1099 /* set pcieDpmLevel to hightest_pcie_level_enabled */ 1100 for (i = 2; i < dpm_table->sclk_table.count; i++) 1101 levels[i].pcieDpmLevel = hightest_pcie_level_enabled; 1102 1103 /* set pcieDpmLevel to lowest_pcie_level_enabled */ 1104 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; 1105 1106 /* set pcieDpmLevel to mid_pcie_level_enabled */ 1107 levels[1].pcieDpmLevel = mid_pcie_level_enabled; 1108 } 1109 /* level count will send to smc once at init smc table and never change */ 1110 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, 1111 (uint32_t)array_size, SMC_RAM_END); 1112 1113 return result; 1114 } 1115 1116 1117 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, 1118 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) 1119 { 1120 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1121 struct phm_ppt_v1_information *table_info = 1122 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1123 int result = 0; 1124 uint32_t mclk_stutter_mode_threshold = 40000; 1125 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL; 1126 1127 1128 if (hwmgr->od_enabled) 1129 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk; 1130 else 1131 vdd_dep_table = table_info->vdd_dep_on_mclk; 1132 1133 if (vdd_dep_table) { 1134 result = polaris10_get_dependency_volt_by_clk(hwmgr, 1135 vdd_dep_table, clock, 1136 &mem_level->MinVoltage, &mem_level->MinMvdd); 1137 PP_ASSERT_WITH_CODE((0 == result), 1138 "can not find MinVddc voltage value from memory " 1139 "VDDC voltage dependency table", return result); 1140 } 1141 1142 mem_level->MclkFrequency = clock; 1143 mem_level->EnabledForThrottle = 1; 1144 mem_level->EnabledForActivity = 0; 1145 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst; 1146 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst; 1147 mem_level->VoltageDownHyst = 0; 1148 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity; 1149 mem_level->StutterEnable = false; 1150 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1151 1152 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; 1153 data->display_timing.vrefresh = hwmgr->display_config->vrefresh; 1154 1155 if (mclk_stutter_mode_threshold && 1156 (clock <= mclk_stutter_mode_threshold) && 1157 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, 1158 STUTTER_ENABLE) & 0x1) && 1159 (data->display_timing.num_existing_displays <= 2) && 1160 data->display_timing.num_existing_displays) 1161 mem_level->StutterEnable = true; 1162 1163 if (!result) { 1164 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd); 1165 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency); 1166 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel); 1167 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage); 1168 } 1169 return result; 1170 } 1171 1172 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1173 { 1174 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1175 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1176 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; 1177 int result; 1178 /* populate MCLK dpm table to SMU7 */ 1179 uint32_t array = smu_data->smu7_data.dpm_table_start + 1180 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); 1181 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) * 1182 SMU74_MAX_LEVELS_MEMORY; 1183 struct SMU74_Discrete_MemoryLevel *levels = 1184 smu_data->smc_state_table.MemoryLevel; 1185 uint32_t i; 1186 1187 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1188 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1189 "can not populate memory level as memory clock is zero", 1190 return -EINVAL); 1191 result = polaris10_populate_single_memory_level(hwmgr, 1192 dpm_table->mclk_table.dpm_levels[i].value, 1193 &levels[i]); 1194 if (i == dpm_table->mclk_table.count - 1) 1195 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1196 if (result) 1197 return result; 1198 } 1199 1200 smu_data->smc_state_table.MemoryDpmLevelCount = 1201 (uint8_t)dpm_table->mclk_table.count; 1202 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = 1203 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1204 1205 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) 1206 smu_data->smc_state_table.MemoryLevel[i].EnabledForActivity = 1207 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i; 1208 1209 /* level count will send to smc once at init smc table and never change */ 1210 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, 1211 (uint32_t)array_size, SMC_RAM_END); 1212 1213 return result; 1214 } 1215 1216 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr, 1217 uint32_t mclk, SMIO_Pattern *smio_pat) 1218 { 1219 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1220 struct phm_ppt_v1_information *table_info = 1221 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1222 uint32_t i = 0; 1223 1224 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { 1225 /* find mvdd value which clock is more than request */ 1226 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { 1227 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { 1228 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value; 1229 break; 1230 } 1231 } 1232 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, 1233 "MVDD Voltage is outside the supported range.", 1234 return -EINVAL); 1235 } else 1236 return -EINVAL; 1237 1238 return 0; 1239 } 1240 1241 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, 1242 SMU74_Discrete_DpmTable *table) 1243 { 1244 int result = 0; 1245 uint32_t sclk_frequency; 1246 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1247 struct phm_ppt_v1_information *table_info = 1248 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1249 SMIO_Pattern vol_level; 1250 uint32_t mvdd; 1251 1252 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1253 1254 /* Get MinVoltage and Frequency from DPM0, 1255 * already converted to SMC_UL */ 1256 sclk_frequency = data->vbios_boot_state.sclk_bootup_value; 1257 result = polaris10_get_dependency_volt_by_clk(hwmgr, 1258 table_info->vdd_dep_on_sclk, 1259 sclk_frequency, 1260 &table->ACPILevel.MinVoltage, &mvdd); 1261 PP_ASSERT_WITH_CODE((0 == result), 1262 "Cannot find ACPI VDDC voltage value " 1263 "in Clock Dependency Table", 1264 ); 1265 1266 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); 1267 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result); 1268 1269 table->ACPILevel.DeepSleepDivId = 0; 1270 table->ACPILevel.CcPwrDynRm = 0; 1271 table->ACPILevel.CcPwrDynRm1 = 0; 1272 1273 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); 1274 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); 1275 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); 1276 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); 1277 1278 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency); 1279 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int); 1280 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac); 1281 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int); 1282 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate); 1283 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate); 1284 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate); 1285 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int); 1286 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac); 1287 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate); 1288 1289 1290 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ 1291 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value; 1292 result = polaris10_get_dependency_volt_by_clk(hwmgr, 1293 table_info->vdd_dep_on_mclk, 1294 table->MemoryACPILevel.MclkFrequency, 1295 &table->MemoryACPILevel.MinVoltage, &mvdd); 1296 PP_ASSERT_WITH_CODE((0 == result), 1297 "Cannot find ACPI VDDCI voltage value " 1298 "in Clock Dependency Table", 1299 ); 1300 1301 if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) || 1302 (data->mclk_dpm_key_disabled))) 1303 polaris10_populate_mvdd_value(hwmgr, 1304 data->dpm_table.mclk_table.dpm_levels[0].value, 1305 &vol_level); 1306 1307 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level)) 1308 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); 1309 else 1310 table->MemoryACPILevel.MinMvdd = 0; 1311 1312 table->MemoryACPILevel.StutterEnable = false; 1313 1314 table->MemoryACPILevel.EnabledForThrottle = 0; 1315 table->MemoryACPILevel.EnabledForActivity = 0; 1316 table->MemoryACPILevel.UpHyst = 0; 1317 table->MemoryACPILevel.DownHyst = 100; 1318 table->MemoryACPILevel.VoltageDownHyst = 0; 1319 /* To align with the settings from other OSes */ 1320 table->MemoryACPILevel.ActivityLevel = 1321 PP_HOST_TO_SMC_US(data->current_profile_setting.sclk_activity); 1322 1323 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency); 1324 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage); 1325 1326 return result; 1327 } 1328 1329 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr, 1330 SMU74_Discrete_DpmTable *table) 1331 { 1332 int result = -EINVAL; 1333 uint8_t count; 1334 struct pp_atomctrl_clock_dividers_vi dividers; 1335 struct phm_ppt_v1_information *table_info = 1336 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1337 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1338 table_info->mm_dep_table; 1339 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1340 uint32_t vddci; 1341 1342 table->VceLevelCount = (uint8_t)(mm_table->count); 1343 table->VceBootLevel = 0; 1344 1345 for (count = 0; count < table->VceLevelCount; count++) { 1346 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; 1347 table->VceLevel[count].MinVoltage = 0; 1348 table->VceLevel[count].MinVoltage |= 1349 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 1350 1351 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) 1352 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), 1353 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1354 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) 1355 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; 1356 else 1357 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; 1358 1359 1360 table->VceLevel[count].MinVoltage |= 1361 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 1362 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT; 1363 1364 /*retrieve divider value for VBIOS */ 1365 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1366 table->VceLevel[count].Frequency, ÷rs); 1367 PP_ASSERT_WITH_CODE((0 == result), 1368 "can not find divide id for VCE engine clock", 1369 return result); 1370 1371 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; 1372 1373 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); 1374 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage); 1375 } 1376 return result; 1377 } 1378 1379 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr, 1380 SMU74_Discrete_DpmTable *table) 1381 { 1382 int result = -EINVAL; 1383 uint8_t count; 1384 struct pp_atomctrl_clock_dividers_vi dividers; 1385 struct phm_ppt_v1_information *table_info = 1386 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1387 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1388 table_info->mm_dep_table; 1389 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1390 uint32_t vddci; 1391 1392 table->SamuLevelCount = (uint8_t)(mm_table->count); 1393 table->SamuBootLevel = 0; 1394 1395 for (count = 0; count < table->SamuLevelCount; count++) { 1396 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; 1397 table->SamuLevel[count].MinVoltage |= 1398 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 1399 1400 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) 1401 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), 1402 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1403 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) 1404 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; 1405 else 1406 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; 1407 1408 1409 table->SamuLevel[count].MinVoltage |= 1410 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 1411 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT; 1412 1413 /*retrieve divider value for VBIOS */ 1414 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1415 table->SamuLevel[count].Frequency, ÷rs); 1416 PP_ASSERT_WITH_CODE((0 == result), 1417 "can not find divide id for VCE engine clock", 1418 return result); 1419 1420 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; 1421 1422 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); 1423 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage); 1424 } 1425 return result; 1426 } 1427 1428 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, 1429 int32_t eng_clock, int32_t mem_clock, 1430 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) 1431 { 1432 uint32_t dram_timing; 1433 uint32_t dram_timing2; 1434 uint32_t burst_time; 1435 int result; 1436 1437 result = atomctrl_set_engine_dram_timings_rv770(hwmgr, 1438 eng_clock, mem_clock); 1439 PP_ASSERT_WITH_CODE(result == 0, 1440 "Error calling VBIOS to set DRAM_TIMING.", return result); 1441 1442 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 1443 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 1444 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); 1445 1446 1447 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing); 1448 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2); 1449 arb_regs->McArbBurstTime = (uint8_t)burst_time; 1450 1451 return 0; 1452 } 1453 1454 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1455 { 1456 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1457 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1458 struct SMU74_Discrete_MCArbDramTimingTable arb_regs; 1459 uint32_t i, j; 1460 int result = 0; 1461 1462 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { 1463 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { 1464 result = polaris10_populate_memory_timing_parameters(hwmgr, 1465 hw_data->dpm_table.sclk_table.dpm_levels[i].value, 1466 hw_data->dpm_table.mclk_table.dpm_levels[j].value, 1467 &arb_regs.entries[i][j]); 1468 if (result == 0) 1469 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); 1470 if (result != 0) 1471 return result; 1472 } 1473 } 1474 1475 result = smu7_copy_bytes_to_smc( 1476 hwmgr, 1477 smu_data->smu7_data.arb_table_start, 1478 (uint8_t *)&arb_regs, 1479 sizeof(SMU74_Discrete_MCArbDramTimingTable), 1480 SMC_RAM_END); 1481 return result; 1482 } 1483 1484 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, 1485 struct SMU74_Discrete_DpmTable *table) 1486 { 1487 int result = -EINVAL; 1488 uint8_t count; 1489 struct pp_atomctrl_clock_dividers_vi dividers; 1490 struct phm_ppt_v1_information *table_info = 1491 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1492 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1493 table_info->mm_dep_table; 1494 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1495 uint32_t vddci; 1496 1497 table->UvdLevelCount = (uint8_t)(mm_table->count); 1498 table->UvdBootLevel = 0; 1499 1500 for (count = 0; count < table->UvdLevelCount; count++) { 1501 table->UvdLevel[count].MinVoltage = 0; 1502 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; 1503 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; 1504 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * 1505 VOLTAGE_SCALE) << VDDC_SHIFT; 1506 1507 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) 1508 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table), 1509 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1510 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) 1511 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA; 1512 else 1513 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; 1514 1515 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; 1516 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT; 1517 1518 /* retrieve divider value for VBIOS */ 1519 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1520 table->UvdLevel[count].VclkFrequency, ÷rs); 1521 PP_ASSERT_WITH_CODE((0 == result), 1522 "can not find divide id for Vclk clock", return result); 1523 1524 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; 1525 1526 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1527 table->UvdLevel[count].DclkFrequency, ÷rs); 1528 PP_ASSERT_WITH_CODE((0 == result), 1529 "can not find divide id for Dclk clock", return result); 1530 1531 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider; 1532 1533 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); 1534 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); 1535 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage); 1536 } 1537 1538 return result; 1539 } 1540 1541 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, 1542 struct SMU74_Discrete_DpmTable *table) 1543 { 1544 int result = 0; 1545 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1546 1547 table->GraphicsBootLevel = 0; 1548 table->MemoryBootLevel = 0; 1549 1550 /* find boot level from dpm table */ 1551 result = phm_find_boot_level(&(data->dpm_table.sclk_table), 1552 data->vbios_boot_state.sclk_bootup_value, 1553 (uint32_t *)&(table->GraphicsBootLevel)); 1554 1555 result = phm_find_boot_level(&(data->dpm_table.mclk_table), 1556 data->vbios_boot_state.mclk_bootup_value, 1557 (uint32_t *)&(table->MemoryBootLevel)); 1558 1559 table->BootVddc = data->vbios_boot_state.vddc_bootup_value * 1560 VOLTAGE_SCALE; 1561 table->BootVddci = data->vbios_boot_state.vddci_bootup_value * 1562 VOLTAGE_SCALE; 1563 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value * 1564 VOLTAGE_SCALE; 1565 1566 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc); 1567 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci); 1568 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); 1569 1570 return 0; 1571 } 1572 1573 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) 1574 { 1575 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1576 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1577 struct phm_ppt_v1_information *table_info = 1578 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1579 uint8_t count, level; 1580 1581 count = (uint8_t)(table_info->vdd_dep_on_sclk->count); 1582 1583 for (level = 0; level < count; level++) { 1584 if (table_info->vdd_dep_on_sclk->entries[level].clk >= 1585 hw_data->vbios_boot_state.sclk_bootup_value) { 1586 smu_data->smc_state_table.GraphicsBootLevel = level; 1587 break; 1588 } 1589 } 1590 1591 count = (uint8_t)(table_info->vdd_dep_on_mclk->count); 1592 for (level = 0; level < count; level++) { 1593 if (table_info->vdd_dep_on_mclk->entries[level].clk >= 1594 hw_data->vbios_boot_state.mclk_bootup_value) { 1595 smu_data->smc_state_table.MemoryBootLevel = level; 1596 break; 1597 } 1598 } 1599 1600 return 0; 1601 } 1602 1603 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 1604 { 1605 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min; 1606 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1607 1608 uint8_t i, stretch_amount, volt_offset = 0; 1609 struct phm_ppt_v1_information *table_info = 1610 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1611 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1612 table_info->vdd_dep_on_sclk; 1613 1614 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; 1615 1616 /* Read SMU_Eefuse to read and calculate RO and determine 1617 * if the part is SS or FF. if RO >= 1660MHz, part is FF. 1618 */ 1619 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1620 ixSMU_EFUSE_0 + (67 * 4)); 1621 efuse &= 0xFF000000; 1622 efuse = efuse >> 24; 1623 1624 if (hwmgr->chip_id == CHIP_POLARIS10) { 1625 if (hwmgr->is_kicker) { 1626 min = 1200; 1627 max = 2500; 1628 } else { 1629 min = 1000; 1630 max = 2300; 1631 } 1632 } else if (hwmgr->chip_id == CHIP_POLARIS11) { 1633 if (hwmgr->is_kicker) { 1634 min = 900; 1635 max = 2100; 1636 } else { 1637 min = 1100; 1638 max = 2100; 1639 } 1640 } else { 1641 min = 1100; 1642 max = 2100; 1643 } 1644 1645 ro = efuse * (max - min) / 255 + min; 1646 1647 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ 1648 for (i = 0; i < sclk_table->count; i++) { 1649 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= 1650 sclk_table->entries[i].cks_enable << i; 1651 if (hwmgr->chip_id == CHIP_POLARIS10) { 1652 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \ 1653 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); 1654 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \ 1655 (2522480 - sclk_table->entries[i].clk/100 * 115764/100)); 1656 } else { 1657 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \ 1658 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000))); 1659 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \ 1660 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000))); 1661 } 1662 1663 if (volt_without_cks >= volt_with_cks) 1664 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + 1665 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625); 1666 1667 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; 1668 } 1669 1670 smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6; 1671 /* Populate CKS Lookup Table */ 1672 if (stretch_amount == 0 || stretch_amount > 5) { 1673 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1674 PHM_PlatformCaps_ClockStretcher); 1675 PP_ASSERT_WITH_CODE(false, 1676 "Stretch Amount in PPTable not supported", 1677 return -EINVAL); 1678 } 1679 1680 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL); 1681 value &= 0xFFFFFFFE; 1682 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); 1683 1684 return 0; 1685 } 1686 1687 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, 1688 struct SMU74_Discrete_DpmTable *table) 1689 { 1690 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1691 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1692 uint16_t config; 1693 1694 config = VR_MERGED_WITH_VDDC; 1695 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); 1696 1697 /* Set Vddc Voltage Controller */ 1698 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 1699 config = VR_SVI2_PLANE_1; 1700 table->VRConfig |= config; 1701 } else { 1702 PP_ASSERT_WITH_CODE(false, 1703 "VDDC should be on SVI2 control in merged mode!", 1704 ); 1705 } 1706 /* Set Vddci Voltage Controller */ 1707 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 1708 config = VR_SVI2_PLANE_2; /* only in merged mode */ 1709 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); 1710 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 1711 config = VR_SMIO_PATTERN_1; 1712 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); 1713 } else { 1714 config = VR_STATIC_VOLTAGE; 1715 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); 1716 } 1717 /* Set Mvdd Voltage Controller */ 1718 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { 1719 config = VR_SVI2_PLANE_2; 1720 table->VRConfig |= (config << VRCONF_MVDD_SHIFT); 1721 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start + 1722 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1); 1723 } else { 1724 config = VR_STATIC_VOLTAGE; 1725 table->VRConfig |= (config << VRCONF_MVDD_SHIFT); 1726 } 1727 1728 return 0; 1729 } 1730 1731 1732 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 1733 { 1734 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1735 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1736 struct amdgpu_device *adev = hwmgr->adev; 1737 1738 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1739 int result = 0; 1740 struct pp_atom_ctrl__avfs_parameters avfs_params = {0}; 1741 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} }; 1742 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} }; 1743 uint32_t tmp, i; 1744 1745 struct phm_ppt_v1_information *table_info = 1746 (struct phm_ppt_v1_information *)hwmgr->pptable; 1747 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1748 table_info->vdd_dep_on_sclk; 1749 1750 1751 if (!hwmgr->avfs_supported) 1752 return 0; 1753 1754 result = atomctrl_get_avfs_information(hwmgr, &avfs_params); 1755 1756 if (0 == result) { 1757 if (((adev->pdev->device == 0x67ef) && 1758 ((adev->pdev->revision == 0xe0) || 1759 (adev->pdev->revision == 0xe5))) || 1760 ((adev->pdev->device == 0x67ff) && 1761 ((adev->pdev->revision == 0xcf) || 1762 (adev->pdev->revision == 0xef) || 1763 (adev->pdev->revision == 0xff)))) { 1764 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1; 1765 if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) || 1766 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) { 1767 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) && 1768 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) && 1769 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) && 1770 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) && 1771 (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) && 1772 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) { 1773 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4; 1774 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD; 1775 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455; 1776 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0; 1777 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0; 1778 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23; 1779 } 1780 } 1781 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) { 1782 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1; 1783 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD; 1784 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E; 1785 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F; 1786 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315; 1787 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1; 1788 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B; 1789 } else if (((adev->pdev->device == 0x67df) && 1790 ((adev->pdev->revision == 0xe0) || 1791 (adev->pdev->revision == 0xe3) || 1792 (adev->pdev->revision == 0xe4) || 1793 (adev->pdev->revision == 0xe5) || 1794 (adev->pdev->revision == 0xe7) || 1795 (adev->pdev->revision == 0xef))) || 1796 ((adev->pdev->device == 0x6fdf) && 1797 ((adev->pdev->revision == 0xef) || 1798 (adev->pdev->revision == 0xff)))) { 1799 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1; 1800 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B; 1801 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5; 1802 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F; 1803 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0; 1804 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23; 1805 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58; 1806 } 1807 } 1808 1809 if (0 == result) { 1810 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0); 1811 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1); 1812 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2); 1813 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0); 1814 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1); 1815 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2); 1816 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1); 1817 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2); 1818 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b); 1819 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24; 1820 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12; 1821 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1); 1822 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2); 1823 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b); 1824 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24; 1825 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12; 1826 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv); 1827 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0); 1828 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1); 1829 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2); 1830 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma); 1831 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean); 1832 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor); 1833 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma); 1834 1835 for (i = 0; i < NUM_VFT_COLUMNS; i++) { 1836 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625); 1837 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100); 1838 } 1839 1840 result = smu7_read_smc_sram_dword(hwmgr, 1841 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma), 1842 &tmp, SMC_RAM_END); 1843 1844 smu7_copy_bytes_to_smc(hwmgr, 1845 tmp, 1846 (uint8_t *)&AVFS_meanNsigma, 1847 sizeof(AVFS_meanNsigma_t), 1848 SMC_RAM_END); 1849 1850 result = smu7_read_smc_sram_dword(hwmgr, 1851 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable), 1852 &tmp, SMC_RAM_END); 1853 smu7_copy_bytes_to_smc(hwmgr, 1854 tmp, 1855 (uint8_t *)&AVFS_SclkOffset, 1856 sizeof(AVFS_Sclk_Offset_t), 1857 SMC_RAM_END); 1858 1859 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) | 1860 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) | 1861 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) | 1862 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT); 1863 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false; 1864 } 1865 return result; 1866 } 1867 1868 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 1869 { 1870 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1871 struct phm_ppt_v1_information *table_info = 1872 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1873 1874 if (table_info && 1875 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && 1876 table_info->cac_dtp_table->usPowerTuneDataSetID) 1877 smu_data->power_tune_defaults = 1878 &polaris10_power_tune_data_set_array 1879 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; 1880 else 1881 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0]; 1882 1883 } 1884 1885 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) 1886 { 1887 int result; 1888 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); 1889 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 1890 1891 struct phm_ppt_v1_information *table_info = 1892 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1893 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 1894 uint8_t i; 1895 struct pp_atomctrl_gpio_pin_assignment gpio_pin; 1896 pp_atomctrl_clock_dividers_vi dividers; 1897 struct phm_ppt_v1_gpio_table *gpio_table = table_info->gpio_table; 1898 1899 polaris10_initialize_power_tune_defaults(hwmgr); 1900 1901 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control) 1902 polaris10_populate_smc_voltage_tables(hwmgr, table); 1903 1904 table->SystemFlags = 0; 1905 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1906 PHM_PlatformCaps_AutomaticDCTransition)) 1907 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 1908 1909 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1910 PHM_PlatformCaps_StepVddc)) 1911 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 1912 1913 if (hw_data->is_memory_gddr5) 1914 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 1915 1916 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) { 1917 result = polaris10_populate_ulv_state(hwmgr, table); 1918 PP_ASSERT_WITH_CODE(0 == result, 1919 "Failed to initialize ULV state!", return result); 1920 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1921 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT); 1922 } 1923 1924 result = polaris10_populate_smc_link_level(hwmgr, table); 1925 PP_ASSERT_WITH_CODE(0 == result, 1926 "Failed to initialize Link Level!", return result); 1927 1928 result = polaris10_populate_all_graphic_levels(hwmgr); 1929 PP_ASSERT_WITH_CODE(0 == result, 1930 "Failed to initialize Graphics Level!", return result); 1931 1932 result = polaris10_populate_all_memory_levels(hwmgr); 1933 PP_ASSERT_WITH_CODE(0 == result, 1934 "Failed to initialize Memory Level!", return result); 1935 1936 result = polaris10_populate_smc_acpi_level(hwmgr, table); 1937 PP_ASSERT_WITH_CODE(0 == result, 1938 "Failed to initialize ACPI Level!", return result); 1939 1940 result = polaris10_populate_smc_vce_level(hwmgr, table); 1941 PP_ASSERT_WITH_CODE(0 == result, 1942 "Failed to initialize VCE Level!", return result); 1943 1944 result = polaris10_populate_smc_samu_level(hwmgr, table); 1945 PP_ASSERT_WITH_CODE(0 == result, 1946 "Failed to initialize SAMU Level!", return result); 1947 1948 /* Since only the initial state is completely set up at this point 1949 * (the other states are just copies of the boot state) we only 1950 * need to populate the ARB settings for the initial state. 1951 */ 1952 result = polaris10_program_memory_timing_parameters(hwmgr); 1953 PP_ASSERT_WITH_CODE(0 == result, 1954 "Failed to Write ARB settings for the initial state.", return result); 1955 1956 result = polaris10_populate_smc_uvd_level(hwmgr, table); 1957 PP_ASSERT_WITH_CODE(0 == result, 1958 "Failed to initialize UVD Level!", return result); 1959 1960 result = polaris10_populate_smc_boot_level(hwmgr, table); 1961 PP_ASSERT_WITH_CODE(0 == result, 1962 "Failed to initialize Boot Level!", return result); 1963 1964 result = polaris10_populate_smc_initailial_state(hwmgr); 1965 PP_ASSERT_WITH_CODE(0 == result, 1966 "Failed to initialize Boot State!", return result); 1967 1968 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr); 1969 PP_ASSERT_WITH_CODE(0 == result, 1970 "Failed to populate BAPM Parameters!", return result); 1971 1972 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1973 PHM_PlatformCaps_ClockStretcher)) { 1974 result = polaris10_populate_clock_stretcher_data_table(hwmgr); 1975 PP_ASSERT_WITH_CODE(0 == result, 1976 "Failed to populate Clock Stretcher Data Table!", 1977 return result); 1978 } 1979 1980 result = polaris10_populate_avfs_parameters(hwmgr); 1981 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;); 1982 1983 table->CurrSclkPllRange = 0xff; 1984 table->GraphicsVoltageChangeEnable = 1; 1985 table->GraphicsThermThrottleEnable = 1; 1986 table->GraphicsInterval = 1; 1987 table->VoltageInterval = 1; 1988 table->ThermalInterval = 1; 1989 table->TemperatureLimitHigh = 1990 table_info->cac_dtp_table->usTargetOperatingTemp * 1991 SMU7_Q88_FORMAT_CONVERSION_UNIT; 1992 table->TemperatureLimitLow = 1993 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * 1994 SMU7_Q88_FORMAT_CONVERSION_UNIT; 1995 table->MemoryVoltageChangeEnable = 1; 1996 table->MemoryInterval = 1; 1997 table->VoltageResponseTime = 0; 1998 table->PhaseResponseTime = 0; 1999 table->MemoryThermThrottleEnable = 1; 2000 table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count; 2001 table->PCIeGenInterval = 1; 2002 table->VRConfig = 0; 2003 2004 result = polaris10_populate_vr_config(hwmgr, table); 2005 PP_ASSERT_WITH_CODE(0 == result, 2006 "Failed to populate VRConfig setting!", return result); 2007 hw_data->vr_config = table->VRConfig; 2008 table->ThermGpio = 17; 2009 table->SclkStepSize = 0x4000; 2010 2011 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { 2012 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; 2013 if (gpio_table) 2014 table->VRHotLevel = gpio_table->vrhot_triggered_sclk_dpm_index; 2015 } else { 2016 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN; 2017 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2018 PHM_PlatformCaps_RegulatorHot); 2019 } 2020 2021 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, 2022 &gpio_pin)) { 2023 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift; 2024 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2025 PHM_PlatformCaps_AutomaticDCTransition); 2026 } else { 2027 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN; 2028 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2029 PHM_PlatformCaps_AutomaticDCTransition); 2030 } 2031 2032 /* Thermal Output GPIO */ 2033 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID, 2034 &gpio_pin)) { 2035 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2036 PHM_PlatformCaps_ThermalOutGPIO); 2037 2038 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift; 2039 2040 /* For porlarity read GPIOPAD_A with assigned Gpio pin 2041 * since VBIOS will program this register to set 'inactive state', 2042 * driver can then determine 'active state' from this and 2043 * program SMU with correct polarity 2044 */ 2045 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) 2046 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0; 2047 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; 2048 2049 /* if required, combine VRHot/PCC with thermal out GPIO */ 2050 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot) 2051 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal)) 2052 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; 2053 } else { 2054 table->ThermOutGpio = 17; 2055 table->ThermOutPolarity = 1; 2056 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; 2057 } 2058 2059 /* Populate BIF_SCLK levels into SMC DPM table */ 2060 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) { 2061 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs); 2062 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result); 2063 2064 if (i == 0) 2065 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); 2066 else 2067 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); 2068 } 2069 2070 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++) 2071 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); 2072 2073 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); 2074 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); 2075 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); 2076 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); 2077 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); 2078 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange); 2079 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); 2080 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); 2081 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); 2082 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); 2083 2084 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 2085 result = smu7_copy_bytes_to_smc(hwmgr, 2086 smu_data->smu7_data.dpm_table_start + 2087 offsetof(SMU74_Discrete_DpmTable, SystemFlags), 2088 (uint8_t *)&(table->SystemFlags), 2089 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController), 2090 SMC_RAM_END); 2091 PP_ASSERT_WITH_CODE(0 == result, 2092 "Failed to upload dpm data to SMC memory!", return result); 2093 2094 result = polaris10_populate_pm_fuses(hwmgr); 2095 PP_ASSERT_WITH_CODE(0 == result, 2096 "Failed to populate PM fuses to SMC memory!", return result); 2097 2098 return 0; 2099 } 2100 2101 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) 2102 { 2103 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2104 2105 if (data->need_update_smu7_dpm_table & 2106 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) 2107 return polaris10_program_memory_timing_parameters(hwmgr); 2108 2109 return 0; 2110 } 2111 2112 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr) 2113 { 2114 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2115 2116 if (!hwmgr->avfs_supported) 2117 return 0; 2118 2119 smum_send_msg_to_smc_with_parameter(hwmgr, 2120 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting, 2121 NULL); 2122 2123 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL); 2124 2125 /* Apply avfs cks-off voltages to avoid the overshoot 2126 * when switching to the highest sclk frequency 2127 */ 2128 if (data->apply_avfs_cks_off_voltage) 2129 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL); 2130 2131 return 0; 2132 } 2133 2134 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 2135 { 2136 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 2137 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 2138 uint32_t duty100; 2139 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; 2140 uint16_t fdo_min, slope1, slope2; 2141 uint32_t reference_clock; 2142 int res; 2143 uint64_t tmp64; 2144 2145 if (hwmgr->thermal_controller.fanInfo.bNoFan) { 2146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2147 PHM_PlatformCaps_MicrocodeFanControl); 2148 return 0; 2149 } 2150 2151 if (smu_data->smu7_data.fan_table_start == 0) { 2152 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2153 PHM_PlatformCaps_MicrocodeFanControl); 2154 return 0; 2155 } 2156 2157 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 2158 CG_FDO_CTRL1, FMAX_DUTY100); 2159 2160 if (duty100 == 0) { 2161 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2162 PHM_PlatformCaps_MicrocodeFanControl); 2163 return 0; 2164 } 2165 2166 /* use hardware fan control */ 2167 if (hwmgr->thermal_controller.use_hw_fan_control) 2168 return 0; 2169 2170 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters. 2171 usPWMMin * duty100; 2172 do_div(tmp64, 10000); 2173 fdo_min = (uint16_t)tmp64; 2174 2175 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - 2176 hwmgr->thermal_controller.advanceFanControlParameters.usTMin; 2177 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - 2178 hwmgr->thermal_controller.advanceFanControlParameters.usTMed; 2179 2180 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - 2181 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; 2182 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - 2183 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; 2184 2185 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 2186 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 2187 2188 fan_table.TempMin = cpu_to_be16((50 + hwmgr-> 2189 thermal_controller.advanceFanControlParameters.usTMin) / 100); 2190 fan_table.TempMed = cpu_to_be16((50 + hwmgr-> 2191 thermal_controller.advanceFanControlParameters.usTMed) / 100); 2192 fan_table.TempMax = cpu_to_be16((50 + hwmgr-> 2193 thermal_controller.advanceFanControlParameters.usTMax) / 100); 2194 2195 fan_table.Slope1 = cpu_to_be16(slope1); 2196 fan_table.Slope2 = cpu_to_be16(slope2); 2197 2198 fan_table.FdoMin = cpu_to_be16(fdo_min); 2199 2200 fan_table.HystDown = cpu_to_be16(hwmgr-> 2201 thermal_controller.advanceFanControlParameters.ucTHyst); 2202 2203 fan_table.HystUp = cpu_to_be16(1); 2204 2205 fan_table.HystSlope = cpu_to_be16(1); 2206 2207 fan_table.TempRespLim = cpu_to_be16(5); 2208 2209 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 2210 2211 fan_table.RefreshPeriod = cpu_to_be32((hwmgr-> 2212 thermal_controller.advanceFanControlParameters.ulCycleDelay * 2213 reference_clock) / 1600); 2214 2215 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); 2216 2217 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD( 2218 hwmgr->device, CGS_IND_REG__SMC, 2219 CG_MULT_THERMAL_CTRL, TEMP_SEL); 2220 2221 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start, 2222 (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), 2223 SMC_RAM_END); 2224 2225 if (!res && hwmgr->thermal_controller. 2226 advanceFanControlParameters.ucMinimumPWMLimit) 2227 res = smum_send_msg_to_smc_with_parameter(hwmgr, 2228 PPSMC_MSG_SetFanMinPwm, 2229 hwmgr->thermal_controller. 2230 advanceFanControlParameters.ucMinimumPWMLimit, 2231 NULL); 2232 2233 if (!res && hwmgr->thermal_controller. 2234 advanceFanControlParameters.ulMinFanSCLKAcousticLimit) 2235 res = smum_send_msg_to_smc_with_parameter(hwmgr, 2236 PPSMC_MSG_SetFanSclkTarget, 2237 hwmgr->thermal_controller. 2238 advanceFanControlParameters.ulMinFanSCLKAcousticLimit, 2239 NULL); 2240 2241 if (res) 2242 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2243 PHM_PlatformCaps_MicrocodeFanControl); 2244 2245 return 0; 2246 } 2247 2248 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr) 2249 { 2250 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 2251 uint32_t mm_boot_level_offset, mm_boot_level_value; 2252 struct phm_ppt_v1_information *table_info = 2253 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2254 2255 smu_data->smc_state_table.UvdBootLevel = 0; 2256 if (table_info->mm_dep_table->count > 0) 2257 smu_data->smc_state_table.UvdBootLevel = 2258 (uint8_t) (table_info->mm_dep_table->count - 1); 2259 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, 2260 UvdBootLevel); 2261 mm_boot_level_offset /= 4; 2262 mm_boot_level_offset *= 4; 2263 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, 2264 CGS_IND_REG__SMC, mm_boot_level_offset); 2265 mm_boot_level_value &= 0x00FFFFFF; 2266 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; 2267 cgs_write_ind_register(hwmgr->device, 2268 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 2269 2270 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2271 PHM_PlatformCaps_UVDDPM) || 2272 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2273 PHM_PlatformCaps_StablePState)) 2274 smum_send_msg_to_smc_with_parameter(hwmgr, 2275 PPSMC_MSG_UVDDPM_SetEnabledMask, 2276 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel), 2277 NULL); 2278 return 0; 2279 } 2280 2281 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr) 2282 { 2283 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 2284 uint32_t mm_boot_level_offset, mm_boot_level_value; 2285 struct phm_ppt_v1_information *table_info = 2286 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2287 2288 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2289 PHM_PlatformCaps_StablePState)) 2290 smu_data->smc_state_table.VceBootLevel = 2291 (uint8_t) (table_info->mm_dep_table->count - 1); 2292 else 2293 smu_data->smc_state_table.VceBootLevel = 0; 2294 2295 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + 2296 offsetof(SMU74_Discrete_DpmTable, VceBootLevel); 2297 mm_boot_level_offset /= 4; 2298 mm_boot_level_offset *= 4; 2299 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, 2300 CGS_IND_REG__SMC, mm_boot_level_offset); 2301 mm_boot_level_value &= 0xFF00FFFF; 2302 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; 2303 cgs_write_ind_register(hwmgr->device, 2304 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 2305 2306 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) 2307 smum_send_msg_to_smc_with_parameter(hwmgr, 2308 PPSMC_MSG_VCEDPM_SetEnabledMask, 2309 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel, 2310 NULL); 2311 return 0; 2312 } 2313 2314 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr) 2315 { 2316 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 2317 struct phm_ppt_v1_information *table_info = 2318 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2319 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; 2320 int max_entry, i; 2321 2322 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ? 2323 SMU74_MAX_LEVELS_LINK : 2324 pcie_table->count; 2325 /* Setup BIF_SCLK levels */ 2326 for (i = 0; i < max_entry; i++) 2327 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk; 2328 return 0; 2329 } 2330 2331 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) 2332 { 2333 switch (type) { 2334 case SMU_UVD_TABLE: 2335 polaris10_update_uvd_smc_table(hwmgr); 2336 break; 2337 case SMU_VCE_TABLE: 2338 polaris10_update_vce_smc_table(hwmgr); 2339 break; 2340 case SMU_BIF_TABLE: 2341 polaris10_update_bif_smc_table(hwmgr); 2342 default: 2343 break; 2344 } 2345 return 0; 2346 } 2347 2348 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2349 { 2350 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2351 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 2352 2353 int result = 0; 2354 uint32_t low_sclk_interrupt_threshold = 0; 2355 2356 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2357 PHM_PlatformCaps_SclkThrottleLowNotification) 2358 && (data->low_sclk_interrupt_threshold != 0)) { 2359 low_sclk_interrupt_threshold = 2360 data->low_sclk_interrupt_threshold; 2361 2362 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2363 2364 result = smu7_copy_bytes_to_smc( 2365 hwmgr, 2366 smu_data->smu7_data.dpm_table_start + 2367 offsetof(SMU74_Discrete_DpmTable, 2368 LowSclkInterruptThreshold), 2369 (uint8_t *)&low_sclk_interrupt_threshold, 2370 sizeof(uint32_t), 2371 SMC_RAM_END); 2372 } 2373 PP_ASSERT_WITH_CODE((result == 0), 2374 "Failed to update SCLK threshold!", return result); 2375 2376 result = polaris10_program_mem_timing_parameters(hwmgr); 2377 PP_ASSERT_WITH_CODE((result == 0), 2378 "Failed to program memory timing parameters!", 2379 ); 2380 2381 return result; 2382 } 2383 2384 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member) 2385 { 2386 switch (type) { 2387 case SMU_SoftRegisters: 2388 switch (member) { 2389 case HandshakeDisables: 2390 return offsetof(SMU74_SoftRegisters, HandshakeDisables); 2391 case VoltageChangeTimeout: 2392 return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout); 2393 case AverageGraphicsActivity: 2394 return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity); 2395 case AverageMemoryActivity: 2396 return offsetof(SMU74_SoftRegisters, AverageMemoryActivity); 2397 case PreVBlankGap: 2398 return offsetof(SMU74_SoftRegisters, PreVBlankGap); 2399 case VBlankTimeout: 2400 return offsetof(SMU74_SoftRegisters, VBlankTimeout); 2401 case UcodeLoadStatus: 2402 return offsetof(SMU74_SoftRegisters, UcodeLoadStatus); 2403 case DRAM_LOG_ADDR_H: 2404 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H); 2405 case DRAM_LOG_ADDR_L: 2406 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L); 2407 case DRAM_LOG_PHY_ADDR_H: 2408 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H); 2409 case DRAM_LOG_PHY_ADDR_L: 2410 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L); 2411 case DRAM_LOG_BUFF_SIZE: 2412 return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE); 2413 } 2414 break; 2415 case SMU_Discrete_DpmTable: 2416 switch (member) { 2417 case UvdBootLevel: 2418 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel); 2419 case VceBootLevel: 2420 return offsetof(SMU74_Discrete_DpmTable, VceBootLevel); 2421 case LowSclkInterruptThreshold: 2422 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold); 2423 } 2424 break; 2425 } 2426 pr_warn("can't get the offset of type %x member %x\n", type, member); 2427 return 0; 2428 } 2429 2430 static uint32_t polaris10_get_mac_definition(uint32_t value) 2431 { 2432 switch (value) { 2433 case SMU_MAX_LEVELS_GRAPHICS: 2434 return SMU74_MAX_LEVELS_GRAPHICS; 2435 case SMU_MAX_LEVELS_MEMORY: 2436 return SMU74_MAX_LEVELS_MEMORY; 2437 case SMU_MAX_LEVELS_LINK: 2438 return SMU74_MAX_LEVELS_LINK; 2439 case SMU_MAX_ENTRIES_SMIO: 2440 return SMU74_MAX_ENTRIES_SMIO; 2441 case SMU_MAX_LEVELS_VDDC: 2442 return SMU74_MAX_LEVELS_VDDC; 2443 case SMU_MAX_LEVELS_VDDGFX: 2444 return SMU74_MAX_LEVELS_VDDGFX; 2445 case SMU_MAX_LEVELS_VDDCI: 2446 return SMU74_MAX_LEVELS_VDDCI; 2447 case SMU_MAX_LEVELS_MVDD: 2448 return SMU74_MAX_LEVELS_MVDD; 2449 case SMU_UVD_MCLK_HANDSHAKE_DISABLE: 2450 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE; 2451 } 2452 2453 pr_warn("can't get the mac of %x\n", value); 2454 return 0; 2455 } 2456 2457 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) 2458 { 2459 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend); 2460 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2461 uint32_t tmp; 2462 int result; 2463 bool error = false; 2464 2465 result = smu7_read_smc_sram_dword(hwmgr, 2466 SMU7_FIRMWARE_HEADER_LOCATION + 2467 offsetof(SMU74_Firmware_Header, DpmTable), 2468 &tmp, SMC_RAM_END); 2469 2470 if (0 == result) 2471 smu_data->smu7_data.dpm_table_start = tmp; 2472 2473 error |= (0 != result); 2474 2475 result = smu7_read_smc_sram_dword(hwmgr, 2476 SMU7_FIRMWARE_HEADER_LOCATION + 2477 offsetof(SMU74_Firmware_Header, SoftRegisters), 2478 &tmp, SMC_RAM_END); 2479 2480 if (!result) { 2481 data->soft_regs_start = tmp; 2482 smu_data->smu7_data.soft_regs_start = tmp; 2483 } 2484 2485 error |= (0 != result); 2486 2487 result = smu7_read_smc_sram_dword(hwmgr, 2488 SMU7_FIRMWARE_HEADER_LOCATION + 2489 offsetof(SMU74_Firmware_Header, mcRegisterTable), 2490 &tmp, SMC_RAM_END); 2491 2492 if (!result) 2493 smu_data->smu7_data.mc_reg_table_start = tmp; 2494 2495 result = smu7_read_smc_sram_dword(hwmgr, 2496 SMU7_FIRMWARE_HEADER_LOCATION + 2497 offsetof(SMU74_Firmware_Header, FanTable), 2498 &tmp, SMC_RAM_END); 2499 2500 if (!result) 2501 smu_data->smu7_data.fan_table_start = tmp; 2502 2503 error |= (0 != result); 2504 2505 result = smu7_read_smc_sram_dword(hwmgr, 2506 SMU7_FIRMWARE_HEADER_LOCATION + 2507 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), 2508 &tmp, SMC_RAM_END); 2509 2510 if (!result) 2511 smu_data->smu7_data.arb_table_start = tmp; 2512 2513 error |= (0 != result); 2514 2515 result = smu7_read_smc_sram_dword(hwmgr, 2516 SMU7_FIRMWARE_HEADER_LOCATION + 2517 offsetof(SMU74_Firmware_Header, Version), 2518 &tmp, SMC_RAM_END); 2519 2520 if (!result) 2521 hwmgr->microcode_version_info.SMC = tmp; 2522 2523 error |= (0 != result); 2524 2525 return error ? -1 : 0; 2526 } 2527 2528 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr) 2529 { 2530 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 2531 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) 2532 ? true : false; 2533 } 2534 2535 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr, 2536 void *profile_setting) 2537 { 2538 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2539 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *) 2540 (hwmgr->smu_backend); 2541 struct profile_mode_setting *setting; 2542 struct SMU74_Discrete_GraphicsLevel *levels = 2543 smu_data->smc_state_table.GraphicsLevel; 2544 uint32_t array = smu_data->smu7_data.dpm_table_start + 2545 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); 2546 2547 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + 2548 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); 2549 struct SMU74_Discrete_MemoryLevel *mclk_levels = 2550 smu_data->smc_state_table.MemoryLevel; 2551 uint32_t i; 2552 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; 2553 2554 if (profile_setting == NULL) 2555 return -EINVAL; 2556 2557 setting = (struct profile_mode_setting *)profile_setting; 2558 2559 if (setting->bupdate_sclk) { 2560 if (!data->sclk_dpm_key_disabled) 2561 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL); 2562 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { 2563 if (levels[i].ActivityLevel != 2564 cpu_to_be16(setting->sclk_activity)) { 2565 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity); 2566 2567 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i) 2568 + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel); 2569 offset = clk_activity_offset & ~0x3; 2570 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 2571 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2572 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 2573 2574 } 2575 if (levels[i].UpHyst != setting->sclk_up_hyst || 2576 levels[i].DownHyst != setting->sclk_down_hyst) { 2577 levels[i].UpHyst = setting->sclk_up_hyst; 2578 levels[i].DownHyst = setting->sclk_down_hyst; 2579 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i) 2580 + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst); 2581 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i) 2582 + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst); 2583 offset = up_hyst_offset & ~0x3; 2584 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 2585 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t)); 2586 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t)); 2587 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 2588 } 2589 } 2590 if (!data->sclk_dpm_key_disabled) 2591 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL); 2592 } 2593 2594 if (setting->bupdate_mclk) { 2595 if (!data->mclk_dpm_key_disabled) 2596 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL); 2597 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { 2598 if (mclk_levels[i].ActivityLevel != 2599 cpu_to_be16(setting->mclk_activity)) { 2600 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity); 2601 2602 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i) 2603 + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel); 2604 offset = clk_activity_offset & ~0x3; 2605 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 2606 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t)); 2607 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 2608 2609 } 2610 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst || 2611 mclk_levels[i].DownHyst != setting->mclk_down_hyst) { 2612 mclk_levels[i].UpHyst = setting->mclk_up_hyst; 2613 mclk_levels[i].DownHyst = setting->mclk_down_hyst; 2614 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i) 2615 + offsetof(SMU74_Discrete_MemoryLevel, UpHyst); 2616 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i) 2617 + offsetof(SMU74_Discrete_MemoryLevel, DownHyst); 2618 offset = up_hyst_offset & ~0x3; 2619 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 2620 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t)); 2621 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t)); 2622 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 2623 } 2624 } 2625 if (!data->mclk_dpm_key_disabled) 2626 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL); 2627 } 2628 return 0; 2629 } 2630 2631 const struct pp_smumgr_func polaris10_smu_funcs = { 2632 .name = "polaris10_smu", 2633 .smu_init = polaris10_smu_init, 2634 .smu_fini = smu7_smu_fini, 2635 .start_smu = polaris10_start_smu, 2636 .check_fw_load_finish = smu7_check_fw_load_finish, 2637 .request_smu_load_fw = smu7_reload_firmware, 2638 .request_smu_load_specific_fw = NULL, 2639 .send_msg_to_smc = smu7_send_msg_to_smc, 2640 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter, 2641 .get_argument = smu7_get_argument, 2642 .download_pptable_settings = NULL, 2643 .upload_pptable_settings = NULL, 2644 .update_smc_table = polaris10_update_smc_table, 2645 .get_offsetof = polaris10_get_offsetof, 2646 .process_firmware_header = polaris10_process_firmware_header, 2647 .init_smc_table = polaris10_init_smc_table, 2648 .update_sclk_threshold = polaris10_update_sclk_threshold, 2649 .thermal_avfs_enable = polaris10_thermal_avfs_enable, 2650 .thermal_setup_fan_table = polaris10_thermal_setup_fan_table, 2651 .populate_all_graphic_levels = polaris10_populate_all_graphic_levels, 2652 .populate_all_memory_levels = polaris10_populate_all_memory_levels, 2653 .get_mac_definition = polaris10_get_mac_definition, 2654 .is_dpm_running = polaris10_is_dpm_running, 2655 .is_hw_avfs_present = polaris10_is_hw_avfs_present, 2656 .update_dpm_settings = polaris10_update_dpm_settings, 2657 }; 2658