1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2014 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan 24*837d542aSEvan Quan #ifndef SMU_UCODE_XFER_VI_H 25*837d542aSEvan Quan #define SMU_UCODE_XFER_VI_H 26*837d542aSEvan Quan 27*837d542aSEvan Quan #define SMU_DRAMData_TOC_VERSION 1 28*837d542aSEvan Quan #define MAX_IH_REGISTER_COUNT 65535 29*837d542aSEvan Quan #define SMU_DIGEST_SIZE_BYTES 20 30*837d542aSEvan Quan #define SMU_FB_SIZE_BYTES 1048576 31*837d542aSEvan Quan #define SMU_MAX_ENTRIES 12 32*837d542aSEvan Quan 33*837d542aSEvan Quan #define UCODE_ID_SMU 0 34*837d542aSEvan Quan #define UCODE_ID_SDMA0 1 35*837d542aSEvan Quan #define UCODE_ID_SDMA1 2 36*837d542aSEvan Quan #define UCODE_ID_CP_CE 3 37*837d542aSEvan Quan #define UCODE_ID_CP_PFP 4 38*837d542aSEvan Quan #define UCODE_ID_CP_ME 5 39*837d542aSEvan Quan #define UCODE_ID_CP_MEC 6 40*837d542aSEvan Quan #define UCODE_ID_CP_MEC_JT1 7 41*837d542aSEvan Quan #define UCODE_ID_CP_MEC_JT2 8 42*837d542aSEvan Quan #define UCODE_ID_GMCON_RENG 9 43*837d542aSEvan Quan #define UCODE_ID_RLC_G 10 44*837d542aSEvan Quan #define UCODE_ID_IH_REG_RESTORE 11 45*837d542aSEvan Quan #define UCODE_ID_VBIOS 12 46*837d542aSEvan Quan #define UCODE_ID_MISC_METADATA 13 47*837d542aSEvan Quan #define UCODE_ID_SMU_SK 14 48*837d542aSEvan Quan #define UCODE_ID_RLC_SCRATCH 32 49*837d542aSEvan Quan #define UCODE_ID_RLC_SRM_ARAM 33 50*837d542aSEvan Quan #define UCODE_ID_RLC_SRM_DRAM 34 51*837d542aSEvan Quan #define UCODE_ID_MEC_STORAGE 35 52*837d542aSEvan Quan #define UCODE_ID_VBIOS_PARAMETERS 36 53*837d542aSEvan Quan #define UCODE_META_DATA 0xFF 54*837d542aSEvan Quan 55*837d542aSEvan Quan #define UCODE_ID_SMU_MASK 0x00000001 56*837d542aSEvan Quan #define UCODE_ID_SDMA0_MASK 0x00000002 57*837d542aSEvan Quan #define UCODE_ID_SDMA1_MASK 0x00000004 58*837d542aSEvan Quan #define UCODE_ID_CP_CE_MASK 0x00000008 59*837d542aSEvan Quan #define UCODE_ID_CP_PFP_MASK 0x00000010 60*837d542aSEvan Quan #define UCODE_ID_CP_ME_MASK 0x00000020 61*837d542aSEvan Quan #define UCODE_ID_CP_MEC_MASK 0x00000040 62*837d542aSEvan Quan #define UCODE_ID_CP_MEC_JT1_MASK 0x00000080 63*837d542aSEvan Quan #define UCODE_ID_CP_MEC_JT2_MASK 0x00000100 64*837d542aSEvan Quan #define UCODE_ID_GMCON_RENG_MASK 0x00000200 65*837d542aSEvan Quan #define UCODE_ID_RLC_G_MASK 0x00000400 66*837d542aSEvan Quan #define UCODE_ID_IH_REG_RESTORE_MASK 0x00000800 67*837d542aSEvan Quan #define UCODE_ID_VBIOS_MASK 0x00001000 68*837d542aSEvan Quan 69*837d542aSEvan Quan #define UCODE_FLAG_UNHALT_MASK 0x1 70*837d542aSEvan Quan 71*837d542aSEvan Quan struct SMU_Entry { 72*837d542aSEvan Quan #ifndef __BIG_ENDIAN 73*837d542aSEvan Quan uint16_t id; 74*837d542aSEvan Quan uint16_t version; 75*837d542aSEvan Quan uint32_t image_addr_high; 76*837d542aSEvan Quan uint32_t image_addr_low; 77*837d542aSEvan Quan uint32_t meta_data_addr_high; 78*837d542aSEvan Quan uint32_t meta_data_addr_low; 79*837d542aSEvan Quan uint32_t data_size_byte; 80*837d542aSEvan Quan uint16_t flags; 81*837d542aSEvan Quan uint16_t num_register_entries; 82*837d542aSEvan Quan #else 83*837d542aSEvan Quan uint16_t version; 84*837d542aSEvan Quan uint16_t id; 85*837d542aSEvan Quan uint32_t image_addr_high; 86*837d542aSEvan Quan uint32_t image_addr_low; 87*837d542aSEvan Quan uint32_t meta_data_addr_high; 88*837d542aSEvan Quan uint32_t meta_data_addr_low; 89*837d542aSEvan Quan uint32_t data_size_byte; 90*837d542aSEvan Quan uint16_t num_register_entries; 91*837d542aSEvan Quan uint16_t flags; 92*837d542aSEvan Quan #endif 93*837d542aSEvan Quan }; 94*837d542aSEvan Quan 95*837d542aSEvan Quan struct SMU_DRAMData_TOC { 96*837d542aSEvan Quan uint32_t structure_version; 97*837d542aSEvan Quan uint32_t num_entries; 98*837d542aSEvan Quan struct SMU_Entry entry[SMU_MAX_ENTRIES]; 99*837d542aSEvan Quan }; 100*837d542aSEvan Quan 101*837d542aSEvan Quan #endif 102