1*837d542aSEvan Quan /*
2*837d542aSEvan Quan  * Copyright 2014 Advanced Micro Devices, Inc.
3*837d542aSEvan Quan  *
4*837d542aSEvan Quan  * Permission is hereby granted, free of charge, to any person obtaining a
5*837d542aSEvan Quan  * copy of this software and associated documentation files (the "Software"),
6*837d542aSEvan Quan  * to deal in the Software without restriction, including without limitation
7*837d542aSEvan Quan  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*837d542aSEvan Quan  * and/or sell copies of the Software, and to permit persons to whom the
9*837d542aSEvan Quan  * Software is furnished to do so, subject to the following conditions:
10*837d542aSEvan Quan  *
11*837d542aSEvan Quan  * The above copyright notice and this permission notice shall be included in
12*837d542aSEvan Quan  * all copies or substantial portions of the Software.
13*837d542aSEvan Quan  *
14*837d542aSEvan Quan  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*837d542aSEvan Quan  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*837d542aSEvan Quan  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*837d542aSEvan Quan  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*837d542aSEvan Quan  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*837d542aSEvan Quan  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*837d542aSEvan Quan  * OTHER DEALINGS IN THE SOFTWARE.
21*837d542aSEvan Quan  *
22*837d542aSEvan Quan  */
23*837d542aSEvan Quan 
24*837d542aSEvan Quan #ifndef SMU8_FUSION_H
25*837d542aSEvan Quan #define SMU8_FUSION_H
26*837d542aSEvan Quan 
27*837d542aSEvan Quan #include "smu8.h"
28*837d542aSEvan Quan 
29*837d542aSEvan Quan #pragma pack(push, 1)
30*837d542aSEvan Quan 
31*837d542aSEvan Quan #define SMU8_MAX_CUS 2
32*837d542aSEvan Quan #define SMU8_PSMS_PER_CU 4
33*837d542aSEvan Quan #define SMU8_CACS_PER_CU 4
34*837d542aSEvan Quan 
35*837d542aSEvan Quan struct SMU8_GfxCuPgScoreboard {
36*837d542aSEvan Quan     uint8_t Enabled;
37*837d542aSEvan Quan     uint8_t spare[3];
38*837d542aSEvan Quan };
39*837d542aSEvan Quan 
40*837d542aSEvan Quan struct SMU8_Port80MonitorTable {
41*837d542aSEvan Quan 	uint32_t MmioAddress;
42*837d542aSEvan Quan 	uint32_t MemoryBaseHi;
43*837d542aSEvan Quan 	uint32_t MemoryBaseLo;
44*837d542aSEvan Quan 	uint16_t MemoryBufferSize;
45*837d542aSEvan Quan 	uint16_t MemoryPosition;
46*837d542aSEvan Quan 	uint16_t PollingInterval;
47*837d542aSEvan Quan 	uint8_t  EnableCsrShadow;
48*837d542aSEvan Quan 	uint8_t  EnableDramShadow;
49*837d542aSEvan Quan };
50*837d542aSEvan Quan 
51*837d542aSEvan Quan /*  Display specific power management parameters */
52*837d542aSEvan Quan #define PWRMGT_SEPARATION_TIME_SHIFT            0
53*837d542aSEvan Quan #define PWRMGT_SEPARATION_TIME_MASK             0xFFFF
54*837d542aSEvan Quan #define PWRMGT_DISABLE_CPU_CSTATES_SHIFT        16
55*837d542aSEvan Quan #define PWRMGT_DISABLE_CPU_CSTATES_MASK         0x1
56*837d542aSEvan Quan #define PWRMGT_DISABLE_CPU_PSTATES_SHIFT        24
57*837d542aSEvan Quan #define PWRMGT_DISABLE_CPU_PSTATES_MASK         0x1
58*837d542aSEvan Quan 
59*837d542aSEvan Quan /* Clock Table Definitions */
60*837d542aSEvan Quan #define NUM_SCLK_LEVELS     8
61*837d542aSEvan Quan #define NUM_LCLK_LEVELS     8
62*837d542aSEvan Quan #define NUM_UVD_LEVELS      8
63*837d542aSEvan Quan #define NUM_ECLK_LEVELS     8
64*837d542aSEvan Quan #define NUM_ACLK_LEVELS     8
65*837d542aSEvan Quan 
66*837d542aSEvan Quan struct SMU8_Fusion_ClkLevel {
67*837d542aSEvan Quan 	uint8_t		GnbVid;
68*837d542aSEvan Quan 	uint8_t		GfxVid;
69*837d542aSEvan Quan 	uint8_t		DfsDid;
70*837d542aSEvan Quan 	uint8_t		DeepSleepDid;
71*837d542aSEvan Quan 	uint32_t	DfsBypass;
72*837d542aSEvan Quan 	uint32_t	Frequency;
73*837d542aSEvan Quan };
74*837d542aSEvan Quan 
75*837d542aSEvan Quan struct SMU8_Fusion_SclkBreakdownTable {
76*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
77*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
78*837d542aSEvan Quan 	/* SMU8_Fusion_ClkLevel PwrOffLevel; */
79*837d542aSEvan Quan 	uint32_t    SclkValidMask;
80*837d542aSEvan Quan 	uint32_t    MaxSclkIndex;
81*837d542aSEvan Quan };
82*837d542aSEvan Quan 
83*837d542aSEvan Quan struct SMU8_Fusion_LclkBreakdownTable {
84*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
85*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
86*837d542aSEvan Quan     /* SMU8_Fusion_ClkLevel PwrOffLevel; */
87*837d542aSEvan Quan 	uint32_t    LclkValidMask;
88*837d542aSEvan Quan 	uint32_t    MaxLclkIndex;
89*837d542aSEvan Quan };
90*837d542aSEvan Quan 
91*837d542aSEvan Quan struct SMU8_Fusion_EclkBreakdownTable {
92*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
93*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
94*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
95*837d542aSEvan Quan 	uint32_t    EclkValidMask;
96*837d542aSEvan Quan 	uint32_t    MaxEclkIndex;
97*837d542aSEvan Quan };
98*837d542aSEvan Quan 
99*837d542aSEvan Quan struct SMU8_Fusion_VclkBreakdownTable {
100*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
101*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
102*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
103*837d542aSEvan Quan 	uint32_t    VclkValidMask;
104*837d542aSEvan Quan 	uint32_t    MaxVclkIndex;
105*837d542aSEvan Quan };
106*837d542aSEvan Quan 
107*837d542aSEvan Quan struct SMU8_Fusion_DclkBreakdownTable {
108*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
109*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
110*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
111*837d542aSEvan Quan 	uint32_t    DclkValidMask;
112*837d542aSEvan Quan 	uint32_t    MaxDclkIndex;
113*837d542aSEvan Quan };
114*837d542aSEvan Quan 
115*837d542aSEvan Quan struct SMU8_Fusion_AclkBreakdownTable {
116*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
117*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
118*837d542aSEvan Quan 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
119*837d542aSEvan Quan 	uint32_t    AclkValidMask;
120*837d542aSEvan Quan 	uint32_t    MaxAclkIndex;
121*837d542aSEvan Quan };
122*837d542aSEvan Quan 
123*837d542aSEvan Quan 
124*837d542aSEvan Quan struct SMU8_Fusion_ClkTable {
125*837d542aSEvan Quan 	struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
126*837d542aSEvan Quan 	struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
127*837d542aSEvan Quan 	struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
128*837d542aSEvan Quan 	struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
129*837d542aSEvan Quan 	struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
130*837d542aSEvan Quan 	struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
131*837d542aSEvan Quan };
132*837d542aSEvan Quan 
133*837d542aSEvan Quan #pragma pack(pop)
134*837d542aSEvan Quan 
135*837d542aSEvan Quan #endif
136