1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef _SMU73_H_
24 #define _SMU73_H_
25 
26 #pragma pack(push, 1)
27 enum SID_OPTION {
28   SID_OPTION_HI,
29   SID_OPTION_LO,
30   SID_OPTION_COUNT
31 };
32 
33 enum Poly3rdOrderCoeff {
34     LEAKAGE_TEMPERATURE_SCALAR,
35     LEAKAGE_VOLTAGE_SCALAR,
36     DYNAMIC_VOLTAGE_SCALAR,
37     POLY_3RD_ORDER_COUNT
38 };
39 
40 struct SMU7_Poly3rdOrder_Data
41 {
42     int32_t a;
43     int32_t b;
44     int32_t c;
45     int32_t d;
46     uint8_t a_shift;
47     uint8_t b_shift;
48     uint8_t c_shift;
49     uint8_t x_shift;
50 };
51 
52 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
53 
54 struct Power_Calculator_Data
55 {
56   uint16_t NoLoadVoltage;
57   uint16_t LoadVoltage;
58   uint16_t Resistance;
59   uint16_t Temperature;
60   uint16_t BaseLeakage;
61   uint16_t LkgTempScalar;
62   uint16_t LkgVoltScalar;
63   uint16_t LkgAreaScalar;
64   uint16_t LkgPower;
65   uint16_t DynVoltScalar;
66   uint32_t Cac;
67   uint32_t DynPower;
68   uint32_t TotalCurrent;
69   uint32_t TotalPower;
70 };
71 
72 typedef struct Power_Calculator_Data PowerCalculatorData_t;
73 
74 struct Gc_Cac_Weight_Data
75 {
76   uint8_t index;
77   uint32_t value;
78 };
79 
80 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
81 
82 
83 typedef struct {
84   uint32_t high;
85   uint32_t low;
86 } data_64_t;
87 
88 typedef struct {
89   data_64_t high;
90   data_64_t low;
91 } data_128_t;
92 
93 #define SMU__NUM_SCLK_DPM_STATE  8
94 #define SMU__NUM_MCLK_DPM_LEVELS 4
95 #define SMU__NUM_LCLK_DPM_LEVELS 8
96 #define SMU__NUM_PCIE_DPM_LEVELS 8
97 
98 #define SMU7_CONTEXT_ID_SMC        1
99 #define SMU7_CONTEXT_ID_VBIOS      2
100 
101 #define SMU73_MAX_LEVELS_VDDC            16
102 #define SMU73_MAX_LEVELS_VDDGFX          16
103 #define SMU73_MAX_LEVELS_VDDCI           8
104 #define SMU73_MAX_LEVELS_MVDD            4
105 
106 #define SMU_MAX_SMIO_LEVELS              4
107 
108 #define SMU73_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
109 #define SMU73_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
110 #define SMU73_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
111 #define SMU73_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
112 #define SMU73_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
113 #define SMU73_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
114 #define SMU73_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
115 #define SMU73_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
116 #define SMU73_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
117 
118 #define DPM_NO_LIMIT 0
119 #define DPM_NO_UP 1
120 #define DPM_GO_DOWN 2
121 #define DPM_GO_UP 3
122 
123 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
124 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
125 
126 #define GPIO_CLAMP_MODE_VRHOT      1
127 #define GPIO_CLAMP_MODE_THERM      2
128 #define GPIO_CLAMP_MODE_DC         4
129 
130 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
131 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
132 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
133 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
134 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
135 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
136 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
137 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
138 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
139 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
140 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
141 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
142 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
143 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
144 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
145 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
146 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
147 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
148 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
149 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
150 
151 // Virtualization Defines
152 #define CG_XDMA_MASK  0x1
153 #define CG_XDMA_SHIFT 0
154 #define CG_UVD_MASK   0x2
155 #define CG_UVD_SHIFT  1
156 #define CG_VCE_MASK   0x4
157 #define CG_VCE_SHIFT  2
158 #define CG_SAMU_MASK  0x8
159 #define CG_SAMU_SHIFT 3
160 #define CG_GFX_MASK   0x10
161 #define CG_GFX_SHIFT  4
162 #define CG_SDMA_MASK  0x20
163 #define CG_SDMA_SHIFT 5
164 #define CG_HDP_MASK   0x40
165 #define CG_HDP_SHIFT  6
166 #define CG_MC_MASK    0x80
167 #define CG_MC_SHIFT   7
168 #define CG_DRM_MASK   0x100
169 #define CG_DRM_SHIFT  8
170 #define CG_ROM_MASK   0x200
171 #define CG_ROM_SHIFT  9
172 #define CG_BIF_MASK   0x400
173 #define CG_BIF_SHIFT  10
174 
175 #define SMU73_DTE_ITERATIONS 5
176 #define SMU73_DTE_SOURCES 3
177 #define SMU73_DTE_SINKS 1
178 #define SMU73_NUM_CPU_TES 0
179 #define SMU73_NUM_GPU_TES 1
180 #define SMU73_NUM_NON_TES 2
181 #define SMU73_DTE_FAN_SCALAR_MIN 0x100
182 #define SMU73_DTE_FAN_SCALAR_MAX 0x166
183 #define SMU73_DTE_FAN_TEMP_MAX 93
184 #define SMU73_DTE_FAN_TEMP_MIN 83
185 
186 #define SMU73_THERMAL_INPUT_LOOP_COUNT 6
187 #define SMU73_THERMAL_CLAMP_MODE_COUNT 8
188 
189 
190 struct SMU7_HystController_Data
191 {
192     uint16_t waterfall_up;
193     uint16_t waterfall_down;
194     uint16_t waterfall_limit;
195     uint16_t release_cnt;
196     uint16_t release_limit;
197     uint16_t spare;
198 };
199 
200 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
201 
202 struct SMU73_PIDController
203 {
204     uint32_t Ki;
205     int32_t LFWindupUpperLim;
206     int32_t LFWindupLowerLim;
207     uint32_t StatePrecision;
208 
209     uint32_t LfPrecision;
210     uint32_t LfOffset;
211     uint32_t MaxState;
212     uint32_t MaxLfFraction;
213     uint32_t StateShift;
214 };
215 
216 typedef struct SMU73_PIDController SMU73_PIDController;
217 
218 struct SMU7_LocalDpmScoreboard
219 {
220     uint32_t PercentageBusy;
221 
222     int32_t  PIDError;
223     int32_t  PIDIntegral;
224     int32_t  PIDOutput;
225 
226     uint32_t SigmaDeltaAccum;
227     uint32_t SigmaDeltaOutput;
228     uint32_t SigmaDeltaLevel;
229 
230     uint32_t UtilizationSetpoint;
231 
232     uint8_t  TdpClampMode;
233     uint8_t  TdcClampMode;
234     uint8_t  ThermClampMode;
235     uint8_t  VoltageBusy;
236 
237     int8_t   CurrLevel;
238     int8_t   TargLevel;
239     uint8_t  LevelChangeInProgress;
240     uint8_t  UpHyst;
241 
242     uint8_t  DownHyst;
243     uint8_t  VoltageDownHyst;
244     uint8_t  DpmEnable;
245     uint8_t  DpmRunning;
246 
247     uint8_t  DpmForce;
248     uint8_t  DpmForceLevel;
249     uint8_t  DisplayWatermark;
250     uint8_t  McArbIndex;
251 
252     uint32_t MinimumPerfSclk;
253 
254     uint8_t  AcpiReq;
255     uint8_t  AcpiAck;
256     uint8_t  GfxClkSlow;
257     uint8_t  GpioClampMode;
258 
259     uint8_t  spare2;
260     uint8_t  EnabledLevelsChange;
261     uint8_t  DteClampMode;
262     uint8_t  FpsClampMode;
263 
264     uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_GRAPHICS];
265     uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_GRAPHICS];
266 
267     void     (*TargetStateCalculator)(uint8_t);
268     void     (*SavedTargetStateCalculator)(uint8_t);
269 
270     uint16_t AutoDpmInterval;
271     uint16_t AutoDpmRange;
272 
273     uint8_t  FpsEnabled;
274     uint8_t  MaxPerfLevel;
275     uint8_t  AllowLowClkInterruptToHost;
276     uint8_t  FpsRunning;
277 
278     uint32_t MaxAllowedFrequency;
279 
280     uint32_t FilteredSclkFrequency;
281     uint32_t LastSclkFrequency;
282     uint32_t FilteredSclkFrequencyCnt;
283 
284     uint8_t  LedEnable;
285     uint8_t  LedPin0;
286     uint8_t  LedPin1;
287     uint8_t  LedPin2;
288     uint32_t LedAndMask;
289 
290     uint16_t FpsAlpha;
291     uint16_t DeltaTime;
292     uint32_t CurrentFps;
293     uint32_t FilteredFps;
294     uint32_t FrameCount;
295     uint32_t FrameCountLast;
296     uint16_t FpsTargetScalar;
297     uint16_t FpsWaterfallLimitScalar;
298     uint16_t FpsAlphaScalar;
299     uint16_t spare8;
300     SMU7_HystController_Data HystControllerData;
301 };
302 
303 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
304 
305 #define SMU7_MAX_VOLTAGE_CLIENTS 12
306 
307 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
308 
309 #define VDDC_MASK    0x00007FFF
310 #define VDDC_SHIFT   0
311 #define VDDCI_MASK   0x3FFF8000
312 #define VDDCI_SHIFT  15
313 #define PHASES_MASK  0xC0000000
314 #define PHASES_SHIFT 30
315 
316 typedef uint32_t SMU_VoltageLevel;
317 
318 struct SMU7_VoltageScoreboard
319 {
320     SMU_VoltageLevel TargetVoltage;
321     uint16_t MaxVid;
322     uint8_t  HighestVidOffset;
323     uint8_t  CurrentVidOffset;
324 
325     uint16_t CurrentVddc;
326     uint16_t CurrentVddci;
327 
328 
329     uint8_t  ControllerBusy;
330     uint8_t  CurrentVid;
331     uint8_t  CurrentVddciVid;
332     uint8_t  padding;
333 
334     SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
335     SMU_VoltageLevel TargetVoltageState;
336     uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
337 
338     uint8_t  padding2;
339     uint8_t  padding3;
340     uint8_t  ControllerEnable;
341     uint8_t  ControllerRunning;
342     uint16_t CurrentStdVoltageHiSidd;
343     uint16_t CurrentStdVoltageLoSidd;
344     uint8_t  OverrideVoltage;
345     uint8_t  padding4;
346     uint8_t  padding5;
347     uint8_t  CurrentPhases;
348 
349     VoltageChangeHandler_t ChangeVddc;
350 
351     VoltageChangeHandler_t ChangeVddci;
352     VoltageChangeHandler_t ChangePhase;
353     VoltageChangeHandler_t ChangeMvdd;
354 
355     VoltageChangeHandler_t functionLinks[6];
356 
357     uint16_t * VddcFollower1;
358 
359     int16_t  Driver_OD_RequestedVidOffset1;
360     int16_t  Driver_OD_RequestedVidOffset2;
361 
362 };
363 
364 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
365 
366 // -------------------------------------------------------------------------------------------------------------------------
367 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
368 
369 struct SMU7_PCIeLinkSpeedScoreboard
370 {
371     uint8_t     DpmEnable;
372     uint8_t     DpmRunning;
373     uint8_t     DpmForce;
374     uint8_t     DpmForceLevel;
375 
376     uint8_t     CurrentLinkSpeed;
377     uint8_t     EnabledLevelsChange;
378     uint16_t    AutoDpmInterval;
379 
380     uint16_t    AutoDpmRange;
381     uint16_t    AutoDpmCount;
382 
383     uint8_t     DpmMode;
384     uint8_t     AcpiReq;
385     uint8_t     AcpiAck;
386     uint8_t     CurrentLinkLevel;
387 
388 };
389 
390 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
391 
392 // -------------------------------------------------------- CAC table ------------------------------------------------------
393 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
394 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
395 
396 #define SMU7_SCALE_I  7
397 #define SMU7_SCALE_R 12
398 
399 struct SMU7_PowerScoreboard
400 {
401     uint32_t GpuPower;
402 
403     uint32_t VddcPower;
404     uint32_t VddcVoltage;
405     uint32_t VddcCurrent;
406 
407     uint32_t MvddPower;
408     uint32_t MvddVoltage;
409     uint32_t MvddCurrent;
410 
411     uint32_t RocPower;
412 
413     uint16_t Telemetry_1_slope;
414     uint16_t Telemetry_2_slope;
415     int32_t  Telemetry_1_offset;
416     int32_t  Telemetry_2_offset;
417 };
418 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
419 
420 // For FeatureEnables:
421 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
422 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
423 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
424 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
425 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
426 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
427 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
428 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
429 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
430 
431 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
432 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
433 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
434 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
435 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
436 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
437 
438 // All 'soft registers' should be uint32_t.
439 struct SMU73_SoftRegisters
440 {
441     uint32_t        RefClockFrequency;
442     uint32_t        PmTimerPeriod;
443     uint32_t        FeatureEnables;
444 
445     uint32_t        PreVBlankGap;
446     uint32_t        VBlankTimeout;
447     uint32_t        TrainTimeGap;
448 
449     uint32_t        MvddSwitchTime;
450     uint32_t        LongestAcpiTrainTime;
451     uint32_t        AcpiDelay;
452     uint32_t        G5TrainTime;
453     uint32_t        DelayMpllPwron;
454     uint32_t        VoltageChangeTimeout;
455 
456     uint32_t        HandshakeDisables;
457 
458     uint8_t         DisplayPhy1Config;
459     uint8_t         DisplayPhy2Config;
460     uint8_t         DisplayPhy3Config;
461     uint8_t         DisplayPhy4Config;
462 
463     uint8_t         DisplayPhy5Config;
464     uint8_t         DisplayPhy6Config;
465     uint8_t         DisplayPhy7Config;
466     uint8_t         DisplayPhy8Config;
467 
468     uint32_t        AverageGraphicsActivity;
469     uint32_t        AverageMemoryActivity;
470     uint32_t        AverageGioActivity;
471 
472     uint8_t         SClkDpmEnabledLevels;
473     uint8_t         MClkDpmEnabledLevels;
474     uint8_t         LClkDpmEnabledLevels;
475     uint8_t         PCIeDpmEnabledLevels;
476 
477     uint8_t         UVDDpmEnabledLevels;
478     uint8_t         SAMUDpmEnabledLevels;
479     uint8_t         ACPDpmEnabledLevels;
480     uint8_t         VCEDpmEnabledLevels;
481 
482     uint32_t        DRAM_LOG_ADDR_H;
483     uint32_t        DRAM_LOG_ADDR_L;
484     uint32_t        DRAM_LOG_PHY_ADDR_H;
485     uint32_t        DRAM_LOG_PHY_ADDR_L;
486     uint32_t        DRAM_LOG_BUFF_SIZE;
487     uint32_t        UlvEnterCount;
488     uint32_t        UlvTime;
489     uint32_t        UcodeLoadStatus;
490     uint32_t        Reserved[2];
491 
492 };
493 
494 typedef struct SMU73_SoftRegisters SMU73_SoftRegisters;
495 
496 struct SMU73_Firmware_Header
497 {
498     uint32_t Digest[5];
499     uint32_t Version;
500     uint32_t HeaderSize;
501     uint32_t Flags;
502     uint32_t EntryPoint;
503     uint32_t CodeSize;
504     uint32_t ImageSize;
505 
506     uint32_t Rtos;
507     uint32_t SoftRegisters;
508     uint32_t DpmTable;
509     uint32_t FanTable;
510     uint32_t CacConfigTable;
511     uint32_t CacStatusTable;
512 
513 
514     uint32_t mcRegisterTable;
515 
516 
517     uint32_t mcArbDramTimingTable;
518 
519 
520 
521 
522     uint32_t PmFuseTable;
523     uint32_t Globals;
524     uint32_t ClockStretcherTable;
525     uint32_t Reserved[41];
526     uint32_t Signature;
527 };
528 
529 typedef struct SMU73_Firmware_Header SMU73_Firmware_Header;
530 
531 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
532 
533 enum  DisplayConfig {
534     PowerDown = 1,
535     DP54x4,
536     DP54x2,
537     DP54x1,
538     DP27x4,
539     DP27x2,
540     DP27x1,
541     HDMI297,
542     HDMI162,
543     LVDS,
544     DP324x4,
545     DP324x2,
546     DP324x1
547 };
548 
549 
550 #define MC_BLOCK_COUNT 1
551 #define CPL_BLOCK_COUNT 5
552 #define SE_BLOCK_COUNT 15
553 #define GC_BLOCK_COUNT 24
554 
555 struct SMU7_Local_Cac {
556   uint8_t BlockId;
557   uint8_t SignalId;
558   uint8_t Threshold;
559   uint8_t Padding;
560 };
561 
562 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
563 
564 struct SMU7_Local_Cac_Table {
565 
566   SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
567   SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
568   SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
569   SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
570 };
571 
572 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
573 
574 #if !defined(SMC_MICROCODE)
575 #pragma pack(pop)
576 #endif
577 
578 // Description of Clock Gating bitmask for Tonga:
579 // System Clock Gating
580 #define CG_SYS_BITMASK_FIRST_BIT      0  // First bit of Sys CG bitmask
581 #define CG_SYS_BITMASK_LAST_BIT       9  // Last bit of Sys CG bitmask
582 #define CG_SYS_BIF_MGLS_SHIFT         0
583 #define CG_SYS_ROM_SHIFT              1
584 #define CG_SYS_MC_MGCG_SHIFT          2
585 #define CG_SYS_MC_MGLS_SHIFT          3
586 #define CG_SYS_SDMA_MGCG_SHIFT        4
587 #define CG_SYS_SDMA_MGLS_SHIFT        5
588 #define CG_SYS_DRM_MGCG_SHIFT         6
589 #define CG_SYS_HDP_MGCG_SHIFT         7
590 #define CG_SYS_HDP_MGLS_SHIFT         8
591 #define CG_SYS_DRM_MGLS_SHIFT         9
592 
593 #define CG_SYS_BIF_MGLS_MASK          0x1
594 #define CG_SYS_ROM_MASK               0x2
595 #define CG_SYS_MC_MGCG_MASK           0x4
596 #define CG_SYS_MC_MGLS_MASK           0x8
597 #define CG_SYS_SDMA_MGCG_MASK         0x10
598 #define CG_SYS_SDMA_MGLS_MASK         0x20
599 #define CG_SYS_DRM_MGCG_MASK          0x40
600 #define CG_SYS_HDP_MGCG_MASK          0x80
601 #define CG_SYS_HDP_MGLS_MASK          0x100
602 #define CG_SYS_DRM_MGLS_MASK          0x200
603 
604 // Graphics Clock Gating
605 #define CG_GFX_BITMASK_FIRST_BIT      16 // First bit of Gfx CG bitmask
606 #define CG_GFX_BITMASK_LAST_BIT       20 // Last bit of Gfx CG bitmask
607 #define CG_GFX_CGCG_SHIFT             16
608 #define CG_GFX_CGLS_SHIFT             17
609 #define CG_CPF_MGCG_SHIFT             18
610 #define CG_RLC_MGCG_SHIFT             19
611 #define CG_GFX_OTHERS_MGCG_SHIFT      20
612 
613 #define CG_GFX_CGCG_MASK              0x00010000
614 #define CG_GFX_CGLS_MASK              0x00020000
615 #define CG_CPF_MGCG_MASK              0x00040000
616 #define CG_RLC_MGCG_MASK              0x00080000
617 #define CG_GFX_OTHERS_MGCG_MASK       0x00100000
618 
619 
620 
621 // Voltage Regulator Configuration
622 // VR Config info is contained in dpmTable.VRConfig
623 
624 #define VRCONF_VDDC_MASK         0x000000FF
625 #define VRCONF_VDDC_SHIFT        0
626 #define VRCONF_VDDGFX_MASK       0x0000FF00
627 #define VRCONF_VDDGFX_SHIFT      8
628 #define VRCONF_VDDCI_MASK        0x00FF0000
629 #define VRCONF_VDDCI_SHIFT       16
630 #define VRCONF_MVDD_MASK         0xFF000000
631 #define VRCONF_MVDD_SHIFT        24
632 
633 #define VR_MERGED_WITH_VDDC      0
634 #define VR_SVI2_PLANE_1          1
635 #define VR_SVI2_PLANE_2          2
636 #define VR_SMIO_PATTERN_1        3
637 #define VR_SMIO_PATTERN_2        4
638 #define VR_STATIC_VOLTAGE        5
639 
640 // Clock Stretcher Configuration
641 
642 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4
643 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4
644 
645 // The 'settings' field is subdivided in the following way:
646 #define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
647 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
648 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
649 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
650 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
651 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
652 
653 struct SMU_ClockStretcherDataTableEntry {
654   uint8_t minVID;
655   uint8_t maxVID;
656 
657 
658   uint16_t setting;
659 };
660 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
661 
662 struct SMU_ClockStretcherDataTable {
663   SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
664 };
665 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
666 
667 struct SMU_CKS_LOOKUPTableEntry {
668   uint16_t minFreq;
669   uint16_t maxFreq;
670 
671   uint8_t setting;
672   uint8_t padding[3];
673 };
674 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
675 
676 struct SMU_CKS_LOOKUPTable {
677   SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
678 };
679 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
680 
681 struct AgmAvfsData_t {
682   uint16_t avgPsmCount[28];
683   uint16_t minPsmCount[28];
684 };
685 typedef struct AgmAvfsData_t AgmAvfsData_t;
686 
687 // AVFS DEFINES
688 
689 enum VFT_COLUMNS {
690   SCLK0,
691   SCLK1,
692   SCLK2,
693   SCLK3,
694   SCLK4,
695   SCLK5,
696   SCLK6,
697   SCLK7,
698 
699   NUM_VFT_COLUMNS
700 };
701 
702 #define TEMP_RANGE_MAXSTEPS 12
703 struct VFT_CELL_t {
704   uint16_t Voltage;
705 };
706 
707 typedef struct VFT_CELL_t VFT_CELL_t;
708 
709 struct VFT_TABLE_t {
710   VFT_CELL_t    Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
711   uint16_t      AvfsGbv [NUM_VFT_COLUMNS];
712   uint16_t      BtcGbv  [NUM_VFT_COLUMNS];
713   uint16_t      Temperature [TEMP_RANGE_MAXSTEPS];
714 
715   uint8_t       NumTemperatureSteps;
716   uint8_t       padding[3];
717 };
718 typedef struct VFT_TABLE_t VFT_TABLE_t;
719 
720 #endif
721