1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef SMU71_H
24 #define SMU71_H
25 
26 #if !defined(SMC_MICROCODE)
27 #pragma pack(push, 1)
28 #endif
29 
30 #define SMU__NUM_PCIE_DPM_LEVELS 8
31 #define SMU__NUM_SCLK_DPM_STATE 8
32 #define SMU__NUM_MCLK_DPM_LEVELS 4
33 #define SMU__VARIANT__ICELAND 1
34 #define SMU__DGPU_ONLY 1
35 #define SMU__DYNAMIC_MCARB_SETTINGS 1
36 
37 enum SID_OPTION {
38   SID_OPTION_HI,
39   SID_OPTION_LO,
40   SID_OPTION_COUNT
41 };
42 
43 typedef struct {
44   uint32_t high;
45   uint32_t low;
46 } data_64_t;
47 
48 typedef struct {
49   data_64_t high;
50   data_64_t low;
51 } data_128_t;
52 
53 #define SMU7_CONTEXT_ID_SMC        1
54 #define SMU7_CONTEXT_ID_VBIOS      2
55 
56 #define SMU71_MAX_LEVELS_VDDC            8
57 #define SMU71_MAX_LEVELS_VDDCI           4
58 #define SMU71_MAX_LEVELS_MVDD            4
59 #define SMU71_MAX_LEVELS_VDDNB           8
60 
61 #define SMU71_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE
62 #define SMU71_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS
63 #define SMU71_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS
64 #define SMU71_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS
65 #define SMU71_MAX_ENTRIES_SMIO           32
66 
67 #define DPM_NO_LIMIT 0
68 #define DPM_NO_UP 1
69 #define DPM_GO_DOWN 2
70 #define DPM_GO_UP 3
71 
72 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
73 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
74 
75 #define GPIO_CLAMP_MODE_VRHOT      1
76 #define GPIO_CLAMP_MODE_THERM      2
77 #define GPIO_CLAMP_MODE_DC         4
78 
79 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
80 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
81 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
82 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
83 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
84 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
85 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
86 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
87 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
88 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
89 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
90 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
91 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
92 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
93 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
94 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
95 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
96 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
97 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
98 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
99 
100 
101 #if defined SMU__DGPU_ONLY
102 #define SMU71_DTE_ITERATIONS 5
103 #define SMU71_DTE_SOURCES 3
104 #define SMU71_DTE_SINKS 1
105 #define SMU71_NUM_CPU_TES 0
106 #define SMU71_NUM_GPU_TES 1
107 #define SMU71_NUM_NON_TES 2
108 
109 #endif
110 
111 #if defined SMU__FUSION_ONLY
112 #define SMU7_DTE_ITERATIONS 5
113 #define SMU7_DTE_SOURCES 5
114 #define SMU7_DTE_SINKS 3
115 #define SMU7_NUM_CPU_TES 2
116 #define SMU7_NUM_GPU_TES 1
117 #define SMU7_NUM_NON_TES 2
118 
119 #endif
120 
121 struct SMU71_PIDController
122 {
123     uint32_t Ki;
124     int32_t LFWindupUpperLim;
125     int32_t LFWindupLowerLim;
126     uint32_t StatePrecision;
127     uint32_t LfPrecision;
128     uint32_t LfOffset;
129     uint32_t MaxState;
130     uint32_t MaxLfFraction;
131     uint32_t StateShift;
132 };
133 
134 typedef struct SMU71_PIDController SMU71_PIDController;
135 
136 struct SMU7_LocalDpmScoreboard
137 {
138     uint32_t PercentageBusy;
139 
140     int32_t  PIDError;
141     int32_t  PIDIntegral;
142     int32_t  PIDOutput;
143 
144     uint32_t SigmaDeltaAccum;
145     uint32_t SigmaDeltaOutput;
146     uint32_t SigmaDeltaLevel;
147 
148     uint32_t UtilizationSetpoint;
149 
150     uint8_t  TdpClampMode;
151     uint8_t  TdcClampMode;
152     uint8_t  ThermClampMode;
153     uint8_t  VoltageBusy;
154 
155     int8_t   CurrLevel;
156     int8_t   TargLevel;
157     uint8_t  LevelChangeInProgress;
158     uint8_t  UpHyst;
159 
160     uint8_t  DownHyst;
161     uint8_t  VoltageDownHyst;
162     uint8_t  DpmEnable;
163     uint8_t  DpmRunning;
164 
165     uint8_t  DpmForce;
166     uint8_t  DpmForceLevel;
167     uint8_t  DisplayWatermark;
168     uint8_t  McArbIndex;
169 
170     uint32_t MinimumPerfSclk;
171 
172     uint8_t  AcpiReq;
173     uint8_t  AcpiAck;
174     uint8_t  GfxClkSlow;
175     uint8_t  GpioClampMode;
176 
177     uint8_t  FpsFilterWeight;
178     uint8_t  EnabledLevelsChange;
179     uint8_t  DteClampMode;
180     uint8_t  FpsClampMode;
181 
182     uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_GRAPHICS];
183     uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_GRAPHICS];
184 
185     void     (*TargetStateCalculator)(uint8_t);
186     void     (*SavedTargetStateCalculator)(uint8_t);
187 
188     uint16_t AutoDpmInterval;
189     uint16_t AutoDpmRange;
190 
191     uint8_t  FpsEnabled;
192     uint8_t  MaxPerfLevel;
193     uint8_t  AllowLowClkInterruptToHost;
194     uint8_t  FpsRunning;
195 
196     uint32_t MaxAllowedFrequency;
197 };
198 
199 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
200 
201 #define SMU7_MAX_VOLTAGE_CLIENTS 12
202 
203 struct SMU7_VoltageScoreboard
204 {
205     uint16_t CurrentVoltage;
206     uint16_t HighestVoltage;
207     uint16_t MaxVid;
208     uint8_t  HighestVidOffset;
209     uint8_t  CurrentVidOffset;
210 #if defined (SMU__DGPU_ONLY)
211     uint8_t  CurrentPhases;
212     uint8_t  HighestPhases;
213 #else
214     uint8_t  AvsOffset;
215     uint8_t  AvsOffsetApplied;
216 #endif
217     uint8_t  ControllerBusy;
218     uint8_t  CurrentVid;
219     uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
220 #if defined (SMU__DGPU_ONLY)
221     uint8_t  RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];
222 #endif
223     uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
224     uint8_t  TargetIndex;
225     uint8_t  Delay;
226     uint8_t  ControllerEnable;
227     uint8_t  ControllerRunning;
228     uint16_t CurrentStdVoltageHiSidd;
229     uint16_t CurrentStdVoltageLoSidd;
230 #if defined (SMU__DGPU_ONLY)
231     uint16_t RequestedVddci;
232     uint16_t CurrentVddci;
233     uint16_t HighestVddci;
234     uint8_t  CurrentVddciVid;
235     uint8_t  TargetVddciIndex;
236 #endif
237 };
238 
239 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
240 
241 // -------------------------------------------------------------------------------------------------------------------------
242 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
243 
244 struct SMU7_PCIeLinkSpeedScoreboard
245 {
246     uint8_t     DpmEnable;
247     uint8_t     DpmRunning;
248     uint8_t     DpmForce;
249     uint8_t     DpmForceLevel;
250 
251     uint8_t     CurrentLinkSpeed;
252     uint8_t     EnabledLevelsChange;
253     uint16_t    AutoDpmInterval;
254 
255     uint16_t    AutoDpmRange;
256     uint16_t    AutoDpmCount;
257 
258     uint8_t     DpmMode;
259     uint8_t     AcpiReq;
260     uint8_t     AcpiAck;
261     uint8_t     CurrentLinkLevel;
262 
263 };
264 
265 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
266 
267 // -------------------------------------------------------- CAC table ------------------------------------------------------
268 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
269 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
270 
271 #define SMU7_SCALE_I  7
272 #define SMU7_SCALE_R 12
273 
274 struct SMU7_PowerScoreboard
275 {
276     uint16_t   MinVoltage;
277     uint16_t   MaxVoltage;
278 
279     uint32_t   AvgGpuPower;
280 
281     uint16_t   VddcLeakagePower[SID_OPTION_COUNT];
282     uint16_t   VddcSclkConstantPower[SID_OPTION_COUNT];
283     uint16_t   VddcSclkDynamicPower[SID_OPTION_COUNT];
284     uint16_t   VddcNonSclkDynamicPower[SID_OPTION_COUNT];
285     uint16_t   VddcTotalPower[SID_OPTION_COUNT];
286     uint16_t   VddcTotalCurrent[SID_OPTION_COUNT];
287     uint16_t   VddcLoadVoltage[SID_OPTION_COUNT];
288     uint16_t   VddcNoLoadVoltage[SID_OPTION_COUNT];
289 
290     uint16_t   DisplayPhyPower;
291     uint16_t   PciePhyPower;
292 
293     uint16_t   VddciTotalPower;
294     uint16_t   Vddr1TotalPower;
295 
296     uint32_t   RocPower;
297 
298     uint32_t   last_power;
299     uint32_t   enableWinAvg;
300 
301     uint32_t   lkg_acc;
302     uint16_t   VoltLkgeScaler;
303     uint16_t   TempLkgeScaler;
304 
305     uint32_t   uvd_cac_dclk;
306     uint32_t   uvd_cac_vclk;
307     uint32_t   vce_cac_eclk;
308     uint32_t   samu_cac_samclk;
309     uint32_t   display_cac_dispclk;
310     uint32_t   acp_cac_aclk;
311     uint32_t   unb_cac;
312 
313     uint32_t   WinTime;
314 
315     uint16_t  GpuPwr_MAWt;
316     uint16_t  FilteredVddcTotalPower;
317 
318     uint8_t   CalculationRepeats;
319     uint8_t   WaterfallUp;
320     uint8_t   WaterfallDown;
321     uint8_t   WaterfallLimit;
322 };
323 
324 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
325 
326 // --------------------------------------------------------------------------------------------------
327 
328 struct SMU7_ThermalScoreboard
329 {
330    int16_t  GpuLimit;
331    int16_t  GpuHyst;
332    uint16_t CurrGnbTemp;
333    uint16_t FilteredGnbTemp;
334    uint8_t  ControllerEnable;
335    uint8_t  ControllerRunning;
336    uint8_t  WaterfallUp;
337    uint8_t  WaterfallDown;
338    uint8_t  WaterfallLimit;
339    uint8_t  padding[3];
340 };
341 
342 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
343 
344 // For FeatureEnables:
345 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
346 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
347 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
348 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
349 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
350 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
351 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
352 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
353 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
354 
355 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
356 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
357 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
358 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
359 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
360 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
361 
362 // All 'soft registers' should be uint32_t.
363 struct SMU71_SoftRegisters
364 {
365     uint32_t        RefClockFrequency;
366     uint32_t        PmTimerPeriod;
367     uint32_t        FeatureEnables;
368 #if defined (SMU__DGPU_ONLY)
369     uint32_t        PreVBlankGap;
370     uint32_t        VBlankTimeout;
371     uint32_t        TrainTimeGap;
372     uint32_t        MvddSwitchTime;
373     uint32_t        LongestAcpiTrainTime;
374     uint32_t        AcpiDelay;
375     uint32_t        G5TrainTime;
376     uint32_t        DelayMpllPwron;
377     uint32_t        VoltageChangeTimeout;
378 #endif
379     uint32_t        HandshakeDisables;
380 
381     uint8_t         DisplayPhy1Config;
382     uint8_t         DisplayPhy2Config;
383     uint8_t         DisplayPhy3Config;
384     uint8_t         DisplayPhy4Config;
385 
386     uint8_t         DisplayPhy5Config;
387     uint8_t         DisplayPhy6Config;
388     uint8_t         DisplayPhy7Config;
389     uint8_t         DisplayPhy8Config;
390 
391     uint32_t        AverageGraphicsActivity;
392     uint32_t        AverageMemoryActivity;
393     uint32_t        AverageGioActivity;
394 
395     uint8_t         SClkDpmEnabledLevels;
396     uint8_t         MClkDpmEnabledLevels;
397     uint8_t         LClkDpmEnabledLevels;
398     uint8_t         PCIeDpmEnabledLevels;
399 
400     uint32_t        DRAM_LOG_ADDR_H;
401     uint32_t        DRAM_LOG_ADDR_L;
402     uint32_t        DRAM_LOG_PHY_ADDR_H;
403     uint32_t        DRAM_LOG_PHY_ADDR_L;
404     uint32_t        DRAM_LOG_BUFF_SIZE;
405     uint32_t        UlvEnterCount;
406     uint32_t        UlvTime;
407     uint32_t        UcodeLoadStatus;
408     uint8_t         DPMFreezeAndForced;
409     uint8_t         Activity_Weight;
410     uint8_t         Reserved8[2];
411     uint32_t        Reserved;
412 };
413 
414 typedef struct SMU71_SoftRegisters SMU71_SoftRegisters;
415 
416 struct SMU71_Firmware_Header
417 {
418     uint32_t Digest[5];
419     uint32_t Version;
420     uint32_t HeaderSize;
421     uint32_t Flags;
422     uint32_t EntryPoint;
423     uint32_t CodeSize;
424     uint32_t ImageSize;
425 
426     uint32_t Rtos;
427     uint32_t SoftRegisters;
428     uint32_t DpmTable;
429     uint32_t FanTable;
430     uint32_t CacConfigTable;
431     uint32_t CacStatusTable;
432 
433     uint32_t mcRegisterTable;
434 
435     uint32_t mcArbDramTimingTable;
436 
437     uint32_t PmFuseTable;
438     uint32_t Globals;
439     uint32_t UvdDpmTable;
440     uint32_t AcpDpmTable;
441     uint32_t VceDpmTable;
442     uint32_t SamuDpmTable;
443     uint32_t UlvSettings;
444     uint32_t Reserved[37];
445     uint32_t Signature;
446 };
447 
448 typedef struct SMU71_Firmware_Header SMU71_Firmware_Header;
449 
450 struct SMU7_HystController_Data
451 {
452     uint8_t waterfall_up;
453     uint8_t waterfall_down;
454     uint8_t pstate;
455     uint8_t clamp_mode;
456 };
457 
458 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
459 
460 #define SMU71_FIRMWARE_HEADER_LOCATION 0x20000
461 
462 enum  DisplayConfig {
463     PowerDown = 1,
464     DP54x4,
465     DP54x2,
466     DP54x1,
467     DP27x4,
468     DP27x2,
469     DP27x1,
470     HDMI297,
471     HDMI162,
472     LVDS,
473     DP324x4,
474     DP324x2,
475     DP324x1
476 };
477 
478 //#define SX_BLOCK_COUNT 8
479 //#define MC_BLOCK_COUNT 1
480 //#define CPL_BLOCK_COUNT 27
481 
482 #if defined SMU__VARIANT__ICELAND
483   #define SX_BLOCK_COUNT 8
484   #define MC_BLOCK_COUNT 1
485   #define CPL_BLOCK_COUNT 29
486 #endif
487 
488 struct SMU7_Local_Cac {
489   uint8_t BlockId;
490   uint8_t SignalId;
491   uint8_t Threshold;
492   uint8_t Padding;
493 };
494 
495 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
496 
497 struct SMU7_Local_Cac_Table {
498   SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT];
499   SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
500   SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
501 };
502 
503 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
504 
505 #if !defined(SMC_MICROCODE)
506 #pragma pack(pop)
507 #endif
508 
509 #endif
510 
511