1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef SMU7_H
25 #define SMU7_H
26 
27 #pragma pack(push, 1)
28 
29 #define SMU7_CONTEXT_ID_SMC        1
30 #define SMU7_CONTEXT_ID_VBIOS      2
31 
32 
33 #define SMU7_CONTEXT_ID_SMC        1
34 #define SMU7_CONTEXT_ID_VBIOS      2
35 
36 #define SMU7_MAX_LEVELS_VDDC            8
37 #define SMU7_MAX_LEVELS_VDDCI           4
38 #define SMU7_MAX_LEVELS_MVDD            4
39 #define SMU7_MAX_LEVELS_VDDNB           8
40 
41 #define SMU7_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
42 #define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
43 #define SMU7_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
44 #define SMU7_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
45 #define SMU7_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
46 #define SMU7_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
47 #define SMU7_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
48 #define SMU7_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
49 #define SMU7_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
50 
51 #define DPM_NO_LIMIT 0
52 #define DPM_NO_UP 1
53 #define DPM_GO_DOWN 2
54 #define DPM_GO_UP 3
55 
56 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
57 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
58 
59 #define GPIO_CLAMP_MODE_VRHOT      1
60 #define GPIO_CLAMP_MODE_THERM      2
61 #define GPIO_CLAMP_MODE_DC         4
62 
63 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
64 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
65 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
66 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
67 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
68 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
69 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
70 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
71 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
72 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
73 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
74 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
75 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
76 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
77 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
78 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
79 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
80 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
81 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
82 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
83 
84 
85 /* Voltage Regulator Configuration */
86 /* VR Config info is contained in dpmTable */
87 
88 #define VRCONF_VDDC_MASK         0x000000FF
89 #define VRCONF_VDDC_SHIFT        0
90 #define VRCONF_VDDGFX_MASK       0x0000FF00
91 #define VRCONF_VDDGFX_SHIFT      8
92 #define VRCONF_VDDCI_MASK        0x00FF0000
93 #define VRCONF_VDDCI_SHIFT       16
94 #define VRCONF_MVDD_MASK         0xFF000000
95 #define VRCONF_MVDD_SHIFT        24
96 
97 #define VR_MERGED_WITH_VDDC      0
98 #define VR_SVI2_PLANE_1          1
99 #define VR_SVI2_PLANE_2          2
100 #define VR_SMIO_PATTERN_1        3
101 #define VR_SMIO_PATTERN_2        4
102 #define VR_STATIC_VOLTAGE        5
103 
104 struct SMU7_PIDController
105 {
106     uint32_t Ki;
107     int32_t LFWindupUL;
108     int32_t LFWindupLL;
109     uint32_t StatePrecision;
110     uint32_t LfPrecision;
111     uint32_t LfOffset;
112     uint32_t MaxState;
113     uint32_t MaxLfFraction;
114     uint32_t StateShift;
115 };
116 
117 typedef struct SMU7_PIDController SMU7_PIDController;
118 
119 // -------------------------------------------------------------------------------------------------------------------------
120 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
121 
122 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
123 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
124 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
125 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
126 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
127 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
128 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
129 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
130 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
131 
132 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
133 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
134 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
135 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
136 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
137 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
138 
139 struct SMU7_Firmware_Header
140 {
141     uint32_t Digest[5];
142     uint32_t Version;
143     uint32_t HeaderSize;
144     uint32_t Flags;
145     uint32_t EntryPoint;
146     uint32_t CodeSize;
147     uint32_t ImageSize;
148 
149     uint32_t Rtos;
150     uint32_t SoftRegisters;
151     uint32_t DpmTable;
152     uint32_t FanTable;
153     uint32_t CacConfigTable;
154     uint32_t CacStatusTable;
155 
156     uint32_t mcRegisterTable;
157 
158     uint32_t mcArbDramTimingTable;
159 
160     uint32_t PmFuseTable;
161     uint32_t Globals;
162     uint32_t Reserved[42];
163     uint32_t Signature;
164 };
165 
166 typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
167 
168 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
169 
170 enum  DisplayConfig {
171     PowerDown = 1,
172     DP54x4,
173     DP54x2,
174     DP54x1,
175     DP27x4,
176     DP27x2,
177     DP27x1,
178     HDMI297,
179     HDMI162,
180     LVDS,
181     DP324x4,
182     DP324x2,
183     DP324x1
184 };
185 
186 #pragma pack(pop)
187 
188 #endif
189 
190