1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2013 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan 24*837d542aSEvan Quan #ifndef SMU7_H 25*837d542aSEvan Quan #define SMU7_H 26*837d542aSEvan Quan 27*837d542aSEvan Quan #pragma pack(push, 1) 28*837d542aSEvan Quan 29*837d542aSEvan Quan #define SMU7_CONTEXT_ID_SMC 1 30*837d542aSEvan Quan #define SMU7_CONTEXT_ID_VBIOS 2 31*837d542aSEvan Quan 32*837d542aSEvan Quan 33*837d542aSEvan Quan #define SMU7_CONTEXT_ID_SMC 1 34*837d542aSEvan Quan #define SMU7_CONTEXT_ID_VBIOS 2 35*837d542aSEvan Quan 36*837d542aSEvan Quan #define SMU7_MAX_LEVELS_VDDC 8 37*837d542aSEvan Quan #define SMU7_MAX_LEVELS_VDDCI 4 38*837d542aSEvan Quan #define SMU7_MAX_LEVELS_MVDD 4 39*837d542aSEvan Quan #define SMU7_MAX_LEVELS_VDDNB 8 40*837d542aSEvan Quan 41*837d542aSEvan Quan #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 42*837d542aSEvan Quan #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 43*837d542aSEvan Quan #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 44*837d542aSEvan Quan #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 45*837d542aSEvan Quan #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 46*837d542aSEvan Quan #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 47*837d542aSEvan Quan #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 48*837d542aSEvan Quan #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 49*837d542aSEvan Quan #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 50*837d542aSEvan Quan 51*837d542aSEvan Quan #define DPM_NO_LIMIT 0 52*837d542aSEvan Quan #define DPM_NO_UP 1 53*837d542aSEvan Quan #define DPM_GO_DOWN 2 54*837d542aSEvan Quan #define DPM_GO_UP 3 55*837d542aSEvan Quan 56*837d542aSEvan Quan #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 57*837d542aSEvan Quan #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 58*837d542aSEvan Quan 59*837d542aSEvan Quan #define GPIO_CLAMP_MODE_VRHOT 1 60*837d542aSEvan Quan #define GPIO_CLAMP_MODE_THERM 2 61*837d542aSEvan Quan #define GPIO_CLAMP_MODE_DC 4 62*837d542aSEvan Quan 63*837d542aSEvan Quan #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 64*837d542aSEvan Quan #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 65*837d542aSEvan Quan #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 66*837d542aSEvan Quan #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 67*837d542aSEvan Quan #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 68*837d542aSEvan Quan #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 69*837d542aSEvan Quan #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 70*837d542aSEvan Quan #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 71*837d542aSEvan Quan #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 72*837d542aSEvan Quan #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 73*837d542aSEvan Quan #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 74*837d542aSEvan Quan #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 75*837d542aSEvan Quan #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 76*837d542aSEvan Quan #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 77*837d542aSEvan Quan #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 78*837d542aSEvan Quan #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 79*837d542aSEvan Quan #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 80*837d542aSEvan Quan #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 81*837d542aSEvan Quan #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 82*837d542aSEvan Quan #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 83*837d542aSEvan Quan 84*837d542aSEvan Quan 85*837d542aSEvan Quan /* Voltage Regulator Configuration */ 86*837d542aSEvan Quan /* VR Config info is contained in dpmTable */ 87*837d542aSEvan Quan 88*837d542aSEvan Quan #define VRCONF_VDDC_MASK 0x000000FF 89*837d542aSEvan Quan #define VRCONF_VDDC_SHIFT 0 90*837d542aSEvan Quan #define VRCONF_VDDGFX_MASK 0x0000FF00 91*837d542aSEvan Quan #define VRCONF_VDDGFX_SHIFT 8 92*837d542aSEvan Quan #define VRCONF_VDDCI_MASK 0x00FF0000 93*837d542aSEvan Quan #define VRCONF_VDDCI_SHIFT 16 94*837d542aSEvan Quan #define VRCONF_MVDD_MASK 0xFF000000 95*837d542aSEvan Quan #define VRCONF_MVDD_SHIFT 24 96*837d542aSEvan Quan 97*837d542aSEvan Quan #define VR_MERGED_WITH_VDDC 0 98*837d542aSEvan Quan #define VR_SVI2_PLANE_1 1 99*837d542aSEvan Quan #define VR_SVI2_PLANE_2 2 100*837d542aSEvan Quan #define VR_SMIO_PATTERN_1 3 101*837d542aSEvan Quan #define VR_SMIO_PATTERN_2 4 102*837d542aSEvan Quan #define VR_STATIC_VOLTAGE 5 103*837d542aSEvan Quan 104*837d542aSEvan Quan struct SMU7_PIDController 105*837d542aSEvan Quan { 106*837d542aSEvan Quan uint32_t Ki; 107*837d542aSEvan Quan int32_t LFWindupUL; 108*837d542aSEvan Quan int32_t LFWindupLL; 109*837d542aSEvan Quan uint32_t StatePrecision; 110*837d542aSEvan Quan uint32_t LfPrecision; 111*837d542aSEvan Quan uint32_t LfOffset; 112*837d542aSEvan Quan uint32_t MaxState; 113*837d542aSEvan Quan uint32_t MaxLfFraction; 114*837d542aSEvan Quan uint32_t StateShift; 115*837d542aSEvan Quan }; 116*837d542aSEvan Quan 117*837d542aSEvan Quan typedef struct SMU7_PIDController SMU7_PIDController; 118*837d542aSEvan Quan 119*837d542aSEvan Quan // ------------------------------------------------------------------------------------------------------------------------- 120*837d542aSEvan Quan #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 121*837d542aSEvan Quan 122*837d542aSEvan Quan #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 123*837d542aSEvan Quan #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 124*837d542aSEvan Quan #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 125*837d542aSEvan Quan #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 126*837d542aSEvan Quan #define SMU7_UVD_DPM_CONFIG_MASK 0x10 127*837d542aSEvan Quan #define SMU7_VCE_DPM_CONFIG_MASK 0x20 128*837d542aSEvan Quan #define SMU7_ACP_DPM_CONFIG_MASK 0x40 129*837d542aSEvan Quan #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 130*837d542aSEvan Quan #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 131*837d542aSEvan Quan 132*837d542aSEvan Quan #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 133*837d542aSEvan Quan #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 134*837d542aSEvan Quan #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 135*837d542aSEvan Quan #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 136*837d542aSEvan Quan #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 137*837d542aSEvan Quan #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 138*837d542aSEvan Quan 139*837d542aSEvan Quan struct SMU7_Firmware_Header 140*837d542aSEvan Quan { 141*837d542aSEvan Quan uint32_t Digest[5]; 142*837d542aSEvan Quan uint32_t Version; 143*837d542aSEvan Quan uint32_t HeaderSize; 144*837d542aSEvan Quan uint32_t Flags; 145*837d542aSEvan Quan uint32_t EntryPoint; 146*837d542aSEvan Quan uint32_t CodeSize; 147*837d542aSEvan Quan uint32_t ImageSize; 148*837d542aSEvan Quan 149*837d542aSEvan Quan uint32_t Rtos; 150*837d542aSEvan Quan uint32_t SoftRegisters; 151*837d542aSEvan Quan uint32_t DpmTable; 152*837d542aSEvan Quan uint32_t FanTable; 153*837d542aSEvan Quan uint32_t CacConfigTable; 154*837d542aSEvan Quan uint32_t CacStatusTable; 155*837d542aSEvan Quan 156*837d542aSEvan Quan uint32_t mcRegisterTable; 157*837d542aSEvan Quan 158*837d542aSEvan Quan uint32_t mcArbDramTimingTable; 159*837d542aSEvan Quan 160*837d542aSEvan Quan uint32_t PmFuseTable; 161*837d542aSEvan Quan uint32_t Globals; 162*837d542aSEvan Quan uint32_t Reserved[42]; 163*837d542aSEvan Quan uint32_t Signature; 164*837d542aSEvan Quan }; 165*837d542aSEvan Quan 166*837d542aSEvan Quan typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; 167*837d542aSEvan Quan 168*837d542aSEvan Quan #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 169*837d542aSEvan Quan 170*837d542aSEvan Quan enum DisplayConfig { 171*837d542aSEvan Quan PowerDown = 1, 172*837d542aSEvan Quan DP54x4, 173*837d542aSEvan Quan DP54x2, 174*837d542aSEvan Quan DP54x1, 175*837d542aSEvan Quan DP27x4, 176*837d542aSEvan Quan DP27x2, 177*837d542aSEvan Quan DP27x1, 178*837d542aSEvan Quan HDMI297, 179*837d542aSEvan Quan HDMI162, 180*837d542aSEvan Quan LVDS, 181*837d542aSEvan Quan DP324x4, 182*837d542aSEvan Quan DP324x2, 183*837d542aSEvan Quan DP324x1 184*837d542aSEvan Quan }; 185*837d542aSEvan Quan 186*837d542aSEvan Quan #pragma pack(pop) 187*837d542aSEvan Quan 188*837d542aSEvan Quan #endif 189*837d542aSEvan Quan 190