1*837d542aSEvan Quan /* 2*837d542aSEvan Quan * Copyright 2017 Advanced Micro Devices, Inc. 3*837d542aSEvan Quan * 4*837d542aSEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5*837d542aSEvan Quan * copy of this software and associated documentation files (the "Software"), 6*837d542aSEvan Quan * to deal in the Software without restriction, including without limitation 7*837d542aSEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*837d542aSEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9*837d542aSEvan Quan * Software is furnished to do so, subject to the following conditions: 10*837d542aSEvan Quan * 11*837d542aSEvan Quan * The above copyright notice and this permission notice shall be included in 12*837d542aSEvan Quan * all copies or substantial portions of the Software. 13*837d542aSEvan Quan * 14*837d542aSEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*837d542aSEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*837d542aSEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*837d542aSEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*837d542aSEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*837d542aSEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*837d542aSEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21*837d542aSEvan Quan * 22*837d542aSEvan Quan */ 23*837d542aSEvan Quan 24*837d542aSEvan Quan #ifndef SMU10_H 25*837d542aSEvan Quan #define SMU10_H 26*837d542aSEvan Quan 27*837d542aSEvan Quan #pragma pack(push, 1) 28*837d542aSEvan Quan 29*837d542aSEvan Quan #define ENABLE_DEBUG_FEATURES 30*837d542aSEvan Quan 31*837d542aSEvan Quan /* Feature Control Defines */ 32*837d542aSEvan Quan #define FEATURE_CCLK_CONTROLLER_BIT 0 33*837d542aSEvan Quan #define FEATURE_FAN_CONTROLLER_BIT 1 34*837d542aSEvan Quan #define FEATURE_DATA_CALCULATION_BIT 2 35*837d542aSEvan Quan #define FEATURE_PPT_BIT 3 36*837d542aSEvan Quan #define FEATURE_TDC_BIT 4 37*837d542aSEvan Quan #define FEATURE_THERMAL_BIT 5 38*837d542aSEvan Quan #define FEATURE_FIT_BIT 6 39*837d542aSEvan Quan #define FEATURE_EDC_BIT 7 40*837d542aSEvan Quan #define FEATURE_PLL_POWER_DOWN_BIT 8 41*837d542aSEvan Quan #define FEATURE_ULV_BIT 9 42*837d542aSEvan Quan #define FEATURE_VDDOFF_BIT 10 43*837d542aSEvan Quan #define FEATURE_VCN_DPM_BIT 11 44*837d542aSEvan Quan #define FEATURE_ACP_DPM_BIT 12 45*837d542aSEvan Quan #define FEATURE_ISP_DPM_BIT 13 46*837d542aSEvan Quan #define FEATURE_FCLK_DPM_BIT 14 47*837d542aSEvan Quan #define FEATURE_SOCCLK_DPM_BIT 15 48*837d542aSEvan Quan #define FEATURE_MP0CLK_DPM_BIT 16 49*837d542aSEvan Quan #define FEATURE_LCLK_DPM_BIT 17 50*837d542aSEvan Quan #define FEATURE_SHUBCLK_DPM_BIT 18 51*837d542aSEvan Quan #define FEATURE_DCEFCLK_DPM_BIT 19 52*837d542aSEvan Quan #define FEATURE_GFX_DPM_BIT 20 53*837d542aSEvan Quan #define FEATURE_DS_GFXCLK_BIT 21 54*837d542aSEvan Quan #define FEATURE_DS_SOCCLK_BIT 22 55*837d542aSEvan Quan #define FEATURE_DS_LCLK_BIT 23 56*837d542aSEvan Quan #define FEATURE_DS_DCEFCLK_BIT 24 57*837d542aSEvan Quan #define FEATURE_DS_SHUBCLK_BIT 25 58*837d542aSEvan Quan #define FEATURE_RM_BIT 26 59*837d542aSEvan Quan #define FEATURE_S0i2_BIT 27 60*837d542aSEvan Quan #define FEATURE_WHISPER_MODE_BIT 28 61*837d542aSEvan Quan #define FEATURE_DS_FCLK_BIT 29 62*837d542aSEvan Quan #define FEATURE_DS_SMNCLK_BIT 30 63*837d542aSEvan Quan #define FEATURE_DS_MP1CLK_BIT 31 64*837d542aSEvan Quan #define FEATURE_DS_MP0CLK_BIT 32 65*837d542aSEvan Quan #define FEATURE_MGCG_BIT 33 66*837d542aSEvan Quan #define FEATURE_DS_FUSE_SRAM_BIT 34 67*837d542aSEvan Quan #define FEATURE_GFX_CKS 35 68*837d542aSEvan Quan #define FEATURE_PSI0_BIT 36 69*837d542aSEvan Quan #define FEATURE_PROCHOT_BIT 37 70*837d542aSEvan Quan #define FEATURE_CPUOFF_BIT 38 71*837d542aSEvan Quan #define FEATURE_STAPM_BIT 39 72*837d542aSEvan Quan #define FEATURE_CORE_CSTATES_BIT 40 73*837d542aSEvan Quan #define FEATURE_SPARE_41_BIT 41 74*837d542aSEvan Quan #define FEATURE_SPARE_42_BIT 42 75*837d542aSEvan Quan #define FEATURE_SPARE_43_BIT 43 76*837d542aSEvan Quan #define FEATURE_SPARE_44_BIT 44 77*837d542aSEvan Quan #define FEATURE_SPARE_45_BIT 45 78*837d542aSEvan Quan #define FEATURE_SPARE_46_BIT 46 79*837d542aSEvan Quan #define FEATURE_SPARE_47_BIT 47 80*837d542aSEvan Quan #define FEATURE_SPARE_48_BIT 48 81*837d542aSEvan Quan #define FEATURE_SPARE_49_BIT 49 82*837d542aSEvan Quan #define FEATURE_SPARE_50_BIT 50 83*837d542aSEvan Quan #define FEATURE_SPARE_51_BIT 51 84*837d542aSEvan Quan #define FEATURE_SPARE_52_BIT 52 85*837d542aSEvan Quan #define FEATURE_SPARE_53_BIT 53 86*837d542aSEvan Quan #define FEATURE_SPARE_54_BIT 54 87*837d542aSEvan Quan #define FEATURE_SPARE_55_BIT 55 88*837d542aSEvan Quan #define FEATURE_SPARE_56_BIT 56 89*837d542aSEvan Quan #define FEATURE_SPARE_57_BIT 57 90*837d542aSEvan Quan #define FEATURE_SPARE_58_BIT 58 91*837d542aSEvan Quan #define FEATURE_SPARE_59_BIT 59 92*837d542aSEvan Quan #define FEATURE_SPARE_60_BIT 60 93*837d542aSEvan Quan #define FEATURE_SPARE_61_BIT 61 94*837d542aSEvan Quan #define FEATURE_SPARE_62_BIT 62 95*837d542aSEvan Quan #define FEATURE_SPARE_63_BIT 63 96*837d542aSEvan Quan 97*837d542aSEvan Quan #define NUM_FEATURES 64 98*837d542aSEvan Quan 99*837d542aSEvan Quan #define FEATURE_CCLK_CONTROLLER_MASK (1 << FEATURE_CCLK_CONTROLLER_BIT) 100*837d542aSEvan Quan #define FEATURE_FAN_CONTROLLER_MASK (1 << FEATURE_FAN_CONTROLLER_BIT) 101*837d542aSEvan Quan #define FEATURE_DATA_CALCULATION_MASK (1 << FEATURE_DATA_CALCULATION_BIT) 102*837d542aSEvan Quan #define FEATURE_PPT_MASK (1 << FEATURE_PPT_BIT) 103*837d542aSEvan Quan #define FEATURE_TDC_MASK (1 << FEATURE_TDC_BIT) 104*837d542aSEvan Quan #define FEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT) 105*837d542aSEvan Quan #define FEATURE_FIT_MASK (1 << FEATURE_FIT_BIT) 106*837d542aSEvan Quan #define FEATURE_EDC_MASK (1 << FEATURE_EDC_BIT) 107*837d542aSEvan Quan #define FEATURE_PLL_POWER_DOWN_MASK (1 << FEATURE_PLL_POWER_DOWN_BIT) 108*837d542aSEvan Quan #define FEATURE_ULV_MASK (1 << FEATURE_ULV_BIT) 109*837d542aSEvan Quan #define FEATURE_VDDOFF_MASK (1 << FEATURE_VDDOFF_BIT) 110*837d542aSEvan Quan #define FEATURE_VCN_DPM_MASK (1 << FEATURE_VCN_DPM_BIT) 111*837d542aSEvan Quan #define FEATURE_ACP_DPM_MASK (1 << FEATURE_ACP_DPM_BIT) 112*837d542aSEvan Quan #define FEATURE_ISP_DPM_MASK (1 << FEATURE_ISP_DPM_BIT) 113*837d542aSEvan Quan #define FEATURE_FCLK_DPM_MASK (1 << FEATURE_FCLK_DPM_BIT) 114*837d542aSEvan Quan #define FEATURE_SOCCLK_DPM_MASK (1 << FEATURE_SOCCLK_DPM_BIT) 115*837d542aSEvan Quan #define FEATURE_MP0CLK_DPM_MASK (1 << FEATURE_MP0CLK_DPM_BIT) 116*837d542aSEvan Quan #define FEATURE_LCLK_DPM_MASK (1 << FEATURE_LCLK_DPM_BIT) 117*837d542aSEvan Quan #define FEATURE_SHUBCLK_DPM_MASK (1 << FEATURE_SHUBCLK_DPM_BIT) 118*837d542aSEvan Quan #define FEATURE_DCEFCLK_DPM_MASK (1 << FEATURE_DCEFCLK_DPM_BIT) 119*837d542aSEvan Quan #define FEATURE_GFX_DPM_MASK (1 << FEATURE_GFX_DPM_BIT) 120*837d542aSEvan Quan #define FEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT) 121*837d542aSEvan Quan #define FEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT) 122*837d542aSEvan Quan #define FEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT) 123*837d542aSEvan Quan #define FEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT) 124*837d542aSEvan Quan #define FEATURE_DS_SHUBCLK_MASK (1 << FEATURE_DS_SHUBCLK_BIT) 125*837d542aSEvan Quan #define FEATURE_RM_MASK (1 << FEATURE_RM_BIT) 126*837d542aSEvan Quan #define FEATURE_DS_FCLK_MASK (1 << FEATURE_DS_FCLK_BIT) 127*837d542aSEvan Quan #define FEATURE_DS_SMNCLK_MASK (1 << FEATURE_DS_SMNCLK_BIT) 128*837d542aSEvan Quan #define FEATURE_DS_MP1CLK_MASK (1 << FEATURE_DS_MP1CLK_BIT) 129*837d542aSEvan Quan #define FEATURE_DS_MP0CLK_MASK (1 << FEATURE_DS_MP0CLK_BIT) 130*837d542aSEvan Quan #define FEATURE_MGCG_MASK (1 << FEATURE_MGCG_BIT) 131*837d542aSEvan Quan #define FEATURE_DS_FUSE_SRAM_MASK (1 << FEATURE_DS_FUSE_SRAM_BIT) 132*837d542aSEvan Quan #define FEATURE_PSI0_MASK (1 << FEATURE_PSI0_BIT) 133*837d542aSEvan Quan #define FEATURE_STAPM_MASK (1 << FEATURE_STAPM_BIT) 134*837d542aSEvan Quan #define FEATURE_PROCHOT_MASK (1 << FEATURE_PROCHOT_BIT) 135*837d542aSEvan Quan #define FEATURE_CPUOFF_MASK (1 << FEATURE_CPUOFF_BIT) 136*837d542aSEvan Quan #define FEATURE_CORE_CSTATES_MASK (1 << FEATURE_CORE_CSTATES_BIT) 137*837d542aSEvan Quan 138*837d542aSEvan Quan /* Workload bits */ 139*837d542aSEvan Quan #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 0 140*837d542aSEvan Quan #define WORKLOAD_PPLIB_VIDEO_BIT 2 141*837d542aSEvan Quan #define WORKLOAD_PPLIB_VR_BIT 3 142*837d542aSEvan Quan #define WORKLOAD_PPLIB_COMPUTE_BIT 4 143*837d542aSEvan Quan #define WORKLOAD_PPLIB_CUSTOM_BIT 5 144*837d542aSEvan Quan #define WORKLOAD_PPLIB_COUNT 6 145*837d542aSEvan Quan 146*837d542aSEvan Quan typedef struct { 147*837d542aSEvan Quan /* MP1_EXT_SCRATCH0 */ 148*837d542aSEvan Quan uint32_t CurrLevel_ACP : 4; 149*837d542aSEvan Quan uint32_t CurrLevel_ISP : 4; 150*837d542aSEvan Quan uint32_t CurrLevel_VCN : 4; 151*837d542aSEvan Quan uint32_t CurrLevel_LCLK : 4; 152*837d542aSEvan Quan uint32_t CurrLevel_MP0CLK : 4; 153*837d542aSEvan Quan uint32_t CurrLevel_FCLK : 4; 154*837d542aSEvan Quan uint32_t CurrLevel_SOCCLK : 4; 155*837d542aSEvan Quan uint32_t CurrLevel_DCEFCLK : 4; 156*837d542aSEvan Quan /* MP1_EXT_SCRATCH1 */ 157*837d542aSEvan Quan uint32_t TargLevel_ACP : 4; 158*837d542aSEvan Quan uint32_t TargLevel_ISP : 4; 159*837d542aSEvan Quan uint32_t TargLevel_VCN : 4; 160*837d542aSEvan Quan uint32_t TargLevel_LCLK : 4; 161*837d542aSEvan Quan uint32_t TargLevel_MP0CLK : 4; 162*837d542aSEvan Quan uint32_t TargLevel_FCLK : 4; 163*837d542aSEvan Quan uint32_t TargLevel_SOCCLK : 4; 164*837d542aSEvan Quan uint32_t TargLevel_DCEFCLK : 4; 165*837d542aSEvan Quan /* MP1_EXT_SCRATCH2 */ 166*837d542aSEvan Quan uint32_t CurrLevel_SHUBCLK : 4; 167*837d542aSEvan Quan uint32_t TargLevel_SHUBCLK : 4; 168*837d542aSEvan Quan uint32_t InUlv : 1; 169*837d542aSEvan Quan uint32_t InS0i2 : 1; 170*837d542aSEvan Quan uint32_t InWhisperMode : 1; 171*837d542aSEvan Quan uint32_t Reserved : 21; 172*837d542aSEvan Quan /* MP1_EXT_SCRATCH3-4 */ 173*837d542aSEvan Quan uint32_t Reserved2[2]; 174*837d542aSEvan Quan /* MP1_EXT_SCRATCH5 */ 175*837d542aSEvan Quan uint32_t FeatureStatus[NUM_FEATURES / 32]; 176*837d542aSEvan Quan } FwStatus_t; 177*837d542aSEvan Quan 178*837d542aSEvan Quan #define TABLE_BIOS_IF 0 /* Called by BIOS */ 179*837d542aSEvan Quan #define TABLE_WATERMARKS 1 /* Called by Driver */ 180*837d542aSEvan Quan #define TABLE_CUSTOM_DPM 2 /* Called by Driver */ 181*837d542aSEvan Quan #define TABLE_PMSTATUSLOG 3 /* Called by Tools for Agm logging */ 182*837d542aSEvan Quan #define TABLE_DPMCLOCKS 4 /* Called by Driver */ 183*837d542aSEvan Quan #define TABLE_MOMENTARY_PM 5 /* Called by Tools */ 184*837d542aSEvan Quan #define TABLE_COUNT 6 185*837d542aSEvan Quan 186*837d542aSEvan Quan #pragma pack(pop) 187*837d542aSEvan Quan 188*837d542aSEvan Quan #endif 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