1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/fb.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "vega20_smumgr.h" 32 #include "hardwaremanager.h" 33 #include "ppatomfwctrl.h" 34 #include "atomfirmware.h" 35 #include "cgs_common.h" 36 #include "vega20_powertune.h" 37 #include "vega20_inc.h" 38 #include "pppcielanes.h" 39 #include "vega20_hwmgr.h" 40 #include "vega20_processpptables.h" 41 #include "vega20_pptable.h" 42 #include "vega20_thermal.h" 43 #include "vega20_ppsmc.h" 44 #include "pp_debug.h" 45 #include "amd_pcie_helpers.h" 46 #include "ppinterrupt.h" 47 #include "pp_overdriver.h" 48 #include "pp_thermal.h" 49 #include "soc15_common.h" 50 #include "vega20_baco.h" 51 #include "smuio/smuio_9_0_offset.h" 52 #include "smuio/smuio_9_0_sh_mask.h" 53 #include "nbio/nbio_7_4_sh_mask.h" 54 55 #define smnPCIE_LC_SPEED_CNTL 0x11140290 56 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 57 58 #define LINK_WIDTH_MAX 6 59 #define LINK_SPEED_MAX 3 60 static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 61 static int link_speed[] = {25, 50, 80, 160}; 62 63 static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) 64 { 65 struct vega20_hwmgr *data = 66 (struct vega20_hwmgr *)(hwmgr->backend); 67 68 data->gfxclk_average_alpha = PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT; 69 data->socclk_average_alpha = PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT; 70 data->uclk_average_alpha = PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT; 71 data->gfx_activity_average_alpha = PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT; 72 data->lowest_uclk_reserved_for_ulv = PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT; 73 74 data->display_voltage_mode = PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT; 75 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 76 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 77 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 78 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 79 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 80 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 81 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 82 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 83 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 84 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 85 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 86 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT; 87 88 /* 89 * Disable the following features for now: 90 * GFXCLK DS 91 * SOCLK DS 92 * LCLK DS 93 * DCEFCLK DS 94 * FCLK DS 95 * MP1CLK DS 96 * MP0CLK DS 97 */ 98 data->registry_data.disallowed_features = 0xE0041C00; 99 /* ECC feature should be disabled on old SMUs */ 100 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version); 101 if (hwmgr->smu_version < 0x282100) 102 data->registry_data.disallowed_features |= FEATURE_ECC_MASK; 103 104 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) 105 data->registry_data.disallowed_features |= FEATURE_DPM_LINK_MASK; 106 107 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) 108 data->registry_data.disallowed_features |= FEATURE_DPM_GFXCLK_MASK; 109 110 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) 111 data->registry_data.disallowed_features |= FEATURE_DPM_SOCCLK_MASK; 112 113 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) 114 data->registry_data.disallowed_features |= FEATURE_DPM_UCLK_MASK; 115 116 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) 117 data->registry_data.disallowed_features |= FEATURE_DPM_DCEFCLK_MASK; 118 119 if (!(hwmgr->feature_mask & PP_ULV_MASK)) 120 data->registry_data.disallowed_features |= FEATURE_ULV_MASK; 121 122 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) 123 data->registry_data.disallowed_features |= FEATURE_DS_GFXCLK_MASK; 124 125 data->registry_data.od_state_in_dc_support = 0; 126 data->registry_data.thermal_support = 1; 127 data->registry_data.skip_baco_hardware = 0; 128 129 data->registry_data.log_avfs_param = 0; 130 data->registry_data.sclk_throttle_low_notification = 1; 131 data->registry_data.force_dpm_high = 0; 132 data->registry_data.stable_pstate_sclk_dpm_percentage = 75; 133 134 data->registry_data.didt_support = 0; 135 if (data->registry_data.didt_support) { 136 data->registry_data.didt_mode = 6; 137 data->registry_data.sq_ramping_support = 1; 138 data->registry_data.db_ramping_support = 0; 139 data->registry_data.td_ramping_support = 0; 140 data->registry_data.tcp_ramping_support = 0; 141 data->registry_data.dbr_ramping_support = 0; 142 data->registry_data.edc_didt_support = 1; 143 data->registry_data.gc_didt_support = 0; 144 data->registry_data.psm_didt_support = 0; 145 } 146 147 data->registry_data.pcie_lane_override = 0xff; 148 data->registry_data.pcie_speed_override = 0xff; 149 data->registry_data.pcie_clock_override = 0xffffffff; 150 data->registry_data.regulator_hot_gpio_support = 1; 151 data->registry_data.ac_dc_switch_gpio_support = 0; 152 data->registry_data.quick_transition_support = 0; 153 data->registry_data.zrpm_start_temp = 0xffff; 154 data->registry_data.zrpm_stop_temp = 0xffff; 155 data->registry_data.od8_feature_enable = 1; 156 data->registry_data.disable_water_mark = 0; 157 data->registry_data.disable_pp_tuning = 0; 158 data->registry_data.disable_xlpp_tuning = 0; 159 data->registry_data.disable_workload_policy = 0; 160 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; 161 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; 162 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; 163 data->registry_data.force_workload_policy_mask = 0; 164 data->registry_data.disable_3d_fs_detection = 0; 165 data->registry_data.fps_support = 1; 166 data->registry_data.disable_auto_wattman = 1; 167 data->registry_data.auto_wattman_debug = 0; 168 data->registry_data.auto_wattman_sample_period = 100; 169 data->registry_data.fclk_gfxclk_ratio = 0; 170 data->registry_data.auto_wattman_threshold = 50; 171 data->registry_data.gfxoff_controlled_by_driver = 1; 172 data->gfxoff_allowed = false; 173 data->counter_gfxoff = 0; 174 } 175 176 static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr) 177 { 178 struct vega20_hwmgr *data = 179 (struct vega20_hwmgr *)(hwmgr->backend); 180 struct amdgpu_device *adev = hwmgr->adev; 181 182 if (data->vddci_control == VEGA20_VOLTAGE_CONTROL_NONE) 183 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 184 PHM_PlatformCaps_ControlVDDCI); 185 186 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 187 PHM_PlatformCaps_TablelessHardwareInterface); 188 189 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 190 PHM_PlatformCaps_BACO); 191 192 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 193 PHM_PlatformCaps_EnableSMU7ThermalManagement); 194 195 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 196 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 197 PHM_PlatformCaps_UVDPowerGating); 198 199 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 201 PHM_PlatformCaps_VCEPowerGating); 202 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_UnTabledHardwareInterface); 205 206 if (data->registry_data.od8_feature_enable) 207 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 208 PHM_PlatformCaps_OD8inACSupport); 209 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_ActivityReporting); 212 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 213 PHM_PlatformCaps_FanSpeedInTableIsRPM); 214 215 if (data->registry_data.od_state_in_dc_support) { 216 if (data->registry_data.od8_feature_enable) 217 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 218 PHM_PlatformCaps_OD8inDCSupport); 219 } 220 221 if (data->registry_data.thermal_support && 222 data->registry_data.fuzzy_fan_control_support && 223 hwmgr->thermal_controller.advanceFanControlParameters.usTMax) 224 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 225 PHM_PlatformCaps_ODFuzzyFanControlSupport); 226 227 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_DynamicPowerManagement); 229 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 230 PHM_PlatformCaps_SMC); 231 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 232 PHM_PlatformCaps_ThermalPolicyDelay); 233 234 if (data->registry_data.force_dpm_high) 235 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 236 PHM_PlatformCaps_ExclusiveModeAlwaysHigh); 237 238 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 239 PHM_PlatformCaps_DynamicUVDState); 240 241 if (data->registry_data.sclk_throttle_low_notification) 242 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 243 PHM_PlatformCaps_SclkThrottleLowNotification); 244 245 /* power tune caps */ 246 /* assume disabled */ 247 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 248 PHM_PlatformCaps_PowerContainment); 249 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 250 PHM_PlatformCaps_DiDtSupport); 251 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 252 PHM_PlatformCaps_SQRamping); 253 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 254 PHM_PlatformCaps_DBRamping); 255 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 256 PHM_PlatformCaps_TDRamping); 257 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 258 PHM_PlatformCaps_TCPRamping); 259 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 260 PHM_PlatformCaps_DBRRamping); 261 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 262 PHM_PlatformCaps_DiDtEDCEnable); 263 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 264 PHM_PlatformCaps_GCEDC); 265 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 266 PHM_PlatformCaps_PSM); 267 268 if (data->registry_data.didt_support) { 269 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 270 PHM_PlatformCaps_DiDtSupport); 271 if (data->registry_data.sq_ramping_support) 272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 273 PHM_PlatformCaps_SQRamping); 274 if (data->registry_data.db_ramping_support) 275 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 276 PHM_PlatformCaps_DBRamping); 277 if (data->registry_data.td_ramping_support) 278 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 279 PHM_PlatformCaps_TDRamping); 280 if (data->registry_data.tcp_ramping_support) 281 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 282 PHM_PlatformCaps_TCPRamping); 283 if (data->registry_data.dbr_ramping_support) 284 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 285 PHM_PlatformCaps_DBRRamping); 286 if (data->registry_data.edc_didt_support) 287 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 288 PHM_PlatformCaps_DiDtEDCEnable); 289 if (data->registry_data.gc_didt_support) 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_GCEDC); 292 if (data->registry_data.psm_didt_support) 293 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 294 PHM_PlatformCaps_PSM); 295 } 296 297 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 298 PHM_PlatformCaps_RegulatorHot); 299 300 if (data->registry_data.ac_dc_switch_gpio_support) { 301 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 302 PHM_PlatformCaps_AutomaticDCTransition); 303 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 304 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 305 } 306 307 if (data->registry_data.quick_transition_support) { 308 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 309 PHM_PlatformCaps_AutomaticDCTransition); 310 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 311 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 312 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 313 PHM_PlatformCaps_Falcon_QuickTransition); 314 } 315 316 if (data->lowest_uclk_reserved_for_ulv != PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT) { 317 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 318 PHM_PlatformCaps_LowestUclkReservedForUlv); 319 if (data->lowest_uclk_reserved_for_ulv == 1) 320 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 321 PHM_PlatformCaps_LowestUclkReservedForUlv); 322 } 323 324 if (data->registry_data.custom_fan_support) 325 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 326 PHM_PlatformCaps_CustomFanControlSupport); 327 328 return 0; 329 } 330 331 static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr) 332 { 333 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 334 struct amdgpu_device *adev = hwmgr->adev; 335 uint32_t top32, bottom32; 336 int i; 337 338 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 339 FEATURE_DPM_PREFETCHER_BIT; 340 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 341 FEATURE_DPM_GFXCLK_BIT; 342 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 343 FEATURE_DPM_UCLK_BIT; 344 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 345 FEATURE_DPM_SOCCLK_BIT; 346 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 347 FEATURE_DPM_UVD_BIT; 348 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 349 FEATURE_DPM_VCE_BIT; 350 data->smu_features[GNLD_ULV].smu_feature_id = 351 FEATURE_ULV_BIT; 352 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 353 FEATURE_DPM_MP0CLK_BIT; 354 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 355 FEATURE_DPM_LINK_BIT; 356 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 357 FEATURE_DPM_DCEFCLK_BIT; 358 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 359 FEATURE_DS_GFXCLK_BIT; 360 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 361 FEATURE_DS_SOCCLK_BIT; 362 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 363 FEATURE_DS_LCLK_BIT; 364 data->smu_features[GNLD_PPT].smu_feature_id = 365 FEATURE_PPT_BIT; 366 data->smu_features[GNLD_TDC].smu_feature_id = 367 FEATURE_TDC_BIT; 368 data->smu_features[GNLD_THERMAL].smu_feature_id = 369 FEATURE_THERMAL_BIT; 370 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 371 FEATURE_GFX_PER_CU_CG_BIT; 372 data->smu_features[GNLD_RM].smu_feature_id = 373 FEATURE_RM_BIT; 374 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 375 FEATURE_DS_DCEFCLK_BIT; 376 data->smu_features[GNLD_ACDC].smu_feature_id = 377 FEATURE_ACDC_BIT; 378 data->smu_features[GNLD_VR0HOT].smu_feature_id = 379 FEATURE_VR0HOT_BIT; 380 data->smu_features[GNLD_VR1HOT].smu_feature_id = 381 FEATURE_VR1HOT_BIT; 382 data->smu_features[GNLD_FW_CTF].smu_feature_id = 383 FEATURE_FW_CTF_BIT; 384 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 385 FEATURE_LED_DISPLAY_BIT; 386 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 387 FEATURE_FAN_CONTROL_BIT; 388 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 389 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; 390 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; 391 data->smu_features[GNLD_DPM_FCLK].smu_feature_id = FEATURE_DPM_FCLK_BIT; 392 data->smu_features[GNLD_DS_FCLK].smu_feature_id = FEATURE_DS_FCLK_BIT; 393 data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT; 394 data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT; 395 data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT; 396 data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT; 397 398 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 399 data->smu_features[i].smu_feature_bitmap = 400 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); 401 data->smu_features[i].allowed = 402 ((data->registry_data.disallowed_features >> i) & 1) ? 403 false : true; 404 } 405 406 /* Get the SN to turn into a Unique ID */ 407 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 408 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 409 410 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 411 } 412 413 static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 414 { 415 return 0; 416 } 417 418 static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 419 { 420 kfree(hwmgr->backend); 421 hwmgr->backend = NULL; 422 423 return 0; 424 } 425 426 static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 427 { 428 struct vega20_hwmgr *data; 429 struct amdgpu_device *adev = hwmgr->adev; 430 431 data = kzalloc(sizeof(struct vega20_hwmgr), GFP_KERNEL); 432 if (data == NULL) 433 return -ENOMEM; 434 435 hwmgr->backend = data; 436 437 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 438 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 439 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 440 441 vega20_set_default_registry_data(hwmgr); 442 443 data->disable_dpm_mask = 0xff; 444 445 /* need to set voltage control types before EVV patching */ 446 data->vddc_control = VEGA20_VOLTAGE_CONTROL_NONE; 447 data->mvdd_control = VEGA20_VOLTAGE_CONTROL_NONE; 448 data->vddci_control = VEGA20_VOLTAGE_CONTROL_NONE; 449 450 data->water_marks_bitmap = 0; 451 data->avfs_exist = false; 452 453 vega20_set_features_platform_caps(hwmgr); 454 455 vega20_init_dpm_defaults(hwmgr); 456 457 /* Parse pptable data read from VBIOS */ 458 vega20_set_private_data_based_on_pptable(hwmgr); 459 460 data->is_tlu_enabled = false; 461 462 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 463 VEGA20_MAX_HARDWARE_POWERLEVELS; 464 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 465 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 466 467 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 468 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 469 hwmgr->platform_descriptor.clockStep.engineClock = 500; 470 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 471 472 data->total_active_cus = adev->gfx.cu_info.number; 473 data->is_custom_profile_set = false; 474 475 return 0; 476 } 477 478 static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr) 479 { 480 struct vega20_hwmgr *data = 481 (struct vega20_hwmgr *)(hwmgr->backend); 482 483 data->low_sclk_interrupt_threshold = 0; 484 485 return 0; 486 } 487 488 static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr) 489 { 490 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 491 int ret = 0; 492 bool use_baco = (amdgpu_in_reset(adev) && 493 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) || 494 (adev->in_runpm && amdgpu_asic_supports_baco(adev)); 495 496 ret = vega20_init_sclk_threshold(hwmgr); 497 PP_ASSERT_WITH_CODE(!ret, 498 "Failed to init sclk threshold!", 499 return ret); 500 501 if (use_baco) { 502 ret = vega20_baco_apply_vdci_flush_workaround(hwmgr); 503 if (ret) 504 pr_err("Failed to apply vega20 baco workaround!\n"); 505 } 506 507 return ret; 508 } 509 510 /* 511 * @fn vega20_init_dpm_state 512 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 513 * 514 * @param dpm_state - the address of the DPM Table to initiailize. 515 * @return None. 516 */ 517 static void vega20_init_dpm_state(struct vega20_dpm_state *dpm_state) 518 { 519 dpm_state->soft_min_level = 0x0; 520 dpm_state->soft_max_level = VG20_CLOCK_MAX_DEFAULT; 521 dpm_state->hard_min_level = 0x0; 522 dpm_state->hard_max_level = VG20_CLOCK_MAX_DEFAULT; 523 } 524 525 static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 526 PPCLK_e clk_id, uint32_t *num_of_levels) 527 { 528 int ret = 0; 529 530 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 531 PPSMC_MSG_GetDpmFreqByIndex, 532 (clk_id << 16 | 0xFF), 533 num_of_levels); 534 PP_ASSERT_WITH_CODE(!ret, 535 "[GetNumOfDpmLevel] failed to get dpm levels!", 536 return ret); 537 538 return ret; 539 } 540 541 static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 542 PPCLK_e clk_id, uint32_t index, uint32_t *clk) 543 { 544 int ret = 0; 545 546 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 547 PPSMC_MSG_GetDpmFreqByIndex, 548 (clk_id << 16 | index), 549 clk); 550 PP_ASSERT_WITH_CODE(!ret, 551 "[GetDpmFreqByIndex] failed to get dpm freq by index!", 552 return ret); 553 554 return ret; 555 } 556 557 static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr, 558 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) 559 { 560 int ret = 0; 561 uint32_t i, num_of_levels, clk; 562 563 ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); 564 PP_ASSERT_WITH_CODE(!ret, 565 "[SetupSingleDpmTable] failed to get clk levels!", 566 return ret); 567 568 dpm_table->count = num_of_levels; 569 570 for (i = 0; i < num_of_levels; i++) { 571 ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); 572 PP_ASSERT_WITH_CODE(!ret, 573 "[SetupSingleDpmTable] failed to get clk of specific level!", 574 return ret); 575 dpm_table->dpm_levels[i].value = clk; 576 dpm_table->dpm_levels[i].enabled = true; 577 } 578 579 return ret; 580 } 581 582 static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr) 583 { 584 struct vega20_hwmgr *data = 585 (struct vega20_hwmgr *)(hwmgr->backend); 586 struct vega20_single_dpm_table *dpm_table; 587 int ret = 0; 588 589 dpm_table = &(data->dpm_table.gfx_table); 590 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 591 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 592 PP_ASSERT_WITH_CODE(!ret, 593 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", 594 return ret); 595 } else { 596 dpm_table->count = 1; 597 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 598 } 599 600 return ret; 601 } 602 603 static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr) 604 { 605 struct vega20_hwmgr *data = 606 (struct vega20_hwmgr *)(hwmgr->backend); 607 struct vega20_single_dpm_table *dpm_table; 608 int ret = 0; 609 610 dpm_table = &(data->dpm_table.mem_table); 611 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 612 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); 613 PP_ASSERT_WITH_CODE(!ret, 614 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", 615 return ret); 616 } else { 617 dpm_table->count = 1; 618 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 619 } 620 621 return ret; 622 } 623 624 /* 625 * This function is to initialize all DPM state tables 626 * for SMU based on the dependency table. 627 * Dynamic state patching function will then trim these 628 * state tables to the allowed range based 629 * on the power policy or external client requests, 630 * such as UVD request, etc. 631 */ 632 static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 633 { 634 struct vega20_hwmgr *data = 635 (struct vega20_hwmgr *)(hwmgr->backend); 636 struct vega20_single_dpm_table *dpm_table; 637 int ret = 0; 638 639 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 640 641 /* socclk */ 642 dpm_table = &(data->dpm_table.soc_table); 643 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 644 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); 645 PP_ASSERT_WITH_CODE(!ret, 646 "[SetupDefaultDpmTable] failed to get socclk dpm levels!", 647 return ret); 648 } else { 649 dpm_table->count = 1; 650 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 651 } 652 vega20_init_dpm_state(&(dpm_table->dpm_state)); 653 654 /* gfxclk */ 655 dpm_table = &(data->dpm_table.gfx_table); 656 ret = vega20_setup_gfxclk_dpm_table(hwmgr); 657 if (ret) 658 return ret; 659 vega20_init_dpm_state(&(dpm_table->dpm_state)); 660 661 /* memclk */ 662 dpm_table = &(data->dpm_table.mem_table); 663 ret = vega20_setup_memclk_dpm_table(hwmgr); 664 if (ret) 665 return ret; 666 vega20_init_dpm_state(&(dpm_table->dpm_state)); 667 668 /* eclk */ 669 dpm_table = &(data->dpm_table.eclk_table); 670 if (data->smu_features[GNLD_DPM_VCE].enabled) { 671 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); 672 PP_ASSERT_WITH_CODE(!ret, 673 "[SetupDefaultDpmTable] failed to get eclk dpm levels!", 674 return ret); 675 } else { 676 dpm_table->count = 1; 677 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 678 } 679 vega20_init_dpm_state(&(dpm_table->dpm_state)); 680 681 /* vclk */ 682 dpm_table = &(data->dpm_table.vclk_table); 683 if (data->smu_features[GNLD_DPM_UVD].enabled) { 684 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); 685 PP_ASSERT_WITH_CODE(!ret, 686 "[SetupDefaultDpmTable] failed to get vclk dpm levels!", 687 return ret); 688 } else { 689 dpm_table->count = 1; 690 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 691 } 692 vega20_init_dpm_state(&(dpm_table->dpm_state)); 693 694 /* dclk */ 695 dpm_table = &(data->dpm_table.dclk_table); 696 if (data->smu_features[GNLD_DPM_UVD].enabled) { 697 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); 698 PP_ASSERT_WITH_CODE(!ret, 699 "[SetupDefaultDpmTable] failed to get dclk dpm levels!", 700 return ret); 701 } else { 702 dpm_table->count = 1; 703 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 704 } 705 vega20_init_dpm_state(&(dpm_table->dpm_state)); 706 707 /* dcefclk */ 708 dpm_table = &(data->dpm_table.dcef_table); 709 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 710 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); 711 PP_ASSERT_WITH_CODE(!ret, 712 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", 713 return ret); 714 } else { 715 dpm_table->count = 1; 716 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 717 } 718 vega20_init_dpm_state(&(dpm_table->dpm_state)); 719 720 /* pixclk */ 721 dpm_table = &(data->dpm_table.pixel_table); 722 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 723 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); 724 PP_ASSERT_WITH_CODE(!ret, 725 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", 726 return ret); 727 } else 728 dpm_table->count = 0; 729 vega20_init_dpm_state(&(dpm_table->dpm_state)); 730 731 /* dispclk */ 732 dpm_table = &(data->dpm_table.display_table); 733 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 734 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); 735 PP_ASSERT_WITH_CODE(!ret, 736 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", 737 return ret); 738 } else 739 dpm_table->count = 0; 740 vega20_init_dpm_state(&(dpm_table->dpm_state)); 741 742 /* phyclk */ 743 dpm_table = &(data->dpm_table.phy_table); 744 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 745 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); 746 PP_ASSERT_WITH_CODE(!ret, 747 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", 748 return ret); 749 } else 750 dpm_table->count = 0; 751 vega20_init_dpm_state(&(dpm_table->dpm_state)); 752 753 /* fclk */ 754 dpm_table = &(data->dpm_table.fclk_table); 755 if (data->smu_features[GNLD_DPM_FCLK].enabled) { 756 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK); 757 PP_ASSERT_WITH_CODE(!ret, 758 "[SetupDefaultDpmTable] failed to get fclk dpm levels!", 759 return ret); 760 } else { 761 dpm_table->count = 1; 762 dpm_table->dpm_levels[0].value = data->vbios_boot_state.fclock / 100; 763 } 764 vega20_init_dpm_state(&(dpm_table->dpm_state)); 765 766 /* save a copy of the default DPM table */ 767 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 768 sizeof(struct vega20_dpm_table)); 769 770 return 0; 771 } 772 773 /** 774 * Initializes the SMC table and uploads it 775 * 776 * @hwmgr: the address of the powerplay hardware manager. 777 * return: always 0 778 */ 779 static int vega20_init_smc_table(struct pp_hwmgr *hwmgr) 780 { 781 int result; 782 struct vega20_hwmgr *data = 783 (struct vega20_hwmgr *)(hwmgr->backend); 784 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 785 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 786 struct phm_ppt_v3_information *pptable_information = 787 (struct phm_ppt_v3_information *)hwmgr->pptable; 788 789 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 790 PP_ASSERT_WITH_CODE(!result, 791 "[InitSMCTable] Failed to get vbios bootup values!", 792 return result); 793 794 data->vbios_boot_state.vddc = boot_up_values.usVddc; 795 data->vbios_boot_state.vddci = boot_up_values.usVddci; 796 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 797 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 798 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 799 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 800 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 801 data->vbios_boot_state.eclock = boot_up_values.ulEClk; 802 data->vbios_boot_state.vclock = boot_up_values.ulVClk; 803 data->vbios_boot_state.dclock = boot_up_values.ulDClk; 804 data->vbios_boot_state.fclock = boot_up_values.ulFClk; 805 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; 806 807 smum_send_msg_to_smc_with_parameter(hwmgr, 808 PPSMC_MSG_SetMinDeepSleepDcefclk, 809 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 810 NULL); 811 812 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 813 814 result = smum_smc_table_manager(hwmgr, 815 (uint8_t *)pp_table, TABLE_PPTABLE, false); 816 PP_ASSERT_WITH_CODE(!result, 817 "[InitSMCTable] Failed to upload PPtable!", 818 return result); 819 820 return 0; 821 } 822 823 /* 824 * Override PCIe link speed and link width for DPM Level 1. PPTable entries 825 * reflect the ASIC capabilities and not the system capabilities. For e.g. 826 * Vega20 board in a PCI Gen3 system. In this case, when SMU's tries to switch 827 * to DPM1, it fails as system doesn't support Gen4. 828 */ 829 static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr) 830 { 831 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 832 struct vega20_hwmgr *data = 833 (struct vega20_hwmgr *)(hwmgr->backend); 834 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; 835 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 836 int i; 837 int ret; 838 839 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 840 pcie_gen = 3; 841 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 842 pcie_gen = 2; 843 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 844 pcie_gen = 1; 845 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 846 pcie_gen = 0; 847 848 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 849 pcie_width = 6; 850 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 851 pcie_width = 5; 852 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 853 pcie_width = 4; 854 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 855 pcie_width = 3; 856 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 857 pcie_width = 2; 858 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 859 pcie_width = 1; 860 861 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 862 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 863 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 864 */ 865 for (i = 0; i < NUM_LINK_LEVELS; i++) { 866 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : 867 pp_table->PcieGenSpeed[i]; 868 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : 869 pp_table->PcieLaneCount[i]; 870 871 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != 872 pp_table->PcieLaneCount[i]) { 873 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; 874 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 875 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 876 NULL); 877 PP_ASSERT_WITH_CODE(!ret, 878 "[OverridePcieParameters] Attempt to override pcie params failed!", 879 return ret); 880 } 881 882 /* update the pptable */ 883 pp_table->PcieGenSpeed[i] = pcie_gen_arg; 884 pp_table->PcieLaneCount[i] = pcie_width_arg; 885 } 886 887 return 0; 888 } 889 890 static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) 891 { 892 struct vega20_hwmgr *data = 893 (struct vega20_hwmgr *)(hwmgr->backend); 894 uint32_t allowed_features_low = 0, allowed_features_high = 0; 895 int i; 896 int ret = 0; 897 898 for (i = 0; i < GNLD_FEATURES_MAX; i++) 899 if (data->smu_features[i].allowed) 900 data->smu_features[i].smu_feature_id > 31 ? 901 (allowed_features_high |= 902 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) 903 & 0xFFFFFFFF)) : 904 (allowed_features_low |= 905 ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) 906 & 0xFFFFFFFF)); 907 908 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 909 PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, NULL); 910 PP_ASSERT_WITH_CODE(!ret, 911 "[SetAllowedFeaturesMask] Attempt to set allowed features mask(high) failed!", 912 return ret); 913 914 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 915 PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, NULL); 916 PP_ASSERT_WITH_CODE(!ret, 917 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", 918 return ret); 919 920 return 0; 921 } 922 923 static int vega20_run_btc(struct pp_hwmgr *hwmgr) 924 { 925 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc, NULL); 926 } 927 928 static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr) 929 { 930 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc, NULL); 931 } 932 933 static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr) 934 { 935 struct vega20_hwmgr *data = 936 (struct vega20_hwmgr *)(hwmgr->backend); 937 uint64_t features_enabled; 938 int i; 939 bool enabled; 940 int ret = 0; 941 942 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, 943 PPSMC_MSG_EnableAllSmuFeatures, 944 NULL)) == 0, 945 "[EnableAllSMUFeatures] Failed to enable all smu features!", 946 return ret); 947 948 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 949 PP_ASSERT_WITH_CODE(!ret, 950 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 951 return ret); 952 953 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 954 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? 955 true : false; 956 data->smu_features[i].enabled = enabled; 957 data->smu_features[i].supported = enabled; 958 959 #if 0 960 if (data->smu_features[i].allowed && !enabled) 961 pr_info("[EnableAllSMUFeatures] feature %d is expected enabled!", i); 962 else if (!data->smu_features[i].allowed && enabled) 963 pr_info("[EnableAllSMUFeatures] feature %d is expected disabled!", i); 964 #endif 965 } 966 967 return 0; 968 } 969 970 static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr) 971 { 972 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 973 974 if (data->smu_features[GNLD_DPM_UCLK].enabled) 975 return smum_send_msg_to_smc_with_parameter(hwmgr, 976 PPSMC_MSG_SetUclkFastSwitch, 977 1, 978 NULL); 979 980 return 0; 981 } 982 983 static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr) 984 { 985 struct vega20_hwmgr *data = 986 (struct vega20_hwmgr *)(hwmgr->backend); 987 988 return smum_send_msg_to_smc_with_parameter(hwmgr, 989 PPSMC_MSG_SetFclkGfxClkRatio, 990 data->registry_data.fclk_gfxclk_ratio, 991 NULL); 992 } 993 994 static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr) 995 { 996 struct vega20_hwmgr *data = 997 (struct vega20_hwmgr *)(hwmgr->backend); 998 int i, ret = 0; 999 1000 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, 1001 PPSMC_MSG_DisableAllSmuFeatures, 1002 NULL)) == 0, 1003 "[DisableAllSMUFeatures] Failed to disable all smu features!", 1004 return ret); 1005 1006 for (i = 0; i < GNLD_FEATURES_MAX; i++) 1007 data->smu_features[i].enabled = 0; 1008 1009 return 0; 1010 } 1011 1012 static int vega20_od8_set_feature_capabilities( 1013 struct pp_hwmgr *hwmgr) 1014 { 1015 struct phm_ppt_v3_information *pptable_information = 1016 (struct phm_ppt_v3_information *)hwmgr->pptable; 1017 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1018 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1019 struct vega20_od8_settings *od_settings = &(data->od8_settings); 1020 1021 od_settings->overdrive8_capabilities = 0; 1022 1023 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1024 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] && 1025 pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 && 1026 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN] > 0 && 1027 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_FMAX] >= 1028 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_FMIN])) 1029 od_settings->overdrive8_capabilities |= OD8_GFXCLK_LIMITS; 1030 1031 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE] && 1032 (pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1] >= 1033 pp_table->MinVoltageGfx / VOLTAGE_SCALE) && 1034 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] <= 1035 pp_table->MaxVoltageGfx / VOLTAGE_SCALE) && 1036 (pptable_information->od_settings_max[OD8_SETTING_GFXCLK_VOLTAGE3] >= 1037 pptable_information->od_settings_min[OD8_SETTING_GFXCLK_VOLTAGE1])) 1038 od_settings->overdrive8_capabilities |= OD8_GFXCLK_CURVE; 1039 } 1040 1041 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1042 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] = 1043 data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value; 1044 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_UCLK_MAX] && 1045 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX] > 0 && 1046 pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] > 0 && 1047 (pptable_information->od_settings_max[OD8_SETTING_UCLK_FMAX] >= 1048 pptable_information->od_settings_min[OD8_SETTING_UCLK_FMAX])) 1049 od_settings->overdrive8_capabilities |= OD8_UCLK_MAX; 1050 } 1051 1052 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_POWER_LIMIT] && 1053 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] > 0 && 1054 pptable_information->od_settings_max[OD8_SETTING_POWER_PERCENTAGE] <= 100 && 1055 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] > 0 && 1056 pptable_information->od_settings_min[OD8_SETTING_POWER_PERCENTAGE] <= 100) 1057 od_settings->overdrive8_capabilities |= OD8_POWER_LIMIT; 1058 1059 if (data->smu_features[GNLD_FAN_CONTROL].enabled) { 1060 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT] && 1061 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 && 1062 pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] > 0 && 1063 (pptable_information->od_settings_max[OD8_SETTING_FAN_ACOUSTIC_LIMIT] >= 1064 pptable_information->od_settings_min[OD8_SETTING_FAN_ACOUSTIC_LIMIT])) 1065 od_settings->overdrive8_capabilities |= OD8_ACOUSTIC_LIMIT_SCLK; 1066 1067 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN] && 1068 (pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED] >= 1069 (pp_table->FanPwmMin * pp_table->FanMaximumRpm / 100)) && 1070 pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] > 0 && 1071 (pptable_information->od_settings_max[OD8_SETTING_FAN_MIN_SPEED] >= 1072 pptable_information->od_settings_min[OD8_SETTING_FAN_MIN_SPEED])) 1073 od_settings->overdrive8_capabilities |= OD8_FAN_SPEED_MIN; 1074 } 1075 1076 if (data->smu_features[GNLD_THERMAL].enabled) { 1077 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN] && 1078 pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] > 0 && 1079 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP] > 0 && 1080 (pptable_information->od_settings_max[OD8_SETTING_FAN_TARGET_TEMP] >= 1081 pptable_information->od_settings_min[OD8_SETTING_FAN_TARGET_TEMP])) 1082 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_FAN; 1083 1084 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM] && 1085 pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] > 0 && 1086 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX] > 0 && 1087 (pptable_information->od_settings_max[OD8_SETTING_OPERATING_TEMP_MAX] >= 1088 pptable_information->od_settings_min[OD8_SETTING_OPERATING_TEMP_MAX])) 1089 od_settings->overdrive8_capabilities |= OD8_TEMPERATURE_SYSTEM; 1090 } 1091 1092 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE]) 1093 od_settings->overdrive8_capabilities |= OD8_MEMORY_TIMING_TUNE; 1094 1095 if (pptable_information->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL] && 1096 pp_table->FanZeroRpmEnable) 1097 od_settings->overdrive8_capabilities |= OD8_FAN_ZERO_RPM_CONTROL; 1098 1099 if (!od_settings->overdrive8_capabilities) 1100 hwmgr->od_enabled = false; 1101 1102 return 0; 1103 } 1104 1105 static int vega20_od8_set_feature_id( 1106 struct pp_hwmgr *hwmgr) 1107 { 1108 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1109 struct vega20_od8_settings *od_settings = &(data->od8_settings); 1110 1111 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) { 1112 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id = 1113 OD8_GFXCLK_LIMITS; 1114 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id = 1115 OD8_GFXCLK_LIMITS; 1116 } else { 1117 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].feature_id = 1118 0; 1119 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].feature_id = 1120 0; 1121 } 1122 1123 if (od_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) { 1124 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id = 1125 OD8_GFXCLK_CURVE; 1126 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id = 1127 OD8_GFXCLK_CURVE; 1128 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id = 1129 OD8_GFXCLK_CURVE; 1130 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id = 1131 OD8_GFXCLK_CURVE; 1132 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id = 1133 OD8_GFXCLK_CURVE; 1134 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id = 1135 OD8_GFXCLK_CURVE; 1136 } else { 1137 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].feature_id = 1138 0; 1139 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id = 1140 0; 1141 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].feature_id = 1142 0; 1143 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id = 1144 0; 1145 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].feature_id = 1146 0; 1147 od_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id = 1148 0; 1149 } 1150 1151 if (od_settings->overdrive8_capabilities & OD8_UCLK_MAX) 1152 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = OD8_UCLK_MAX; 1153 else 1154 od_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].feature_id = 0; 1155 1156 if (od_settings->overdrive8_capabilities & OD8_POWER_LIMIT) 1157 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = OD8_POWER_LIMIT; 1158 else 1159 od_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].feature_id = 0; 1160 1161 if (od_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK) 1162 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id = 1163 OD8_ACOUSTIC_LIMIT_SCLK; 1164 else 1165 od_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].feature_id = 1166 0; 1167 1168 if (od_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN) 1169 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id = 1170 OD8_FAN_SPEED_MIN; 1171 else 1172 od_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].feature_id = 1173 0; 1174 1175 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN) 1176 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id = 1177 OD8_TEMPERATURE_FAN; 1178 else 1179 od_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].feature_id = 1180 0; 1181 1182 if (od_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM) 1183 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id = 1184 OD8_TEMPERATURE_SYSTEM; 1185 else 1186 od_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].feature_id = 1187 0; 1188 1189 return 0; 1190 } 1191 1192 static int vega20_od8_get_gfx_clock_base_voltage( 1193 struct pp_hwmgr *hwmgr, 1194 uint32_t *voltage, 1195 uint32_t freq) 1196 { 1197 int ret = 0; 1198 1199 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1200 PPSMC_MSG_GetAVFSVoltageByDpm, 1201 ((AVFS_CURVE << 24) | (OD8_HOTCURVE_TEMPERATURE << 16) | freq), 1202 voltage); 1203 PP_ASSERT_WITH_CODE(!ret, 1204 "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!", 1205 return ret); 1206 1207 *voltage = *voltage / VOLTAGE_SCALE; 1208 1209 return 0; 1210 } 1211 1212 static int vega20_od8_initialize_default_settings( 1213 struct pp_hwmgr *hwmgr) 1214 { 1215 struct phm_ppt_v3_information *pptable_information = 1216 (struct phm_ppt_v3_information *)hwmgr->pptable; 1217 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1218 struct vega20_od8_settings *od8_settings = &(data->od8_settings); 1219 OverDriveTable_t *od_table = &(data->smc_state_table.overdrive_table); 1220 int i, ret = 0; 1221 1222 /* Set Feature Capabilities */ 1223 vega20_od8_set_feature_capabilities(hwmgr); 1224 1225 /* Map FeatureID to individual settings */ 1226 vega20_od8_set_feature_id(hwmgr); 1227 1228 /* Set default values */ 1229 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true); 1230 PP_ASSERT_WITH_CODE(!ret, 1231 "Failed to export over drive table!", 1232 return ret); 1233 1234 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_LIMITS) { 1235 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value = 1236 od_table->GfxclkFmin; 1237 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value = 1238 od_table->GfxclkFmax; 1239 } else { 1240 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].default_value = 1241 0; 1242 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].default_value = 1243 0; 1244 } 1245 1246 if (od8_settings->overdrive8_capabilities & OD8_GFXCLK_CURVE) { 1247 od_table->GfxclkFreq1 = od_table->GfxclkFmin; 1248 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value = 1249 od_table->GfxclkFreq1; 1250 1251 od_table->GfxclkFreq3 = od_table->GfxclkFmax; 1252 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value = 1253 od_table->GfxclkFreq3; 1254 1255 od_table->GfxclkFreq2 = (od_table->GfxclkFreq1 + od_table->GfxclkFreq3) / 2; 1256 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value = 1257 od_table->GfxclkFreq2; 1258 1259 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, 1260 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value), 1261 od_table->GfxclkFreq1), 1262 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", 1263 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 0); 1264 od_table->GfxclkVolt1 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value 1265 * VOLTAGE_SCALE; 1266 1267 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, 1268 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value), 1269 od_table->GfxclkFreq2), 1270 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", 1271 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 0); 1272 od_table->GfxclkVolt2 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value 1273 * VOLTAGE_SCALE; 1274 1275 PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr, 1276 &(od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value), 1277 od_table->GfxclkFreq3), 1278 "[PhwVega20_OD8_InitializeDefaultSettings] Failed to get Base clock voltage from SMU!", 1279 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 0); 1280 od_table->GfxclkVolt3 = od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value 1281 * VOLTAGE_SCALE; 1282 } else { 1283 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ1].default_value = 1284 0; 1285 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE1].default_value = 1286 0; 1287 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ2].default_value = 1288 0; 1289 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE2].default_value = 1290 0; 1291 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FREQ3].default_value = 1292 0; 1293 od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_VOLTAGE3].default_value = 1294 0; 1295 } 1296 1297 if (od8_settings->overdrive8_capabilities & OD8_UCLK_MAX) 1298 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value = 1299 od_table->UclkFmax; 1300 else 1301 od8_settings->od8_settings_array[OD8_SETTING_UCLK_FMAX].default_value = 1302 0; 1303 1304 if (od8_settings->overdrive8_capabilities & OD8_POWER_LIMIT) 1305 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value = 1306 od_table->OverDrivePct; 1307 else 1308 od8_settings->od8_settings_array[OD8_SETTING_POWER_PERCENTAGE].default_value = 1309 0; 1310 1311 if (od8_settings->overdrive8_capabilities & OD8_ACOUSTIC_LIMIT_SCLK) 1312 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value = 1313 od_table->FanMaximumRpm; 1314 else 1315 od8_settings->od8_settings_array[OD8_SETTING_FAN_ACOUSTIC_LIMIT].default_value = 1316 0; 1317 1318 if (od8_settings->overdrive8_capabilities & OD8_FAN_SPEED_MIN) 1319 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value = 1320 od_table->FanMinimumPwm * data->smc_state_table.pp_table.FanMaximumRpm / 100; 1321 else 1322 od8_settings->od8_settings_array[OD8_SETTING_FAN_MIN_SPEED].default_value = 1323 0; 1324 1325 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_FAN) 1326 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value = 1327 od_table->FanTargetTemperature; 1328 else 1329 od8_settings->od8_settings_array[OD8_SETTING_FAN_TARGET_TEMP].default_value = 1330 0; 1331 1332 if (od8_settings->overdrive8_capabilities & OD8_TEMPERATURE_SYSTEM) 1333 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value = 1334 od_table->MaxOpTemp; 1335 else 1336 od8_settings->od8_settings_array[OD8_SETTING_OPERATING_TEMP_MAX].default_value = 1337 0; 1338 1339 for (i = 0; i < OD8_SETTING_COUNT; i++) { 1340 if (od8_settings->od8_settings_array[i].feature_id) { 1341 od8_settings->od8_settings_array[i].min_value = 1342 pptable_information->od_settings_min[i]; 1343 od8_settings->od8_settings_array[i].max_value = 1344 pptable_information->od_settings_max[i]; 1345 od8_settings->od8_settings_array[i].current_value = 1346 od8_settings->od8_settings_array[i].default_value; 1347 } else { 1348 od8_settings->od8_settings_array[i].min_value = 1349 0; 1350 od8_settings->od8_settings_array[i].max_value = 1351 0; 1352 od8_settings->od8_settings_array[i].current_value = 1353 0; 1354 } 1355 } 1356 1357 ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false); 1358 PP_ASSERT_WITH_CODE(!ret, 1359 "Failed to import over drive table!", 1360 return ret); 1361 1362 return 0; 1363 } 1364 1365 static int vega20_od8_set_settings( 1366 struct pp_hwmgr *hwmgr, 1367 uint32_t index, 1368 uint32_t value) 1369 { 1370 OverDriveTable_t od_table; 1371 int ret = 0; 1372 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1373 struct vega20_od8_single_setting *od8_settings = 1374 data->od8_settings.od8_settings_array; 1375 1376 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true); 1377 PP_ASSERT_WITH_CODE(!ret, 1378 "Failed to export over drive table!", 1379 return ret); 1380 1381 switch(index) { 1382 case OD8_SETTING_GFXCLK_FMIN: 1383 od_table.GfxclkFmin = (uint16_t)value; 1384 break; 1385 case OD8_SETTING_GFXCLK_FMAX: 1386 if (value < od8_settings[OD8_SETTING_GFXCLK_FMAX].min_value || 1387 value > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) 1388 return -EINVAL; 1389 1390 od_table.GfxclkFmax = (uint16_t)value; 1391 break; 1392 case OD8_SETTING_GFXCLK_FREQ1: 1393 od_table.GfxclkFreq1 = (uint16_t)value; 1394 break; 1395 case OD8_SETTING_GFXCLK_VOLTAGE1: 1396 od_table.GfxclkVolt1 = (uint16_t)value; 1397 break; 1398 case OD8_SETTING_GFXCLK_FREQ2: 1399 od_table.GfxclkFreq2 = (uint16_t)value; 1400 break; 1401 case OD8_SETTING_GFXCLK_VOLTAGE2: 1402 od_table.GfxclkVolt2 = (uint16_t)value; 1403 break; 1404 case OD8_SETTING_GFXCLK_FREQ3: 1405 od_table.GfxclkFreq3 = (uint16_t)value; 1406 break; 1407 case OD8_SETTING_GFXCLK_VOLTAGE3: 1408 od_table.GfxclkVolt3 = (uint16_t)value; 1409 break; 1410 case OD8_SETTING_UCLK_FMAX: 1411 if (value < od8_settings[OD8_SETTING_UCLK_FMAX].min_value || 1412 value > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) 1413 return -EINVAL; 1414 od_table.UclkFmax = (uint16_t)value; 1415 break; 1416 case OD8_SETTING_POWER_PERCENTAGE: 1417 od_table.OverDrivePct = (int16_t)value; 1418 break; 1419 case OD8_SETTING_FAN_ACOUSTIC_LIMIT: 1420 od_table.FanMaximumRpm = (uint16_t)value; 1421 break; 1422 case OD8_SETTING_FAN_MIN_SPEED: 1423 od_table.FanMinimumPwm = (uint16_t)value; 1424 break; 1425 case OD8_SETTING_FAN_TARGET_TEMP: 1426 od_table.FanTargetTemperature = (uint16_t)value; 1427 break; 1428 case OD8_SETTING_OPERATING_TEMP_MAX: 1429 od_table.MaxOpTemp = (uint16_t)value; 1430 break; 1431 } 1432 1433 ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false); 1434 PP_ASSERT_WITH_CODE(!ret, 1435 "Failed to import over drive table!", 1436 return ret); 1437 1438 return 0; 1439 } 1440 1441 static int vega20_get_sclk_od( 1442 struct pp_hwmgr *hwmgr) 1443 { 1444 struct vega20_hwmgr *data = hwmgr->backend; 1445 struct vega20_single_dpm_table *sclk_table = 1446 &(data->dpm_table.gfx_table); 1447 struct vega20_single_dpm_table *golden_sclk_table = 1448 &(data->golden_dpm_table.gfx_table); 1449 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 1450 int golden_value = golden_sclk_table->dpm_levels 1451 [golden_sclk_table->count - 1].value; 1452 1453 /* od percentage */ 1454 value -= golden_value; 1455 value = DIV_ROUND_UP(value * 100, golden_value); 1456 1457 return value; 1458 } 1459 1460 static int vega20_set_sclk_od( 1461 struct pp_hwmgr *hwmgr, uint32_t value) 1462 { 1463 struct vega20_hwmgr *data = hwmgr->backend; 1464 struct vega20_single_dpm_table *golden_sclk_table = 1465 &(data->golden_dpm_table.gfx_table); 1466 uint32_t od_sclk; 1467 int ret = 0; 1468 1469 od_sclk = golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * value; 1470 od_sclk /= 100; 1471 od_sclk += golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 1472 1473 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk); 1474 PP_ASSERT_WITH_CODE(!ret, 1475 "[SetSclkOD] failed to set od gfxclk!", 1476 return ret); 1477 1478 /* retrieve updated gfxclk table */ 1479 ret = vega20_setup_gfxclk_dpm_table(hwmgr); 1480 PP_ASSERT_WITH_CODE(!ret, 1481 "[SetSclkOD] failed to refresh gfxclk table!", 1482 return ret); 1483 1484 return 0; 1485 } 1486 1487 static int vega20_get_mclk_od( 1488 struct pp_hwmgr *hwmgr) 1489 { 1490 struct vega20_hwmgr *data = hwmgr->backend; 1491 struct vega20_single_dpm_table *mclk_table = 1492 &(data->dpm_table.mem_table); 1493 struct vega20_single_dpm_table *golden_mclk_table = 1494 &(data->golden_dpm_table.mem_table); 1495 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 1496 int golden_value = golden_mclk_table->dpm_levels 1497 [golden_mclk_table->count - 1].value; 1498 1499 /* od percentage */ 1500 value -= golden_value; 1501 value = DIV_ROUND_UP(value * 100, golden_value); 1502 1503 return value; 1504 } 1505 1506 static int vega20_set_mclk_od( 1507 struct pp_hwmgr *hwmgr, uint32_t value) 1508 { 1509 struct vega20_hwmgr *data = hwmgr->backend; 1510 struct vega20_single_dpm_table *golden_mclk_table = 1511 &(data->golden_dpm_table.mem_table); 1512 uint32_t od_mclk; 1513 int ret = 0; 1514 1515 od_mclk = golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * value; 1516 od_mclk /= 100; 1517 od_mclk += golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 1518 1519 ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk); 1520 PP_ASSERT_WITH_CODE(!ret, 1521 "[SetMclkOD] failed to set od memclk!", 1522 return ret); 1523 1524 /* retrieve updated memclk table */ 1525 ret = vega20_setup_memclk_dpm_table(hwmgr); 1526 PP_ASSERT_WITH_CODE(!ret, 1527 "[SetMclkOD] failed to refresh memclk table!", 1528 return ret); 1529 1530 return 0; 1531 } 1532 1533 static int vega20_populate_umdpstate_clocks( 1534 struct pp_hwmgr *hwmgr) 1535 { 1536 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 1537 struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); 1538 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); 1539 1540 hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; 1541 hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; 1542 1543 if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && 1544 mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) { 1545 hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 1546 hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 1547 } 1548 1549 hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100; 1550 hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100; 1551 1552 return 0; 1553 } 1554 1555 static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, 1556 PP_Clock *clock, PPCLK_e clock_select) 1557 { 1558 int ret = 0; 1559 1560 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1561 PPSMC_MSG_GetDcModeMaxDpmFreq, 1562 (clock_select << 16), 1563 clock)) == 0, 1564 "[GetMaxSustainableClock] Failed to get max DC clock from SMC!", 1565 return ret); 1566 1567 /* if DC limit is zero, return AC limit */ 1568 if (*clock == 0) { 1569 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1570 PPSMC_MSG_GetMaxDpmFreq, 1571 (clock_select << 16), 1572 clock)) == 0, 1573 "[GetMaxSustainableClock] failed to get max AC clock from SMC!", 1574 return ret); 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr) 1581 { 1582 struct vega20_hwmgr *data = 1583 (struct vega20_hwmgr *)(hwmgr->backend); 1584 struct vega20_max_sustainable_clocks *max_sustainable_clocks = 1585 &(data->max_sustainable_clocks); 1586 int ret = 0; 1587 1588 max_sustainable_clocks->uclock = data->vbios_boot_state.mem_clock / 100; 1589 max_sustainable_clocks->soc_clock = data->vbios_boot_state.soc_clock / 100; 1590 max_sustainable_clocks->dcef_clock = data->vbios_boot_state.dcef_clock / 100; 1591 max_sustainable_clocks->display_clock = 0xFFFFFFFF; 1592 max_sustainable_clocks->phy_clock = 0xFFFFFFFF; 1593 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; 1594 1595 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1596 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1597 &(max_sustainable_clocks->uclock), 1598 PPCLK_UCLK)) == 0, 1599 "[InitMaxSustainableClocks] failed to get max UCLK from SMC!", 1600 return ret); 1601 1602 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) 1603 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1604 &(max_sustainable_clocks->soc_clock), 1605 PPCLK_SOCCLK)) == 0, 1606 "[InitMaxSustainableClocks] failed to get max SOCCLK from SMC!", 1607 return ret); 1608 1609 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1610 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1611 &(max_sustainable_clocks->dcef_clock), 1612 PPCLK_DCEFCLK)) == 0, 1613 "[InitMaxSustainableClocks] failed to get max DCEFCLK from SMC!", 1614 return ret); 1615 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1616 &(max_sustainable_clocks->display_clock), 1617 PPCLK_DISPCLK)) == 0, 1618 "[InitMaxSustainableClocks] failed to get max DISPCLK from SMC!", 1619 return ret); 1620 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1621 &(max_sustainable_clocks->phy_clock), 1622 PPCLK_PHYCLK)) == 0, 1623 "[InitMaxSustainableClocks] failed to get max PHYCLK from SMC!", 1624 return ret); 1625 PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr, 1626 &(max_sustainable_clocks->pixel_clock), 1627 PPCLK_PIXCLK)) == 0, 1628 "[InitMaxSustainableClocks] failed to get max PIXCLK from SMC!", 1629 return ret); 1630 } 1631 1632 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) 1633 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; 1634 1635 return 0; 1636 } 1637 1638 static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) 1639 { 1640 int result; 1641 1642 result = smum_send_msg_to_smc(hwmgr, 1643 PPSMC_MSG_SetMGpuFanBoostLimitRpm, 1644 NULL); 1645 PP_ASSERT_WITH_CODE(!result, 1646 "[EnableMgpuFan] Failed to enable mgpu fan boost!", 1647 return result); 1648 1649 return 0; 1650 } 1651 1652 static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) 1653 { 1654 struct vega20_hwmgr *data = 1655 (struct vega20_hwmgr *)(hwmgr->backend); 1656 1657 data->uvd_power_gated = true; 1658 data->vce_power_gated = true; 1659 } 1660 1661 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1662 { 1663 int result = 0; 1664 1665 smum_send_msg_to_smc_with_parameter(hwmgr, 1666 PPSMC_MSG_NumOfDisplays, 0, NULL); 1667 1668 result = vega20_set_allowed_featuresmask(hwmgr); 1669 PP_ASSERT_WITH_CODE(!result, 1670 "[EnableDPMTasks] Failed to set allowed featuresmask!\n", 1671 return result); 1672 1673 result = vega20_init_smc_table(hwmgr); 1674 PP_ASSERT_WITH_CODE(!result, 1675 "[EnableDPMTasks] Failed to initialize SMC table!", 1676 return result); 1677 1678 result = vega20_run_btc(hwmgr); 1679 PP_ASSERT_WITH_CODE(!result, 1680 "[EnableDPMTasks] Failed to run btc!", 1681 return result); 1682 1683 result = vega20_run_btc_afll(hwmgr); 1684 PP_ASSERT_WITH_CODE(!result, 1685 "[EnableDPMTasks] Failed to run btc afll!", 1686 return result); 1687 1688 result = vega20_enable_all_smu_features(hwmgr); 1689 PP_ASSERT_WITH_CODE(!result, 1690 "[EnableDPMTasks] Failed to enable all smu features!", 1691 return result); 1692 1693 result = vega20_override_pcie_parameters(hwmgr); 1694 PP_ASSERT_WITH_CODE(!result, 1695 "[EnableDPMTasks] Failed to override pcie parameters!", 1696 return result); 1697 1698 result = vega20_notify_smc_display_change(hwmgr); 1699 PP_ASSERT_WITH_CODE(!result, 1700 "[EnableDPMTasks] Failed to notify smc display change!", 1701 return result); 1702 1703 result = vega20_send_clock_ratio(hwmgr); 1704 PP_ASSERT_WITH_CODE(!result, 1705 "[EnableDPMTasks] Failed to send clock ratio!", 1706 return result); 1707 1708 /* Initialize UVD/VCE powergating state */ 1709 vega20_init_powergate_state(hwmgr); 1710 1711 result = vega20_setup_default_dpm_tables(hwmgr); 1712 PP_ASSERT_WITH_CODE(!result, 1713 "[EnableDPMTasks] Failed to setup default DPM tables!", 1714 return result); 1715 1716 result = vega20_init_max_sustainable_clocks(hwmgr); 1717 PP_ASSERT_WITH_CODE(!result, 1718 "[EnableDPMTasks] Failed to get maximum sustainable clocks!", 1719 return result); 1720 1721 result = vega20_power_control_set_level(hwmgr); 1722 PP_ASSERT_WITH_CODE(!result, 1723 "[EnableDPMTasks] Failed to power control set level!", 1724 return result); 1725 1726 result = vega20_od8_initialize_default_settings(hwmgr); 1727 PP_ASSERT_WITH_CODE(!result, 1728 "[EnableDPMTasks] Failed to initialize odn settings!", 1729 return result); 1730 1731 result = vega20_populate_umdpstate_clocks(hwmgr); 1732 PP_ASSERT_WITH_CODE(!result, 1733 "[EnableDPMTasks] Failed to populate umdpstate clocks!", 1734 return result); 1735 1736 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit, 1737 POWER_SOURCE_AC << 16, &hwmgr->default_power_limit); 1738 PP_ASSERT_WITH_CODE(!result, 1739 "[GetPptLimit] get default PPT limit failed!", 1740 return result); 1741 hwmgr->power_limit = 1742 hwmgr->default_power_limit; 1743 1744 return 0; 1745 } 1746 1747 static uint32_t vega20_find_lowest_dpm_level( 1748 struct vega20_single_dpm_table *table) 1749 { 1750 uint32_t i; 1751 1752 for (i = 0; i < table->count; i++) { 1753 if (table->dpm_levels[i].enabled) 1754 break; 1755 } 1756 if (i >= table->count) { 1757 i = 0; 1758 table->dpm_levels[i].enabled = true; 1759 } 1760 1761 return i; 1762 } 1763 1764 static uint32_t vega20_find_highest_dpm_level( 1765 struct vega20_single_dpm_table *table) 1766 { 1767 int i = 0; 1768 1769 PP_ASSERT_WITH_CODE(table != NULL, 1770 "[FindHighestDPMLevel] DPM Table does not exist!", 1771 return 0); 1772 PP_ASSERT_WITH_CODE(table->count > 0, 1773 "[FindHighestDPMLevel] DPM Table has no entry!", 1774 return 0); 1775 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, 1776 "[FindHighestDPMLevel] DPM Table has too many entries!", 1777 return MAX_REGULAR_DPM_NUMBER - 1); 1778 1779 for (i = table->count - 1; i >= 0; i--) { 1780 if (table->dpm_levels[i].enabled) 1781 break; 1782 } 1783 if (i < 0) { 1784 i = 0; 1785 table->dpm_levels[i].enabled = true; 1786 } 1787 1788 return i; 1789 } 1790 1791 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) 1792 { 1793 struct vega20_hwmgr *data = 1794 (struct vega20_hwmgr *)(hwmgr->backend); 1795 uint32_t min_freq; 1796 int ret = 0; 1797 1798 if (data->smu_features[GNLD_DPM_GFXCLK].enabled && 1799 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 1800 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1801 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1802 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1803 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), 1804 NULL)), 1805 "Failed to set soft min gfxclk !", 1806 return ret); 1807 } 1808 1809 if (data->smu_features[GNLD_DPM_UCLK].enabled && 1810 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 1811 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1812 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1813 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1814 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1815 NULL)), 1816 "Failed to set soft min memclk !", 1817 return ret); 1818 } 1819 1820 if (data->smu_features[GNLD_DPM_UVD].enabled && 1821 (feature_mask & FEATURE_DPM_UVD_MASK)) { 1822 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1823 1824 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1825 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1826 (PPCLK_VCLK << 16) | (min_freq & 0xffff), 1827 NULL)), 1828 "Failed to set soft min vclk!", 1829 return ret); 1830 1831 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1832 1833 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1834 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1835 (PPCLK_DCLK << 16) | (min_freq & 0xffff), 1836 NULL)), 1837 "Failed to set soft min dclk!", 1838 return ret); 1839 } 1840 1841 if (data->smu_features[GNLD_DPM_VCE].enabled && 1842 (feature_mask & FEATURE_DPM_VCE_MASK)) { 1843 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1844 1845 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1846 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1847 (PPCLK_ECLK << 16) | (min_freq & 0xffff), 1848 NULL)), 1849 "Failed to set soft min eclk!", 1850 return ret); 1851 } 1852 1853 if (data->smu_features[GNLD_DPM_SOCCLK].enabled && 1854 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 1855 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1856 1857 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1858 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1859 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), 1860 NULL)), 1861 "Failed to set soft min socclk!", 1862 return ret); 1863 } 1864 1865 if (data->smu_features[GNLD_DPM_FCLK].enabled && 1866 (feature_mask & FEATURE_DPM_FCLK_MASK)) { 1867 min_freq = data->dpm_table.fclk_table.dpm_state.soft_min_level; 1868 1869 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1870 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1871 (PPCLK_FCLK << 16) | (min_freq & 0xffff), 1872 NULL)), 1873 "Failed to set soft min fclk!", 1874 return ret); 1875 } 1876 1877 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled && 1878 (feature_mask & FEATURE_DPM_DCEFCLK_MASK)) { 1879 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; 1880 1881 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1882 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1883 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), 1884 NULL)), 1885 "Failed to set hard min dcefclk!", 1886 return ret); 1887 } 1888 1889 return ret; 1890 } 1891 1892 static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) 1893 { 1894 struct vega20_hwmgr *data = 1895 (struct vega20_hwmgr *)(hwmgr->backend); 1896 uint32_t max_freq; 1897 int ret = 0; 1898 1899 if (data->smu_features[GNLD_DPM_GFXCLK].enabled && 1900 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 1901 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1902 1903 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1904 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1905 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), 1906 NULL)), 1907 "Failed to set soft max gfxclk!", 1908 return ret); 1909 } 1910 1911 if (data->smu_features[GNLD_DPM_UCLK].enabled && 1912 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 1913 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1914 1915 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1916 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1917 (PPCLK_UCLK << 16) | (max_freq & 0xffff), 1918 NULL)), 1919 "Failed to set soft max memclk!", 1920 return ret); 1921 } 1922 1923 if (data->smu_features[GNLD_DPM_UVD].enabled && 1924 (feature_mask & FEATURE_DPM_UVD_MASK)) { 1925 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1926 1927 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1928 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1929 (PPCLK_VCLK << 16) | (max_freq & 0xffff), 1930 NULL)), 1931 "Failed to set soft max vclk!", 1932 return ret); 1933 1934 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1935 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1936 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1937 (PPCLK_DCLK << 16) | (max_freq & 0xffff), 1938 NULL)), 1939 "Failed to set soft max dclk!", 1940 return ret); 1941 } 1942 1943 if (data->smu_features[GNLD_DPM_VCE].enabled && 1944 (feature_mask & FEATURE_DPM_VCE_MASK)) { 1945 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1946 1947 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1948 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1949 (PPCLK_ECLK << 16) | (max_freq & 0xffff), 1950 NULL)), 1951 "Failed to set soft max eclk!", 1952 return ret); 1953 } 1954 1955 if (data->smu_features[GNLD_DPM_SOCCLK].enabled && 1956 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 1957 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1958 1959 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1960 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1961 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), 1962 NULL)), 1963 "Failed to set soft max socclk!", 1964 return ret); 1965 } 1966 1967 if (data->smu_features[GNLD_DPM_FCLK].enabled && 1968 (feature_mask & FEATURE_DPM_FCLK_MASK)) { 1969 max_freq = data->dpm_table.fclk_table.dpm_state.soft_max_level; 1970 1971 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1972 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1973 (PPCLK_FCLK << 16) | (max_freq & 0xffff), 1974 NULL)), 1975 "Failed to set soft max fclk!", 1976 return ret); 1977 } 1978 1979 return ret; 1980 } 1981 1982 static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 1983 { 1984 struct vega20_hwmgr *data = 1985 (struct vega20_hwmgr *)(hwmgr->backend); 1986 int ret = 0; 1987 1988 if (data->smu_features[GNLD_DPM_VCE].supported) { 1989 if (data->smu_features[GNLD_DPM_VCE].enabled == enable) { 1990 if (enable) 1991 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already enabled!\n"); 1992 else 1993 PP_DBG_LOG("[EnableDisableVCEDPM] feature VCE DPM already disabled!\n"); 1994 } 1995 1996 ret = vega20_enable_smc_features(hwmgr, 1997 enable, 1998 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap); 1999 PP_ASSERT_WITH_CODE(!ret, 2000 "Attempt to Enable/Disable DPM VCE Failed!", 2001 return ret); 2002 data->smu_features[GNLD_DPM_VCE].enabled = enable; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr, 2009 uint32_t *clock, 2010 PPCLK_e clock_select, 2011 bool max) 2012 { 2013 int ret; 2014 *clock = 0; 2015 2016 if (max) { 2017 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2018 PPSMC_MSG_GetMaxDpmFreq, (clock_select << 16), 2019 clock)) == 0, 2020 "[GetClockRanges] Failed to get max clock from SMC!", 2021 return ret); 2022 } else { 2023 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2024 PPSMC_MSG_GetMinDpmFreq, 2025 (clock_select << 16), 2026 clock)) == 0, 2027 "[GetClockRanges] Failed to get min clock from SMC!", 2028 return ret); 2029 } 2030 2031 return 0; 2032 } 2033 2034 static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 2035 { 2036 struct vega20_hwmgr *data = 2037 (struct vega20_hwmgr *)(hwmgr->backend); 2038 uint32_t gfx_clk; 2039 int ret = 0; 2040 2041 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_GFXCLK].enabled, 2042 "[GetSclks]: gfxclk dpm not enabled!\n", 2043 return -EPERM); 2044 2045 if (low) { 2046 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false); 2047 PP_ASSERT_WITH_CODE(!ret, 2048 "[GetSclks]: fail to get min PPCLK_GFXCLK\n", 2049 return ret); 2050 } else { 2051 ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true); 2052 PP_ASSERT_WITH_CODE(!ret, 2053 "[GetSclks]: fail to get max PPCLK_GFXCLK\n", 2054 return ret); 2055 } 2056 2057 return (gfx_clk * 100); 2058 } 2059 2060 static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 2061 { 2062 struct vega20_hwmgr *data = 2063 (struct vega20_hwmgr *)(hwmgr->backend); 2064 uint32_t mem_clk; 2065 int ret = 0; 2066 2067 PP_ASSERT_WITH_CODE(data->smu_features[GNLD_DPM_UCLK].enabled, 2068 "[MemMclks]: memclk dpm not enabled!\n", 2069 return -EPERM); 2070 2071 if (low) { 2072 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false); 2073 PP_ASSERT_WITH_CODE(!ret, 2074 "[GetMclks]: fail to get min PPCLK_UCLK\n", 2075 return ret); 2076 } else { 2077 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true); 2078 PP_ASSERT_WITH_CODE(!ret, 2079 "[GetMclks]: fail to get max PPCLK_UCLK\n", 2080 return ret); 2081 } 2082 2083 return (mem_clk * 100); 2084 } 2085 2086 static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, 2087 SmuMetrics_t *metrics_table, 2088 bool bypass_cache) 2089 { 2090 struct vega20_hwmgr *data = 2091 (struct vega20_hwmgr *)(hwmgr->backend); 2092 int ret = 0; 2093 2094 if (bypass_cache || 2095 !data->metrics_time || 2096 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { 2097 ret = smum_smc_table_manager(hwmgr, 2098 (uint8_t *)(&data->metrics_table), 2099 TABLE_SMU_METRICS, 2100 true); 2101 if (ret) { 2102 pr_info("Failed to export SMU metrics table!\n"); 2103 return ret; 2104 } 2105 data->metrics_time = jiffies; 2106 } 2107 2108 if (metrics_table) 2109 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); 2110 2111 return ret; 2112 } 2113 2114 static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr, 2115 uint32_t *query) 2116 { 2117 int ret = 0; 2118 SmuMetrics_t metrics_table; 2119 2120 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2121 if (ret) 2122 return ret; 2123 2124 /* For the 40.46 release, they changed the value name */ 2125 if (hwmgr->smu_version == 0x282e00) 2126 *query = metrics_table.AverageSocketPower << 8; 2127 else 2128 *query = metrics_table.CurrSocketPower << 8; 2129 2130 return ret; 2131 } 2132 2133 static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr, 2134 PPCLK_e clk_id, uint32_t *clk_freq) 2135 { 2136 int ret = 0; 2137 2138 *clk_freq = 0; 2139 2140 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2141 PPSMC_MSG_GetDpmClockFreq, (clk_id << 16), 2142 clk_freq)) == 0, 2143 "[GetCurrentClkFreq] Attempt to get Current Frequency Failed!", 2144 return ret); 2145 2146 *clk_freq = *clk_freq * 100; 2147 2148 return 0; 2149 } 2150 2151 static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr, 2152 int idx, 2153 uint32_t *activity_percent) 2154 { 2155 int ret = 0; 2156 SmuMetrics_t metrics_table; 2157 2158 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2159 if (ret) 2160 return ret; 2161 2162 switch (idx) { 2163 case AMDGPU_PP_SENSOR_GPU_LOAD: 2164 *activity_percent = metrics_table.AverageGfxActivity; 2165 break; 2166 case AMDGPU_PP_SENSOR_MEM_LOAD: 2167 *activity_percent = metrics_table.AverageUclkActivity; 2168 break; 2169 default: 2170 pr_err("Invalid index for retrieving clock activity\n"); 2171 return -EINVAL; 2172 } 2173 2174 return ret; 2175 } 2176 2177 static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx, 2178 void *value, int *size) 2179 { 2180 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2181 struct amdgpu_device *adev = hwmgr->adev; 2182 SmuMetrics_t metrics_table; 2183 uint32_t val_vid; 2184 int ret = 0; 2185 2186 switch (idx) { 2187 case AMDGPU_PP_SENSOR_GFX_SCLK: 2188 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2189 if (ret) 2190 return ret; 2191 2192 *((uint32_t *)value) = metrics_table.AverageGfxclkFrequency * 100; 2193 *size = 4; 2194 break; 2195 case AMDGPU_PP_SENSOR_GFX_MCLK: 2196 ret = vega20_get_current_clk_freq(hwmgr, 2197 PPCLK_UCLK, 2198 (uint32_t *)value); 2199 if (!ret) 2200 *size = 4; 2201 break; 2202 case AMDGPU_PP_SENSOR_GPU_LOAD: 2203 case AMDGPU_PP_SENSOR_MEM_LOAD: 2204 ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); 2205 if (!ret) 2206 *size = 4; 2207 break; 2208 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 2209 *((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr); 2210 *size = 4; 2211 break; 2212 case AMDGPU_PP_SENSOR_EDGE_TEMP: 2213 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2214 if (ret) 2215 return ret; 2216 2217 *((uint32_t *)value) = metrics_table.TemperatureEdge * 2218 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2219 *size = 4; 2220 break; 2221 case AMDGPU_PP_SENSOR_MEM_TEMP: 2222 ret = vega20_get_metrics_table(hwmgr, &metrics_table, false); 2223 if (ret) 2224 return ret; 2225 2226 *((uint32_t *)value) = metrics_table.TemperatureHBM * 2227 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2228 *size = 4; 2229 break; 2230 case AMDGPU_PP_SENSOR_UVD_POWER: 2231 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 2232 *size = 4; 2233 break; 2234 case AMDGPU_PP_SENSOR_VCE_POWER: 2235 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 2236 *size = 4; 2237 break; 2238 case AMDGPU_PP_SENSOR_GPU_POWER: 2239 *size = 16; 2240 ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value); 2241 break; 2242 case AMDGPU_PP_SENSOR_VDDGFX: 2243 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) & 2244 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >> 2245 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT; 2246 *((uint32_t *)value) = 2247 (uint32_t)convert_to_vddc((uint8_t)val_vid); 2248 break; 2249 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 2250 ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value); 2251 if (!ret) 2252 *size = 8; 2253 break; 2254 default: 2255 ret = -EINVAL; 2256 break; 2257 } 2258 return ret; 2259 } 2260 2261 static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 2262 struct pp_display_clock_request *clock_req) 2263 { 2264 int result = 0; 2265 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2266 enum amd_pp_clock_type clk_type = clock_req->clock_type; 2267 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 2268 PPCLK_e clk_select = 0; 2269 uint32_t clk_request = 0; 2270 2271 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 2272 switch (clk_type) { 2273 case amd_pp_dcef_clock: 2274 clk_select = PPCLK_DCEFCLK; 2275 break; 2276 case amd_pp_disp_clock: 2277 clk_select = PPCLK_DISPCLK; 2278 break; 2279 case amd_pp_pixel_clock: 2280 clk_select = PPCLK_PIXCLK; 2281 break; 2282 case amd_pp_phy_clock: 2283 clk_select = PPCLK_PHYCLK; 2284 break; 2285 default: 2286 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 2287 result = -EINVAL; 2288 break; 2289 } 2290 2291 if (!result) { 2292 clk_request = (clk_select << 16) | clk_freq; 2293 result = smum_send_msg_to_smc_with_parameter(hwmgr, 2294 PPSMC_MSG_SetHardMinByFreq, 2295 clk_request, 2296 NULL); 2297 } 2298 } 2299 2300 return result; 2301 } 2302 2303 static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 2304 PHM_PerformanceLevelDesignation designation, uint32_t index, 2305 PHM_PerformanceLevel *level) 2306 { 2307 return 0; 2308 } 2309 2310 static int vega20_notify_smc_display_config_after_ps_adjustment( 2311 struct pp_hwmgr *hwmgr) 2312 { 2313 struct vega20_hwmgr *data = 2314 (struct vega20_hwmgr *)(hwmgr->backend); 2315 struct vega20_single_dpm_table *dpm_table = 2316 &data->dpm_table.mem_table; 2317 struct PP_Clocks min_clocks = {0}; 2318 struct pp_display_clock_request clock_req; 2319 int ret = 0; 2320 2321 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 2322 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 2323 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 2324 2325 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { 2326 clock_req.clock_type = amd_pp_dcef_clock; 2327 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; 2328 if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) { 2329 if (data->smu_features[GNLD_DS_DCEFCLK].supported) 2330 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter( 2331 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 2332 min_clocks.dcefClockInSR / 100, 2333 NULL)) == 0, 2334 "Attempt to set divider for DCEFCLK Failed!", 2335 return ret); 2336 } else { 2337 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 2338 } 2339 } 2340 2341 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 2342 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; 2343 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2344 PPSMC_MSG_SetHardMinByFreq, 2345 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, 2346 NULL)), 2347 "[SetHardMinFreq] Set hard min uclk failed!", 2348 return ret); 2349 } 2350 2351 return 0; 2352 } 2353 2354 static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr) 2355 { 2356 struct vega20_hwmgr *data = 2357 (struct vega20_hwmgr *)(hwmgr->backend); 2358 uint32_t soft_level; 2359 int ret = 0; 2360 2361 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 2362 2363 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2364 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2365 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 2366 2367 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); 2368 2369 data->dpm_table.mem_table.dpm_state.soft_min_level = 2370 data->dpm_table.mem_table.dpm_state.soft_max_level = 2371 data->dpm_table.mem_table.dpm_levels[soft_level].value; 2372 2373 soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); 2374 2375 data->dpm_table.soc_table.dpm_state.soft_min_level = 2376 data->dpm_table.soc_table.dpm_state.soft_max_level = 2377 data->dpm_table.soc_table.dpm_levels[soft_level].value; 2378 2379 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2380 FEATURE_DPM_UCLK_MASK | 2381 FEATURE_DPM_SOCCLK_MASK); 2382 PP_ASSERT_WITH_CODE(!ret, 2383 "Failed to upload boot level to highest!", 2384 return ret); 2385 2386 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2387 FEATURE_DPM_UCLK_MASK | 2388 FEATURE_DPM_SOCCLK_MASK); 2389 PP_ASSERT_WITH_CODE(!ret, 2390 "Failed to upload dpm max level to highest!", 2391 return ret); 2392 2393 return 0; 2394 } 2395 2396 static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr) 2397 { 2398 struct vega20_hwmgr *data = 2399 (struct vega20_hwmgr *)(hwmgr->backend); 2400 uint32_t soft_level; 2401 int ret = 0; 2402 2403 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 2404 2405 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2406 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2407 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 2408 2409 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 2410 2411 data->dpm_table.mem_table.dpm_state.soft_min_level = 2412 data->dpm_table.mem_table.dpm_state.soft_max_level = 2413 data->dpm_table.mem_table.dpm_levels[soft_level].value; 2414 2415 soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 2416 2417 data->dpm_table.soc_table.dpm_state.soft_min_level = 2418 data->dpm_table.soc_table.dpm_state.soft_max_level = 2419 data->dpm_table.soc_table.dpm_levels[soft_level].value; 2420 2421 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2422 FEATURE_DPM_UCLK_MASK | 2423 FEATURE_DPM_SOCCLK_MASK); 2424 PP_ASSERT_WITH_CODE(!ret, 2425 "Failed to upload boot level to highest!", 2426 return ret); 2427 2428 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2429 FEATURE_DPM_UCLK_MASK | 2430 FEATURE_DPM_SOCCLK_MASK); 2431 PP_ASSERT_WITH_CODE(!ret, 2432 "Failed to upload dpm max level to highest!", 2433 return ret); 2434 2435 return 0; 2436 2437 } 2438 2439 static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 2440 { 2441 struct vega20_hwmgr *data = 2442 (struct vega20_hwmgr *)(hwmgr->backend); 2443 uint32_t soft_min_level, soft_max_level; 2444 int ret = 0; 2445 2446 /* gfxclk soft min/max settings */ 2447 soft_min_level = 2448 vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 2449 soft_max_level = 2450 vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 2451 2452 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2453 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2454 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2455 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2456 2457 /* uclk soft min/max settings */ 2458 soft_min_level = 2459 vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 2460 soft_max_level = 2461 vega20_find_highest_dpm_level(&(data->dpm_table.mem_table)); 2462 2463 data->dpm_table.mem_table.dpm_state.soft_min_level = 2464 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2465 data->dpm_table.mem_table.dpm_state.soft_max_level = 2466 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2467 2468 /* socclk soft min/max settings */ 2469 soft_min_level = 2470 vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 2471 soft_max_level = 2472 vega20_find_highest_dpm_level(&(data->dpm_table.soc_table)); 2473 2474 data->dpm_table.soc_table.dpm_state.soft_min_level = 2475 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2476 data->dpm_table.soc_table.dpm_state.soft_max_level = 2477 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2478 2479 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2480 FEATURE_DPM_UCLK_MASK | 2481 FEATURE_DPM_SOCCLK_MASK); 2482 PP_ASSERT_WITH_CODE(!ret, 2483 "Failed to upload DPM Bootup Levels!", 2484 return ret); 2485 2486 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK | 2487 FEATURE_DPM_UCLK_MASK | 2488 FEATURE_DPM_SOCCLK_MASK); 2489 PP_ASSERT_WITH_CODE(!ret, 2490 "Failed to upload DPM Max Levels!", 2491 return ret); 2492 2493 return 0; 2494 } 2495 2496 static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 2497 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 2498 { 2499 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2500 struct vega20_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 2501 struct vega20_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 2502 struct vega20_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); 2503 2504 *sclk_mask = 0; 2505 *mclk_mask = 0; 2506 *soc_mask = 0; 2507 2508 if (gfx_dpm_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && 2509 mem_dpm_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL && 2510 soc_dpm_table->count > VEGA20_UMD_PSTATE_SOCCLK_LEVEL) { 2511 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; 2512 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; 2513 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; 2514 } 2515 2516 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2517 *sclk_mask = 0; 2518 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 2519 *mclk_mask = 0; 2520 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2521 *sclk_mask = gfx_dpm_table->count - 1; 2522 *mclk_mask = mem_dpm_table->count - 1; 2523 *soc_mask = soc_dpm_table->count - 1; 2524 } 2525 2526 return 0; 2527 } 2528 2529 static int vega20_force_clock_level(struct pp_hwmgr *hwmgr, 2530 enum pp_clock_type type, uint32_t mask) 2531 { 2532 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2533 uint32_t soft_min_level, soft_max_level, hard_min_level; 2534 int ret = 0; 2535 2536 switch (type) { 2537 case PP_SCLK: 2538 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2539 soft_max_level = mask ? (fls(mask) - 1) : 0; 2540 2541 if (soft_max_level >= data->dpm_table.gfx_table.count) { 2542 pr_err("Clock level specified %d is over max allowed %d\n", 2543 soft_max_level, 2544 data->dpm_table.gfx_table.count - 1); 2545 return -EINVAL; 2546 } 2547 2548 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2549 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2550 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2551 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2552 2553 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK); 2554 PP_ASSERT_WITH_CODE(!ret, 2555 "Failed to upload boot level to lowest!", 2556 return ret); 2557 2558 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK); 2559 PP_ASSERT_WITH_CODE(!ret, 2560 "Failed to upload dpm max level to highest!", 2561 return ret); 2562 break; 2563 2564 case PP_MCLK: 2565 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2566 soft_max_level = mask ? (fls(mask) - 1) : 0; 2567 2568 if (soft_max_level >= data->dpm_table.mem_table.count) { 2569 pr_err("Clock level specified %d is over max allowed %d\n", 2570 soft_max_level, 2571 data->dpm_table.mem_table.count - 1); 2572 return -EINVAL; 2573 } 2574 2575 data->dpm_table.mem_table.dpm_state.soft_min_level = 2576 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2577 data->dpm_table.mem_table.dpm_state.soft_max_level = 2578 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2579 2580 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK); 2581 PP_ASSERT_WITH_CODE(!ret, 2582 "Failed to upload boot level to lowest!", 2583 return ret); 2584 2585 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK); 2586 PP_ASSERT_WITH_CODE(!ret, 2587 "Failed to upload dpm max level to highest!", 2588 return ret); 2589 2590 break; 2591 2592 case PP_SOCCLK: 2593 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2594 soft_max_level = mask ? (fls(mask) - 1) : 0; 2595 2596 if (soft_max_level >= data->dpm_table.soc_table.count) { 2597 pr_err("Clock level specified %d is over max allowed %d\n", 2598 soft_max_level, 2599 data->dpm_table.soc_table.count - 1); 2600 return -EINVAL; 2601 } 2602 2603 data->dpm_table.soc_table.dpm_state.soft_min_level = 2604 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2605 data->dpm_table.soc_table.dpm_state.soft_max_level = 2606 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2607 2608 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK); 2609 PP_ASSERT_WITH_CODE(!ret, 2610 "Failed to upload boot level to lowest!", 2611 return ret); 2612 2613 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK); 2614 PP_ASSERT_WITH_CODE(!ret, 2615 "Failed to upload dpm max level to highest!", 2616 return ret); 2617 2618 break; 2619 2620 case PP_FCLK: 2621 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2622 soft_max_level = mask ? (fls(mask) - 1) : 0; 2623 2624 if (soft_max_level >= data->dpm_table.fclk_table.count) { 2625 pr_err("Clock level specified %d is over max allowed %d\n", 2626 soft_max_level, 2627 data->dpm_table.fclk_table.count - 1); 2628 return -EINVAL; 2629 } 2630 2631 data->dpm_table.fclk_table.dpm_state.soft_min_level = 2632 data->dpm_table.fclk_table.dpm_levels[soft_min_level].value; 2633 data->dpm_table.fclk_table.dpm_state.soft_max_level = 2634 data->dpm_table.fclk_table.dpm_levels[soft_max_level].value; 2635 2636 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK); 2637 PP_ASSERT_WITH_CODE(!ret, 2638 "Failed to upload boot level to lowest!", 2639 return ret); 2640 2641 ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK); 2642 PP_ASSERT_WITH_CODE(!ret, 2643 "Failed to upload dpm max level to highest!", 2644 return ret); 2645 2646 break; 2647 2648 case PP_DCEFCLK: 2649 hard_min_level = mask ? (ffs(mask) - 1) : 0; 2650 2651 if (hard_min_level >= data->dpm_table.dcef_table.count) { 2652 pr_err("Clock level specified %d is over max allowed %d\n", 2653 hard_min_level, 2654 data->dpm_table.dcef_table.count - 1); 2655 return -EINVAL; 2656 } 2657 2658 data->dpm_table.dcef_table.dpm_state.hard_min_level = 2659 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; 2660 2661 ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK); 2662 PP_ASSERT_WITH_CODE(!ret, 2663 "Failed to upload boot level to lowest!", 2664 return ret); 2665 2666 //TODO: Setting DCEFCLK max dpm level is not supported 2667 2668 break; 2669 2670 case PP_PCIE: 2671 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2672 soft_max_level = mask ? (fls(mask) - 1) : 0; 2673 if (soft_min_level >= NUM_LINK_LEVELS || 2674 soft_max_level >= NUM_LINK_LEVELS) 2675 return -EINVAL; 2676 2677 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2678 PPSMC_MSG_SetMinLinkDpmByIndex, soft_min_level, 2679 NULL); 2680 PP_ASSERT_WITH_CODE(!ret, 2681 "Failed to set min link dpm level!", 2682 return ret); 2683 2684 break; 2685 2686 default: 2687 break; 2688 } 2689 2690 return 0; 2691 } 2692 2693 static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 2694 enum amd_dpm_forced_level level) 2695 { 2696 int ret = 0; 2697 uint32_t sclk_mask, mclk_mask, soc_mask; 2698 2699 switch (level) { 2700 case AMD_DPM_FORCED_LEVEL_HIGH: 2701 ret = vega20_force_dpm_highest(hwmgr); 2702 break; 2703 2704 case AMD_DPM_FORCED_LEVEL_LOW: 2705 ret = vega20_force_dpm_lowest(hwmgr); 2706 break; 2707 2708 case AMD_DPM_FORCED_LEVEL_AUTO: 2709 ret = vega20_unforce_dpm_levels(hwmgr); 2710 break; 2711 2712 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 2713 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 2714 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 2715 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 2716 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 2717 if (ret) 2718 return ret; 2719 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 2720 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); 2721 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); 2722 break; 2723 2724 case AMD_DPM_FORCED_LEVEL_MANUAL: 2725 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 2726 default: 2727 break; 2728 } 2729 2730 return ret; 2731 } 2732 2733 static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr) 2734 { 2735 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2736 2737 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 2738 return AMD_FAN_CTRL_MANUAL; 2739 else 2740 return AMD_FAN_CTRL_AUTO; 2741 } 2742 2743 static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 2744 { 2745 switch (mode) { 2746 case AMD_FAN_CTRL_NONE: 2747 vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100); 2748 break; 2749 case AMD_FAN_CTRL_MANUAL: 2750 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 2751 vega20_fan_ctrl_stop_smc_fan_control(hwmgr); 2752 break; 2753 case AMD_FAN_CTRL_AUTO: 2754 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 2755 vega20_fan_ctrl_start_smc_fan_control(hwmgr); 2756 break; 2757 default: 2758 break; 2759 } 2760 } 2761 2762 static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr, 2763 struct amd_pp_simple_clock_info *info) 2764 { 2765 #if 0 2766 struct phm_ppt_v2_information *table_info = 2767 (struct phm_ppt_v2_information *)hwmgr->pptable; 2768 struct phm_clock_and_voltage_limits *max_limits = 2769 &table_info->max_clock_voltage_on_ac; 2770 2771 info->engine_max_clock = max_limits->sclk; 2772 info->memory_max_clock = max_limits->mclk; 2773 #endif 2774 return 0; 2775 } 2776 2777 2778 static int vega20_get_sclks(struct pp_hwmgr *hwmgr, 2779 struct pp_clock_levels_with_latency *clocks) 2780 { 2781 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2782 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 2783 int i, count; 2784 2785 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 2786 return -1; 2787 2788 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2789 clocks->num_levels = count; 2790 2791 for (i = 0; i < count; i++) { 2792 clocks->data[i].clocks_in_khz = 2793 dpm_table->dpm_levels[i].value * 1000; 2794 clocks->data[i].latency_in_us = 0; 2795 } 2796 2797 return 0; 2798 } 2799 2800 static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr, 2801 uint32_t clock) 2802 { 2803 return 25; 2804 } 2805 2806 static int vega20_get_memclocks(struct pp_hwmgr *hwmgr, 2807 struct pp_clock_levels_with_latency *clocks) 2808 { 2809 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2810 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); 2811 int i, count; 2812 2813 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 2814 return -1; 2815 2816 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2817 clocks->num_levels = data->mclk_latency_table.count = count; 2818 2819 for (i = 0; i < count; i++) { 2820 clocks->data[i].clocks_in_khz = 2821 data->mclk_latency_table.entries[i].frequency = 2822 dpm_table->dpm_levels[i].value * 1000; 2823 clocks->data[i].latency_in_us = 2824 data->mclk_latency_table.entries[i].latency = 2825 vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); 2826 } 2827 2828 return 0; 2829 } 2830 2831 static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr, 2832 struct pp_clock_levels_with_latency *clocks) 2833 { 2834 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2835 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.dcef_table); 2836 int i, count; 2837 2838 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) 2839 return -1; 2840 2841 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2842 clocks->num_levels = count; 2843 2844 for (i = 0; i < count; i++) { 2845 clocks->data[i].clocks_in_khz = 2846 dpm_table->dpm_levels[i].value * 1000; 2847 clocks->data[i].latency_in_us = 0; 2848 } 2849 2850 return 0; 2851 } 2852 2853 static int vega20_get_socclocks(struct pp_hwmgr *hwmgr, 2854 struct pp_clock_levels_with_latency *clocks) 2855 { 2856 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2857 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.soc_table); 2858 int i, count; 2859 2860 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) 2861 return -1; 2862 2863 count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count; 2864 clocks->num_levels = count; 2865 2866 for (i = 0; i < count; i++) { 2867 clocks->data[i].clocks_in_khz = 2868 dpm_table->dpm_levels[i].value * 1000; 2869 clocks->data[i].latency_in_us = 0; 2870 } 2871 2872 return 0; 2873 2874 } 2875 2876 static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 2877 enum amd_pp_clock_type type, 2878 struct pp_clock_levels_with_latency *clocks) 2879 { 2880 int ret; 2881 2882 switch (type) { 2883 case amd_pp_sys_clock: 2884 ret = vega20_get_sclks(hwmgr, clocks); 2885 break; 2886 case amd_pp_mem_clock: 2887 ret = vega20_get_memclocks(hwmgr, clocks); 2888 break; 2889 case amd_pp_dcef_clock: 2890 ret = vega20_get_dcefclocks(hwmgr, clocks); 2891 break; 2892 case amd_pp_soc_clock: 2893 ret = vega20_get_socclocks(hwmgr, clocks); 2894 break; 2895 default: 2896 return -EINVAL; 2897 } 2898 2899 return ret; 2900 } 2901 2902 static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 2903 enum amd_pp_clock_type type, 2904 struct pp_clock_levels_with_voltage *clocks) 2905 { 2906 clocks->num_levels = 0; 2907 2908 return 0; 2909 } 2910 2911 static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 2912 void *clock_ranges) 2913 { 2914 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 2915 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 2916 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 2917 2918 if (!data->registry_data.disable_water_mark && 2919 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2920 data->smu_features[GNLD_DPM_SOCCLK].supported) { 2921 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 2922 data->water_marks_bitmap |= WaterMarksExist; 2923 data->water_marks_bitmap &= ~WaterMarksLoaded; 2924 } 2925 2926 return 0; 2927 } 2928 2929 static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 2930 enum PP_OD_DPM_TABLE_COMMAND type, 2931 long *input, uint32_t size) 2932 { 2933 struct vega20_hwmgr *data = 2934 (struct vega20_hwmgr *)(hwmgr->backend); 2935 struct vega20_od8_single_setting *od8_settings = 2936 data->od8_settings.od8_settings_array; 2937 OverDriveTable_t *od_table = 2938 &(data->smc_state_table.overdrive_table); 2939 int32_t input_index, input_clk, input_vol, i; 2940 int od8_id; 2941 int ret; 2942 2943 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 2944 return -EINVAL); 2945 2946 switch (type) { 2947 case PP_OD_EDIT_SCLK_VDDC_TABLE: 2948 if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && 2949 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) { 2950 pr_info("Sclk min/max frequency overdrive not supported\n"); 2951 return -EOPNOTSUPP; 2952 } 2953 2954 for (i = 0; i < size; i += 2) { 2955 if (i + 2 > size) { 2956 pr_info("invalid number of input parameters %d\n", 2957 size); 2958 return -EINVAL; 2959 } 2960 2961 input_index = input[i]; 2962 input_clk = input[i + 1]; 2963 2964 if (input_index != 0 && input_index != 1) { 2965 pr_info("Invalid index %d\n", input_index); 2966 pr_info("Support min/max sclk frequency setting only which index by 0/1\n"); 2967 return -EINVAL; 2968 } 2969 2970 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || 2971 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { 2972 pr_info("clock freq %d is not within allowed range [%d - %d]\n", 2973 input_clk, 2974 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, 2975 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); 2976 return -EINVAL; 2977 } 2978 2979 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || 2980 (input_index == 1 && od_table->GfxclkFmax != input_clk)) 2981 data->gfxclk_overdrive = true; 2982 2983 if (input_index == 0) 2984 od_table->GfxclkFmin = input_clk; 2985 else 2986 od_table->GfxclkFmax = input_clk; 2987 } 2988 2989 break; 2990 2991 case PP_OD_EDIT_MCLK_VDDC_TABLE: 2992 if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { 2993 pr_info("Mclk max frequency overdrive not supported\n"); 2994 return -EOPNOTSUPP; 2995 } 2996 2997 for (i = 0; i < size; i += 2) { 2998 if (i + 2 > size) { 2999 pr_info("invalid number of input parameters %d\n", 3000 size); 3001 return -EINVAL; 3002 } 3003 3004 input_index = input[i]; 3005 input_clk = input[i + 1]; 3006 3007 if (input_index != 1) { 3008 pr_info("Invalid index %d\n", input_index); 3009 pr_info("Support max Mclk frequency setting only which index by 1\n"); 3010 return -EINVAL; 3011 } 3012 3013 if (input_clk < od8_settings[OD8_SETTING_UCLK_FMAX].min_value || 3014 input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) { 3015 pr_info("clock freq %d is not within allowed range [%d - %d]\n", 3016 input_clk, 3017 od8_settings[OD8_SETTING_UCLK_FMAX].min_value, 3018 od8_settings[OD8_SETTING_UCLK_FMAX].max_value); 3019 return -EINVAL; 3020 } 3021 3022 if (input_index == 1 && od_table->UclkFmax != input_clk) 3023 data->memclk_overdrive = true; 3024 3025 od_table->UclkFmax = input_clk; 3026 } 3027 3028 break; 3029 3030 case PP_OD_EDIT_VDDC_CURVE: 3031 if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && 3032 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && 3033 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && 3034 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && 3035 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && 3036 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) { 3037 pr_info("Voltage curve calibrate not supported\n"); 3038 return -EOPNOTSUPP; 3039 } 3040 3041 for (i = 0; i < size; i += 3) { 3042 if (i + 3 > size) { 3043 pr_info("invalid number of input parameters %d\n", 3044 size); 3045 return -EINVAL; 3046 } 3047 3048 input_index = input[i]; 3049 input_clk = input[i + 1]; 3050 input_vol = input[i + 2]; 3051 3052 if (input_index > 2) { 3053 pr_info("Setting for point %d is not supported\n", 3054 input_index + 1); 3055 pr_info("Three supported points index by 0, 1, 2\n"); 3056 return -EINVAL; 3057 } 3058 3059 od8_id = OD8_SETTING_GFXCLK_FREQ1 + 2 * input_index; 3060 if (input_clk < od8_settings[od8_id].min_value || 3061 input_clk > od8_settings[od8_id].max_value) { 3062 pr_info("clock freq %d is not within allowed range [%d - %d]\n", 3063 input_clk, 3064 od8_settings[od8_id].min_value, 3065 od8_settings[od8_id].max_value); 3066 return -EINVAL; 3067 } 3068 3069 od8_id = OD8_SETTING_GFXCLK_VOLTAGE1 + 2 * input_index; 3070 if (input_vol < od8_settings[od8_id].min_value || 3071 input_vol > od8_settings[od8_id].max_value) { 3072 pr_info("clock voltage %d is not within allowed range [%d - %d]\n", 3073 input_vol, 3074 od8_settings[od8_id].min_value, 3075 od8_settings[od8_id].max_value); 3076 return -EINVAL; 3077 } 3078 3079 switch (input_index) { 3080 case 0: 3081 od_table->GfxclkFreq1 = input_clk; 3082 od_table->GfxclkVolt1 = input_vol * VOLTAGE_SCALE; 3083 break; 3084 case 1: 3085 od_table->GfxclkFreq2 = input_clk; 3086 od_table->GfxclkVolt2 = input_vol * VOLTAGE_SCALE; 3087 break; 3088 case 2: 3089 od_table->GfxclkFreq3 = input_clk; 3090 od_table->GfxclkVolt3 = input_vol * VOLTAGE_SCALE; 3091 break; 3092 } 3093 } 3094 break; 3095 3096 case PP_OD_RESTORE_DEFAULT_TABLE: 3097 data->gfxclk_overdrive = false; 3098 data->memclk_overdrive = false; 3099 3100 ret = smum_smc_table_manager(hwmgr, 3101 (uint8_t *)od_table, 3102 TABLE_OVERDRIVE, true); 3103 PP_ASSERT_WITH_CODE(!ret, 3104 "Failed to export overdrive table!", 3105 return ret); 3106 break; 3107 3108 case PP_OD_COMMIT_DPM_TABLE: 3109 ret = smum_smc_table_manager(hwmgr, 3110 (uint8_t *)od_table, 3111 TABLE_OVERDRIVE, false); 3112 PP_ASSERT_WITH_CODE(!ret, 3113 "Failed to import overdrive table!", 3114 return ret); 3115 3116 /* retrieve updated gfxclk table */ 3117 if (data->gfxclk_overdrive) { 3118 data->gfxclk_overdrive = false; 3119 3120 ret = vega20_setup_gfxclk_dpm_table(hwmgr); 3121 if (ret) 3122 return ret; 3123 } 3124 3125 /* retrieve updated memclk table */ 3126 if (data->memclk_overdrive) { 3127 data->memclk_overdrive = false; 3128 3129 ret = vega20_setup_memclk_dpm_table(hwmgr); 3130 if (ret) 3131 return ret; 3132 } 3133 break; 3134 3135 default: 3136 return -EINVAL; 3137 } 3138 3139 return 0; 3140 } 3141 3142 static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr, 3143 enum pp_mp1_state mp1_state) 3144 { 3145 uint16_t msg; 3146 int ret; 3147 3148 switch (mp1_state) { 3149 case PP_MP1_STATE_SHUTDOWN: 3150 msg = PPSMC_MSG_PrepareMp1ForShutdown; 3151 break; 3152 case PP_MP1_STATE_UNLOAD: 3153 msg = PPSMC_MSG_PrepareMp1ForUnload; 3154 break; 3155 case PP_MP1_STATE_RESET: 3156 msg = PPSMC_MSG_PrepareMp1ForReset; 3157 break; 3158 case PP_MP1_STATE_NONE: 3159 default: 3160 return 0; 3161 } 3162 3163 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 3164 "[PrepareMp1] Failed!", 3165 return ret); 3166 3167 return 0; 3168 } 3169 3170 static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 3171 { 3172 static const char *ppfeature_name[] = { 3173 "DPM_PREFETCHER", 3174 "GFXCLK_DPM", 3175 "UCLK_DPM", 3176 "SOCCLK_DPM", 3177 "UVD_DPM", 3178 "VCE_DPM", 3179 "ULV", 3180 "MP0CLK_DPM", 3181 "LINK_DPM", 3182 "DCEFCLK_DPM", 3183 "GFXCLK_DS", 3184 "SOCCLK_DS", 3185 "LCLK_DS", 3186 "PPT", 3187 "TDC", 3188 "THERMAL", 3189 "GFX_PER_CU_CG", 3190 "RM", 3191 "DCEFCLK_DS", 3192 "ACDC", 3193 "VR0HOT", 3194 "VR1HOT", 3195 "FW_CTF", 3196 "LED_DISPLAY", 3197 "FAN_CONTROL", 3198 "GFX_EDC", 3199 "GFXOFF", 3200 "CG", 3201 "FCLK_DPM", 3202 "FCLK_DS", 3203 "MP1CLK_DS", 3204 "MP0CLK_DS", 3205 "XGMI", 3206 "ECC"}; 3207 static const char *output_title[] = { 3208 "FEATURES", 3209 "BITMASK", 3210 "ENABLEMENT"}; 3211 uint64_t features_enabled; 3212 int i; 3213 int ret = 0; 3214 int size = 0; 3215 3216 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 3217 PP_ASSERT_WITH_CODE(!ret, 3218 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 3219 return ret); 3220 3221 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); 3222 size += sprintf(buf + size, "%-19s %-22s %s\n", 3223 output_title[0], 3224 output_title[1], 3225 output_title[2]); 3226 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 3227 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", 3228 ppfeature_name[i], 3229 1ULL << i, 3230 (features_enabled & (1ULL << i)) ? "Y" : "N"); 3231 } 3232 3233 return size; 3234 } 3235 3236 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 3237 { 3238 struct vega20_hwmgr *data = 3239 (struct vega20_hwmgr *)(hwmgr->backend); 3240 uint64_t features_enabled, features_to_enable, features_to_disable; 3241 int i, ret = 0; 3242 bool enabled; 3243 3244 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 3245 return -EINVAL; 3246 3247 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 3248 if (ret) 3249 return ret; 3250 3251 features_to_disable = 3252 features_enabled & ~new_ppfeature_masks; 3253 features_to_enable = 3254 ~features_enabled & new_ppfeature_masks; 3255 3256 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 3257 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 3258 3259 if (features_to_disable) { 3260 ret = vega20_enable_smc_features(hwmgr, false, features_to_disable); 3261 if (ret) 3262 return ret; 3263 } 3264 3265 if (features_to_enable) { 3266 ret = vega20_enable_smc_features(hwmgr, true, features_to_enable); 3267 if (ret) 3268 return ret; 3269 } 3270 3271 /* Update the cached feature enablement state */ 3272 ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled); 3273 if (ret) 3274 return ret; 3275 3276 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 3277 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? 3278 true : false; 3279 data->smu_features[i].enabled = enabled; 3280 } 3281 3282 return 0; 3283 } 3284 3285 static int vega20_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 3286 { 3287 struct amdgpu_device *adev = hwmgr->adev; 3288 3289 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 3290 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 3291 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 3292 } 3293 3294 static int vega20_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) 3295 { 3296 uint32_t width_level; 3297 3298 width_level = vega20_get_current_pcie_link_width_level(hwmgr); 3299 if (width_level > LINK_WIDTH_MAX) 3300 width_level = 0; 3301 3302 return link_width[width_level]; 3303 } 3304 3305 static int vega20_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 3306 { 3307 struct amdgpu_device *adev = hwmgr->adev; 3308 3309 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 3310 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 3311 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 3312 } 3313 3314 static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) 3315 { 3316 uint32_t speed_level; 3317 3318 speed_level = vega20_get_current_pcie_link_speed_level(hwmgr); 3319 if (speed_level > LINK_SPEED_MAX) 3320 speed_level = 0; 3321 3322 return link_speed[speed_level]; 3323 } 3324 3325 static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, 3326 enum pp_clock_type type, char *buf) 3327 { 3328 struct vega20_hwmgr *data = 3329 (struct vega20_hwmgr *)(hwmgr->backend); 3330 struct vega20_od8_single_setting *od8_settings = 3331 data->od8_settings.od8_settings_array; 3332 OverDriveTable_t *od_table = 3333 &(data->smc_state_table.overdrive_table); 3334 PPTable_t *pptable = &(data->smc_state_table.pp_table); 3335 struct pp_clock_levels_with_latency clocks; 3336 struct vega20_single_dpm_table *fclk_dpm_table = 3337 &(data->dpm_table.fclk_table); 3338 int i, now, size = 0; 3339 int ret = 0; 3340 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 3341 3342 switch (type) { 3343 case PP_SCLK: 3344 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now); 3345 PP_ASSERT_WITH_CODE(!ret, 3346 "Attempt to get current gfx clk Failed!", 3347 return ret); 3348 3349 if (vega20_get_sclks(hwmgr, &clocks)) { 3350 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", 3351 now / 100); 3352 break; 3353 } 3354 3355 for (i = 0; i < clocks.num_levels; i++) 3356 size += sprintf(buf + size, "%d: %uMhz %s\n", 3357 i, clocks.data[i].clocks_in_khz / 1000, 3358 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); 3359 break; 3360 3361 case PP_MCLK: 3362 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now); 3363 PP_ASSERT_WITH_CODE(!ret, 3364 "Attempt to get current mclk freq Failed!", 3365 return ret); 3366 3367 if (vega20_get_memclocks(hwmgr, &clocks)) { 3368 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", 3369 now / 100); 3370 break; 3371 } 3372 3373 for (i = 0; i < clocks.num_levels; i++) 3374 size += sprintf(buf + size, "%d: %uMhz %s\n", 3375 i, clocks.data[i].clocks_in_khz / 1000, 3376 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); 3377 break; 3378 3379 case PP_SOCCLK: 3380 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now); 3381 PP_ASSERT_WITH_CODE(!ret, 3382 "Attempt to get current socclk freq Failed!", 3383 return ret); 3384 3385 if (vega20_get_socclocks(hwmgr, &clocks)) { 3386 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", 3387 now / 100); 3388 break; 3389 } 3390 3391 for (i = 0; i < clocks.num_levels; i++) 3392 size += sprintf(buf + size, "%d: %uMhz %s\n", 3393 i, clocks.data[i].clocks_in_khz / 1000, 3394 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); 3395 break; 3396 3397 case PP_FCLK: 3398 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now); 3399 PP_ASSERT_WITH_CODE(!ret, 3400 "Attempt to get current fclk freq Failed!", 3401 return ret); 3402 3403 for (i = 0; i < fclk_dpm_table->count; i++) 3404 size += sprintf(buf + size, "%d: %uMhz %s\n", 3405 i, fclk_dpm_table->dpm_levels[i].value, 3406 fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : ""); 3407 break; 3408 3409 case PP_DCEFCLK: 3410 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now); 3411 PP_ASSERT_WITH_CODE(!ret, 3412 "Attempt to get current dcefclk freq Failed!", 3413 return ret); 3414 3415 if (vega20_get_dcefclocks(hwmgr, &clocks)) { 3416 size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", 3417 now / 100); 3418 break; 3419 } 3420 3421 for (i = 0; i < clocks.num_levels; i++) 3422 size += sprintf(buf + size, "%d: %uMhz %s\n", 3423 i, clocks.data[i].clocks_in_khz / 1000, 3424 (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); 3425 break; 3426 3427 case PP_PCIE: 3428 current_gen_speed = 3429 vega20_get_current_pcie_link_speed_level(hwmgr); 3430 current_lane_width = 3431 vega20_get_current_pcie_link_width_level(hwmgr); 3432 for (i = 0; i < NUM_LINK_LEVELS; i++) { 3433 gen_speed = pptable->PcieGenSpeed[i]; 3434 lane_width = pptable->PcieLaneCount[i]; 3435 3436 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, 3437 (gen_speed == 0) ? "2.5GT/s," : 3438 (gen_speed == 1) ? "5.0GT/s," : 3439 (gen_speed == 2) ? "8.0GT/s," : 3440 (gen_speed == 3) ? "16.0GT/s," : "", 3441 (lane_width == 1) ? "x1" : 3442 (lane_width == 2) ? "x2" : 3443 (lane_width == 3) ? "x4" : 3444 (lane_width == 4) ? "x8" : 3445 (lane_width == 5) ? "x12" : 3446 (lane_width == 6) ? "x16" : "", 3447 pptable->LclkFreq[i], 3448 (current_gen_speed == gen_speed) && 3449 (current_lane_width == lane_width) ? 3450 "*" : ""); 3451 } 3452 break; 3453 3454 case OD_SCLK: 3455 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && 3456 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { 3457 size = sprintf(buf, "%s:\n", "OD_SCLK"); 3458 size += sprintf(buf + size, "0: %10uMhz\n", 3459 od_table->GfxclkFmin); 3460 size += sprintf(buf + size, "1: %10uMhz\n", 3461 od_table->GfxclkFmax); 3462 } 3463 break; 3464 3465 case OD_MCLK: 3466 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { 3467 size = sprintf(buf, "%s:\n", "OD_MCLK"); 3468 size += sprintf(buf + size, "1: %10uMhz\n", 3469 od_table->UclkFmax); 3470 } 3471 3472 break; 3473 3474 case OD_VDDC_CURVE: 3475 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && 3476 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && 3477 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && 3478 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && 3479 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && 3480 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { 3481 size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE"); 3482 size += sprintf(buf + size, "0: %10uMhz %10dmV\n", 3483 od_table->GfxclkFreq1, 3484 od_table->GfxclkVolt1 / VOLTAGE_SCALE); 3485 size += sprintf(buf + size, "1: %10uMhz %10dmV\n", 3486 od_table->GfxclkFreq2, 3487 od_table->GfxclkVolt2 / VOLTAGE_SCALE); 3488 size += sprintf(buf + size, "2: %10uMhz %10dmV\n", 3489 od_table->GfxclkFreq3, 3490 od_table->GfxclkVolt3 / VOLTAGE_SCALE); 3491 } 3492 3493 break; 3494 3495 case OD_RANGE: 3496 size = sprintf(buf, "%s:\n", "OD_RANGE"); 3497 3498 if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && 3499 od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { 3500 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", 3501 od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, 3502 od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); 3503 } 3504 3505 if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { 3506 size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", 3507 od8_settings[OD8_SETTING_UCLK_FMAX].min_value, 3508 od8_settings[OD8_SETTING_UCLK_FMAX].max_value); 3509 } 3510 3511 if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id && 3512 od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id && 3513 od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id && 3514 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && 3515 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && 3516 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { 3517 size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", 3518 od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value, 3519 od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value); 3520 size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", 3521 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value, 3522 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value); 3523 size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", 3524 od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value, 3525 od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value); 3526 size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", 3527 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value, 3528 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value); 3529 size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", 3530 od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value, 3531 od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value); 3532 size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", 3533 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value, 3534 od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value); 3535 } 3536 3537 break; 3538 default: 3539 break; 3540 } 3541 return size; 3542 } 3543 3544 static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, 3545 struct vega20_single_dpm_table *dpm_table) 3546 { 3547 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3548 int ret = 0; 3549 3550 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 3551 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 3552 "[SetUclkToHightestDpmLevel] Dpm table has no entry!", 3553 return -EINVAL); 3554 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, 3555 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", 3556 return -EINVAL); 3557 3558 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3559 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 3560 PPSMC_MSG_SetHardMinByFreq, 3561 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, 3562 NULL)), 3563 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", 3564 return ret); 3565 } 3566 3567 return ret; 3568 } 3569 3570 static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr) 3571 { 3572 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3573 struct vega20_single_dpm_table *dpm_table = &(data->dpm_table.fclk_table); 3574 int ret = 0; 3575 3576 if (data->smu_features[GNLD_DPM_FCLK].enabled) { 3577 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 3578 "[SetFclkToHightestDpmLevel] Dpm table has no entry!", 3579 return -EINVAL); 3580 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_FCLK_DPM_LEVELS, 3581 "[SetFclkToHightestDpmLevel] Dpm table has too many entries!", 3582 return -EINVAL); 3583 3584 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3585 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 3586 PPSMC_MSG_SetSoftMinByFreq, 3587 (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level, 3588 NULL)), 3589 "[SetFclkToHightestDpmLevel] Set soft min fclk failed!", 3590 return ret); 3591 } 3592 3593 return ret; 3594 } 3595 3596 static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 3597 { 3598 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3599 int ret = 0; 3600 3601 smum_send_msg_to_smc_with_parameter(hwmgr, 3602 PPSMC_MSG_NumOfDisplays, 0, NULL); 3603 3604 ret = vega20_set_uclk_to_highest_dpm_level(hwmgr, 3605 &data->dpm_table.mem_table); 3606 if (ret) 3607 return ret; 3608 3609 return vega20_set_fclk_to_highest_dpm_level(hwmgr); 3610 } 3611 3612 static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 3613 { 3614 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3615 int result = 0; 3616 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 3617 3618 if ((data->water_marks_bitmap & WaterMarksExist) && 3619 !(data->water_marks_bitmap & WaterMarksLoaded)) { 3620 result = smum_smc_table_manager(hwmgr, 3621 (uint8_t *)wm_table, TABLE_WATERMARKS, false); 3622 PP_ASSERT_WITH_CODE(!result, 3623 "Failed to update WMTABLE!", 3624 return result); 3625 data->water_marks_bitmap |= WaterMarksLoaded; 3626 } 3627 3628 if ((data->water_marks_bitmap & WaterMarksExist) && 3629 data->smu_features[GNLD_DPM_DCEFCLK].supported && 3630 data->smu_features[GNLD_DPM_SOCCLK].supported) { 3631 result = smum_send_msg_to_smc_with_parameter(hwmgr, 3632 PPSMC_MSG_NumOfDisplays, 3633 hwmgr->display_config->num_display, 3634 NULL); 3635 } 3636 3637 return result; 3638 } 3639 3640 static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 3641 { 3642 struct vega20_hwmgr *data = 3643 (struct vega20_hwmgr *)(hwmgr->backend); 3644 int ret = 0; 3645 3646 if (data->smu_features[GNLD_DPM_UVD].supported) { 3647 if (data->smu_features[GNLD_DPM_UVD].enabled == enable) { 3648 if (enable) 3649 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already enabled!\n"); 3650 else 3651 PP_DBG_LOG("[EnableDisableUVDDPM] feature DPM UVD already disabled!\n"); 3652 } 3653 3654 ret = vega20_enable_smc_features(hwmgr, 3655 enable, 3656 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap); 3657 PP_ASSERT_WITH_CODE(!ret, 3658 "[EnableDisableUVDDPM] Attempt to Enable/Disable DPM UVD Failed!", 3659 return ret); 3660 data->smu_features[GNLD_DPM_UVD].enabled = enable; 3661 } 3662 3663 return 0; 3664 } 3665 3666 static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 3667 { 3668 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3669 3670 if (data->vce_power_gated == bgate) 3671 return ; 3672 3673 data->vce_power_gated = bgate; 3674 if (bgate) { 3675 vega20_enable_disable_vce_dpm(hwmgr, !bgate); 3676 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 3677 AMD_IP_BLOCK_TYPE_VCE, 3678 AMD_PG_STATE_GATE); 3679 } else { 3680 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 3681 AMD_IP_BLOCK_TYPE_VCE, 3682 AMD_PG_STATE_UNGATE); 3683 vega20_enable_disable_vce_dpm(hwmgr, !bgate); 3684 } 3685 3686 } 3687 3688 static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 3689 { 3690 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3691 3692 if (data->uvd_power_gated == bgate) 3693 return ; 3694 3695 data->uvd_power_gated = bgate; 3696 vega20_enable_disable_uvd_dpm(hwmgr, !bgate); 3697 } 3698 3699 static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 3700 { 3701 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3702 struct vega20_single_dpm_table *dpm_table; 3703 bool vblank_too_short = false; 3704 bool disable_mclk_switching; 3705 bool disable_fclk_switching; 3706 uint32_t i, latency; 3707 3708 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 3709 !hwmgr->display_config->multi_monitor_in_sync) || 3710 vblank_too_short; 3711 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3712 3713 /* gfxclk */ 3714 dpm_table = &(data->dpm_table.gfx_table); 3715 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3716 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3717 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3718 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3719 3720 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3721 if (VEGA20_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { 3722 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 3723 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; 3724 } 3725 3726 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 3727 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3728 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 3729 } 3730 3731 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3732 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3733 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3734 } 3735 } 3736 3737 /* memclk */ 3738 dpm_table = &(data->dpm_table.mem_table); 3739 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3740 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3741 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3742 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3743 3744 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3745 if (VEGA20_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { 3746 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 3747 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; 3748 } 3749 3750 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 3751 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3752 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 3753 } 3754 3755 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3756 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3757 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3758 } 3759 } 3760 3761 /* honour DAL's UCLK Hardmin */ 3762 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) 3763 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; 3764 3765 /* Hardmin is dependent on displayconfig */ 3766 if (disable_mclk_switching) { 3767 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3768 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { 3769 if (data->mclk_latency_table.entries[i].latency <= latency) { 3770 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { 3771 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; 3772 break; 3773 } 3774 } 3775 } 3776 } 3777 3778 if (hwmgr->display_config->nb_pstate_switch_disable) 3779 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3780 3781 if ((disable_mclk_switching && 3782 (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) || 3783 hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value) 3784 disable_fclk_switching = true; 3785 else 3786 disable_fclk_switching = false; 3787 3788 /* fclk */ 3789 dpm_table = &(data->dpm_table.fclk_table); 3790 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3791 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3792 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3793 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3794 if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching) 3795 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3796 3797 /* vclk */ 3798 dpm_table = &(data->dpm_table.vclk_table); 3799 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3800 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3801 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3802 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3803 3804 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3805 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 3806 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3807 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3808 } 3809 3810 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3811 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3812 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3813 } 3814 } 3815 3816 /* dclk */ 3817 dpm_table = &(data->dpm_table.dclk_table); 3818 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3819 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3820 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3821 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3822 3823 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3824 if (VEGA20_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 3825 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3826 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_UVDCLK_LEVEL].value; 3827 } 3828 3829 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3830 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3831 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3832 } 3833 } 3834 3835 /* socclk */ 3836 dpm_table = &(data->dpm_table.soc_table); 3837 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3838 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3839 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3840 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3841 3842 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3843 if (VEGA20_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { 3844 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value; 3845 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_SOCCLK_LEVEL].value; 3846 } 3847 3848 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3849 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3850 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3851 } 3852 } 3853 3854 /* eclk */ 3855 dpm_table = &(data->dpm_table.eclk_table); 3856 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 3857 dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT; 3858 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 3859 dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT; 3860 3861 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 3862 if (VEGA20_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { 3863 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value; 3864 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA20_UMD_PSTATE_VCEMCLK_LEVEL].value; 3865 } 3866 3867 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 3868 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3869 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 3870 } 3871 } 3872 3873 return 0; 3874 } 3875 3876 static bool 3877 vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 3878 { 3879 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3880 bool is_update_required = false; 3881 3882 if (data->display_timing.num_existing_displays != 3883 hwmgr->display_config->num_display) 3884 is_update_required = true; 3885 3886 if (data->registry_data.gfx_clk_deep_sleep_support && 3887 (data->display_timing.min_clock_in_sr != 3888 hwmgr->display_config->min_core_set_clock_in_sr)) 3889 is_update_required = true; 3890 3891 return is_update_required; 3892 } 3893 3894 static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 3895 { 3896 int ret = 0; 3897 3898 ret = vega20_disable_all_smu_features(hwmgr); 3899 PP_ASSERT_WITH_CODE(!ret, 3900 "[DisableDpmTasks] Failed to disable all smu features!", 3901 return ret); 3902 3903 return 0; 3904 } 3905 3906 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr) 3907 { 3908 struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); 3909 int result; 3910 3911 result = vega20_disable_dpm_tasks(hwmgr); 3912 PP_ASSERT_WITH_CODE((0 == result), 3913 "[PowerOffAsic] Failed to disable DPM!", 3914 ); 3915 data->water_marks_bitmap &= ~(WaterMarksLoaded); 3916 3917 return result; 3918 } 3919 3920 static int conv_power_profile_to_pplib_workload(int power_profile) 3921 { 3922 int pplib_workload = 0; 3923 3924 switch (power_profile) { 3925 case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT: 3926 pplib_workload = WORKLOAD_DEFAULT_BIT; 3927 break; 3928 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 3929 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; 3930 break; 3931 case PP_SMC_POWER_PROFILE_POWERSAVING: 3932 pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT; 3933 break; 3934 case PP_SMC_POWER_PROFILE_VIDEO: 3935 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; 3936 break; 3937 case PP_SMC_POWER_PROFILE_VR: 3938 pplib_workload = WORKLOAD_PPLIB_VR_BIT; 3939 break; 3940 case PP_SMC_POWER_PROFILE_COMPUTE: 3941 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; 3942 break; 3943 case PP_SMC_POWER_PROFILE_CUSTOM: 3944 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; 3945 break; 3946 } 3947 3948 return pplib_workload; 3949 } 3950 3951 static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 3952 { 3953 DpmActivityMonitorCoeffInt_t activity_monitor; 3954 uint32_t i, size = 0; 3955 uint16_t workload_type = 0; 3956 static const char *profile_name[] = { 3957 "BOOTUP_DEFAULT", 3958 "3D_FULL_SCREEN", 3959 "POWER_SAVING", 3960 "VIDEO", 3961 "VR", 3962 "COMPUTE", 3963 "CUSTOM"}; 3964 static const char *title[] = { 3965 "PROFILE_INDEX(NAME)", 3966 "CLOCK_TYPE(NAME)", 3967 "FPS", 3968 "UseRlcBusy", 3969 "MinActiveFreqType", 3970 "MinActiveFreq", 3971 "BoosterFreqType", 3972 "BoosterFreq", 3973 "PD_Data_limit_c", 3974 "PD_Data_error_coeff", 3975 "PD_Data_error_rate_coeff"}; 3976 int result = 0; 3977 3978 if (!buf) 3979 return -EINVAL; 3980 3981 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n", 3982 title[0], title[1], title[2], title[3], title[4], title[5], 3983 title[6], title[7], title[8], title[9], title[10]); 3984 3985 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) { 3986 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 3987 workload_type = conv_power_profile_to_pplib_workload(i); 3988 result = vega20_get_activity_monitor_coeff(hwmgr, 3989 (uint8_t *)(&activity_monitor), workload_type); 3990 PP_ASSERT_WITH_CODE(!result, 3991 "[GetPowerProfile] Failed to get activity monitor!", 3992 return result); 3993 3994 size += sprintf(buf + size, "%2d %14s%s:\n", 3995 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " "); 3996 3997 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 3998 " ", 3999 0, 4000 "GFXCLK", 4001 activity_monitor.Gfx_FPS, 4002 activity_monitor.Gfx_UseRlcBusy, 4003 activity_monitor.Gfx_MinActiveFreqType, 4004 activity_monitor.Gfx_MinActiveFreq, 4005 activity_monitor.Gfx_BoosterFreqType, 4006 activity_monitor.Gfx_BoosterFreq, 4007 activity_monitor.Gfx_PD_Data_limit_c, 4008 activity_monitor.Gfx_PD_Data_error_coeff, 4009 activity_monitor.Gfx_PD_Data_error_rate_coeff); 4010 4011 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4012 " ", 4013 1, 4014 "SOCCLK", 4015 activity_monitor.Soc_FPS, 4016 activity_monitor.Soc_UseRlcBusy, 4017 activity_monitor.Soc_MinActiveFreqType, 4018 activity_monitor.Soc_MinActiveFreq, 4019 activity_monitor.Soc_BoosterFreqType, 4020 activity_monitor.Soc_BoosterFreq, 4021 activity_monitor.Soc_PD_Data_limit_c, 4022 activity_monitor.Soc_PD_Data_error_coeff, 4023 activity_monitor.Soc_PD_Data_error_rate_coeff); 4024 4025 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4026 " ", 4027 2, 4028 "UCLK", 4029 activity_monitor.Mem_FPS, 4030 activity_monitor.Mem_UseRlcBusy, 4031 activity_monitor.Mem_MinActiveFreqType, 4032 activity_monitor.Mem_MinActiveFreq, 4033 activity_monitor.Mem_BoosterFreqType, 4034 activity_monitor.Mem_BoosterFreq, 4035 activity_monitor.Mem_PD_Data_limit_c, 4036 activity_monitor.Mem_PD_Data_error_coeff, 4037 activity_monitor.Mem_PD_Data_error_rate_coeff); 4038 4039 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", 4040 " ", 4041 3, 4042 "FCLK", 4043 activity_monitor.Fclk_FPS, 4044 activity_monitor.Fclk_UseRlcBusy, 4045 activity_monitor.Fclk_MinActiveFreqType, 4046 activity_monitor.Fclk_MinActiveFreq, 4047 activity_monitor.Fclk_BoosterFreqType, 4048 activity_monitor.Fclk_BoosterFreq, 4049 activity_monitor.Fclk_PD_Data_limit_c, 4050 activity_monitor.Fclk_PD_Data_error_coeff, 4051 activity_monitor.Fclk_PD_Data_error_rate_coeff); 4052 } 4053 4054 return size; 4055 } 4056 4057 static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 4058 { 4059 DpmActivityMonitorCoeffInt_t activity_monitor; 4060 int workload_type, result = 0; 4061 uint32_t power_profile_mode = input[size]; 4062 4063 if (power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) { 4064 pr_err("Invalid power profile mode %d\n", power_profile_mode); 4065 return -EINVAL; 4066 } 4067 4068 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 4069 struct vega20_hwmgr *data = 4070 (struct vega20_hwmgr *)(hwmgr->backend); 4071 if (size == 0 && !data->is_custom_profile_set) 4072 return -EINVAL; 4073 if (size < 10 && size != 0) 4074 return -EINVAL; 4075 4076 result = vega20_get_activity_monitor_coeff(hwmgr, 4077 (uint8_t *)(&activity_monitor), 4078 WORKLOAD_PPLIB_CUSTOM_BIT); 4079 PP_ASSERT_WITH_CODE(!result, 4080 "[SetPowerProfile] Failed to get activity monitor!", 4081 return result); 4082 4083 /* If size==0, then we want to apply the already-configured 4084 * CUSTOM profile again. Just apply it, since we checked its 4085 * validity above 4086 */ 4087 if (size == 0) 4088 goto out; 4089 4090 switch (input[0]) { 4091 case 0: /* Gfxclk */ 4092 activity_monitor.Gfx_FPS = input[1]; 4093 activity_monitor.Gfx_UseRlcBusy = input[2]; 4094 activity_monitor.Gfx_MinActiveFreqType = input[3]; 4095 activity_monitor.Gfx_MinActiveFreq = input[4]; 4096 activity_monitor.Gfx_BoosterFreqType = input[5]; 4097 activity_monitor.Gfx_BoosterFreq = input[6]; 4098 activity_monitor.Gfx_PD_Data_limit_c = input[7]; 4099 activity_monitor.Gfx_PD_Data_error_coeff = input[8]; 4100 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; 4101 break; 4102 case 1: /* Socclk */ 4103 activity_monitor.Soc_FPS = input[1]; 4104 activity_monitor.Soc_UseRlcBusy = input[2]; 4105 activity_monitor.Soc_MinActiveFreqType = input[3]; 4106 activity_monitor.Soc_MinActiveFreq = input[4]; 4107 activity_monitor.Soc_BoosterFreqType = input[5]; 4108 activity_monitor.Soc_BoosterFreq = input[6]; 4109 activity_monitor.Soc_PD_Data_limit_c = input[7]; 4110 activity_monitor.Soc_PD_Data_error_coeff = input[8]; 4111 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9]; 4112 break; 4113 case 2: /* Uclk */ 4114 activity_monitor.Mem_FPS = input[1]; 4115 activity_monitor.Mem_UseRlcBusy = input[2]; 4116 activity_monitor.Mem_MinActiveFreqType = input[3]; 4117 activity_monitor.Mem_MinActiveFreq = input[4]; 4118 activity_monitor.Mem_BoosterFreqType = input[5]; 4119 activity_monitor.Mem_BoosterFreq = input[6]; 4120 activity_monitor.Mem_PD_Data_limit_c = input[7]; 4121 activity_monitor.Mem_PD_Data_error_coeff = input[8]; 4122 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; 4123 break; 4124 case 3: /* Fclk */ 4125 activity_monitor.Fclk_FPS = input[1]; 4126 activity_monitor.Fclk_UseRlcBusy = input[2]; 4127 activity_monitor.Fclk_MinActiveFreqType = input[3]; 4128 activity_monitor.Fclk_MinActiveFreq = input[4]; 4129 activity_monitor.Fclk_BoosterFreqType = input[5]; 4130 activity_monitor.Fclk_BoosterFreq = input[6]; 4131 activity_monitor.Fclk_PD_Data_limit_c = input[7]; 4132 activity_monitor.Fclk_PD_Data_error_coeff = input[8]; 4133 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; 4134 break; 4135 } 4136 4137 result = vega20_set_activity_monitor_coeff(hwmgr, 4138 (uint8_t *)(&activity_monitor), 4139 WORKLOAD_PPLIB_CUSTOM_BIT); 4140 data->is_custom_profile_set = true; 4141 PP_ASSERT_WITH_CODE(!result, 4142 "[SetPowerProfile] Failed to set activity monitor!", 4143 return result); 4144 } 4145 4146 out: 4147 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 4148 workload_type = 4149 conv_power_profile_to_pplib_workload(power_profile_mode); 4150 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 4151 1 << workload_type, 4152 NULL); 4153 4154 hwmgr->power_profile_mode = power_profile_mode; 4155 4156 return 0; 4157 } 4158 4159 static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 4160 uint32_t virtual_addr_low, 4161 uint32_t virtual_addr_hi, 4162 uint32_t mc_addr_low, 4163 uint32_t mc_addr_hi, 4164 uint32_t size) 4165 { 4166 smum_send_msg_to_smc_with_parameter(hwmgr, 4167 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 4168 virtual_addr_hi, 4169 NULL); 4170 smum_send_msg_to_smc_with_parameter(hwmgr, 4171 PPSMC_MSG_SetSystemVirtualDramAddrLow, 4172 virtual_addr_low, 4173 NULL); 4174 smum_send_msg_to_smc_with_parameter(hwmgr, 4175 PPSMC_MSG_DramLogSetDramAddrHigh, 4176 mc_addr_hi, 4177 NULL); 4178 4179 smum_send_msg_to_smc_with_parameter(hwmgr, 4180 PPSMC_MSG_DramLogSetDramAddrLow, 4181 mc_addr_low, 4182 NULL); 4183 4184 smum_send_msg_to_smc_with_parameter(hwmgr, 4185 PPSMC_MSG_DramLogSetDramSize, 4186 size, 4187 NULL); 4188 return 0; 4189 } 4190 4191 static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 4192 struct PP_TemperatureRange *thermal_data) 4193 { 4194 struct vega20_hwmgr *data = 4195 (struct vega20_hwmgr *)(hwmgr->backend); 4196 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 4197 4198 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 4199 4200 thermal_data->max = pp_table->TedgeLimit * 4201 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4202 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 4203 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4204 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 4205 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4206 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 4207 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4208 thermal_data->mem_crit_max = pp_table->ThbmLimit * 4209 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4210 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 4211 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4212 4213 return 0; 4214 } 4215 4216 static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire) 4217 { 4218 int res; 4219 4220 /* I2C bus access can happen very early, when SMU not loaded yet */ 4221 if (!vega20_is_smc_ram_running(hwmgr)) 4222 return 0; 4223 4224 res = smum_send_msg_to_smc_with_parameter(hwmgr, 4225 (acquire ? 4226 PPSMC_MSG_RequestI2CBus : 4227 PPSMC_MSG_ReleaseI2CBus), 4228 0, 4229 NULL); 4230 4231 PP_ASSERT_WITH_CODE(!res, "[SmuI2CAccessBus] Failed to access bus!", return res); 4232 return res; 4233 } 4234 4235 static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr, 4236 enum pp_df_cstate state) 4237 { 4238 int ret; 4239 4240 /* PPSMC_MSG_DFCstateControl is supported with 40.50 and later fws */ 4241 if (hwmgr->smu_version < 0x283200) { 4242 pr_err("Df cstate control is supported with 40.50 and later SMC fw!\n"); 4243 return -EINVAL; 4244 } 4245 4246 ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DFCstateControl, state, 4247 NULL); 4248 if (ret) 4249 pr_err("SetDfCstate failed!\n"); 4250 4251 return ret; 4252 } 4253 4254 static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr, 4255 uint32_t pstate) 4256 { 4257 int ret; 4258 4259 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4260 PPSMC_MSG_SetXgmiMode, 4261 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3, 4262 NULL); 4263 if (ret) 4264 pr_err("SetXgmiPstate failed!\n"); 4265 4266 return ret; 4267 } 4268 4269 static void vega20_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) 4270 { 4271 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); 4272 4273 gpu_metrics->common_header.structure_size = 4274 sizeof(struct gpu_metrics_v1_0); 4275 gpu_metrics->common_header.format_revision = 1; 4276 gpu_metrics->common_header.content_revision = 0; 4277 4278 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 4279 } 4280 4281 static ssize_t vega20_get_gpu_metrics(struct pp_hwmgr *hwmgr, 4282 void **table) 4283 { 4284 struct vega20_hwmgr *data = 4285 (struct vega20_hwmgr *)(hwmgr->backend); 4286 struct gpu_metrics_v1_0 *gpu_metrics = 4287 &data->gpu_metrics_table; 4288 SmuMetrics_t metrics; 4289 uint32_t fan_speed_rpm; 4290 int ret; 4291 4292 ret = vega20_get_metrics_table(hwmgr, &metrics, true); 4293 if (ret) 4294 return ret; 4295 4296 vega20_init_gpu_metrics_v1_0(gpu_metrics); 4297 4298 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 4299 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 4300 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 4301 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 4302 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; 4303 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; 4304 4305 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 4306 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 4307 4308 gpu_metrics->average_socket_power = metrics.AverageSocketPower; 4309 4310 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 4311 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 4312 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 4313 4314 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 4315 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 4316 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 4317 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 4318 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 4319 4320 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 4321 4322 vega20_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); 4323 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; 4324 4325 gpu_metrics->pcie_link_width = 4326 vega20_get_current_pcie_link_width(hwmgr); 4327 gpu_metrics->pcie_link_speed = 4328 vega20_get_current_pcie_link_speed(hwmgr); 4329 4330 *table = (void *)gpu_metrics; 4331 4332 return sizeof(struct gpu_metrics_v1_0); 4333 } 4334 4335 static const struct pp_hwmgr_func vega20_hwmgr_funcs = { 4336 /* init/fini related */ 4337 .backend_init = vega20_hwmgr_backend_init, 4338 .backend_fini = vega20_hwmgr_backend_fini, 4339 .asic_setup = vega20_setup_asic_task, 4340 .power_off_asic = vega20_power_off_asic, 4341 .dynamic_state_management_enable = vega20_enable_dpm_tasks, 4342 .dynamic_state_management_disable = vega20_disable_dpm_tasks, 4343 /* power state related */ 4344 .apply_clocks_adjust_rules = vega20_apply_clocks_adjust_rules, 4345 .pre_display_config_changed = vega20_pre_display_configuration_changed_task, 4346 .display_config_changed = vega20_display_configuration_changed_task, 4347 .check_smc_update_required_for_display_configuration = 4348 vega20_check_smc_update_required_for_display_configuration, 4349 .notify_smc_display_config_after_ps_adjustment = 4350 vega20_notify_smc_display_config_after_ps_adjustment, 4351 /* export to DAL */ 4352 .get_sclk = vega20_dpm_get_sclk, 4353 .get_mclk = vega20_dpm_get_mclk, 4354 .get_dal_power_level = vega20_get_dal_power_level, 4355 .get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency, 4356 .get_clock_by_type_with_voltage = vega20_get_clock_by_type_with_voltage, 4357 .set_watermarks_for_clocks_ranges = vega20_set_watermarks_for_clocks_ranges, 4358 .display_clock_voltage_request = vega20_display_clock_voltage_request, 4359 .get_performance_level = vega20_get_performance_level, 4360 /* UMD pstate, profile related */ 4361 .force_dpm_level = vega20_dpm_force_dpm_level, 4362 .get_power_profile_mode = vega20_get_power_profile_mode, 4363 .set_power_profile_mode = vega20_set_power_profile_mode, 4364 /* od related */ 4365 .set_power_limit = vega20_set_power_limit, 4366 .get_sclk_od = vega20_get_sclk_od, 4367 .set_sclk_od = vega20_set_sclk_od, 4368 .get_mclk_od = vega20_get_mclk_od, 4369 .set_mclk_od = vega20_set_mclk_od, 4370 .odn_edit_dpm_table = vega20_odn_edit_dpm_table, 4371 /* for sysfs to retrive/set gfxclk/memclk */ 4372 .force_clock_level = vega20_force_clock_level, 4373 .print_clock_levels = vega20_print_clock_levels, 4374 .read_sensor = vega20_read_sensor, 4375 .get_ppfeature_status = vega20_get_ppfeature_status, 4376 .set_ppfeature_status = vega20_set_ppfeature_status, 4377 /* powergate related */ 4378 .powergate_uvd = vega20_power_gate_uvd, 4379 .powergate_vce = vega20_power_gate_vce, 4380 /* thermal related */ 4381 .start_thermal_controller = vega20_start_thermal_controller, 4382 .stop_thermal_controller = vega20_thermal_stop_thermal_controller, 4383 .get_thermal_temperature_range = vega20_get_thermal_temperature_range, 4384 .register_irq_handlers = smu9_register_irq_handlers, 4385 .disable_smc_firmware_ctf = vega20_thermal_disable_alert, 4386 /* fan control related */ 4387 .get_fan_speed_percent = vega20_fan_ctrl_get_fan_speed_percent, 4388 .set_fan_speed_percent = vega20_fan_ctrl_set_fan_speed_percent, 4389 .get_fan_speed_info = vega20_fan_ctrl_get_fan_speed_info, 4390 .get_fan_speed_rpm = vega20_fan_ctrl_get_fan_speed_rpm, 4391 .set_fan_speed_rpm = vega20_fan_ctrl_set_fan_speed_rpm, 4392 .get_fan_control_mode = vega20_get_fan_control_mode, 4393 .set_fan_control_mode = vega20_set_fan_control_mode, 4394 /* smu memory related */ 4395 .notify_cac_buffer_info = vega20_notify_cac_buffer_info, 4396 .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost, 4397 /* BACO related */ 4398 .get_asic_baco_capability = vega20_baco_get_capability, 4399 .get_asic_baco_state = vega20_baco_get_state, 4400 .set_asic_baco_state = vega20_baco_set_state, 4401 .set_mp1_state = vega20_set_mp1_state, 4402 .smu_i2c_bus_access = vega20_smu_i2c_bus_access, 4403 .set_df_cstate = vega20_set_df_cstate, 4404 .set_xgmi_pstate = vega20_set_xgmi_pstate, 4405 .get_gpu_metrics = vega20_get_gpu_metrics, 4406 }; 4407 4408 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) 4409 { 4410 hwmgr->hwmgr_func = &vega20_hwmgr_funcs; 4411 hwmgr->pptable_func = &vega20_pptable_funcs; 4412 4413 return 0; 4414 } 4415