1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "amdgpu.h"
24 #include "soc15.h"
25 #include "soc15_hw_ip.h"
26 #include "soc15_common.h"
27 #include "vega20_inc.h"
28 #include "vega20_ppsmc.h"
29 #include "vega20_baco.h"
30 #include "vega20_smumgr.h"
31 
32 #include "amdgpu_ras.h"
33 
34 static const struct soc15_baco_cmd_entry clean_baco_tbl[] = {
35 	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
36 	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
37 };
38 
39 int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
40 {
41 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
42 	uint32_t reg;
43 
44 	*cap = false;
45 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
46 		return 0;
47 
48 	if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
49 		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
50 
51 		if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
52 			*cap = true;
53 	}
54 
55 	return 0;
56 }
57 
58 int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
59 {
60 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
61 	uint32_t reg;
62 
63 	reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
64 
65 	if (reg & BACO_CNTL__BACO_MODE_MASK)
66 		/* gfx has already entered BACO state */
67 		*state = BACO_STATE_IN;
68 	else
69 		*state = BACO_STATE_OUT;
70 	return 0;
71 }
72 
73 int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
74 {
75 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
76 	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
77 	enum BACO_STATE cur_state;
78 	uint32_t data;
79 
80 	vega20_baco_get_state(hwmgr, &cur_state);
81 
82 	if (cur_state == state)
83 		/* aisc already in the target state */
84 		return 0;
85 
86 	if (state == BACO_STATE_IN) {
87 		if (!ras || !adev->ras_enabled) {
88 			data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
89 			data |= 0x80000000;
90 			WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
91 
92 			if (smum_send_msg_to_smc_with_parameter(hwmgr,
93 					PPSMC_MSG_EnterBaco, 0, NULL))
94 				return -EINVAL;
95 		} else {
96 			if (smum_send_msg_to_smc_with_parameter(hwmgr,
97 					PPSMC_MSG_EnterBaco, 1, NULL))
98 				return -EINVAL;
99 		}
100 
101 	} else if (state == BACO_STATE_OUT) {
102 		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco, NULL))
103 			return -EINVAL;
104 		if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
105 						     ARRAY_SIZE(clean_baco_tbl)))
106 			return -EINVAL;
107 	}
108 
109 	return 0;
110 }
111 
112 int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
113 {
114 	int ret = 0;
115 
116 	ret = vega20_set_pptable_driver_address(hwmgr);
117 	if (ret)
118 		return ret;
119 
120 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, NULL);
121 }
122