1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2018 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan #include "amdgpu.h"
24e098bc96SEvan Quan #include "soc15.h"
25e098bc96SEvan Quan #include "soc15_hw_ip.h"
26e098bc96SEvan Quan #include "soc15_common.h"
27e098bc96SEvan Quan #include "vega20_inc.h"
28e098bc96SEvan Quan #include "vega20_ppsmc.h"
29e098bc96SEvan Quan #include "vega20_baco.h"
30e098bc96SEvan Quan #include "vega20_smumgr.h"
31e098bc96SEvan Quan
32e098bc96SEvan Quan #include "amdgpu_ras.h"
33e098bc96SEvan Quan
34*ffa702d2SRan Sun static const struct soc15_baco_cmd_entry clean_baco_tbl[] = {
35e098bc96SEvan Quan {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0},
36e098bc96SEvan Quan {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},
37e098bc96SEvan Quan };
38e098bc96SEvan Quan
vega20_baco_get_capability(struct pp_hwmgr * hwmgr,bool * cap)39e098bc96SEvan Quan int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
40e098bc96SEvan Quan {
41e098bc96SEvan Quan struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
42e098bc96SEvan Quan uint32_t reg;
43e098bc96SEvan Quan
44e098bc96SEvan Quan *cap = false;
45e098bc96SEvan Quan if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
46e098bc96SEvan Quan return 0;
47e098bc96SEvan Quan
48e098bc96SEvan Quan if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) {
49e098bc96SEvan Quan reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
50e098bc96SEvan Quan
51e098bc96SEvan Quan if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
52e098bc96SEvan Quan *cap = true;
53e098bc96SEvan Quan }
54e098bc96SEvan Quan
55e098bc96SEvan Quan return 0;
56e098bc96SEvan Quan }
57e098bc96SEvan Quan
vega20_baco_get_state(struct pp_hwmgr * hwmgr,enum BACO_STATE * state)58e098bc96SEvan Quan int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
59e098bc96SEvan Quan {
60e098bc96SEvan Quan struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
61e098bc96SEvan Quan uint32_t reg;
62e098bc96SEvan Quan
63e098bc96SEvan Quan reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
64e098bc96SEvan Quan
65e098bc96SEvan Quan if (reg & BACO_CNTL__BACO_MODE_MASK)
66e098bc96SEvan Quan /* gfx has already entered BACO state */
67e098bc96SEvan Quan *state = BACO_STATE_IN;
68e098bc96SEvan Quan else
69e098bc96SEvan Quan *state = BACO_STATE_OUT;
70e098bc96SEvan Quan return 0;
71e098bc96SEvan Quan }
72e098bc96SEvan Quan
vega20_baco_set_state(struct pp_hwmgr * hwmgr,enum BACO_STATE state)73e098bc96SEvan Quan int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
74e098bc96SEvan Quan {
75e098bc96SEvan Quan struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
76e098bc96SEvan Quan struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
77e098bc96SEvan Quan enum BACO_STATE cur_state;
78e098bc96SEvan Quan uint32_t data;
79e098bc96SEvan Quan
80e098bc96SEvan Quan vega20_baco_get_state(hwmgr, &cur_state);
81e098bc96SEvan Quan
82e098bc96SEvan Quan if (cur_state == state)
83e098bc96SEvan Quan /* aisc already in the target state */
84e098bc96SEvan Quan return 0;
85e098bc96SEvan Quan
86e098bc96SEvan Quan if (state == BACO_STATE_IN) {
878ab0d6f0SLuben Tuikov if (!ras || !adev->ras_enabled) {
88e098bc96SEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
89e098bc96SEvan Quan data |= 0x80000000;
90e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
91e098bc96SEvan Quan
92e098bc96SEvan Quan if (smum_send_msg_to_smc_with_parameter(hwmgr,
93e098bc96SEvan Quan PPSMC_MSG_EnterBaco, 0, NULL))
94e098bc96SEvan Quan return -EINVAL;
95e098bc96SEvan Quan } else {
96e098bc96SEvan Quan if (smum_send_msg_to_smc_with_parameter(hwmgr,
97e098bc96SEvan Quan PPSMC_MSG_EnterBaco, 1, NULL))
98e098bc96SEvan Quan return -EINVAL;
99e098bc96SEvan Quan }
100e098bc96SEvan Quan
101e098bc96SEvan Quan } else if (state == BACO_STATE_OUT) {
102e098bc96SEvan Quan if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco, NULL))
103e098bc96SEvan Quan return -EINVAL;
104e098bc96SEvan Quan if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
105e098bc96SEvan Quan ARRAY_SIZE(clean_baco_tbl)))
106e098bc96SEvan Quan return -EINVAL;
107e098bc96SEvan Quan }
108e098bc96SEvan Quan
109e098bc96SEvan Quan return 0;
110e098bc96SEvan Quan }
111e098bc96SEvan Quan
vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr * hwmgr)112e098bc96SEvan Quan int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
113e098bc96SEvan Quan {
114e098bc96SEvan Quan int ret = 0;
115e098bc96SEvan Quan
116e098bc96SEvan Quan ret = vega20_set_pptable_driver_address(hwmgr);
117e098bc96SEvan Quan if (ret)
118e098bc96SEvan Quan return ret;
119e098bc96SEvan Quan
120e098bc96SEvan Quan return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI, NULL);
121e098bc96SEvan Quan }
122