1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2017 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan 24e098bc96SEvan Quan #ifndef VEGA12_PROCESSPPTABLES_H 25e098bc96SEvan Quan #define VEGA12_PROCESSPPTABLES_H 26e098bc96SEvan Quan 27e098bc96SEvan Quan #include "hwmgr.h" 28e098bc96SEvan Quan 29e098bc96SEvan Quan enum Vega12_I2CLineID { 30e098bc96SEvan Quan Vega12_I2CLineID_DDC1 = 0x90, 31e098bc96SEvan Quan Vega12_I2CLineID_DDC2 = 0x91, 32e098bc96SEvan Quan Vega12_I2CLineID_DDC3 = 0x92, 33e098bc96SEvan Quan Vega12_I2CLineID_DDC4 = 0x93, 34e098bc96SEvan Quan Vega12_I2CLineID_DDC5 = 0x94, 35e098bc96SEvan Quan Vega12_I2CLineID_DDC6 = 0x95, 36e098bc96SEvan Quan Vega12_I2CLineID_SCLSDA = 0x96, 37e098bc96SEvan Quan Vega12_I2CLineID_DDCVGA = 0x97 38e098bc96SEvan Quan }; 39e098bc96SEvan Quan 40e098bc96SEvan Quan #define Vega12_I2C_DDC1DATA 0 41e098bc96SEvan Quan #define Vega12_I2C_DDC1CLK 1 42e098bc96SEvan Quan #define Vega12_I2C_DDC2DATA 2 43e098bc96SEvan Quan #define Vega12_I2C_DDC2CLK 3 44e098bc96SEvan Quan #define Vega12_I2C_DDC3DATA 4 45e098bc96SEvan Quan #define Vega12_I2C_DDC3CLK 5 46e098bc96SEvan Quan #define Vega12_I2C_SDA 40 47e098bc96SEvan Quan #define Vega12_I2C_SCL 41 48e098bc96SEvan Quan #define Vega12_I2C_DDC4DATA 65 49e098bc96SEvan Quan #define Vega12_I2C_DDC4CLK 66 50e098bc96SEvan Quan #define Vega12_I2C_DDC5DATA 0x48 51e098bc96SEvan Quan #define Vega12_I2C_DDC5CLK 0x49 52e098bc96SEvan Quan #define Vega12_I2C_DDC6DATA 0x4a 53e098bc96SEvan Quan #define Vega12_I2C_DDC6CLK 0x4b 54e098bc96SEvan Quan #define Vega12_I2C_DDCVGADATA 0x4c 55e098bc96SEvan Quan #define Vega12_I2C_DDCVGACLK 0x4d 56e098bc96SEvan Quan 57e098bc96SEvan Quan extern const struct pp_table_func vega12_pptable_funcs; 58e098bc96SEvan Quan #endif 59