1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/fb.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "vega12_smumgr.h" 32 #include "hardwaremanager.h" 33 #include "ppatomfwctrl.h" 34 #include "atomfirmware.h" 35 #include "cgs_common.h" 36 #include "vega12_inc.h" 37 #include "pppcielanes.h" 38 #include "vega12_hwmgr.h" 39 #include "vega12_processpptables.h" 40 #include "vega12_pptable.h" 41 #include "vega12_thermal.h" 42 #include "vega12_ppsmc.h" 43 #include "pp_debug.h" 44 #include "amd_pcie_helpers.h" 45 #include "ppinterrupt.h" 46 #include "pp_overdriver.h" 47 #include "pp_thermal.h" 48 #include "vega12_baco.h" 49 50 #define smnPCIE_LC_SPEED_CNTL 0x11140290 51 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 52 53 #define LINK_WIDTH_MAX 6 54 #define LINK_SPEED_MAX 3 55 static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 56 static int link_speed[] = {25, 50, 80, 160}; 57 58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 59 enum pp_clock_type type, uint32_t mask); 60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 61 uint32_t *clock, 62 PPCLK_e clock_select, 63 bool max); 64 65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) 66 { 67 struct vega12_hwmgr *data = 68 (struct vega12_hwmgr *)(hwmgr->backend); 69 70 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT; 71 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT; 72 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT; 73 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT; 74 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT; 75 76 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT; 77 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 78 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 79 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 80 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 81 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 82 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 83 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 84 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 85 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 86 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 87 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 88 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 89 90 data->registry_data.disallowed_features = 0x0; 91 data->registry_data.od_state_in_dc_support = 0; 92 data->registry_data.thermal_support = 1; 93 data->registry_data.skip_baco_hardware = 0; 94 95 data->registry_data.log_avfs_param = 0; 96 data->registry_data.sclk_throttle_low_notification = 1; 97 data->registry_data.force_dpm_high = 0; 98 data->registry_data.stable_pstate_sclk_dpm_percentage = 75; 99 100 data->registry_data.didt_support = 0; 101 if (data->registry_data.didt_support) { 102 data->registry_data.didt_mode = 6; 103 data->registry_data.sq_ramping_support = 1; 104 data->registry_data.db_ramping_support = 0; 105 data->registry_data.td_ramping_support = 0; 106 data->registry_data.tcp_ramping_support = 0; 107 data->registry_data.dbr_ramping_support = 0; 108 data->registry_data.edc_didt_support = 1; 109 data->registry_data.gc_didt_support = 0; 110 data->registry_data.psm_didt_support = 0; 111 } 112 113 data->registry_data.pcie_lane_override = 0xff; 114 data->registry_data.pcie_speed_override = 0xff; 115 data->registry_data.pcie_clock_override = 0xffffffff; 116 data->registry_data.regulator_hot_gpio_support = 1; 117 data->registry_data.ac_dc_switch_gpio_support = 0; 118 data->registry_data.quick_transition_support = 0; 119 data->registry_data.zrpm_start_temp = 0xffff; 120 data->registry_data.zrpm_stop_temp = 0xffff; 121 data->registry_data.odn_feature_enable = 1; 122 data->registry_data.disable_water_mark = 0; 123 data->registry_data.disable_pp_tuning = 0; 124 data->registry_data.disable_xlpp_tuning = 0; 125 data->registry_data.disable_workload_policy = 0; 126 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; 127 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; 128 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; 129 data->registry_data.force_workload_policy_mask = 0; 130 data->registry_data.disable_3d_fs_detection = 0; 131 data->registry_data.fps_support = 1; 132 data->registry_data.disable_auto_wattman = 1; 133 data->registry_data.auto_wattman_debug = 0; 134 data->registry_data.auto_wattman_sample_period = 100; 135 data->registry_data.auto_wattman_threshold = 50; 136 } 137 138 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) 139 { 140 struct vega12_hwmgr *data = 141 (struct vega12_hwmgr *)(hwmgr->backend); 142 struct amdgpu_device *adev = hwmgr->adev; 143 144 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE) 145 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 146 PHM_PlatformCaps_ControlVDDCI); 147 148 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 149 PHM_PlatformCaps_TablelessHardwareInterface); 150 151 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 152 PHM_PlatformCaps_EnableSMU7ThermalManagement); 153 154 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) { 155 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 156 PHM_PlatformCaps_UVDPowerGating); 157 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 158 PHM_PlatformCaps_UVDDynamicPowerGating); 159 } 160 161 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 162 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 163 PHM_PlatformCaps_VCEPowerGating); 164 165 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 166 PHM_PlatformCaps_UnTabledHardwareInterface); 167 168 if (data->registry_data.odn_feature_enable) 169 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 170 PHM_PlatformCaps_ODNinACSupport); 171 else { 172 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 173 PHM_PlatformCaps_OD6inACSupport); 174 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 175 PHM_PlatformCaps_OD6PlusinACSupport); 176 } 177 178 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 179 PHM_PlatformCaps_ActivityReporting); 180 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 181 PHM_PlatformCaps_FanSpeedInTableIsRPM); 182 183 if (data->registry_data.od_state_in_dc_support) { 184 if (data->registry_data.odn_feature_enable) 185 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 186 PHM_PlatformCaps_ODNinDCSupport); 187 else { 188 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 189 PHM_PlatformCaps_OD6inDCSupport); 190 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 191 PHM_PlatformCaps_OD6PlusinDCSupport); 192 } 193 } 194 195 if (data->registry_data.thermal_support 196 && data->registry_data.fuzzy_fan_control_support 197 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax) 198 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 199 PHM_PlatformCaps_ODFuzzyFanControlSupport); 200 201 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 202 PHM_PlatformCaps_DynamicPowerManagement); 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_SMC); 205 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 206 PHM_PlatformCaps_ThermalPolicyDelay); 207 208 if (data->registry_data.force_dpm_high) 209 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 210 PHM_PlatformCaps_ExclusiveModeAlwaysHigh); 211 212 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 213 PHM_PlatformCaps_DynamicUVDState); 214 215 if (data->registry_data.sclk_throttle_low_notification) 216 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 217 PHM_PlatformCaps_SclkThrottleLowNotification); 218 219 /* power tune caps */ 220 /* assume disabled */ 221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 222 PHM_PlatformCaps_PowerContainment); 223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 224 PHM_PlatformCaps_DiDtSupport); 225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 226 PHM_PlatformCaps_SQRamping); 227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_DBRamping); 229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 230 PHM_PlatformCaps_TDRamping); 231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 232 PHM_PlatformCaps_TCPRamping); 233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_DBRRamping); 235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 236 PHM_PlatformCaps_DiDtEDCEnable); 237 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 238 PHM_PlatformCaps_GCEDC); 239 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 240 PHM_PlatformCaps_PSM); 241 242 if (data->registry_data.didt_support) { 243 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 244 if (data->registry_data.sq_ramping_support) 245 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 246 if (data->registry_data.db_ramping_support) 247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 248 if (data->registry_data.td_ramping_support) 249 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 250 if (data->registry_data.tcp_ramping_support) 251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 252 if (data->registry_data.dbr_ramping_support) 253 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 254 if (data->registry_data.edc_didt_support) 255 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 256 if (data->registry_data.gc_didt_support) 257 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 258 if (data->registry_data.psm_didt_support) 259 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 260 } 261 262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 263 PHM_PlatformCaps_RegulatorHot); 264 265 if (data->registry_data.ac_dc_switch_gpio_support) { 266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 267 PHM_PlatformCaps_AutomaticDCTransition); 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 270 } 271 272 if (data->registry_data.quick_transition_support) { 273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 274 PHM_PlatformCaps_AutomaticDCTransition); 275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 277 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 278 PHM_PlatformCaps_Falcon_QuickTransition); 279 } 280 281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) { 282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 283 PHM_PlatformCaps_LowestUclkReservedForUlv); 284 if (data->lowest_uclk_reserved_for_ulv == 1) 285 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 286 PHM_PlatformCaps_LowestUclkReservedForUlv); 287 } 288 289 if (data->registry_data.custom_fan_support) 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_CustomFanControlSupport); 292 293 return 0; 294 } 295 296 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) 297 { 298 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 299 struct amdgpu_device *adev = hwmgr->adev; 300 uint32_t top32, bottom32; 301 int i; 302 303 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 304 FEATURE_DPM_PREFETCHER_BIT; 305 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 306 FEATURE_DPM_GFXCLK_BIT; 307 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 308 FEATURE_DPM_UCLK_BIT; 309 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 310 FEATURE_DPM_SOCCLK_BIT; 311 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 312 FEATURE_DPM_UVD_BIT; 313 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 314 FEATURE_DPM_VCE_BIT; 315 data->smu_features[GNLD_ULV].smu_feature_id = 316 FEATURE_ULV_BIT; 317 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 318 FEATURE_DPM_MP0CLK_BIT; 319 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 320 FEATURE_DPM_LINK_BIT; 321 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 322 FEATURE_DPM_DCEFCLK_BIT; 323 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 324 FEATURE_DS_GFXCLK_BIT; 325 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 326 FEATURE_DS_SOCCLK_BIT; 327 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 328 FEATURE_DS_LCLK_BIT; 329 data->smu_features[GNLD_PPT].smu_feature_id = 330 FEATURE_PPT_BIT; 331 data->smu_features[GNLD_TDC].smu_feature_id = 332 FEATURE_TDC_BIT; 333 data->smu_features[GNLD_THERMAL].smu_feature_id = 334 FEATURE_THERMAL_BIT; 335 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 336 FEATURE_GFX_PER_CU_CG_BIT; 337 data->smu_features[GNLD_RM].smu_feature_id = 338 FEATURE_RM_BIT; 339 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 340 FEATURE_DS_DCEFCLK_BIT; 341 data->smu_features[GNLD_ACDC].smu_feature_id = 342 FEATURE_ACDC_BIT; 343 data->smu_features[GNLD_VR0HOT].smu_feature_id = 344 FEATURE_VR0HOT_BIT; 345 data->smu_features[GNLD_VR1HOT].smu_feature_id = 346 FEATURE_VR1HOT_BIT; 347 data->smu_features[GNLD_FW_CTF].smu_feature_id = 348 FEATURE_FW_CTF_BIT; 349 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 350 FEATURE_LED_DISPLAY_BIT; 351 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 352 FEATURE_FAN_CONTROL_BIT; 353 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 354 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; 355 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; 356 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 357 358 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 359 data->smu_features[i].smu_feature_bitmap = 360 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); 361 data->smu_features[i].allowed = 362 ((data->registry_data.disallowed_features >> i) & 1) ? 363 false : true; 364 } 365 366 /* Get the SN to turn into a Unique ID */ 367 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 368 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 369 370 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 371 } 372 373 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 374 { 375 return 0; 376 } 377 378 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 379 { 380 kfree(hwmgr->backend); 381 hwmgr->backend = NULL; 382 383 return 0; 384 } 385 386 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 387 { 388 int result = 0; 389 struct vega12_hwmgr *data; 390 struct amdgpu_device *adev = hwmgr->adev; 391 392 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL); 393 if (data == NULL) 394 return -ENOMEM; 395 396 hwmgr->backend = data; 397 398 vega12_set_default_registry_data(hwmgr); 399 400 data->disable_dpm_mask = 0xff; 401 data->workload_mask = 0xff; 402 403 /* need to set voltage control types before EVV patching */ 404 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE; 405 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; 406 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE; 407 408 data->water_marks_bitmap = 0; 409 data->avfs_exist = false; 410 411 vega12_set_features_platform_caps(hwmgr); 412 413 vega12_init_dpm_defaults(hwmgr); 414 415 /* Parse pptable data read from VBIOS */ 416 vega12_set_private_data_based_on_pptable(hwmgr); 417 418 data->is_tlu_enabled = false; 419 420 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 421 VEGA12_MAX_HARDWARE_POWERLEVELS; 422 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 423 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 424 425 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 426 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 427 hwmgr->platform_descriptor.clockStep.engineClock = 500; 428 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 429 430 data->total_active_cus = adev->gfx.cu_info.number; 431 /* Setup default Overdrive Fan control settings */ 432 data->odn_fan_table.target_fan_speed = 433 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 434 data->odn_fan_table.target_temperature = 435 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature; 436 data->odn_fan_table.min_performance_clock = 437 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit; 438 data->odn_fan_table.min_fan_limit = 439 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * 440 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 441 442 if (hwmgr->feature_mask & PP_GFXOFF_MASK) 443 data->gfxoff_controlled_by_driver = true; 444 else 445 data->gfxoff_controlled_by_driver = false; 446 447 return result; 448 } 449 450 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) 451 { 452 struct vega12_hwmgr *data = 453 (struct vega12_hwmgr *)(hwmgr->backend); 454 455 data->low_sclk_interrupt_threshold = 0; 456 457 return 0; 458 } 459 460 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) 461 { 462 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), 463 "Failed to init sclk threshold!", 464 return -EINVAL); 465 466 return 0; 467 } 468 469 /* 470 * @fn vega12_init_dpm_state 471 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 472 * 473 * @param dpm_state - the address of the DPM Table to initiailize. 474 * @return None. 475 */ 476 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) 477 { 478 dpm_state->soft_min_level = 0x0; 479 dpm_state->soft_max_level = 0xffff; 480 dpm_state->hard_min_level = 0x0; 481 dpm_state->hard_max_level = 0xffff; 482 } 483 484 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 485 PPCLK_e clk_id, uint32_t *num_of_levels) 486 { 487 int ret = 0; 488 489 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 490 PPSMC_MSG_GetDpmFreqByIndex, 491 (clk_id << 16 | 0xFF), 492 num_of_levels); 493 PP_ASSERT_WITH_CODE(!ret, 494 "[GetNumOfDpmLevel] failed to get dpm levels!", 495 return ret); 496 497 return ret; 498 } 499 500 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 501 PPCLK_e clkID, uint32_t index, uint32_t *clock) 502 { 503 /* 504 *SMU expects the Clock ID to be in the top 16 bits. 505 *Lower 16 bits specify the level 506 */ 507 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 508 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index), 509 clock) == 0, 510 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", 511 return -EINVAL); 512 513 return 0; 514 } 515 516 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, 517 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) 518 { 519 int ret = 0; 520 uint32_t i, num_of_levels, clk; 521 522 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); 523 PP_ASSERT_WITH_CODE(!ret, 524 "[SetupSingleDpmTable] failed to get clk levels!", 525 return ret); 526 527 dpm_table->count = num_of_levels; 528 529 for (i = 0; i < num_of_levels; i++) { 530 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); 531 PP_ASSERT_WITH_CODE(!ret, 532 "[SetupSingleDpmTable] failed to get clk of specific level!", 533 return ret); 534 dpm_table->dpm_levels[i].value = clk; 535 dpm_table->dpm_levels[i].enabled = true; 536 } 537 538 return ret; 539 } 540 541 /* 542 * This function is to initialize all DPM state tables 543 * for SMU based on the dependency table. 544 * Dynamic state patching function will then trim these 545 * state tables to the allowed range based 546 * on the power policy or external client requests, 547 * such as UVD request, etc. 548 */ 549 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 550 { 551 552 struct vega12_hwmgr *data = 553 (struct vega12_hwmgr *)(hwmgr->backend); 554 struct vega12_single_dpm_table *dpm_table; 555 int ret = 0; 556 557 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 558 559 /* socclk */ 560 dpm_table = &(data->dpm_table.soc_table); 561 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 562 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); 563 PP_ASSERT_WITH_CODE(!ret, 564 "[SetupDefaultDpmTable] failed to get socclk dpm levels!", 565 return ret); 566 } else { 567 dpm_table->count = 1; 568 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 569 } 570 vega12_init_dpm_state(&(dpm_table->dpm_state)); 571 572 /* gfxclk */ 573 dpm_table = &(data->dpm_table.gfx_table); 574 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 575 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 576 PP_ASSERT_WITH_CODE(!ret, 577 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", 578 return ret); 579 } else { 580 dpm_table->count = 1; 581 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 582 } 583 vega12_init_dpm_state(&(dpm_table->dpm_state)); 584 585 /* memclk */ 586 dpm_table = &(data->dpm_table.mem_table); 587 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 588 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); 589 PP_ASSERT_WITH_CODE(!ret, 590 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", 591 return ret); 592 } else { 593 dpm_table->count = 1; 594 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 595 } 596 vega12_init_dpm_state(&(dpm_table->dpm_state)); 597 598 /* eclk */ 599 dpm_table = &(data->dpm_table.eclk_table); 600 if (data->smu_features[GNLD_DPM_VCE].enabled) { 601 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); 602 PP_ASSERT_WITH_CODE(!ret, 603 "[SetupDefaultDpmTable] failed to get eclk dpm levels!", 604 return ret); 605 } else { 606 dpm_table->count = 1; 607 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 608 } 609 vega12_init_dpm_state(&(dpm_table->dpm_state)); 610 611 /* vclk */ 612 dpm_table = &(data->dpm_table.vclk_table); 613 if (data->smu_features[GNLD_DPM_UVD].enabled) { 614 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); 615 PP_ASSERT_WITH_CODE(!ret, 616 "[SetupDefaultDpmTable] failed to get vclk dpm levels!", 617 return ret); 618 } else { 619 dpm_table->count = 1; 620 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 621 } 622 vega12_init_dpm_state(&(dpm_table->dpm_state)); 623 624 /* dclk */ 625 dpm_table = &(data->dpm_table.dclk_table); 626 if (data->smu_features[GNLD_DPM_UVD].enabled) { 627 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); 628 PP_ASSERT_WITH_CODE(!ret, 629 "[SetupDefaultDpmTable] failed to get dclk dpm levels!", 630 return ret); 631 } else { 632 dpm_table->count = 1; 633 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 634 } 635 vega12_init_dpm_state(&(dpm_table->dpm_state)); 636 637 /* dcefclk */ 638 dpm_table = &(data->dpm_table.dcef_table); 639 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 640 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); 641 PP_ASSERT_WITH_CODE(!ret, 642 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", 643 return ret); 644 } else { 645 dpm_table->count = 1; 646 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 647 } 648 vega12_init_dpm_state(&(dpm_table->dpm_state)); 649 650 /* pixclk */ 651 dpm_table = &(data->dpm_table.pixel_table); 652 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 653 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); 654 PP_ASSERT_WITH_CODE(!ret, 655 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", 656 return ret); 657 } else 658 dpm_table->count = 0; 659 vega12_init_dpm_state(&(dpm_table->dpm_state)); 660 661 /* dispclk */ 662 dpm_table = &(data->dpm_table.display_table); 663 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 664 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); 665 PP_ASSERT_WITH_CODE(!ret, 666 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", 667 return ret); 668 } else 669 dpm_table->count = 0; 670 vega12_init_dpm_state(&(dpm_table->dpm_state)); 671 672 /* phyclk */ 673 dpm_table = &(data->dpm_table.phy_table); 674 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 675 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); 676 PP_ASSERT_WITH_CODE(!ret, 677 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", 678 return ret); 679 } else 680 dpm_table->count = 0; 681 vega12_init_dpm_state(&(dpm_table->dpm_state)); 682 683 /* save a copy of the default DPM table */ 684 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 685 sizeof(struct vega12_dpm_table)); 686 687 return 0; 688 } 689 690 #if 0 691 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) 692 { 693 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 694 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 695 uint32_t min_level; 696 697 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; 698 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; 699 700 /* Optimize compute power profile: Use only highest 701 * 2 power levels (if more than 2 are available) 702 */ 703 if (dpm_table->count > 2) 704 min_level = dpm_table->count - 2; 705 else if (dpm_table->count == 2) 706 min_level = 1; 707 else 708 min_level = 0; 709 710 hwmgr->default_compute_power_profile.min_sclk = 711 dpm_table->dpm_levels[min_level].value; 712 713 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; 714 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; 715 716 return 0; 717 } 718 #endif 719 720 /** 721 * Initializes the SMC table and uploads it 722 * 723 * @hwmgr: the address of the powerplay hardware manager. 724 * return: always 0 725 */ 726 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) 727 { 728 int result; 729 struct vega12_hwmgr *data = 730 (struct vega12_hwmgr *)(hwmgr->backend); 731 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 732 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 733 struct phm_ppt_v3_information *pptable_information = 734 (struct phm_ppt_v3_information *)hwmgr->pptable; 735 736 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 737 if (!result) { 738 data->vbios_boot_state.vddc = boot_up_values.usVddc; 739 data->vbios_boot_state.vddci = boot_up_values.usVddci; 740 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 741 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 742 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 743 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 744 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 745 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; 746 data->vbios_boot_state.eclock = boot_up_values.ulEClk; 747 data->vbios_boot_state.dclock = boot_up_values.ulDClk; 748 data->vbios_boot_state.vclock = boot_up_values.ulVClk; 749 smum_send_msg_to_smc_with_parameter(hwmgr, 750 PPSMC_MSG_SetMinDeepSleepDcefclk, 751 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 752 NULL); 753 } 754 755 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 756 757 result = smum_smc_table_manager(hwmgr, 758 (uint8_t *)pp_table, TABLE_PPTABLE, false); 759 PP_ASSERT_WITH_CODE(!result, 760 "Failed to upload PPtable!", return result); 761 762 return 0; 763 } 764 765 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr) 766 { 767 uint32_t result; 768 769 PP_ASSERT_WITH_CODE( 770 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0, 771 "[Run_ACG_BTC] Attempt to run ACG BTC failed!", 772 return -EINVAL); 773 774 PP_ASSERT_WITH_CODE(result == 1, 775 "Failed to run ACG BTC!", return -EINVAL); 776 777 return 0; 778 } 779 780 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) 781 { 782 struct vega12_hwmgr *data = 783 (struct vega12_hwmgr *)(hwmgr->backend); 784 int i; 785 uint32_t allowed_features_low = 0, allowed_features_high = 0; 786 787 for (i = 0; i < GNLD_FEATURES_MAX; i++) 788 if (data->smu_features[i].allowed) 789 data->smu_features[i].smu_feature_id > 31 ? 790 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) : 791 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF)); 792 793 PP_ASSERT_WITH_CODE( 794 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, 795 NULL) == 0, 796 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!", 797 return -1); 798 799 PP_ASSERT_WITH_CODE( 800 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, 801 NULL) == 0, 802 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", 803 return -1); 804 805 return 0; 806 } 807 808 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) 809 { 810 struct vega12_hwmgr *data = 811 (struct vega12_hwmgr *)(hwmgr->backend); 812 813 data->uvd_power_gated = true; 814 data->vce_power_gated = true; 815 816 if (data->smu_features[GNLD_DPM_UVD].enabled) 817 data->uvd_power_gated = false; 818 819 if (data->smu_features[GNLD_DPM_VCE].enabled) 820 data->vce_power_gated = false; 821 } 822 823 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) 824 { 825 struct vega12_hwmgr *data = 826 (struct vega12_hwmgr *)(hwmgr->backend); 827 uint64_t features_enabled; 828 int i; 829 bool enabled; 830 831 PP_ASSERT_WITH_CODE( 832 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0, 833 "[EnableAllSMUFeatures] Failed to enable all smu features!", 834 return -1); 835 836 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 837 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 838 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 839 data->smu_features[i].enabled = enabled; 840 data->smu_features[i].supported = enabled; 841 } 842 } 843 844 vega12_init_powergate_state(hwmgr); 845 846 return 0; 847 } 848 849 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) 850 { 851 struct vega12_hwmgr *data = 852 (struct vega12_hwmgr *)(hwmgr->backend); 853 uint64_t features_enabled; 854 int i; 855 bool enabled; 856 857 PP_ASSERT_WITH_CODE( 858 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0, 859 "[DisableAllSMUFeatures] Failed to disable all smu features!", 860 return -1); 861 862 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 863 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 864 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 865 data->smu_features[i].enabled = enabled; 866 data->smu_features[i].supported = enabled; 867 } 868 } 869 870 return 0; 871 } 872 873 static int vega12_odn_initialize_default_settings( 874 struct pp_hwmgr *hwmgr) 875 { 876 return 0; 877 } 878 879 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 880 uint32_t adjust_percent) 881 { 882 return smum_send_msg_to_smc_with_parameter(hwmgr, 883 PPSMC_MSG_OverDriveSetPercentage, adjust_percent, 884 NULL); 885 } 886 887 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) 888 { 889 int adjust_percent, result = 0; 890 891 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 892 adjust_percent = 893 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? 894 hwmgr->platform_descriptor.TDPAdjustment : 895 (-1 * hwmgr->platform_descriptor.TDPAdjustment); 896 result = vega12_set_overdrive_target_percentage(hwmgr, 897 (uint32_t)adjust_percent); 898 } 899 return result; 900 } 901 902 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, 903 PPCLK_e clkid, struct vega12_clock_range *clock) 904 { 905 /* AC Max */ 906 PP_ASSERT_WITH_CODE( 907 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16), 908 &(clock->ACMax)) == 0, 909 "[GetClockRanges] Failed to get max ac clock from SMC!", 910 return -EINVAL); 911 912 /* AC Min */ 913 PP_ASSERT_WITH_CODE( 914 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16), 915 &(clock->ACMin)) == 0, 916 "[GetClockRanges] Failed to get min ac clock from SMC!", 917 return -EINVAL); 918 919 /* DC Max */ 920 PP_ASSERT_WITH_CODE( 921 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16), 922 &(clock->DCMax)) == 0, 923 "[GetClockRanges] Failed to get max dc clock from SMC!", 924 return -EINVAL); 925 926 return 0; 927 } 928 929 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) 930 { 931 struct vega12_hwmgr *data = 932 (struct vega12_hwmgr *)(hwmgr->backend); 933 uint32_t i; 934 935 for (i = 0; i < PPCLK_COUNT; i++) 936 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, 937 i, &(data->clk_range[i])), 938 "Failed to get clk range from SMC!", 939 return -EINVAL); 940 941 return 0; 942 } 943 944 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 945 { 946 int tmp_result, result = 0; 947 948 smum_send_msg_to_smc_with_parameter(hwmgr, 949 PPSMC_MSG_NumOfDisplays, 0, NULL); 950 951 result = vega12_set_allowed_featuresmask(hwmgr); 952 PP_ASSERT_WITH_CODE(result == 0, 953 "[EnableDPMTasks] Failed to set allowed featuresmask!\n", 954 return result); 955 956 tmp_result = vega12_init_smc_table(hwmgr); 957 PP_ASSERT_WITH_CODE(!tmp_result, 958 "Failed to initialize SMC table!", 959 result = tmp_result); 960 961 tmp_result = vega12_run_acg_btc(hwmgr); 962 PP_ASSERT_WITH_CODE(!tmp_result, 963 "Failed to run ACG BTC!", 964 result = tmp_result); 965 966 result = vega12_enable_all_smu_features(hwmgr); 967 PP_ASSERT_WITH_CODE(!result, 968 "Failed to enable all smu features!", 969 return result); 970 971 tmp_result = vega12_power_control_set_level(hwmgr); 972 PP_ASSERT_WITH_CODE(!tmp_result, 973 "Failed to power control set level!", 974 result = tmp_result); 975 976 result = vega12_get_all_clock_ranges(hwmgr); 977 PP_ASSERT_WITH_CODE(!result, 978 "Failed to get all clock ranges!", 979 return result); 980 981 result = vega12_odn_initialize_default_settings(hwmgr); 982 PP_ASSERT_WITH_CODE(!result, 983 "Failed to power control set level!", 984 return result); 985 986 result = vega12_setup_default_dpm_tables(hwmgr); 987 PP_ASSERT_WITH_CODE(!result, 988 "Failed to setup default DPM tables!", 989 return result); 990 return result; 991 } 992 993 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, 994 struct pp_hw_power_state *hw_ps) 995 { 996 return 0; 997 } 998 999 static uint32_t vega12_find_lowest_dpm_level( 1000 struct vega12_single_dpm_table *table) 1001 { 1002 uint32_t i; 1003 1004 for (i = 0; i < table->count; i++) { 1005 if (table->dpm_levels[i].enabled) 1006 break; 1007 } 1008 1009 if (i >= table->count) { 1010 i = 0; 1011 table->dpm_levels[i].enabled = true; 1012 } 1013 1014 return i; 1015 } 1016 1017 static uint32_t vega12_find_highest_dpm_level( 1018 struct vega12_single_dpm_table *table) 1019 { 1020 int32_t i = 0; 1021 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, 1022 "[FindHighestDPMLevel] DPM Table has too many entries!", 1023 return MAX_REGULAR_DPM_NUMBER - 1); 1024 1025 for (i = table->count - 1; i >= 0; i--) { 1026 if (table->dpm_levels[i].enabled) 1027 break; 1028 } 1029 1030 if (i < 0) { 1031 i = 0; 1032 table->dpm_levels[i].enabled = true; 1033 } 1034 1035 return (uint32_t)i; 1036 } 1037 1038 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) 1039 { 1040 struct vega12_hwmgr *data = hwmgr->backend; 1041 uint32_t min_freq; 1042 int ret = 0; 1043 1044 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1045 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1046 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1047 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1048 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), 1049 NULL)), 1050 "Failed to set soft min gfxclk !", 1051 return ret); 1052 } 1053 1054 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1055 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1056 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1057 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1058 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1059 NULL)), 1060 "Failed to set soft min memclk !", 1061 return ret); 1062 1063 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; 1064 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1065 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1066 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1067 NULL)), 1068 "Failed to set hard min memclk !", 1069 return ret); 1070 } 1071 1072 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1073 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1074 1075 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1076 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1077 (PPCLK_VCLK << 16) | (min_freq & 0xffff), 1078 NULL)), 1079 "Failed to set soft min vclk!", 1080 return ret); 1081 1082 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1083 1084 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1085 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1086 (PPCLK_DCLK << 16) | (min_freq & 0xffff), 1087 NULL)), 1088 "Failed to set soft min dclk!", 1089 return ret); 1090 } 1091 1092 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1093 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1094 1095 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1096 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1097 (PPCLK_ECLK << 16) | (min_freq & 0xffff), 1098 NULL)), 1099 "Failed to set soft min eclk!", 1100 return ret); 1101 } 1102 1103 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1104 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1105 1106 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1107 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1108 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), 1109 NULL)), 1110 "Failed to set soft min socclk!", 1111 return ret); 1112 } 1113 1114 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1115 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; 1116 1117 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1118 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1119 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), 1120 NULL)), 1121 "Failed to set hard min dcefclk!", 1122 return ret); 1123 } 1124 1125 return ret; 1126 1127 } 1128 1129 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 1130 { 1131 struct vega12_hwmgr *data = hwmgr->backend; 1132 uint32_t max_freq; 1133 int ret = 0; 1134 1135 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1136 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1137 1138 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1139 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1140 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), 1141 NULL)), 1142 "Failed to set soft max gfxclk!", 1143 return ret); 1144 } 1145 1146 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1147 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1148 1149 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1150 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1151 (PPCLK_UCLK << 16) | (max_freq & 0xffff), 1152 NULL)), 1153 "Failed to set soft max memclk!", 1154 return ret); 1155 } 1156 1157 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1158 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1159 1160 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1161 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1162 (PPCLK_VCLK << 16) | (max_freq & 0xffff), 1163 NULL)), 1164 "Failed to set soft max vclk!", 1165 return ret); 1166 1167 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1168 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1169 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1170 (PPCLK_DCLK << 16) | (max_freq & 0xffff), 1171 NULL)), 1172 "Failed to set soft max dclk!", 1173 return ret); 1174 } 1175 1176 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1177 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1178 1179 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1180 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1181 (PPCLK_ECLK << 16) | (max_freq & 0xffff), 1182 NULL)), 1183 "Failed to set soft max eclk!", 1184 return ret); 1185 } 1186 1187 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1188 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1189 1190 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1191 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1192 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), 1193 NULL)), 1194 "Failed to set soft max socclk!", 1195 return ret); 1196 } 1197 1198 return ret; 1199 } 1200 1201 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 1202 { 1203 struct vega12_hwmgr *data = 1204 (struct vega12_hwmgr *)(hwmgr->backend); 1205 1206 if (data->smu_features[GNLD_DPM_VCE].supported) { 1207 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 1208 enable, 1209 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 1210 "Attempt to Enable/Disable DPM VCE Failed!", 1211 return -1); 1212 data->smu_features[GNLD_DPM_VCE].enabled = enable; 1213 } 1214 1215 return 0; 1216 } 1217 1218 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 1219 { 1220 struct vega12_hwmgr *data = 1221 (struct vega12_hwmgr *)(hwmgr->backend); 1222 uint32_t gfx_clk; 1223 1224 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1225 return -1; 1226 1227 if (low) 1228 PP_ASSERT_WITH_CODE( 1229 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0, 1230 "[GetSclks]: fail to get min PPCLK_GFXCLK\n", 1231 return -1); 1232 else 1233 PP_ASSERT_WITH_CODE( 1234 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0, 1235 "[GetSclks]: fail to get max PPCLK_GFXCLK\n", 1236 return -1); 1237 1238 return (gfx_clk * 100); 1239 } 1240 1241 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 1242 { 1243 struct vega12_hwmgr *data = 1244 (struct vega12_hwmgr *)(hwmgr->backend); 1245 uint32_t mem_clk; 1246 1247 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1248 return -1; 1249 1250 if (low) 1251 PP_ASSERT_WITH_CODE( 1252 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, 1253 "[GetMclks]: fail to get min PPCLK_UCLK\n", 1254 return -1); 1255 else 1256 PP_ASSERT_WITH_CODE( 1257 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, 1258 "[GetMclks]: fail to get max PPCLK_UCLK\n", 1259 return -1); 1260 1261 return (mem_clk * 100); 1262 } 1263 1264 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, 1265 SmuMetrics_t *metrics_table, 1266 bool bypass_cache) 1267 { 1268 struct vega12_hwmgr *data = 1269 (struct vega12_hwmgr *)(hwmgr->backend); 1270 int ret = 0; 1271 1272 if (bypass_cache || 1273 !data->metrics_time || 1274 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { 1275 ret = smum_smc_table_manager(hwmgr, 1276 (uint8_t *)(&data->metrics_table), 1277 TABLE_SMU_METRICS, 1278 true); 1279 if (ret) { 1280 pr_info("Failed to export SMU metrics table!\n"); 1281 return ret; 1282 } 1283 data->metrics_time = jiffies; 1284 } 1285 1286 if (metrics_table) 1287 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); 1288 1289 return ret; 1290 } 1291 1292 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) 1293 { 1294 SmuMetrics_t metrics_table; 1295 int ret = 0; 1296 1297 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1298 if (ret) 1299 return ret; 1300 1301 *query = metrics_table.CurrSocketPower << 8; 1302 1303 return ret; 1304 } 1305 1306 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) 1307 { 1308 uint32_t gfx_clk = 0; 1309 1310 *gfx_freq = 0; 1311 1312 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 1313 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16), 1314 &gfx_clk) == 0, 1315 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!", 1316 return -EINVAL); 1317 1318 *gfx_freq = gfx_clk * 100; 1319 1320 return 0; 1321 } 1322 1323 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) 1324 { 1325 uint32_t mem_clk = 0; 1326 1327 *mclk_freq = 0; 1328 1329 PP_ASSERT_WITH_CODE( 1330 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16), 1331 &mem_clk) == 0, 1332 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!", 1333 return -EINVAL); 1334 1335 *mclk_freq = mem_clk * 100; 1336 1337 return 0; 1338 } 1339 1340 static int vega12_get_current_activity_percent( 1341 struct pp_hwmgr *hwmgr, 1342 int idx, 1343 uint32_t *activity_percent) 1344 { 1345 SmuMetrics_t metrics_table; 1346 int ret = 0; 1347 1348 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1349 if (ret) 1350 return ret; 1351 1352 switch (idx) { 1353 case AMDGPU_PP_SENSOR_GPU_LOAD: 1354 *activity_percent = metrics_table.AverageGfxActivity; 1355 break; 1356 case AMDGPU_PP_SENSOR_MEM_LOAD: 1357 *activity_percent = metrics_table.AverageUclkActivity; 1358 break; 1359 default: 1360 pr_err("Invalid index for retrieving clock activity\n"); 1361 return -EINVAL; 1362 } 1363 1364 return ret; 1365 } 1366 1367 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1368 void *value, int *size) 1369 { 1370 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1371 SmuMetrics_t metrics_table; 1372 int ret = 0; 1373 1374 switch (idx) { 1375 case AMDGPU_PP_SENSOR_GFX_SCLK: 1376 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); 1377 if (!ret) 1378 *size = 4; 1379 break; 1380 case AMDGPU_PP_SENSOR_GFX_MCLK: 1381 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); 1382 if (!ret) 1383 *size = 4; 1384 break; 1385 case AMDGPU_PP_SENSOR_GPU_LOAD: 1386 case AMDGPU_PP_SENSOR_MEM_LOAD: 1387 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); 1388 if (!ret) 1389 *size = 4; 1390 break; 1391 case AMDGPU_PP_SENSOR_GPU_TEMP: 1392 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); 1393 *size = 4; 1394 break; 1395 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1396 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1397 if (ret) 1398 return ret; 1399 1400 *((uint32_t *)value) = metrics_table.TemperatureHotspot * 1401 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1402 *size = 4; 1403 break; 1404 case AMDGPU_PP_SENSOR_MEM_TEMP: 1405 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1406 if (ret) 1407 return ret; 1408 1409 *((uint32_t *)value) = metrics_table.TemperatureHBM * 1410 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1411 *size = 4; 1412 break; 1413 case AMDGPU_PP_SENSOR_UVD_POWER: 1414 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 1415 *size = 4; 1416 break; 1417 case AMDGPU_PP_SENSOR_VCE_POWER: 1418 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 1419 *size = 4; 1420 break; 1421 case AMDGPU_PP_SENSOR_GPU_POWER: 1422 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); 1423 if (!ret) 1424 *size = 4; 1425 break; 1426 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 1427 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value); 1428 if (!ret) 1429 *size = 8; 1430 break; 1431 default: 1432 ret = -EINVAL; 1433 break; 1434 } 1435 return ret; 1436 } 1437 1438 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, 1439 bool has_disp) 1440 { 1441 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1442 1443 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1444 return smum_send_msg_to_smc_with_parameter(hwmgr, 1445 PPSMC_MSG_SetUclkFastSwitch, 1446 has_disp ? 1 : 0, 1447 NULL); 1448 1449 return 0; 1450 } 1451 1452 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 1453 struct pp_display_clock_request *clock_req) 1454 { 1455 int result = 0; 1456 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1457 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1458 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1459 PPCLK_e clk_select = 0; 1460 uint32_t clk_request = 0; 1461 1462 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1463 switch (clk_type) { 1464 case amd_pp_dcef_clock: 1465 clk_select = PPCLK_DCEFCLK; 1466 break; 1467 case amd_pp_disp_clock: 1468 clk_select = PPCLK_DISPCLK; 1469 break; 1470 case amd_pp_pixel_clock: 1471 clk_select = PPCLK_PIXCLK; 1472 break; 1473 case amd_pp_phy_clock: 1474 clk_select = PPCLK_PHYCLK; 1475 break; 1476 default: 1477 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 1478 result = -1; 1479 break; 1480 } 1481 1482 if (!result) { 1483 clk_request = (clk_select << 16) | clk_freq; 1484 result = smum_send_msg_to_smc_with_parameter(hwmgr, 1485 PPSMC_MSG_SetHardMinByFreq, 1486 clk_request, 1487 NULL); 1488 } 1489 } 1490 1491 return result; 1492 } 1493 1494 static int vega12_notify_smc_display_config_after_ps_adjustment( 1495 struct pp_hwmgr *hwmgr) 1496 { 1497 struct vega12_hwmgr *data = 1498 (struct vega12_hwmgr *)(hwmgr->backend); 1499 struct PP_Clocks min_clocks = {0}; 1500 struct pp_display_clock_request clock_req; 1501 1502 if ((hwmgr->display_config->num_display > 1) && 1503 !hwmgr->display_config->multi_monitor_in_sync && 1504 !hwmgr->display_config->nb_pstate_switch_disable) 1505 vega12_notify_smc_display_change(hwmgr, false); 1506 else 1507 vega12_notify_smc_display_change(hwmgr, true); 1508 1509 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 1510 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 1511 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 1512 1513 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { 1514 clock_req.clock_type = amd_pp_dcef_clock; 1515 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; 1516 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { 1517 if (data->smu_features[GNLD_DS_DCEFCLK].supported) 1518 PP_ASSERT_WITH_CODE( 1519 !smum_send_msg_to_smc_with_parameter( 1520 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 1521 min_clocks.dcefClockInSR /100, 1522 NULL), 1523 "Attempt to set divider for DCEFCLK Failed!", 1524 return -1); 1525 } else { 1526 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 1527 } 1528 } 1529 1530 return 0; 1531 } 1532 1533 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) 1534 { 1535 struct vega12_hwmgr *data = 1536 (struct vega12_hwmgr *)(hwmgr->backend); 1537 1538 uint32_t soft_level; 1539 1540 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 1541 1542 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1543 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1544 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1545 1546 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table)); 1547 1548 data->dpm_table.mem_table.dpm_state.soft_min_level = 1549 data->dpm_table.mem_table.dpm_state.soft_max_level = 1550 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1551 1552 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1553 "Failed to upload boot level to highest!", 1554 return -1); 1555 1556 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1557 "Failed to upload dpm max level to highest!", 1558 return -1); 1559 1560 return 0; 1561 } 1562 1563 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) 1564 { 1565 struct vega12_hwmgr *data = 1566 (struct vega12_hwmgr *)(hwmgr->backend); 1567 uint32_t soft_level; 1568 1569 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 1570 1571 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1572 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1573 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1574 1575 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 1576 1577 data->dpm_table.mem_table.dpm_state.soft_min_level = 1578 data->dpm_table.mem_table.dpm_state.soft_max_level = 1579 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1580 1581 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1582 "Failed to upload boot level to highest!", 1583 return -1); 1584 1585 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1586 "Failed to upload dpm max level to highest!", 1587 return -1); 1588 1589 return 0; 1590 1591 } 1592 1593 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 1594 { 1595 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1596 "Failed to upload DPM Bootup Levels!", 1597 return -1); 1598 1599 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1600 "Failed to upload DPM Max Levels!", 1601 return -1); 1602 1603 return 0; 1604 } 1605 1606 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 1607 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 1608 { 1609 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1610 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 1611 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 1612 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); 1613 1614 *sclk_mask = 0; 1615 *mclk_mask = 0; 1616 *soc_mask = 0; 1617 1618 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && 1619 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL && 1620 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) { 1621 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; 1622 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; 1623 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; 1624 } 1625 1626 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 1627 *sclk_mask = 0; 1628 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 1629 *mclk_mask = 0; 1630 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 1631 *sclk_mask = gfx_dpm_table->count - 1; 1632 *mclk_mask = mem_dpm_table->count - 1; 1633 *soc_mask = soc_dpm_table->count - 1; 1634 } 1635 1636 return 0; 1637 } 1638 1639 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 1640 { 1641 switch (mode) { 1642 case AMD_FAN_CTRL_NONE: 1643 break; 1644 case AMD_FAN_CTRL_MANUAL: 1645 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1646 vega12_fan_ctrl_stop_smc_fan_control(hwmgr); 1647 break; 1648 case AMD_FAN_CTRL_AUTO: 1649 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1650 vega12_fan_ctrl_start_smc_fan_control(hwmgr); 1651 break; 1652 default: 1653 break; 1654 } 1655 } 1656 1657 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 1658 enum amd_dpm_forced_level level) 1659 { 1660 int ret = 0; 1661 uint32_t sclk_mask = 0; 1662 uint32_t mclk_mask = 0; 1663 uint32_t soc_mask = 0; 1664 1665 switch (level) { 1666 case AMD_DPM_FORCED_LEVEL_HIGH: 1667 ret = vega12_force_dpm_highest(hwmgr); 1668 break; 1669 case AMD_DPM_FORCED_LEVEL_LOW: 1670 ret = vega12_force_dpm_lowest(hwmgr); 1671 break; 1672 case AMD_DPM_FORCED_LEVEL_AUTO: 1673 ret = vega12_unforce_dpm_levels(hwmgr); 1674 break; 1675 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1676 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1677 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1678 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1679 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 1680 if (ret) 1681 return ret; 1682 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 1683 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); 1684 break; 1685 case AMD_DPM_FORCED_LEVEL_MANUAL: 1686 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1687 default: 1688 break; 1689 } 1690 1691 return ret; 1692 } 1693 1694 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) 1695 { 1696 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1697 1698 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 1699 return AMD_FAN_CTRL_MANUAL; 1700 else 1701 return AMD_FAN_CTRL_AUTO; 1702 } 1703 1704 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, 1705 struct amd_pp_simple_clock_info *info) 1706 { 1707 #if 0 1708 struct phm_ppt_v2_information *table_info = 1709 (struct phm_ppt_v2_information *)hwmgr->pptable; 1710 struct phm_clock_and_voltage_limits *max_limits = 1711 &table_info->max_clock_voltage_on_ac; 1712 1713 info->engine_max_clock = max_limits->sclk; 1714 info->memory_max_clock = max_limits->mclk; 1715 #endif 1716 return 0; 1717 } 1718 1719 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 1720 uint32_t *clock, 1721 PPCLK_e clock_select, 1722 bool max) 1723 { 1724 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1725 1726 if (max) 1727 *clock = data->clk_range[clock_select].ACMax; 1728 else 1729 *clock = data->clk_range[clock_select].ACMin; 1730 1731 return 0; 1732 } 1733 1734 static int vega12_get_sclks(struct pp_hwmgr *hwmgr, 1735 struct pp_clock_levels_with_latency *clocks) 1736 { 1737 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1738 uint32_t ucount; 1739 int i; 1740 struct vega12_single_dpm_table *dpm_table; 1741 1742 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1743 return -1; 1744 1745 dpm_table = &(data->dpm_table.gfx_table); 1746 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1747 MAX_NUM_CLOCKS : dpm_table->count; 1748 1749 for (i = 0; i < ucount; i++) { 1750 clocks->data[i].clocks_in_khz = 1751 dpm_table->dpm_levels[i].value * 1000; 1752 1753 clocks->data[i].latency_in_us = 0; 1754 } 1755 1756 clocks->num_levels = ucount; 1757 1758 return 0; 1759 } 1760 1761 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, 1762 uint32_t clock) 1763 { 1764 return 25; 1765 } 1766 1767 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, 1768 struct pp_clock_levels_with_latency *clocks) 1769 { 1770 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1771 uint32_t ucount; 1772 int i; 1773 struct vega12_single_dpm_table *dpm_table; 1774 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1775 return -1; 1776 1777 dpm_table = &(data->dpm_table.mem_table); 1778 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1779 MAX_NUM_CLOCKS : dpm_table->count; 1780 1781 for (i = 0; i < ucount; i++) { 1782 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; 1783 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; 1784 clocks->data[i].latency_in_us = 1785 data->mclk_latency_table.entries[i].latency = 1786 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); 1787 } 1788 1789 clocks->num_levels = data->mclk_latency_table.count = ucount; 1790 1791 return 0; 1792 } 1793 1794 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, 1795 struct pp_clock_levels_with_latency *clocks) 1796 { 1797 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1798 uint32_t ucount; 1799 int i; 1800 struct vega12_single_dpm_table *dpm_table; 1801 1802 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) 1803 return -1; 1804 1805 1806 dpm_table = &(data->dpm_table.dcef_table); 1807 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1808 MAX_NUM_CLOCKS : dpm_table->count; 1809 1810 for (i = 0; i < ucount; i++) { 1811 clocks->data[i].clocks_in_khz = 1812 dpm_table->dpm_levels[i].value * 1000; 1813 1814 clocks->data[i].latency_in_us = 0; 1815 } 1816 1817 clocks->num_levels = ucount; 1818 1819 return 0; 1820 } 1821 1822 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, 1823 struct pp_clock_levels_with_latency *clocks) 1824 { 1825 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1826 uint32_t ucount; 1827 int i; 1828 struct vega12_single_dpm_table *dpm_table; 1829 1830 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) 1831 return -1; 1832 1833 1834 dpm_table = &(data->dpm_table.soc_table); 1835 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1836 MAX_NUM_CLOCKS : dpm_table->count; 1837 1838 for (i = 0; i < ucount; i++) { 1839 clocks->data[i].clocks_in_khz = 1840 dpm_table->dpm_levels[i].value * 1000; 1841 1842 clocks->data[i].latency_in_us = 0; 1843 } 1844 1845 clocks->num_levels = ucount; 1846 1847 return 0; 1848 1849 } 1850 1851 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 1852 enum amd_pp_clock_type type, 1853 struct pp_clock_levels_with_latency *clocks) 1854 { 1855 int ret; 1856 1857 switch (type) { 1858 case amd_pp_sys_clock: 1859 ret = vega12_get_sclks(hwmgr, clocks); 1860 break; 1861 case amd_pp_mem_clock: 1862 ret = vega12_get_memclocks(hwmgr, clocks); 1863 break; 1864 case amd_pp_dcef_clock: 1865 ret = vega12_get_dcefclocks(hwmgr, clocks); 1866 break; 1867 case amd_pp_soc_clock: 1868 ret = vega12_get_socclocks(hwmgr, clocks); 1869 break; 1870 default: 1871 return -EINVAL; 1872 } 1873 1874 return ret; 1875 } 1876 1877 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 1878 enum amd_pp_clock_type type, 1879 struct pp_clock_levels_with_voltage *clocks) 1880 { 1881 clocks->num_levels = 0; 1882 1883 return 0; 1884 } 1885 1886 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 1887 void *clock_ranges) 1888 { 1889 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1890 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 1891 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 1892 1893 if (!data->registry_data.disable_water_mark && 1894 data->smu_features[GNLD_DPM_DCEFCLK].supported && 1895 data->smu_features[GNLD_DPM_SOCCLK].supported) { 1896 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 1897 data->water_marks_bitmap |= WaterMarksExist; 1898 data->water_marks_bitmap &= ~WaterMarksLoaded; 1899 } 1900 1901 return 0; 1902 } 1903 1904 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 1905 enum pp_clock_type type, uint32_t mask) 1906 { 1907 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1908 uint32_t soft_min_level, soft_max_level, hard_min_level; 1909 int ret = 0; 1910 1911 switch (type) { 1912 case PP_SCLK: 1913 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1914 soft_max_level = mask ? (fls(mask) - 1) : 0; 1915 1916 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1917 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 1918 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1919 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 1920 1921 ret = vega12_upload_dpm_min_level(hwmgr); 1922 PP_ASSERT_WITH_CODE(!ret, 1923 "Failed to upload boot level to lowest!", 1924 return ret); 1925 1926 ret = vega12_upload_dpm_max_level(hwmgr); 1927 PP_ASSERT_WITH_CODE(!ret, 1928 "Failed to upload dpm max level to highest!", 1929 return ret); 1930 break; 1931 1932 case PP_MCLK: 1933 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1934 soft_max_level = mask ? (fls(mask) - 1) : 0; 1935 1936 data->dpm_table.mem_table.dpm_state.soft_min_level = 1937 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 1938 data->dpm_table.mem_table.dpm_state.soft_max_level = 1939 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 1940 1941 ret = vega12_upload_dpm_min_level(hwmgr); 1942 PP_ASSERT_WITH_CODE(!ret, 1943 "Failed to upload boot level to lowest!", 1944 return ret); 1945 1946 ret = vega12_upload_dpm_max_level(hwmgr); 1947 PP_ASSERT_WITH_CODE(!ret, 1948 "Failed to upload dpm max level to highest!", 1949 return ret); 1950 1951 break; 1952 1953 case PP_SOCCLK: 1954 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1955 soft_max_level = mask ? (fls(mask) - 1) : 0; 1956 1957 if (soft_max_level >= data->dpm_table.soc_table.count) { 1958 pr_err("Clock level specified %d is over max allowed %d\n", 1959 soft_max_level, 1960 data->dpm_table.soc_table.count - 1); 1961 return -EINVAL; 1962 } 1963 1964 data->dpm_table.soc_table.dpm_state.soft_min_level = 1965 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 1966 data->dpm_table.soc_table.dpm_state.soft_max_level = 1967 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 1968 1969 ret = vega12_upload_dpm_min_level(hwmgr); 1970 PP_ASSERT_WITH_CODE(!ret, 1971 "Failed to upload boot level to lowest!", 1972 return ret); 1973 1974 ret = vega12_upload_dpm_max_level(hwmgr); 1975 PP_ASSERT_WITH_CODE(!ret, 1976 "Failed to upload dpm max level to highest!", 1977 return ret); 1978 1979 break; 1980 1981 case PP_DCEFCLK: 1982 hard_min_level = mask ? (ffs(mask) - 1) : 0; 1983 1984 if (hard_min_level >= data->dpm_table.dcef_table.count) { 1985 pr_err("Clock level specified %d is over max allowed %d\n", 1986 hard_min_level, 1987 data->dpm_table.dcef_table.count - 1); 1988 return -EINVAL; 1989 } 1990 1991 data->dpm_table.dcef_table.dpm_state.hard_min_level = 1992 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; 1993 1994 ret = vega12_upload_dpm_min_level(hwmgr); 1995 PP_ASSERT_WITH_CODE(!ret, 1996 "Failed to upload boot level to lowest!", 1997 return ret); 1998 1999 //TODO: Setting DCEFCLK max dpm level is not supported 2000 2001 break; 2002 2003 case PP_PCIE: 2004 break; 2005 2006 default: 2007 break; 2008 } 2009 2010 return 0; 2011 } 2012 2013 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 2014 { 2015 static const char *ppfeature_name[] = { 2016 "DPM_PREFETCHER", 2017 "GFXCLK_DPM", 2018 "UCLK_DPM", 2019 "SOCCLK_DPM", 2020 "UVD_DPM", 2021 "VCE_DPM", 2022 "ULV", 2023 "MP0CLK_DPM", 2024 "LINK_DPM", 2025 "DCEFCLK_DPM", 2026 "GFXCLK_DS", 2027 "SOCCLK_DS", 2028 "LCLK_DS", 2029 "PPT", 2030 "TDC", 2031 "THERMAL", 2032 "GFX_PER_CU_CG", 2033 "RM", 2034 "DCEFCLK_DS", 2035 "ACDC", 2036 "VR0HOT", 2037 "VR1HOT", 2038 "FW_CTF", 2039 "LED_DISPLAY", 2040 "FAN_CONTROL", 2041 "DIDT", 2042 "GFXOFF", 2043 "CG", 2044 "ACG"}; 2045 static const char *output_title[] = { 2046 "FEATURES", 2047 "BITMASK", 2048 "ENABLEMENT"}; 2049 uint64_t features_enabled; 2050 int i; 2051 int ret = 0; 2052 int size = 0; 2053 2054 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2055 PP_ASSERT_WITH_CODE(!ret, 2056 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 2057 return ret); 2058 2059 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); 2060 size += sprintf(buf + size, "%-19s %-22s %s\n", 2061 output_title[0], 2062 output_title[1], 2063 output_title[2]); 2064 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 2065 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", 2066 ppfeature_name[i], 2067 1ULL << i, 2068 (features_enabled & (1ULL << i)) ? "Y" : "N"); 2069 } 2070 2071 return size; 2072 } 2073 2074 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 2075 { 2076 uint64_t features_enabled; 2077 uint64_t features_to_enable; 2078 uint64_t features_to_disable; 2079 int ret = 0; 2080 2081 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 2082 return -EINVAL; 2083 2084 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2085 if (ret) 2086 return ret; 2087 2088 features_to_disable = 2089 features_enabled & ~new_ppfeature_masks; 2090 features_to_enable = 2091 ~features_enabled & new_ppfeature_masks; 2092 2093 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 2094 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 2095 2096 if (features_to_disable) { 2097 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable); 2098 if (ret) 2099 return ret; 2100 } 2101 2102 if (features_to_enable) { 2103 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable); 2104 if (ret) 2105 return ret; 2106 } 2107 2108 return 0; 2109 } 2110 2111 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 2112 { 2113 struct amdgpu_device *adev = hwmgr->adev; 2114 2115 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2116 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2117 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2118 } 2119 2120 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) 2121 { 2122 uint32_t width_level; 2123 2124 width_level = vega12_get_current_pcie_link_width_level(hwmgr); 2125 if (width_level > LINK_WIDTH_MAX) 2126 width_level = 0; 2127 2128 return link_width[width_level]; 2129 } 2130 2131 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 2132 { 2133 struct amdgpu_device *adev = hwmgr->adev; 2134 2135 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2136 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2137 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2138 } 2139 2140 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) 2141 { 2142 uint32_t speed_level; 2143 2144 speed_level = vega12_get_current_pcie_link_speed_level(hwmgr); 2145 if (speed_level > LINK_SPEED_MAX) 2146 speed_level = 0; 2147 2148 return link_speed[speed_level]; 2149 } 2150 2151 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 2152 enum pp_clock_type type, char *buf) 2153 { 2154 int i, now, size = 0; 2155 struct pp_clock_levels_with_latency clocks; 2156 2157 switch (type) { 2158 case PP_SCLK: 2159 PP_ASSERT_WITH_CODE( 2160 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0, 2161 "Attempt to get current gfx clk Failed!", 2162 return -1); 2163 2164 PP_ASSERT_WITH_CODE( 2165 vega12_get_sclks(hwmgr, &clocks) == 0, 2166 "Attempt to get gfx clk levels Failed!", 2167 return -1); 2168 for (i = 0; i < clocks.num_levels; i++) 2169 size += sprintf(buf + size, "%d: %uMhz %s\n", 2170 i, clocks.data[i].clocks_in_khz / 1000, 2171 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2172 break; 2173 2174 case PP_MCLK: 2175 PP_ASSERT_WITH_CODE( 2176 vega12_get_current_mclk_freq(hwmgr, &now) == 0, 2177 "Attempt to get current mclk freq Failed!", 2178 return -1); 2179 2180 PP_ASSERT_WITH_CODE( 2181 vega12_get_memclocks(hwmgr, &clocks) == 0, 2182 "Attempt to get memory clk levels Failed!", 2183 return -1); 2184 for (i = 0; i < clocks.num_levels; i++) 2185 size += sprintf(buf + size, "%d: %uMhz %s\n", 2186 i, clocks.data[i].clocks_in_khz / 1000, 2187 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2188 break; 2189 2190 case PP_SOCCLK: 2191 PP_ASSERT_WITH_CODE( 2192 smum_send_msg_to_smc_with_parameter(hwmgr, 2193 PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16), 2194 &now) == 0, 2195 "Attempt to get Current SOCCLK Frequency Failed!", 2196 return -EINVAL); 2197 2198 PP_ASSERT_WITH_CODE( 2199 vega12_get_socclocks(hwmgr, &clocks) == 0, 2200 "Attempt to get soc clk levels Failed!", 2201 return -1); 2202 for (i = 0; i < clocks.num_levels; i++) 2203 size += sprintf(buf + size, "%d: %uMhz %s\n", 2204 i, clocks.data[i].clocks_in_khz / 1000, 2205 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2206 break; 2207 2208 case PP_DCEFCLK: 2209 PP_ASSERT_WITH_CODE( 2210 smum_send_msg_to_smc_with_parameter(hwmgr, 2211 PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16), 2212 &now) == 0, 2213 "Attempt to get Current DCEFCLK Frequency Failed!", 2214 return -EINVAL); 2215 2216 PP_ASSERT_WITH_CODE( 2217 vega12_get_dcefclocks(hwmgr, &clocks) == 0, 2218 "Attempt to get dcef clk levels Failed!", 2219 return -1); 2220 for (i = 0; i < clocks.num_levels; i++) 2221 size += sprintf(buf + size, "%d: %uMhz %s\n", 2222 i, clocks.data[i].clocks_in_khz / 1000, 2223 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2224 break; 2225 2226 case PP_PCIE: 2227 break; 2228 2229 default: 2230 break; 2231 } 2232 return size; 2233 } 2234 2235 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 2236 { 2237 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2238 struct vega12_single_dpm_table *dpm_table; 2239 bool vblank_too_short = false; 2240 bool disable_mclk_switching; 2241 uint32_t i, latency; 2242 2243 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 2244 !hwmgr->display_config->multi_monitor_in_sync) || 2245 vblank_too_short; 2246 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 2247 2248 /* gfxclk */ 2249 dpm_table = &(data->dpm_table.gfx_table); 2250 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2251 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2252 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2253 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2254 2255 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2256 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { 2257 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2258 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2259 } 2260 2261 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2262 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2263 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2264 } 2265 2266 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2267 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2268 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2269 } 2270 } 2271 2272 /* memclk */ 2273 dpm_table = &(data->dpm_table.mem_table); 2274 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2275 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2276 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2277 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2278 2279 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2280 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { 2281 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2282 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2283 } 2284 2285 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 2286 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2287 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2288 } 2289 2290 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2291 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2292 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2293 } 2294 } 2295 2296 /* honour DAL's UCLK Hardmin */ 2297 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) 2298 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; 2299 2300 /* Hardmin is dependent on displayconfig */ 2301 if (disable_mclk_switching) { 2302 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2303 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { 2304 if (data->mclk_latency_table.entries[i].latency <= latency) { 2305 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { 2306 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; 2307 break; 2308 } 2309 } 2310 } 2311 } 2312 2313 if (hwmgr->display_config->nb_pstate_switch_disable) 2314 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2315 2316 /* vclk */ 2317 dpm_table = &(data->dpm_table.vclk_table); 2318 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2319 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2320 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2321 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2322 2323 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2324 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2325 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2326 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2327 } 2328 2329 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2330 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2331 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2332 } 2333 } 2334 2335 /* dclk */ 2336 dpm_table = &(data->dpm_table.dclk_table); 2337 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2338 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2339 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2340 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2341 2342 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2343 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2344 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2345 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2346 } 2347 2348 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2349 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2350 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2351 } 2352 } 2353 2354 /* socclk */ 2355 dpm_table = &(data->dpm_table.soc_table); 2356 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2357 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2358 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2359 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2360 2361 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2362 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { 2363 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2364 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2365 } 2366 2367 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2368 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2369 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2370 } 2371 } 2372 2373 /* eclk */ 2374 dpm_table = &(data->dpm_table.eclk_table); 2375 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2376 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2377 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2378 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2379 2380 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2381 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { 2382 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2383 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2384 } 2385 2386 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2387 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2388 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2389 } 2390 } 2391 2392 return 0; 2393 } 2394 2395 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, 2396 struct vega12_single_dpm_table *dpm_table) 2397 { 2398 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2399 int ret = 0; 2400 2401 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 2402 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 2403 "[SetUclkToHightestDpmLevel] Dpm table has no entry!", 2404 return -EINVAL); 2405 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, 2406 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", 2407 return -EINVAL); 2408 2409 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2410 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2411 PPSMC_MSG_SetHardMinByFreq, 2412 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, 2413 NULL)), 2414 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", 2415 return ret); 2416 } 2417 2418 return ret; 2419 } 2420 2421 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2422 { 2423 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2424 int ret = 0; 2425 2426 smum_send_msg_to_smc_with_parameter(hwmgr, 2427 PPSMC_MSG_NumOfDisplays, 0, 2428 NULL); 2429 2430 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr, 2431 &data->dpm_table.mem_table); 2432 2433 return ret; 2434 } 2435 2436 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2437 { 2438 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2439 int result = 0; 2440 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 2441 2442 if ((data->water_marks_bitmap & WaterMarksExist) && 2443 !(data->water_marks_bitmap & WaterMarksLoaded)) { 2444 result = smum_smc_table_manager(hwmgr, 2445 (uint8_t *)wm_table, TABLE_WATERMARKS, false); 2446 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 2447 data->water_marks_bitmap |= WaterMarksLoaded; 2448 } 2449 2450 if ((data->water_marks_bitmap & WaterMarksExist) && 2451 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2452 data->smu_features[GNLD_DPM_SOCCLK].supported) 2453 smum_send_msg_to_smc_with_parameter(hwmgr, 2454 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 2455 NULL); 2456 2457 return result; 2458 } 2459 2460 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 2461 { 2462 struct vega12_hwmgr *data = 2463 (struct vega12_hwmgr *)(hwmgr->backend); 2464 2465 if (data->smu_features[GNLD_DPM_UVD].supported) { 2466 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 2467 enable, 2468 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 2469 "Attempt to Enable/Disable DPM UVD Failed!", 2470 return -1); 2471 data->smu_features[GNLD_DPM_UVD].enabled = enable; 2472 } 2473 2474 return 0; 2475 } 2476 2477 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 2478 { 2479 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2480 2481 if (data->vce_power_gated == bgate) 2482 return; 2483 2484 data->vce_power_gated = bgate; 2485 vega12_enable_disable_vce_dpm(hwmgr, !bgate); 2486 } 2487 2488 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 2489 { 2490 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2491 2492 if (data->uvd_power_gated == bgate) 2493 return; 2494 2495 data->uvd_power_gated = bgate; 2496 vega12_enable_disable_uvd_dpm(hwmgr, !bgate); 2497 } 2498 2499 static bool 2500 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 2501 { 2502 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2503 bool is_update_required = false; 2504 2505 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 2506 is_update_required = true; 2507 2508 if (data->registry_data.gfx_clk_deep_sleep_support) { 2509 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 2510 is_update_required = true; 2511 } 2512 2513 return is_update_required; 2514 } 2515 2516 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 2517 { 2518 int tmp_result, result = 0; 2519 2520 tmp_result = vega12_disable_all_smu_features(hwmgr); 2521 PP_ASSERT_WITH_CODE((tmp_result == 0), 2522 "Failed to disable all smu features!", result = tmp_result); 2523 2524 return result; 2525 } 2526 2527 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) 2528 { 2529 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2530 int result; 2531 2532 result = vega12_disable_dpm_tasks(hwmgr); 2533 PP_ASSERT_WITH_CODE((0 == result), 2534 "[disable_dpm_tasks] Failed to disable DPM!", 2535 ); 2536 data->water_marks_bitmap &= ~(WaterMarksLoaded); 2537 2538 return result; 2539 } 2540 2541 #if 0 2542 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr, 2543 uint32_t *sclk_idx, uint32_t *mclk_idx, 2544 uint32_t min_sclk, uint32_t min_mclk) 2545 { 2546 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2547 struct vega12_dpm_table *dpm_table = &(data->dpm_table); 2548 uint32_t i; 2549 2550 for (i = 0; i < dpm_table->gfx_table.count; i++) { 2551 if (dpm_table->gfx_table.dpm_levels[i].enabled && 2552 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { 2553 *sclk_idx = i; 2554 break; 2555 } 2556 } 2557 2558 for (i = 0; i < dpm_table->mem_table.count; i++) { 2559 if (dpm_table->mem_table.dpm_levels[i].enabled && 2560 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { 2561 *mclk_idx = i; 2562 break; 2563 } 2564 } 2565 } 2566 #endif 2567 2568 #if 0 2569 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr, 2570 struct amd_pp_profile *request) 2571 { 2572 return 0; 2573 } 2574 2575 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) 2576 { 2577 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2578 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 2579 struct vega12_single_dpm_table *golden_sclk_table = 2580 &(data->golden_dpm_table.gfx_table); 2581 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 2582 int golden_value = golden_sclk_table->dpm_levels 2583 [golden_sclk_table->count - 1].value; 2584 2585 value -= golden_value; 2586 value = DIV_ROUND_UP(value * 100, golden_value); 2587 2588 return value; 2589 } 2590 2591 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2592 { 2593 return 0; 2594 } 2595 2596 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) 2597 { 2598 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2599 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 2600 struct vega12_single_dpm_table *golden_mclk_table = 2601 &(data->golden_dpm_table.mem_table); 2602 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 2603 int golden_value = golden_mclk_table->dpm_levels 2604 [golden_mclk_table->count - 1].value; 2605 2606 value -= golden_value; 2607 value = DIV_ROUND_UP(value * 100, golden_value); 2608 2609 return value; 2610 } 2611 2612 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2613 { 2614 return 0; 2615 } 2616 #endif 2617 2618 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 2619 uint32_t virtual_addr_low, 2620 uint32_t virtual_addr_hi, 2621 uint32_t mc_addr_low, 2622 uint32_t mc_addr_hi, 2623 uint32_t size) 2624 { 2625 smum_send_msg_to_smc_with_parameter(hwmgr, 2626 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 2627 virtual_addr_hi, 2628 NULL); 2629 smum_send_msg_to_smc_with_parameter(hwmgr, 2630 PPSMC_MSG_SetSystemVirtualDramAddrLow, 2631 virtual_addr_low, 2632 NULL); 2633 smum_send_msg_to_smc_with_parameter(hwmgr, 2634 PPSMC_MSG_DramLogSetDramAddrHigh, 2635 mc_addr_hi, 2636 NULL); 2637 2638 smum_send_msg_to_smc_with_parameter(hwmgr, 2639 PPSMC_MSG_DramLogSetDramAddrLow, 2640 mc_addr_low, 2641 NULL); 2642 2643 smum_send_msg_to_smc_with_parameter(hwmgr, 2644 PPSMC_MSG_DramLogSetDramSize, 2645 size, 2646 NULL); 2647 return 0; 2648 } 2649 2650 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 2651 struct PP_TemperatureRange *thermal_data) 2652 { 2653 struct vega12_hwmgr *data = 2654 (struct vega12_hwmgr *)(hwmgr->backend); 2655 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2656 2657 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 2658 2659 thermal_data->max = pp_table->TedgeLimit * 2660 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2661 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 2662 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2663 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 2664 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2665 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2666 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2667 thermal_data->mem_crit_max = pp_table->ThbmLimit * 2668 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2669 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 2670 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2671 2672 return 0; 2673 } 2674 2675 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) 2676 { 2677 struct vega12_hwmgr *data = 2678 (struct vega12_hwmgr *)(hwmgr->backend); 2679 int ret = 0; 2680 2681 if (data->gfxoff_controlled_by_driver) 2682 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL); 2683 2684 return ret; 2685 } 2686 2687 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) 2688 { 2689 struct vega12_hwmgr *data = 2690 (struct vega12_hwmgr *)(hwmgr->backend); 2691 int ret = 0; 2692 2693 if (data->gfxoff_controlled_by_driver) 2694 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL); 2695 2696 return ret; 2697 } 2698 2699 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) 2700 { 2701 if (enable) 2702 return vega12_enable_gfx_off(hwmgr); 2703 else 2704 return vega12_disable_gfx_off(hwmgr); 2705 } 2706 2707 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 2708 PHM_PerformanceLevelDesignation designation, uint32_t index, 2709 PHM_PerformanceLevel *level) 2710 { 2711 return 0; 2712 } 2713 2714 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr, 2715 enum pp_mp1_state mp1_state) 2716 { 2717 uint16_t msg; 2718 int ret; 2719 2720 switch (mp1_state) { 2721 case PP_MP1_STATE_UNLOAD: 2722 msg = PPSMC_MSG_PrepareMp1ForUnload; 2723 break; 2724 case PP_MP1_STATE_SHUTDOWN: 2725 case PP_MP1_STATE_RESET: 2726 case PP_MP1_STATE_NONE: 2727 default: 2728 return 0; 2729 } 2730 2731 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 2732 "[PrepareMp1] Failed!", 2733 return ret); 2734 2735 return 0; 2736 } 2737 2738 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) 2739 { 2740 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); 2741 2742 gpu_metrics->common_header.structure_size = 2743 sizeof(struct gpu_metrics_v1_0); 2744 gpu_metrics->common_header.format_revision = 1; 2745 gpu_metrics->common_header.content_revision = 0; 2746 2747 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2748 } 2749 2750 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr, 2751 void **table) 2752 { 2753 struct vega12_hwmgr *data = 2754 (struct vega12_hwmgr *)(hwmgr->backend); 2755 struct gpu_metrics_v1_0 *gpu_metrics = 2756 &data->gpu_metrics_table; 2757 SmuMetrics_t metrics; 2758 uint32_t fan_speed_rpm; 2759 int ret; 2760 2761 ret = vega12_get_metrics_table(hwmgr, &metrics, true); 2762 if (ret) 2763 return ret; 2764 2765 vega12_init_gpu_metrics_v1_0(gpu_metrics); 2766 2767 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2768 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2769 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2770 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2771 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2772 2773 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2774 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2775 2776 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2777 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2778 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2779 2780 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2781 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2782 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2783 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2784 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2785 2786 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2787 2788 vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); 2789 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; 2790 2791 gpu_metrics->pcie_link_width = 2792 vega12_get_current_pcie_link_width(hwmgr); 2793 gpu_metrics->pcie_link_speed = 2794 vega12_get_current_pcie_link_speed(hwmgr); 2795 2796 *table = (void *)gpu_metrics; 2797 2798 return sizeof(struct gpu_metrics_v1_0); 2799 } 2800 2801 static const struct pp_hwmgr_func vega12_hwmgr_funcs = { 2802 .backend_init = vega12_hwmgr_backend_init, 2803 .backend_fini = vega12_hwmgr_backend_fini, 2804 .asic_setup = vega12_setup_asic_task, 2805 .dynamic_state_management_enable = vega12_enable_dpm_tasks, 2806 .dynamic_state_management_disable = vega12_disable_dpm_tasks, 2807 .patch_boot_state = vega12_patch_boot_state, 2808 .get_sclk = vega12_dpm_get_sclk, 2809 .get_mclk = vega12_dpm_get_mclk, 2810 .notify_smc_display_config_after_ps_adjustment = 2811 vega12_notify_smc_display_config_after_ps_adjustment, 2812 .force_dpm_level = vega12_dpm_force_dpm_level, 2813 .stop_thermal_controller = vega12_thermal_stop_thermal_controller, 2814 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info, 2815 .reset_fan_speed_to_default = 2816 vega12_fan_ctrl_reset_fan_speed_to_default, 2817 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm, 2818 .set_fan_control_mode = vega12_set_fan_control_mode, 2819 .get_fan_control_mode = vega12_get_fan_control_mode, 2820 .read_sensor = vega12_read_sensor, 2821 .get_dal_power_level = vega12_get_dal_power_level, 2822 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency, 2823 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage, 2824 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges, 2825 .display_clock_voltage_request = vega12_display_clock_voltage_request, 2826 .force_clock_level = vega12_force_clock_level, 2827 .print_clock_levels = vega12_print_clock_levels, 2828 .apply_clocks_adjust_rules = 2829 vega12_apply_clocks_adjust_rules, 2830 .pre_display_config_changed = 2831 vega12_pre_display_configuration_changed_task, 2832 .display_config_changed = vega12_display_configuration_changed_task, 2833 .powergate_uvd = vega12_power_gate_uvd, 2834 .powergate_vce = vega12_power_gate_vce, 2835 .check_smc_update_required_for_display_configuration = 2836 vega12_check_smc_update_required_for_display_configuration, 2837 .power_off_asic = vega12_power_off_asic, 2838 .disable_smc_firmware_ctf = vega12_thermal_disable_alert, 2839 #if 0 2840 .set_power_profile_state = vega12_set_power_profile_state, 2841 .get_sclk_od = vega12_get_sclk_od, 2842 .set_sclk_od = vega12_set_sclk_od, 2843 .get_mclk_od = vega12_get_mclk_od, 2844 .set_mclk_od = vega12_set_mclk_od, 2845 #endif 2846 .notify_cac_buffer_info = vega12_notify_cac_buffer_info, 2847 .get_thermal_temperature_range = vega12_get_thermal_temperature_range, 2848 .register_irq_handlers = smu9_register_irq_handlers, 2849 .start_thermal_controller = vega12_start_thermal_controller, 2850 .powergate_gfx = vega12_gfx_off_control, 2851 .get_performance_level = vega12_get_performance_level, 2852 .get_asic_baco_capability = smu9_baco_get_capability, 2853 .get_asic_baco_state = smu9_baco_get_state, 2854 .set_asic_baco_state = vega12_baco_set_state, 2855 .get_ppfeature_status = vega12_get_ppfeature_status, 2856 .set_ppfeature_status = vega12_set_ppfeature_status, 2857 .set_mp1_state = vega12_set_mp1_state, 2858 .get_gpu_metrics = vega12_get_gpu_metrics, 2859 }; 2860 2861 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) 2862 { 2863 hwmgr->hwmgr_func = &vega12_hwmgr_funcs; 2864 hwmgr->pptable_func = &vega12_pptable_funcs; 2865 2866 return 0; 2867 } 2868