1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/fb.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "vega12_smumgr.h" 32 #include "hardwaremanager.h" 33 #include "ppatomfwctrl.h" 34 #include "atomfirmware.h" 35 #include "cgs_common.h" 36 #include "vega12_inc.h" 37 #include "pppcielanes.h" 38 #include "vega12_hwmgr.h" 39 #include "vega12_processpptables.h" 40 #include "vega12_pptable.h" 41 #include "vega12_thermal.h" 42 #include "vega12_ppsmc.h" 43 #include "pp_debug.h" 44 #include "amd_pcie_helpers.h" 45 #include "ppinterrupt.h" 46 #include "pp_overdriver.h" 47 #include "pp_thermal.h" 48 #include "vega12_baco.h" 49 50 #define smnPCIE_LC_SPEED_CNTL 0x11140290 51 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 52 53 #define LINK_WIDTH_MAX 6 54 #define LINK_SPEED_MAX 3 55 static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 56 static int link_speed[] = {25, 50, 80, 160}; 57 58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 59 enum pp_clock_type type, uint32_t mask); 60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 61 uint32_t *clock, 62 PPCLK_e clock_select, 63 bool max); 64 65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) 66 { 67 struct vega12_hwmgr *data = 68 (struct vega12_hwmgr *)(hwmgr->backend); 69 70 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT; 71 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT; 72 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT; 73 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT; 74 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT; 75 76 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT; 77 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 78 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 79 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 80 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 81 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 82 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 83 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 84 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 85 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 86 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 87 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 88 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 89 90 data->registry_data.disallowed_features = 0x0; 91 data->registry_data.od_state_in_dc_support = 0; 92 data->registry_data.thermal_support = 1; 93 data->registry_data.skip_baco_hardware = 0; 94 95 data->registry_data.log_avfs_param = 0; 96 data->registry_data.sclk_throttle_low_notification = 1; 97 data->registry_data.force_dpm_high = 0; 98 data->registry_data.stable_pstate_sclk_dpm_percentage = 75; 99 100 data->registry_data.didt_support = 0; 101 if (data->registry_data.didt_support) { 102 data->registry_data.didt_mode = 6; 103 data->registry_data.sq_ramping_support = 1; 104 data->registry_data.db_ramping_support = 0; 105 data->registry_data.td_ramping_support = 0; 106 data->registry_data.tcp_ramping_support = 0; 107 data->registry_data.dbr_ramping_support = 0; 108 data->registry_data.edc_didt_support = 1; 109 data->registry_data.gc_didt_support = 0; 110 data->registry_data.psm_didt_support = 0; 111 } 112 113 data->registry_data.pcie_lane_override = 0xff; 114 data->registry_data.pcie_speed_override = 0xff; 115 data->registry_data.pcie_clock_override = 0xffffffff; 116 data->registry_data.regulator_hot_gpio_support = 1; 117 data->registry_data.ac_dc_switch_gpio_support = 0; 118 data->registry_data.quick_transition_support = 0; 119 data->registry_data.zrpm_start_temp = 0xffff; 120 data->registry_data.zrpm_stop_temp = 0xffff; 121 data->registry_data.odn_feature_enable = 1; 122 data->registry_data.disable_water_mark = 0; 123 data->registry_data.disable_pp_tuning = 0; 124 data->registry_data.disable_xlpp_tuning = 0; 125 data->registry_data.disable_workload_policy = 0; 126 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; 127 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; 128 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; 129 data->registry_data.force_workload_policy_mask = 0; 130 data->registry_data.disable_3d_fs_detection = 0; 131 data->registry_data.fps_support = 1; 132 data->registry_data.disable_auto_wattman = 1; 133 data->registry_data.auto_wattman_debug = 0; 134 data->registry_data.auto_wattman_sample_period = 100; 135 data->registry_data.auto_wattman_threshold = 50; 136 } 137 138 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) 139 { 140 struct vega12_hwmgr *data = 141 (struct vega12_hwmgr *)(hwmgr->backend); 142 struct amdgpu_device *adev = hwmgr->adev; 143 144 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE) 145 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 146 PHM_PlatformCaps_ControlVDDCI); 147 148 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 149 PHM_PlatformCaps_TablelessHardwareInterface); 150 151 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 152 PHM_PlatformCaps_EnableSMU7ThermalManagement); 153 154 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) { 155 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 156 PHM_PlatformCaps_UVDPowerGating); 157 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 158 PHM_PlatformCaps_UVDDynamicPowerGating); 159 } 160 161 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 162 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 163 PHM_PlatformCaps_VCEPowerGating); 164 165 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 166 PHM_PlatformCaps_UnTabledHardwareInterface); 167 168 if (data->registry_data.odn_feature_enable) 169 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 170 PHM_PlatformCaps_ODNinACSupport); 171 else { 172 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 173 PHM_PlatformCaps_OD6inACSupport); 174 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 175 PHM_PlatformCaps_OD6PlusinACSupport); 176 } 177 178 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 179 PHM_PlatformCaps_ActivityReporting); 180 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 181 PHM_PlatformCaps_FanSpeedInTableIsRPM); 182 183 if (data->registry_data.od_state_in_dc_support) { 184 if (data->registry_data.odn_feature_enable) 185 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 186 PHM_PlatformCaps_ODNinDCSupport); 187 else { 188 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 189 PHM_PlatformCaps_OD6inDCSupport); 190 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 191 PHM_PlatformCaps_OD6PlusinDCSupport); 192 } 193 } 194 195 if (data->registry_data.thermal_support 196 && data->registry_data.fuzzy_fan_control_support 197 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax) 198 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 199 PHM_PlatformCaps_ODFuzzyFanControlSupport); 200 201 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 202 PHM_PlatformCaps_DynamicPowerManagement); 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_SMC); 205 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 206 PHM_PlatformCaps_ThermalPolicyDelay); 207 208 if (data->registry_data.force_dpm_high) 209 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 210 PHM_PlatformCaps_ExclusiveModeAlwaysHigh); 211 212 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 213 PHM_PlatformCaps_DynamicUVDState); 214 215 if (data->registry_data.sclk_throttle_low_notification) 216 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 217 PHM_PlatformCaps_SclkThrottleLowNotification); 218 219 /* power tune caps */ 220 /* assume disabled */ 221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 222 PHM_PlatformCaps_PowerContainment); 223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 224 PHM_PlatformCaps_DiDtSupport); 225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 226 PHM_PlatformCaps_SQRamping); 227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_DBRamping); 229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 230 PHM_PlatformCaps_TDRamping); 231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 232 PHM_PlatformCaps_TCPRamping); 233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_DBRRamping); 235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 236 PHM_PlatformCaps_DiDtEDCEnable); 237 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 238 PHM_PlatformCaps_GCEDC); 239 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 240 PHM_PlatformCaps_PSM); 241 242 if (data->registry_data.didt_support) { 243 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 244 if (data->registry_data.sq_ramping_support) 245 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 246 if (data->registry_data.db_ramping_support) 247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 248 if (data->registry_data.td_ramping_support) 249 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 250 if (data->registry_data.tcp_ramping_support) 251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 252 if (data->registry_data.dbr_ramping_support) 253 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 254 if (data->registry_data.edc_didt_support) 255 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 256 if (data->registry_data.gc_didt_support) 257 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 258 if (data->registry_data.psm_didt_support) 259 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 260 } 261 262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 263 PHM_PlatformCaps_RegulatorHot); 264 265 if (data->registry_data.ac_dc_switch_gpio_support) { 266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 267 PHM_PlatformCaps_AutomaticDCTransition); 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 270 } 271 272 if (data->registry_data.quick_transition_support) { 273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 274 PHM_PlatformCaps_AutomaticDCTransition); 275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 277 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 278 PHM_PlatformCaps_Falcon_QuickTransition); 279 } 280 281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) { 282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 283 PHM_PlatformCaps_LowestUclkReservedForUlv); 284 if (data->lowest_uclk_reserved_for_ulv == 1) 285 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 286 PHM_PlatformCaps_LowestUclkReservedForUlv); 287 } 288 289 if (data->registry_data.custom_fan_support) 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_CustomFanControlSupport); 292 293 return 0; 294 } 295 296 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) 297 { 298 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 299 struct amdgpu_device *adev = hwmgr->adev; 300 uint32_t top32, bottom32; 301 int i; 302 303 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 304 FEATURE_DPM_PREFETCHER_BIT; 305 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 306 FEATURE_DPM_GFXCLK_BIT; 307 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 308 FEATURE_DPM_UCLK_BIT; 309 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 310 FEATURE_DPM_SOCCLK_BIT; 311 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 312 FEATURE_DPM_UVD_BIT; 313 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 314 FEATURE_DPM_VCE_BIT; 315 data->smu_features[GNLD_ULV].smu_feature_id = 316 FEATURE_ULV_BIT; 317 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 318 FEATURE_DPM_MP0CLK_BIT; 319 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 320 FEATURE_DPM_LINK_BIT; 321 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 322 FEATURE_DPM_DCEFCLK_BIT; 323 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 324 FEATURE_DS_GFXCLK_BIT; 325 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 326 FEATURE_DS_SOCCLK_BIT; 327 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 328 FEATURE_DS_LCLK_BIT; 329 data->smu_features[GNLD_PPT].smu_feature_id = 330 FEATURE_PPT_BIT; 331 data->smu_features[GNLD_TDC].smu_feature_id = 332 FEATURE_TDC_BIT; 333 data->smu_features[GNLD_THERMAL].smu_feature_id = 334 FEATURE_THERMAL_BIT; 335 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 336 FEATURE_GFX_PER_CU_CG_BIT; 337 data->smu_features[GNLD_RM].smu_feature_id = 338 FEATURE_RM_BIT; 339 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 340 FEATURE_DS_DCEFCLK_BIT; 341 data->smu_features[GNLD_ACDC].smu_feature_id = 342 FEATURE_ACDC_BIT; 343 data->smu_features[GNLD_VR0HOT].smu_feature_id = 344 FEATURE_VR0HOT_BIT; 345 data->smu_features[GNLD_VR1HOT].smu_feature_id = 346 FEATURE_VR1HOT_BIT; 347 data->smu_features[GNLD_FW_CTF].smu_feature_id = 348 FEATURE_FW_CTF_BIT; 349 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 350 FEATURE_LED_DISPLAY_BIT; 351 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 352 FEATURE_FAN_CONTROL_BIT; 353 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 354 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; 355 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; 356 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 357 358 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 359 data->smu_features[i].smu_feature_bitmap = 360 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); 361 data->smu_features[i].allowed = 362 ((data->registry_data.disallowed_features >> i) & 1) ? 363 false : true; 364 } 365 366 /* Get the SN to turn into a Unique ID */ 367 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 368 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 369 370 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 371 } 372 373 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 374 { 375 return 0; 376 } 377 378 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 379 { 380 kfree(hwmgr->backend); 381 hwmgr->backend = NULL; 382 383 return 0; 384 } 385 386 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 387 { 388 int result = 0; 389 struct vega12_hwmgr *data; 390 struct amdgpu_device *adev = hwmgr->adev; 391 392 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL); 393 if (data == NULL) 394 return -ENOMEM; 395 396 hwmgr->backend = data; 397 398 vega12_set_default_registry_data(hwmgr); 399 400 data->disable_dpm_mask = 0xff; 401 data->workload_mask = 0xff; 402 403 /* need to set voltage control types before EVV patching */ 404 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE; 405 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; 406 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE; 407 408 data->water_marks_bitmap = 0; 409 data->avfs_exist = false; 410 411 vega12_set_features_platform_caps(hwmgr); 412 413 vega12_init_dpm_defaults(hwmgr); 414 415 /* Parse pptable data read from VBIOS */ 416 vega12_set_private_data_based_on_pptable(hwmgr); 417 418 data->is_tlu_enabled = false; 419 420 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 421 VEGA12_MAX_HARDWARE_POWERLEVELS; 422 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 423 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 424 425 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 426 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 427 hwmgr->platform_descriptor.clockStep.engineClock = 500; 428 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 429 430 data->total_active_cus = adev->gfx.cu_info.number; 431 /* Setup default Overdrive Fan control settings */ 432 data->odn_fan_table.target_fan_speed = 433 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 434 data->odn_fan_table.target_temperature = 435 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature; 436 data->odn_fan_table.min_performance_clock = 437 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit; 438 data->odn_fan_table.min_fan_limit = 439 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * 440 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 441 442 if (hwmgr->feature_mask & PP_GFXOFF_MASK) 443 data->gfxoff_controlled_by_driver = true; 444 else 445 data->gfxoff_controlled_by_driver = false; 446 447 return result; 448 } 449 450 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) 451 { 452 struct vega12_hwmgr *data = 453 (struct vega12_hwmgr *)(hwmgr->backend); 454 455 data->low_sclk_interrupt_threshold = 0; 456 457 return 0; 458 } 459 460 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) 461 { 462 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), 463 "Failed to init sclk threshold!", 464 return -EINVAL); 465 466 return 0; 467 } 468 469 /* 470 * @fn vega12_init_dpm_state 471 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 472 * 473 * @param dpm_state - the address of the DPM Table to initiailize. 474 * @return None. 475 */ 476 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) 477 { 478 dpm_state->soft_min_level = 0x0; 479 dpm_state->soft_max_level = 0xffff; 480 dpm_state->hard_min_level = 0x0; 481 dpm_state->hard_max_level = 0xffff; 482 } 483 484 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr) 485 { 486 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 487 struct vega12_hwmgr *data = 488 (struct vega12_hwmgr *)(hwmgr->backend); 489 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; 490 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 491 int i; 492 int ret; 493 494 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 495 pcie_gen = 3; 496 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 497 pcie_gen = 2; 498 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 499 pcie_gen = 1; 500 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 501 pcie_gen = 0; 502 503 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 504 pcie_width = 6; 505 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 506 pcie_width = 5; 507 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 508 pcie_width = 4; 509 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 510 pcie_width = 3; 511 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 512 pcie_width = 2; 513 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 514 pcie_width = 1; 515 516 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 517 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 518 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 519 */ 520 for (i = 0; i < NUM_LINK_LEVELS; i++) { 521 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : 522 pp_table->PcieGenSpeed[i]; 523 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : 524 pp_table->PcieLaneCount[i]; 525 526 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != 527 pp_table->PcieLaneCount[i]) { 528 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; 529 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 530 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 531 NULL); 532 PP_ASSERT_WITH_CODE(!ret, 533 "[OverridePcieParameters] Attempt to override pcie params failed!", 534 return ret); 535 } 536 537 /* update the pptable */ 538 pp_table->PcieGenSpeed[i] = pcie_gen_arg; 539 pp_table->PcieLaneCount[i] = pcie_width_arg; 540 } 541 542 return 0; 543 } 544 545 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 546 PPCLK_e clk_id, uint32_t *num_of_levels) 547 { 548 int ret = 0; 549 550 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 551 PPSMC_MSG_GetDpmFreqByIndex, 552 (clk_id << 16 | 0xFF), 553 num_of_levels); 554 PP_ASSERT_WITH_CODE(!ret, 555 "[GetNumOfDpmLevel] failed to get dpm levels!", 556 return ret); 557 558 return ret; 559 } 560 561 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 562 PPCLK_e clkID, uint32_t index, uint32_t *clock) 563 { 564 /* 565 *SMU expects the Clock ID to be in the top 16 bits. 566 *Lower 16 bits specify the level 567 */ 568 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 569 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index), 570 clock) == 0, 571 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", 572 return -EINVAL); 573 574 return 0; 575 } 576 577 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, 578 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) 579 { 580 int ret = 0; 581 uint32_t i, num_of_levels, clk; 582 583 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); 584 PP_ASSERT_WITH_CODE(!ret, 585 "[SetupSingleDpmTable] failed to get clk levels!", 586 return ret); 587 588 dpm_table->count = num_of_levels; 589 590 for (i = 0; i < num_of_levels; i++) { 591 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); 592 PP_ASSERT_WITH_CODE(!ret, 593 "[SetupSingleDpmTable] failed to get clk of specific level!", 594 return ret); 595 dpm_table->dpm_levels[i].value = clk; 596 dpm_table->dpm_levels[i].enabled = true; 597 } 598 599 return ret; 600 } 601 602 /* 603 * This function is to initialize all DPM state tables 604 * for SMU based on the dependency table. 605 * Dynamic state patching function will then trim these 606 * state tables to the allowed range based 607 * on the power policy or external client requests, 608 * such as UVD request, etc. 609 */ 610 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 611 { 612 613 struct vega12_hwmgr *data = 614 (struct vega12_hwmgr *)(hwmgr->backend); 615 struct vega12_single_dpm_table *dpm_table; 616 int ret = 0; 617 618 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 619 620 /* socclk */ 621 dpm_table = &(data->dpm_table.soc_table); 622 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 623 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); 624 PP_ASSERT_WITH_CODE(!ret, 625 "[SetupDefaultDpmTable] failed to get socclk dpm levels!", 626 return ret); 627 } else { 628 dpm_table->count = 1; 629 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 630 } 631 vega12_init_dpm_state(&(dpm_table->dpm_state)); 632 633 /* gfxclk */ 634 dpm_table = &(data->dpm_table.gfx_table); 635 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 636 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 637 PP_ASSERT_WITH_CODE(!ret, 638 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", 639 return ret); 640 } else { 641 dpm_table->count = 1; 642 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 643 } 644 vega12_init_dpm_state(&(dpm_table->dpm_state)); 645 646 /* memclk */ 647 dpm_table = &(data->dpm_table.mem_table); 648 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 649 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); 650 PP_ASSERT_WITH_CODE(!ret, 651 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", 652 return ret); 653 } else { 654 dpm_table->count = 1; 655 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 656 } 657 vega12_init_dpm_state(&(dpm_table->dpm_state)); 658 659 /* eclk */ 660 dpm_table = &(data->dpm_table.eclk_table); 661 if (data->smu_features[GNLD_DPM_VCE].enabled) { 662 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); 663 PP_ASSERT_WITH_CODE(!ret, 664 "[SetupDefaultDpmTable] failed to get eclk dpm levels!", 665 return ret); 666 } else { 667 dpm_table->count = 1; 668 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 669 } 670 vega12_init_dpm_state(&(dpm_table->dpm_state)); 671 672 /* vclk */ 673 dpm_table = &(data->dpm_table.vclk_table); 674 if (data->smu_features[GNLD_DPM_UVD].enabled) { 675 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); 676 PP_ASSERT_WITH_CODE(!ret, 677 "[SetupDefaultDpmTable] failed to get vclk dpm levels!", 678 return ret); 679 } else { 680 dpm_table->count = 1; 681 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 682 } 683 vega12_init_dpm_state(&(dpm_table->dpm_state)); 684 685 /* dclk */ 686 dpm_table = &(data->dpm_table.dclk_table); 687 if (data->smu_features[GNLD_DPM_UVD].enabled) { 688 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); 689 PP_ASSERT_WITH_CODE(!ret, 690 "[SetupDefaultDpmTable] failed to get dclk dpm levels!", 691 return ret); 692 } else { 693 dpm_table->count = 1; 694 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 695 } 696 vega12_init_dpm_state(&(dpm_table->dpm_state)); 697 698 /* dcefclk */ 699 dpm_table = &(data->dpm_table.dcef_table); 700 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 701 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); 702 PP_ASSERT_WITH_CODE(!ret, 703 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", 704 return ret); 705 } else { 706 dpm_table->count = 1; 707 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 708 } 709 vega12_init_dpm_state(&(dpm_table->dpm_state)); 710 711 /* pixclk */ 712 dpm_table = &(data->dpm_table.pixel_table); 713 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 714 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); 715 PP_ASSERT_WITH_CODE(!ret, 716 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", 717 return ret); 718 } else 719 dpm_table->count = 0; 720 vega12_init_dpm_state(&(dpm_table->dpm_state)); 721 722 /* dispclk */ 723 dpm_table = &(data->dpm_table.display_table); 724 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 725 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); 726 PP_ASSERT_WITH_CODE(!ret, 727 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", 728 return ret); 729 } else 730 dpm_table->count = 0; 731 vega12_init_dpm_state(&(dpm_table->dpm_state)); 732 733 /* phyclk */ 734 dpm_table = &(data->dpm_table.phy_table); 735 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 736 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); 737 PP_ASSERT_WITH_CODE(!ret, 738 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", 739 return ret); 740 } else 741 dpm_table->count = 0; 742 vega12_init_dpm_state(&(dpm_table->dpm_state)); 743 744 /* save a copy of the default DPM table */ 745 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 746 sizeof(struct vega12_dpm_table)); 747 748 return 0; 749 } 750 751 #if 0 752 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) 753 { 754 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 755 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 756 uint32_t min_level; 757 758 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; 759 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; 760 761 /* Optimize compute power profile: Use only highest 762 * 2 power levels (if more than 2 are available) 763 */ 764 if (dpm_table->count > 2) 765 min_level = dpm_table->count - 2; 766 else if (dpm_table->count == 2) 767 min_level = 1; 768 else 769 min_level = 0; 770 771 hwmgr->default_compute_power_profile.min_sclk = 772 dpm_table->dpm_levels[min_level].value; 773 774 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; 775 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; 776 777 return 0; 778 } 779 #endif 780 781 /** 782 * Initializes the SMC table and uploads it 783 * 784 * @hwmgr: the address of the powerplay hardware manager. 785 * return: always 0 786 */ 787 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) 788 { 789 int result; 790 struct vega12_hwmgr *data = 791 (struct vega12_hwmgr *)(hwmgr->backend); 792 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 793 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 794 struct phm_ppt_v3_information *pptable_information = 795 (struct phm_ppt_v3_information *)hwmgr->pptable; 796 797 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 798 if (!result) { 799 data->vbios_boot_state.vddc = boot_up_values.usVddc; 800 data->vbios_boot_state.vddci = boot_up_values.usVddci; 801 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 802 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 803 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 804 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 805 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 806 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; 807 data->vbios_boot_state.eclock = boot_up_values.ulEClk; 808 data->vbios_boot_state.dclock = boot_up_values.ulDClk; 809 data->vbios_boot_state.vclock = boot_up_values.ulVClk; 810 smum_send_msg_to_smc_with_parameter(hwmgr, 811 PPSMC_MSG_SetMinDeepSleepDcefclk, 812 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 813 NULL); 814 } 815 816 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 817 818 result = smum_smc_table_manager(hwmgr, 819 (uint8_t *)pp_table, TABLE_PPTABLE, false); 820 PP_ASSERT_WITH_CODE(!result, 821 "Failed to upload PPtable!", return result); 822 823 return 0; 824 } 825 826 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr) 827 { 828 uint32_t result; 829 830 PP_ASSERT_WITH_CODE( 831 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0, 832 "[Run_ACG_BTC] Attempt to run ACG BTC failed!", 833 return -EINVAL); 834 835 PP_ASSERT_WITH_CODE(result == 1, 836 "Failed to run ACG BTC!", return -EINVAL); 837 838 return 0; 839 } 840 841 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) 842 { 843 struct vega12_hwmgr *data = 844 (struct vega12_hwmgr *)(hwmgr->backend); 845 int i; 846 uint32_t allowed_features_low = 0, allowed_features_high = 0; 847 848 for (i = 0; i < GNLD_FEATURES_MAX; i++) 849 if (data->smu_features[i].allowed) 850 data->smu_features[i].smu_feature_id > 31 ? 851 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) : 852 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF)); 853 854 PP_ASSERT_WITH_CODE( 855 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, 856 NULL) == 0, 857 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!", 858 return -1); 859 860 PP_ASSERT_WITH_CODE( 861 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, 862 NULL) == 0, 863 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", 864 return -1); 865 866 return 0; 867 } 868 869 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) 870 { 871 struct vega12_hwmgr *data = 872 (struct vega12_hwmgr *)(hwmgr->backend); 873 874 data->uvd_power_gated = true; 875 data->vce_power_gated = true; 876 877 if (data->smu_features[GNLD_DPM_UVD].enabled) 878 data->uvd_power_gated = false; 879 880 if (data->smu_features[GNLD_DPM_VCE].enabled) 881 data->vce_power_gated = false; 882 } 883 884 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) 885 { 886 struct vega12_hwmgr *data = 887 (struct vega12_hwmgr *)(hwmgr->backend); 888 uint64_t features_enabled; 889 int i; 890 bool enabled; 891 892 PP_ASSERT_WITH_CODE( 893 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0, 894 "[EnableAllSMUFeatures] Failed to enable all smu features!", 895 return -1); 896 897 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 898 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 899 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 900 data->smu_features[i].enabled = enabled; 901 data->smu_features[i].supported = enabled; 902 } 903 } 904 905 vega12_init_powergate_state(hwmgr); 906 907 return 0; 908 } 909 910 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) 911 { 912 struct vega12_hwmgr *data = 913 (struct vega12_hwmgr *)(hwmgr->backend); 914 uint64_t features_enabled; 915 int i; 916 bool enabled; 917 918 PP_ASSERT_WITH_CODE( 919 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0, 920 "[DisableAllSMUFeatures] Failed to disable all smu features!", 921 return -1); 922 923 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 924 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 925 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 926 data->smu_features[i].enabled = enabled; 927 data->smu_features[i].supported = enabled; 928 } 929 } 930 931 return 0; 932 } 933 934 static int vega12_odn_initialize_default_settings( 935 struct pp_hwmgr *hwmgr) 936 { 937 return 0; 938 } 939 940 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 941 uint32_t adjust_percent) 942 { 943 return smum_send_msg_to_smc_with_parameter(hwmgr, 944 PPSMC_MSG_OverDriveSetPercentage, adjust_percent, 945 NULL); 946 } 947 948 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) 949 { 950 int adjust_percent, result = 0; 951 952 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 953 adjust_percent = 954 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? 955 hwmgr->platform_descriptor.TDPAdjustment : 956 (-1 * hwmgr->platform_descriptor.TDPAdjustment); 957 result = vega12_set_overdrive_target_percentage(hwmgr, 958 (uint32_t)adjust_percent); 959 } 960 return result; 961 } 962 963 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, 964 PPCLK_e clkid, struct vega12_clock_range *clock) 965 { 966 /* AC Max */ 967 PP_ASSERT_WITH_CODE( 968 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16), 969 &(clock->ACMax)) == 0, 970 "[GetClockRanges] Failed to get max ac clock from SMC!", 971 return -EINVAL); 972 973 /* AC Min */ 974 PP_ASSERT_WITH_CODE( 975 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16), 976 &(clock->ACMin)) == 0, 977 "[GetClockRanges] Failed to get min ac clock from SMC!", 978 return -EINVAL); 979 980 /* DC Max */ 981 PP_ASSERT_WITH_CODE( 982 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16), 983 &(clock->DCMax)) == 0, 984 "[GetClockRanges] Failed to get max dc clock from SMC!", 985 return -EINVAL); 986 987 return 0; 988 } 989 990 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) 991 { 992 struct vega12_hwmgr *data = 993 (struct vega12_hwmgr *)(hwmgr->backend); 994 uint32_t i; 995 996 for (i = 0; i < PPCLK_COUNT; i++) 997 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, 998 i, &(data->clk_range[i])), 999 "Failed to get clk range from SMC!", 1000 return -EINVAL); 1001 1002 return 0; 1003 } 1004 1005 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1006 { 1007 int tmp_result, result = 0; 1008 1009 smum_send_msg_to_smc_with_parameter(hwmgr, 1010 PPSMC_MSG_NumOfDisplays, 0, NULL); 1011 1012 result = vega12_set_allowed_featuresmask(hwmgr); 1013 PP_ASSERT_WITH_CODE(result == 0, 1014 "[EnableDPMTasks] Failed to set allowed featuresmask!\n", 1015 return result); 1016 1017 tmp_result = vega12_init_smc_table(hwmgr); 1018 PP_ASSERT_WITH_CODE(!tmp_result, 1019 "Failed to initialize SMC table!", 1020 result = tmp_result); 1021 1022 tmp_result = vega12_run_acg_btc(hwmgr); 1023 PP_ASSERT_WITH_CODE(!tmp_result, 1024 "Failed to run ACG BTC!", 1025 result = tmp_result); 1026 1027 result = vega12_enable_all_smu_features(hwmgr); 1028 PP_ASSERT_WITH_CODE(!result, 1029 "Failed to enable all smu features!", 1030 return result); 1031 1032 result = vega12_override_pcie_parameters(hwmgr); 1033 PP_ASSERT_WITH_CODE(!result, 1034 "[EnableDPMTasks] Failed to override pcie parameters!", 1035 return result); 1036 1037 tmp_result = vega12_power_control_set_level(hwmgr); 1038 PP_ASSERT_WITH_CODE(!tmp_result, 1039 "Failed to power control set level!", 1040 result = tmp_result); 1041 1042 result = vega12_get_all_clock_ranges(hwmgr); 1043 PP_ASSERT_WITH_CODE(!result, 1044 "Failed to get all clock ranges!", 1045 return result); 1046 1047 result = vega12_odn_initialize_default_settings(hwmgr); 1048 PP_ASSERT_WITH_CODE(!result, 1049 "Failed to power control set level!", 1050 return result); 1051 1052 result = vega12_setup_default_dpm_tables(hwmgr); 1053 PP_ASSERT_WITH_CODE(!result, 1054 "Failed to setup default DPM tables!", 1055 return result); 1056 return result; 1057 } 1058 1059 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, 1060 struct pp_hw_power_state *hw_ps) 1061 { 1062 return 0; 1063 } 1064 1065 static uint32_t vega12_find_lowest_dpm_level( 1066 struct vega12_single_dpm_table *table) 1067 { 1068 uint32_t i; 1069 1070 for (i = 0; i < table->count; i++) { 1071 if (table->dpm_levels[i].enabled) 1072 break; 1073 } 1074 1075 if (i >= table->count) { 1076 i = 0; 1077 table->dpm_levels[i].enabled = true; 1078 } 1079 1080 return i; 1081 } 1082 1083 static uint32_t vega12_find_highest_dpm_level( 1084 struct vega12_single_dpm_table *table) 1085 { 1086 int32_t i = 0; 1087 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, 1088 "[FindHighestDPMLevel] DPM Table has too many entries!", 1089 return MAX_REGULAR_DPM_NUMBER - 1); 1090 1091 for (i = table->count - 1; i >= 0; i--) { 1092 if (table->dpm_levels[i].enabled) 1093 break; 1094 } 1095 1096 if (i < 0) { 1097 i = 0; 1098 table->dpm_levels[i].enabled = true; 1099 } 1100 1101 return (uint32_t)i; 1102 } 1103 1104 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) 1105 { 1106 struct vega12_hwmgr *data = hwmgr->backend; 1107 uint32_t min_freq; 1108 int ret = 0; 1109 1110 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1111 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1112 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1113 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1114 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), 1115 NULL)), 1116 "Failed to set soft min gfxclk !", 1117 return ret); 1118 } 1119 1120 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1121 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1122 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1123 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1124 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1125 NULL)), 1126 "Failed to set soft min memclk !", 1127 return ret); 1128 1129 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; 1130 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1131 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1132 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1133 NULL)), 1134 "Failed to set hard min memclk !", 1135 return ret); 1136 } 1137 1138 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1139 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1140 1141 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1142 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1143 (PPCLK_VCLK << 16) | (min_freq & 0xffff), 1144 NULL)), 1145 "Failed to set soft min vclk!", 1146 return ret); 1147 1148 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1149 1150 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1151 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1152 (PPCLK_DCLK << 16) | (min_freq & 0xffff), 1153 NULL)), 1154 "Failed to set soft min dclk!", 1155 return ret); 1156 } 1157 1158 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1159 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1160 1161 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1162 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1163 (PPCLK_ECLK << 16) | (min_freq & 0xffff), 1164 NULL)), 1165 "Failed to set soft min eclk!", 1166 return ret); 1167 } 1168 1169 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1170 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1171 1172 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1173 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1174 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), 1175 NULL)), 1176 "Failed to set soft min socclk!", 1177 return ret); 1178 } 1179 1180 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1181 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; 1182 1183 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1184 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1185 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), 1186 NULL)), 1187 "Failed to set hard min dcefclk!", 1188 return ret); 1189 } 1190 1191 return ret; 1192 1193 } 1194 1195 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 1196 { 1197 struct vega12_hwmgr *data = hwmgr->backend; 1198 uint32_t max_freq; 1199 int ret = 0; 1200 1201 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1202 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1203 1204 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1205 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1206 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), 1207 NULL)), 1208 "Failed to set soft max gfxclk!", 1209 return ret); 1210 } 1211 1212 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1213 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1214 1215 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1216 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1217 (PPCLK_UCLK << 16) | (max_freq & 0xffff), 1218 NULL)), 1219 "Failed to set soft max memclk!", 1220 return ret); 1221 } 1222 1223 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1224 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1225 1226 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1227 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1228 (PPCLK_VCLK << 16) | (max_freq & 0xffff), 1229 NULL)), 1230 "Failed to set soft max vclk!", 1231 return ret); 1232 1233 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1234 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1235 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1236 (PPCLK_DCLK << 16) | (max_freq & 0xffff), 1237 NULL)), 1238 "Failed to set soft max dclk!", 1239 return ret); 1240 } 1241 1242 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1243 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1244 1245 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1246 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1247 (PPCLK_ECLK << 16) | (max_freq & 0xffff), 1248 NULL)), 1249 "Failed to set soft max eclk!", 1250 return ret); 1251 } 1252 1253 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1254 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1255 1256 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1257 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1258 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), 1259 NULL)), 1260 "Failed to set soft max socclk!", 1261 return ret); 1262 } 1263 1264 return ret; 1265 } 1266 1267 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 1268 { 1269 struct vega12_hwmgr *data = 1270 (struct vega12_hwmgr *)(hwmgr->backend); 1271 1272 if (data->smu_features[GNLD_DPM_VCE].supported) { 1273 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 1274 enable, 1275 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 1276 "Attempt to Enable/Disable DPM VCE Failed!", 1277 return -1); 1278 data->smu_features[GNLD_DPM_VCE].enabled = enable; 1279 } 1280 1281 return 0; 1282 } 1283 1284 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 1285 { 1286 struct vega12_hwmgr *data = 1287 (struct vega12_hwmgr *)(hwmgr->backend); 1288 uint32_t gfx_clk; 1289 1290 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1291 return -1; 1292 1293 if (low) 1294 PP_ASSERT_WITH_CODE( 1295 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0, 1296 "[GetSclks]: fail to get min PPCLK_GFXCLK\n", 1297 return -1); 1298 else 1299 PP_ASSERT_WITH_CODE( 1300 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0, 1301 "[GetSclks]: fail to get max PPCLK_GFXCLK\n", 1302 return -1); 1303 1304 return (gfx_clk * 100); 1305 } 1306 1307 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 1308 { 1309 struct vega12_hwmgr *data = 1310 (struct vega12_hwmgr *)(hwmgr->backend); 1311 uint32_t mem_clk; 1312 1313 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1314 return -1; 1315 1316 if (low) 1317 PP_ASSERT_WITH_CODE( 1318 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, 1319 "[GetMclks]: fail to get min PPCLK_UCLK\n", 1320 return -1); 1321 else 1322 PP_ASSERT_WITH_CODE( 1323 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, 1324 "[GetMclks]: fail to get max PPCLK_UCLK\n", 1325 return -1); 1326 1327 return (mem_clk * 100); 1328 } 1329 1330 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, 1331 SmuMetrics_t *metrics_table, 1332 bool bypass_cache) 1333 { 1334 struct vega12_hwmgr *data = 1335 (struct vega12_hwmgr *)(hwmgr->backend); 1336 int ret = 0; 1337 1338 if (bypass_cache || 1339 !data->metrics_time || 1340 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { 1341 ret = smum_smc_table_manager(hwmgr, 1342 (uint8_t *)(&data->metrics_table), 1343 TABLE_SMU_METRICS, 1344 true); 1345 if (ret) { 1346 pr_info("Failed to export SMU metrics table!\n"); 1347 return ret; 1348 } 1349 data->metrics_time = jiffies; 1350 } 1351 1352 if (metrics_table) 1353 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); 1354 1355 return ret; 1356 } 1357 1358 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) 1359 { 1360 SmuMetrics_t metrics_table; 1361 int ret = 0; 1362 1363 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1364 if (ret) 1365 return ret; 1366 1367 *query = metrics_table.CurrSocketPower << 8; 1368 1369 return ret; 1370 } 1371 1372 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) 1373 { 1374 uint32_t gfx_clk = 0; 1375 1376 *gfx_freq = 0; 1377 1378 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 1379 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16), 1380 &gfx_clk) == 0, 1381 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!", 1382 return -EINVAL); 1383 1384 *gfx_freq = gfx_clk * 100; 1385 1386 return 0; 1387 } 1388 1389 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) 1390 { 1391 uint32_t mem_clk = 0; 1392 1393 *mclk_freq = 0; 1394 1395 PP_ASSERT_WITH_CODE( 1396 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16), 1397 &mem_clk) == 0, 1398 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!", 1399 return -EINVAL); 1400 1401 *mclk_freq = mem_clk * 100; 1402 1403 return 0; 1404 } 1405 1406 static int vega12_get_current_activity_percent( 1407 struct pp_hwmgr *hwmgr, 1408 int idx, 1409 uint32_t *activity_percent) 1410 { 1411 SmuMetrics_t metrics_table; 1412 int ret = 0; 1413 1414 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1415 if (ret) 1416 return ret; 1417 1418 switch (idx) { 1419 case AMDGPU_PP_SENSOR_GPU_LOAD: 1420 *activity_percent = metrics_table.AverageGfxActivity; 1421 break; 1422 case AMDGPU_PP_SENSOR_MEM_LOAD: 1423 *activity_percent = metrics_table.AverageUclkActivity; 1424 break; 1425 default: 1426 pr_err("Invalid index for retrieving clock activity\n"); 1427 return -EINVAL; 1428 } 1429 1430 return ret; 1431 } 1432 1433 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1434 void *value, int *size) 1435 { 1436 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1437 SmuMetrics_t metrics_table; 1438 int ret = 0; 1439 1440 switch (idx) { 1441 case AMDGPU_PP_SENSOR_GFX_SCLK: 1442 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); 1443 if (!ret) 1444 *size = 4; 1445 break; 1446 case AMDGPU_PP_SENSOR_GFX_MCLK: 1447 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); 1448 if (!ret) 1449 *size = 4; 1450 break; 1451 case AMDGPU_PP_SENSOR_GPU_LOAD: 1452 case AMDGPU_PP_SENSOR_MEM_LOAD: 1453 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); 1454 if (!ret) 1455 *size = 4; 1456 break; 1457 case AMDGPU_PP_SENSOR_GPU_TEMP: 1458 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); 1459 *size = 4; 1460 break; 1461 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1462 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1463 if (ret) 1464 return ret; 1465 1466 *((uint32_t *)value) = metrics_table.TemperatureHotspot * 1467 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1468 *size = 4; 1469 break; 1470 case AMDGPU_PP_SENSOR_MEM_TEMP: 1471 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1472 if (ret) 1473 return ret; 1474 1475 *((uint32_t *)value) = metrics_table.TemperatureHBM * 1476 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1477 *size = 4; 1478 break; 1479 case AMDGPU_PP_SENSOR_UVD_POWER: 1480 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 1481 *size = 4; 1482 break; 1483 case AMDGPU_PP_SENSOR_VCE_POWER: 1484 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 1485 *size = 4; 1486 break; 1487 case AMDGPU_PP_SENSOR_GPU_POWER: 1488 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); 1489 if (!ret) 1490 *size = 4; 1491 break; 1492 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 1493 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value); 1494 if (!ret) 1495 *size = 8; 1496 break; 1497 default: 1498 ret = -EINVAL; 1499 break; 1500 } 1501 return ret; 1502 } 1503 1504 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, 1505 bool has_disp) 1506 { 1507 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1508 1509 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1510 return smum_send_msg_to_smc_with_parameter(hwmgr, 1511 PPSMC_MSG_SetUclkFastSwitch, 1512 has_disp ? 1 : 0, 1513 NULL); 1514 1515 return 0; 1516 } 1517 1518 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 1519 struct pp_display_clock_request *clock_req) 1520 { 1521 int result = 0; 1522 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1523 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1524 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1525 PPCLK_e clk_select = 0; 1526 uint32_t clk_request = 0; 1527 1528 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1529 switch (clk_type) { 1530 case amd_pp_dcef_clock: 1531 clk_select = PPCLK_DCEFCLK; 1532 break; 1533 case amd_pp_disp_clock: 1534 clk_select = PPCLK_DISPCLK; 1535 break; 1536 case amd_pp_pixel_clock: 1537 clk_select = PPCLK_PIXCLK; 1538 break; 1539 case amd_pp_phy_clock: 1540 clk_select = PPCLK_PHYCLK; 1541 break; 1542 default: 1543 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 1544 result = -1; 1545 break; 1546 } 1547 1548 if (!result) { 1549 clk_request = (clk_select << 16) | clk_freq; 1550 result = smum_send_msg_to_smc_with_parameter(hwmgr, 1551 PPSMC_MSG_SetHardMinByFreq, 1552 clk_request, 1553 NULL); 1554 } 1555 } 1556 1557 return result; 1558 } 1559 1560 static int vega12_notify_smc_display_config_after_ps_adjustment( 1561 struct pp_hwmgr *hwmgr) 1562 { 1563 struct vega12_hwmgr *data = 1564 (struct vega12_hwmgr *)(hwmgr->backend); 1565 struct PP_Clocks min_clocks = {0}; 1566 struct pp_display_clock_request clock_req; 1567 1568 if ((hwmgr->display_config->num_display > 1) && 1569 !hwmgr->display_config->multi_monitor_in_sync && 1570 !hwmgr->display_config->nb_pstate_switch_disable) 1571 vega12_notify_smc_display_change(hwmgr, false); 1572 else 1573 vega12_notify_smc_display_change(hwmgr, true); 1574 1575 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 1576 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 1577 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 1578 1579 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { 1580 clock_req.clock_type = amd_pp_dcef_clock; 1581 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; 1582 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { 1583 if (data->smu_features[GNLD_DS_DCEFCLK].supported) 1584 PP_ASSERT_WITH_CODE( 1585 !smum_send_msg_to_smc_with_parameter( 1586 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 1587 min_clocks.dcefClockInSR /100, 1588 NULL), 1589 "Attempt to set divider for DCEFCLK Failed!", 1590 return -1); 1591 } else { 1592 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 1593 } 1594 } 1595 1596 return 0; 1597 } 1598 1599 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) 1600 { 1601 struct vega12_hwmgr *data = 1602 (struct vega12_hwmgr *)(hwmgr->backend); 1603 1604 uint32_t soft_level; 1605 1606 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 1607 1608 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1609 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1610 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1611 1612 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table)); 1613 1614 data->dpm_table.mem_table.dpm_state.soft_min_level = 1615 data->dpm_table.mem_table.dpm_state.soft_max_level = 1616 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1617 1618 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1619 "Failed to upload boot level to highest!", 1620 return -1); 1621 1622 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1623 "Failed to upload dpm max level to highest!", 1624 return -1); 1625 1626 return 0; 1627 } 1628 1629 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) 1630 { 1631 struct vega12_hwmgr *data = 1632 (struct vega12_hwmgr *)(hwmgr->backend); 1633 uint32_t soft_level; 1634 1635 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 1636 1637 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1638 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1639 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1640 1641 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 1642 1643 data->dpm_table.mem_table.dpm_state.soft_min_level = 1644 data->dpm_table.mem_table.dpm_state.soft_max_level = 1645 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1646 1647 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1648 "Failed to upload boot level to highest!", 1649 return -1); 1650 1651 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1652 "Failed to upload dpm max level to highest!", 1653 return -1); 1654 1655 return 0; 1656 1657 } 1658 1659 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 1660 { 1661 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1662 "Failed to upload DPM Bootup Levels!", 1663 return -1); 1664 1665 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1666 "Failed to upload DPM Max Levels!", 1667 return -1); 1668 1669 return 0; 1670 } 1671 1672 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 1673 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 1674 { 1675 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1676 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 1677 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 1678 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); 1679 1680 *sclk_mask = 0; 1681 *mclk_mask = 0; 1682 *soc_mask = 0; 1683 1684 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && 1685 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL && 1686 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) { 1687 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; 1688 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; 1689 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; 1690 } 1691 1692 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 1693 *sclk_mask = 0; 1694 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 1695 *mclk_mask = 0; 1696 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 1697 *sclk_mask = gfx_dpm_table->count - 1; 1698 *mclk_mask = mem_dpm_table->count - 1; 1699 *soc_mask = soc_dpm_table->count - 1; 1700 } 1701 1702 return 0; 1703 } 1704 1705 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 1706 { 1707 switch (mode) { 1708 case AMD_FAN_CTRL_NONE: 1709 break; 1710 case AMD_FAN_CTRL_MANUAL: 1711 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1712 vega12_fan_ctrl_stop_smc_fan_control(hwmgr); 1713 break; 1714 case AMD_FAN_CTRL_AUTO: 1715 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1716 vega12_fan_ctrl_start_smc_fan_control(hwmgr); 1717 break; 1718 default: 1719 break; 1720 } 1721 } 1722 1723 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 1724 enum amd_dpm_forced_level level) 1725 { 1726 int ret = 0; 1727 uint32_t sclk_mask = 0; 1728 uint32_t mclk_mask = 0; 1729 uint32_t soc_mask = 0; 1730 1731 switch (level) { 1732 case AMD_DPM_FORCED_LEVEL_HIGH: 1733 ret = vega12_force_dpm_highest(hwmgr); 1734 break; 1735 case AMD_DPM_FORCED_LEVEL_LOW: 1736 ret = vega12_force_dpm_lowest(hwmgr); 1737 break; 1738 case AMD_DPM_FORCED_LEVEL_AUTO: 1739 ret = vega12_unforce_dpm_levels(hwmgr); 1740 break; 1741 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1742 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1743 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1744 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1745 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 1746 if (ret) 1747 return ret; 1748 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 1749 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); 1750 break; 1751 case AMD_DPM_FORCED_LEVEL_MANUAL: 1752 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1753 default: 1754 break; 1755 } 1756 1757 return ret; 1758 } 1759 1760 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) 1761 { 1762 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1763 1764 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 1765 return AMD_FAN_CTRL_MANUAL; 1766 else 1767 return AMD_FAN_CTRL_AUTO; 1768 } 1769 1770 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, 1771 struct amd_pp_simple_clock_info *info) 1772 { 1773 #if 0 1774 struct phm_ppt_v2_information *table_info = 1775 (struct phm_ppt_v2_information *)hwmgr->pptable; 1776 struct phm_clock_and_voltage_limits *max_limits = 1777 &table_info->max_clock_voltage_on_ac; 1778 1779 info->engine_max_clock = max_limits->sclk; 1780 info->memory_max_clock = max_limits->mclk; 1781 #endif 1782 return 0; 1783 } 1784 1785 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 1786 uint32_t *clock, 1787 PPCLK_e clock_select, 1788 bool max) 1789 { 1790 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1791 1792 if (max) 1793 *clock = data->clk_range[clock_select].ACMax; 1794 else 1795 *clock = data->clk_range[clock_select].ACMin; 1796 1797 return 0; 1798 } 1799 1800 static int vega12_get_sclks(struct pp_hwmgr *hwmgr, 1801 struct pp_clock_levels_with_latency *clocks) 1802 { 1803 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1804 uint32_t ucount; 1805 int i; 1806 struct vega12_single_dpm_table *dpm_table; 1807 1808 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1809 return -1; 1810 1811 dpm_table = &(data->dpm_table.gfx_table); 1812 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1813 MAX_NUM_CLOCKS : dpm_table->count; 1814 1815 for (i = 0; i < ucount; i++) { 1816 clocks->data[i].clocks_in_khz = 1817 dpm_table->dpm_levels[i].value * 1000; 1818 1819 clocks->data[i].latency_in_us = 0; 1820 } 1821 1822 clocks->num_levels = ucount; 1823 1824 return 0; 1825 } 1826 1827 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, 1828 uint32_t clock) 1829 { 1830 return 25; 1831 } 1832 1833 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, 1834 struct pp_clock_levels_with_latency *clocks) 1835 { 1836 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1837 uint32_t ucount; 1838 int i; 1839 struct vega12_single_dpm_table *dpm_table; 1840 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1841 return -1; 1842 1843 dpm_table = &(data->dpm_table.mem_table); 1844 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1845 MAX_NUM_CLOCKS : dpm_table->count; 1846 1847 for (i = 0; i < ucount; i++) { 1848 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; 1849 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; 1850 clocks->data[i].latency_in_us = 1851 data->mclk_latency_table.entries[i].latency = 1852 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); 1853 } 1854 1855 clocks->num_levels = data->mclk_latency_table.count = ucount; 1856 1857 return 0; 1858 } 1859 1860 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, 1861 struct pp_clock_levels_with_latency *clocks) 1862 { 1863 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1864 uint32_t ucount; 1865 int i; 1866 struct vega12_single_dpm_table *dpm_table; 1867 1868 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) 1869 return -1; 1870 1871 1872 dpm_table = &(data->dpm_table.dcef_table); 1873 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1874 MAX_NUM_CLOCKS : dpm_table->count; 1875 1876 for (i = 0; i < ucount; i++) { 1877 clocks->data[i].clocks_in_khz = 1878 dpm_table->dpm_levels[i].value * 1000; 1879 1880 clocks->data[i].latency_in_us = 0; 1881 } 1882 1883 clocks->num_levels = ucount; 1884 1885 return 0; 1886 } 1887 1888 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, 1889 struct pp_clock_levels_with_latency *clocks) 1890 { 1891 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1892 uint32_t ucount; 1893 int i; 1894 struct vega12_single_dpm_table *dpm_table; 1895 1896 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) 1897 return -1; 1898 1899 1900 dpm_table = &(data->dpm_table.soc_table); 1901 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1902 MAX_NUM_CLOCKS : dpm_table->count; 1903 1904 for (i = 0; i < ucount; i++) { 1905 clocks->data[i].clocks_in_khz = 1906 dpm_table->dpm_levels[i].value * 1000; 1907 1908 clocks->data[i].latency_in_us = 0; 1909 } 1910 1911 clocks->num_levels = ucount; 1912 1913 return 0; 1914 1915 } 1916 1917 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 1918 enum amd_pp_clock_type type, 1919 struct pp_clock_levels_with_latency *clocks) 1920 { 1921 int ret; 1922 1923 switch (type) { 1924 case amd_pp_sys_clock: 1925 ret = vega12_get_sclks(hwmgr, clocks); 1926 break; 1927 case amd_pp_mem_clock: 1928 ret = vega12_get_memclocks(hwmgr, clocks); 1929 break; 1930 case amd_pp_dcef_clock: 1931 ret = vega12_get_dcefclocks(hwmgr, clocks); 1932 break; 1933 case amd_pp_soc_clock: 1934 ret = vega12_get_socclocks(hwmgr, clocks); 1935 break; 1936 default: 1937 return -EINVAL; 1938 } 1939 1940 return ret; 1941 } 1942 1943 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 1944 enum amd_pp_clock_type type, 1945 struct pp_clock_levels_with_voltage *clocks) 1946 { 1947 clocks->num_levels = 0; 1948 1949 return 0; 1950 } 1951 1952 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 1953 void *clock_ranges) 1954 { 1955 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1956 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 1957 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 1958 1959 if (!data->registry_data.disable_water_mark && 1960 data->smu_features[GNLD_DPM_DCEFCLK].supported && 1961 data->smu_features[GNLD_DPM_SOCCLK].supported) { 1962 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 1963 data->water_marks_bitmap |= WaterMarksExist; 1964 data->water_marks_bitmap &= ~WaterMarksLoaded; 1965 } 1966 1967 return 0; 1968 } 1969 1970 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 1971 enum pp_clock_type type, uint32_t mask) 1972 { 1973 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1974 uint32_t soft_min_level, soft_max_level, hard_min_level; 1975 int ret = 0; 1976 1977 switch (type) { 1978 case PP_SCLK: 1979 soft_min_level = mask ? (ffs(mask) - 1) : 0; 1980 soft_max_level = mask ? (fls(mask) - 1) : 0; 1981 1982 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1983 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 1984 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1985 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 1986 1987 ret = vega12_upload_dpm_min_level(hwmgr); 1988 PP_ASSERT_WITH_CODE(!ret, 1989 "Failed to upload boot level to lowest!", 1990 return ret); 1991 1992 ret = vega12_upload_dpm_max_level(hwmgr); 1993 PP_ASSERT_WITH_CODE(!ret, 1994 "Failed to upload dpm max level to highest!", 1995 return ret); 1996 break; 1997 1998 case PP_MCLK: 1999 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2000 soft_max_level = mask ? (fls(mask) - 1) : 0; 2001 2002 data->dpm_table.mem_table.dpm_state.soft_min_level = 2003 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2004 data->dpm_table.mem_table.dpm_state.soft_max_level = 2005 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2006 2007 ret = vega12_upload_dpm_min_level(hwmgr); 2008 PP_ASSERT_WITH_CODE(!ret, 2009 "Failed to upload boot level to lowest!", 2010 return ret); 2011 2012 ret = vega12_upload_dpm_max_level(hwmgr); 2013 PP_ASSERT_WITH_CODE(!ret, 2014 "Failed to upload dpm max level to highest!", 2015 return ret); 2016 2017 break; 2018 2019 case PP_SOCCLK: 2020 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2021 soft_max_level = mask ? (fls(mask) - 1) : 0; 2022 2023 if (soft_max_level >= data->dpm_table.soc_table.count) { 2024 pr_err("Clock level specified %d is over max allowed %d\n", 2025 soft_max_level, 2026 data->dpm_table.soc_table.count - 1); 2027 return -EINVAL; 2028 } 2029 2030 data->dpm_table.soc_table.dpm_state.soft_min_level = 2031 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2032 data->dpm_table.soc_table.dpm_state.soft_max_level = 2033 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2034 2035 ret = vega12_upload_dpm_min_level(hwmgr); 2036 PP_ASSERT_WITH_CODE(!ret, 2037 "Failed to upload boot level to lowest!", 2038 return ret); 2039 2040 ret = vega12_upload_dpm_max_level(hwmgr); 2041 PP_ASSERT_WITH_CODE(!ret, 2042 "Failed to upload dpm max level to highest!", 2043 return ret); 2044 2045 break; 2046 2047 case PP_DCEFCLK: 2048 hard_min_level = mask ? (ffs(mask) - 1) : 0; 2049 2050 if (hard_min_level >= data->dpm_table.dcef_table.count) { 2051 pr_err("Clock level specified %d is over max allowed %d\n", 2052 hard_min_level, 2053 data->dpm_table.dcef_table.count - 1); 2054 return -EINVAL; 2055 } 2056 2057 data->dpm_table.dcef_table.dpm_state.hard_min_level = 2058 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; 2059 2060 ret = vega12_upload_dpm_min_level(hwmgr); 2061 PP_ASSERT_WITH_CODE(!ret, 2062 "Failed to upload boot level to lowest!", 2063 return ret); 2064 2065 //TODO: Setting DCEFCLK max dpm level is not supported 2066 2067 break; 2068 2069 case PP_PCIE: 2070 break; 2071 2072 default: 2073 break; 2074 } 2075 2076 return 0; 2077 } 2078 2079 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 2080 { 2081 static const char *ppfeature_name[] = { 2082 "DPM_PREFETCHER", 2083 "GFXCLK_DPM", 2084 "UCLK_DPM", 2085 "SOCCLK_DPM", 2086 "UVD_DPM", 2087 "VCE_DPM", 2088 "ULV", 2089 "MP0CLK_DPM", 2090 "LINK_DPM", 2091 "DCEFCLK_DPM", 2092 "GFXCLK_DS", 2093 "SOCCLK_DS", 2094 "LCLK_DS", 2095 "PPT", 2096 "TDC", 2097 "THERMAL", 2098 "GFX_PER_CU_CG", 2099 "RM", 2100 "DCEFCLK_DS", 2101 "ACDC", 2102 "VR0HOT", 2103 "VR1HOT", 2104 "FW_CTF", 2105 "LED_DISPLAY", 2106 "FAN_CONTROL", 2107 "DIDT", 2108 "GFXOFF", 2109 "CG", 2110 "ACG"}; 2111 static const char *output_title[] = { 2112 "FEATURES", 2113 "BITMASK", 2114 "ENABLEMENT"}; 2115 uint64_t features_enabled; 2116 int i; 2117 int ret = 0; 2118 int size = 0; 2119 2120 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2121 PP_ASSERT_WITH_CODE(!ret, 2122 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 2123 return ret); 2124 2125 size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled); 2126 size += sprintf(buf + size, "%-19s %-22s %s\n", 2127 output_title[0], 2128 output_title[1], 2129 output_title[2]); 2130 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 2131 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n", 2132 ppfeature_name[i], 2133 1ULL << i, 2134 (features_enabled & (1ULL << i)) ? "Y" : "N"); 2135 } 2136 2137 return size; 2138 } 2139 2140 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 2141 { 2142 uint64_t features_enabled; 2143 uint64_t features_to_enable; 2144 uint64_t features_to_disable; 2145 int ret = 0; 2146 2147 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 2148 return -EINVAL; 2149 2150 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2151 if (ret) 2152 return ret; 2153 2154 features_to_disable = 2155 features_enabled & ~new_ppfeature_masks; 2156 features_to_enable = 2157 ~features_enabled & new_ppfeature_masks; 2158 2159 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 2160 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 2161 2162 if (features_to_disable) { 2163 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable); 2164 if (ret) 2165 return ret; 2166 } 2167 2168 if (features_to_enable) { 2169 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable); 2170 if (ret) 2171 return ret; 2172 } 2173 2174 return 0; 2175 } 2176 2177 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 2178 { 2179 struct amdgpu_device *adev = hwmgr->adev; 2180 2181 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2182 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2183 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2184 } 2185 2186 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) 2187 { 2188 uint32_t width_level; 2189 2190 width_level = vega12_get_current_pcie_link_width_level(hwmgr); 2191 if (width_level > LINK_WIDTH_MAX) 2192 width_level = 0; 2193 2194 return link_width[width_level]; 2195 } 2196 2197 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 2198 { 2199 struct amdgpu_device *adev = hwmgr->adev; 2200 2201 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2202 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2203 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2204 } 2205 2206 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) 2207 { 2208 uint32_t speed_level; 2209 2210 speed_level = vega12_get_current_pcie_link_speed_level(hwmgr); 2211 if (speed_level > LINK_SPEED_MAX) 2212 speed_level = 0; 2213 2214 return link_speed[speed_level]; 2215 } 2216 2217 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 2218 enum pp_clock_type type, char *buf) 2219 { 2220 int i, now, size = 0; 2221 struct pp_clock_levels_with_latency clocks; 2222 2223 switch (type) { 2224 case PP_SCLK: 2225 PP_ASSERT_WITH_CODE( 2226 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0, 2227 "Attempt to get current gfx clk Failed!", 2228 return -1); 2229 2230 PP_ASSERT_WITH_CODE( 2231 vega12_get_sclks(hwmgr, &clocks) == 0, 2232 "Attempt to get gfx clk levels Failed!", 2233 return -1); 2234 for (i = 0; i < clocks.num_levels; i++) 2235 size += sprintf(buf + size, "%d: %uMhz %s\n", 2236 i, clocks.data[i].clocks_in_khz / 1000, 2237 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2238 break; 2239 2240 case PP_MCLK: 2241 PP_ASSERT_WITH_CODE( 2242 vega12_get_current_mclk_freq(hwmgr, &now) == 0, 2243 "Attempt to get current mclk freq Failed!", 2244 return -1); 2245 2246 PP_ASSERT_WITH_CODE( 2247 vega12_get_memclocks(hwmgr, &clocks) == 0, 2248 "Attempt to get memory clk levels Failed!", 2249 return -1); 2250 for (i = 0; i < clocks.num_levels; i++) 2251 size += sprintf(buf + size, "%d: %uMhz %s\n", 2252 i, clocks.data[i].clocks_in_khz / 1000, 2253 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2254 break; 2255 2256 case PP_SOCCLK: 2257 PP_ASSERT_WITH_CODE( 2258 smum_send_msg_to_smc_with_parameter(hwmgr, 2259 PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16), 2260 &now) == 0, 2261 "Attempt to get Current SOCCLK Frequency Failed!", 2262 return -EINVAL); 2263 2264 PP_ASSERT_WITH_CODE( 2265 vega12_get_socclocks(hwmgr, &clocks) == 0, 2266 "Attempt to get soc clk levels Failed!", 2267 return -1); 2268 for (i = 0; i < clocks.num_levels; i++) 2269 size += sprintf(buf + size, "%d: %uMhz %s\n", 2270 i, clocks.data[i].clocks_in_khz / 1000, 2271 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2272 break; 2273 2274 case PP_DCEFCLK: 2275 PP_ASSERT_WITH_CODE( 2276 smum_send_msg_to_smc_with_parameter(hwmgr, 2277 PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16), 2278 &now) == 0, 2279 "Attempt to get Current DCEFCLK Frequency Failed!", 2280 return -EINVAL); 2281 2282 PP_ASSERT_WITH_CODE( 2283 vega12_get_dcefclocks(hwmgr, &clocks) == 0, 2284 "Attempt to get dcef clk levels Failed!", 2285 return -1); 2286 for (i = 0; i < clocks.num_levels; i++) 2287 size += sprintf(buf + size, "%d: %uMhz %s\n", 2288 i, clocks.data[i].clocks_in_khz / 1000, 2289 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2290 break; 2291 2292 case PP_PCIE: 2293 break; 2294 2295 default: 2296 break; 2297 } 2298 return size; 2299 } 2300 2301 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 2302 { 2303 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2304 struct vega12_single_dpm_table *dpm_table; 2305 bool vblank_too_short = false; 2306 bool disable_mclk_switching; 2307 uint32_t i, latency; 2308 2309 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 2310 !hwmgr->display_config->multi_monitor_in_sync) || 2311 vblank_too_short; 2312 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 2313 2314 /* gfxclk */ 2315 dpm_table = &(data->dpm_table.gfx_table); 2316 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2317 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2318 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2319 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2320 2321 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2322 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { 2323 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2324 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2325 } 2326 2327 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2328 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2329 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2330 } 2331 2332 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2333 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2334 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2335 } 2336 } 2337 2338 /* memclk */ 2339 dpm_table = &(data->dpm_table.mem_table); 2340 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2341 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2342 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2343 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2344 2345 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2346 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { 2347 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2348 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2349 } 2350 2351 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 2352 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2353 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2354 } 2355 2356 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2357 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2358 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2359 } 2360 } 2361 2362 /* honour DAL's UCLK Hardmin */ 2363 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) 2364 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; 2365 2366 /* Hardmin is dependent on displayconfig */ 2367 if (disable_mclk_switching) { 2368 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2369 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { 2370 if (data->mclk_latency_table.entries[i].latency <= latency) { 2371 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { 2372 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; 2373 break; 2374 } 2375 } 2376 } 2377 } 2378 2379 if (hwmgr->display_config->nb_pstate_switch_disable) 2380 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2381 2382 /* vclk */ 2383 dpm_table = &(data->dpm_table.vclk_table); 2384 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2385 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2386 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2387 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2388 2389 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2390 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2391 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2392 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2393 } 2394 2395 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2396 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2397 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2398 } 2399 } 2400 2401 /* dclk */ 2402 dpm_table = &(data->dpm_table.dclk_table); 2403 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2404 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2405 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2406 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2407 2408 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2409 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2410 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2411 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2412 } 2413 2414 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2415 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2416 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2417 } 2418 } 2419 2420 /* socclk */ 2421 dpm_table = &(data->dpm_table.soc_table); 2422 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2423 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2424 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2425 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2426 2427 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2428 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { 2429 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2430 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2431 } 2432 2433 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2434 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2435 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2436 } 2437 } 2438 2439 /* eclk */ 2440 dpm_table = &(data->dpm_table.eclk_table); 2441 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2442 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2443 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2444 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2445 2446 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2447 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { 2448 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2449 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2450 } 2451 2452 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2453 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2454 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2455 } 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, 2462 struct vega12_single_dpm_table *dpm_table) 2463 { 2464 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2465 int ret = 0; 2466 2467 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 2468 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 2469 "[SetUclkToHightestDpmLevel] Dpm table has no entry!", 2470 return -EINVAL); 2471 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, 2472 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", 2473 return -EINVAL); 2474 2475 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2476 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2477 PPSMC_MSG_SetHardMinByFreq, 2478 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, 2479 NULL)), 2480 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", 2481 return ret); 2482 } 2483 2484 return ret; 2485 } 2486 2487 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2488 { 2489 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2490 int ret = 0; 2491 2492 smum_send_msg_to_smc_with_parameter(hwmgr, 2493 PPSMC_MSG_NumOfDisplays, 0, 2494 NULL); 2495 2496 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr, 2497 &data->dpm_table.mem_table); 2498 2499 return ret; 2500 } 2501 2502 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2503 { 2504 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2505 int result = 0; 2506 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 2507 2508 if ((data->water_marks_bitmap & WaterMarksExist) && 2509 !(data->water_marks_bitmap & WaterMarksLoaded)) { 2510 result = smum_smc_table_manager(hwmgr, 2511 (uint8_t *)wm_table, TABLE_WATERMARKS, false); 2512 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 2513 data->water_marks_bitmap |= WaterMarksLoaded; 2514 } 2515 2516 if ((data->water_marks_bitmap & WaterMarksExist) && 2517 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2518 data->smu_features[GNLD_DPM_SOCCLK].supported) 2519 smum_send_msg_to_smc_with_parameter(hwmgr, 2520 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 2521 NULL); 2522 2523 return result; 2524 } 2525 2526 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 2527 { 2528 struct vega12_hwmgr *data = 2529 (struct vega12_hwmgr *)(hwmgr->backend); 2530 2531 if (data->smu_features[GNLD_DPM_UVD].supported) { 2532 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 2533 enable, 2534 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 2535 "Attempt to Enable/Disable DPM UVD Failed!", 2536 return -1); 2537 data->smu_features[GNLD_DPM_UVD].enabled = enable; 2538 } 2539 2540 return 0; 2541 } 2542 2543 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 2544 { 2545 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2546 2547 if (data->vce_power_gated == bgate) 2548 return; 2549 2550 data->vce_power_gated = bgate; 2551 vega12_enable_disable_vce_dpm(hwmgr, !bgate); 2552 } 2553 2554 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 2555 { 2556 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2557 2558 if (data->uvd_power_gated == bgate) 2559 return; 2560 2561 data->uvd_power_gated = bgate; 2562 vega12_enable_disable_uvd_dpm(hwmgr, !bgate); 2563 } 2564 2565 static bool 2566 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 2567 { 2568 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2569 bool is_update_required = false; 2570 2571 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 2572 is_update_required = true; 2573 2574 if (data->registry_data.gfx_clk_deep_sleep_support) { 2575 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 2576 is_update_required = true; 2577 } 2578 2579 return is_update_required; 2580 } 2581 2582 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 2583 { 2584 int tmp_result, result = 0; 2585 2586 tmp_result = vega12_disable_all_smu_features(hwmgr); 2587 PP_ASSERT_WITH_CODE((tmp_result == 0), 2588 "Failed to disable all smu features!", result = tmp_result); 2589 2590 return result; 2591 } 2592 2593 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) 2594 { 2595 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2596 int result; 2597 2598 result = vega12_disable_dpm_tasks(hwmgr); 2599 PP_ASSERT_WITH_CODE((0 == result), 2600 "[disable_dpm_tasks] Failed to disable DPM!", 2601 ); 2602 data->water_marks_bitmap &= ~(WaterMarksLoaded); 2603 2604 return result; 2605 } 2606 2607 #if 0 2608 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr, 2609 uint32_t *sclk_idx, uint32_t *mclk_idx, 2610 uint32_t min_sclk, uint32_t min_mclk) 2611 { 2612 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2613 struct vega12_dpm_table *dpm_table = &(data->dpm_table); 2614 uint32_t i; 2615 2616 for (i = 0; i < dpm_table->gfx_table.count; i++) { 2617 if (dpm_table->gfx_table.dpm_levels[i].enabled && 2618 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { 2619 *sclk_idx = i; 2620 break; 2621 } 2622 } 2623 2624 for (i = 0; i < dpm_table->mem_table.count; i++) { 2625 if (dpm_table->mem_table.dpm_levels[i].enabled && 2626 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { 2627 *mclk_idx = i; 2628 break; 2629 } 2630 } 2631 } 2632 #endif 2633 2634 #if 0 2635 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr, 2636 struct amd_pp_profile *request) 2637 { 2638 return 0; 2639 } 2640 2641 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) 2642 { 2643 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2644 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 2645 struct vega12_single_dpm_table *golden_sclk_table = 2646 &(data->golden_dpm_table.gfx_table); 2647 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 2648 int golden_value = golden_sclk_table->dpm_levels 2649 [golden_sclk_table->count - 1].value; 2650 2651 value -= golden_value; 2652 value = DIV_ROUND_UP(value * 100, golden_value); 2653 2654 return value; 2655 } 2656 2657 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2658 { 2659 return 0; 2660 } 2661 2662 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) 2663 { 2664 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2665 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 2666 struct vega12_single_dpm_table *golden_mclk_table = 2667 &(data->golden_dpm_table.mem_table); 2668 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 2669 int golden_value = golden_mclk_table->dpm_levels 2670 [golden_mclk_table->count - 1].value; 2671 2672 value -= golden_value; 2673 value = DIV_ROUND_UP(value * 100, golden_value); 2674 2675 return value; 2676 } 2677 2678 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2679 { 2680 return 0; 2681 } 2682 #endif 2683 2684 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 2685 uint32_t virtual_addr_low, 2686 uint32_t virtual_addr_hi, 2687 uint32_t mc_addr_low, 2688 uint32_t mc_addr_hi, 2689 uint32_t size) 2690 { 2691 smum_send_msg_to_smc_with_parameter(hwmgr, 2692 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 2693 virtual_addr_hi, 2694 NULL); 2695 smum_send_msg_to_smc_with_parameter(hwmgr, 2696 PPSMC_MSG_SetSystemVirtualDramAddrLow, 2697 virtual_addr_low, 2698 NULL); 2699 smum_send_msg_to_smc_with_parameter(hwmgr, 2700 PPSMC_MSG_DramLogSetDramAddrHigh, 2701 mc_addr_hi, 2702 NULL); 2703 2704 smum_send_msg_to_smc_with_parameter(hwmgr, 2705 PPSMC_MSG_DramLogSetDramAddrLow, 2706 mc_addr_low, 2707 NULL); 2708 2709 smum_send_msg_to_smc_with_parameter(hwmgr, 2710 PPSMC_MSG_DramLogSetDramSize, 2711 size, 2712 NULL); 2713 return 0; 2714 } 2715 2716 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 2717 struct PP_TemperatureRange *thermal_data) 2718 { 2719 struct vega12_hwmgr *data = 2720 (struct vega12_hwmgr *)(hwmgr->backend); 2721 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2722 2723 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 2724 2725 thermal_data->max = pp_table->TedgeLimit * 2726 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2727 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 2728 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2729 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 2730 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2731 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2732 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2733 thermal_data->mem_crit_max = pp_table->ThbmLimit * 2734 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2735 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 2736 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2737 2738 return 0; 2739 } 2740 2741 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) 2742 { 2743 struct vega12_hwmgr *data = 2744 (struct vega12_hwmgr *)(hwmgr->backend); 2745 int ret = 0; 2746 2747 if (data->gfxoff_controlled_by_driver) 2748 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL); 2749 2750 return ret; 2751 } 2752 2753 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) 2754 { 2755 struct vega12_hwmgr *data = 2756 (struct vega12_hwmgr *)(hwmgr->backend); 2757 int ret = 0; 2758 2759 if (data->gfxoff_controlled_by_driver) 2760 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL); 2761 2762 return ret; 2763 } 2764 2765 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) 2766 { 2767 if (enable) 2768 return vega12_enable_gfx_off(hwmgr); 2769 else 2770 return vega12_disable_gfx_off(hwmgr); 2771 } 2772 2773 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 2774 PHM_PerformanceLevelDesignation designation, uint32_t index, 2775 PHM_PerformanceLevel *level) 2776 { 2777 return 0; 2778 } 2779 2780 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr, 2781 enum pp_mp1_state mp1_state) 2782 { 2783 uint16_t msg; 2784 int ret; 2785 2786 switch (mp1_state) { 2787 case PP_MP1_STATE_UNLOAD: 2788 msg = PPSMC_MSG_PrepareMp1ForUnload; 2789 break; 2790 case PP_MP1_STATE_SHUTDOWN: 2791 case PP_MP1_STATE_RESET: 2792 case PP_MP1_STATE_NONE: 2793 default: 2794 return 0; 2795 } 2796 2797 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 2798 "[PrepareMp1] Failed!", 2799 return ret); 2800 2801 return 0; 2802 } 2803 2804 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) 2805 { 2806 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); 2807 2808 gpu_metrics->common_header.structure_size = 2809 sizeof(struct gpu_metrics_v1_0); 2810 gpu_metrics->common_header.format_revision = 1; 2811 gpu_metrics->common_header.content_revision = 0; 2812 2813 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2814 } 2815 2816 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr, 2817 void **table) 2818 { 2819 struct vega12_hwmgr *data = 2820 (struct vega12_hwmgr *)(hwmgr->backend); 2821 struct gpu_metrics_v1_0 *gpu_metrics = 2822 &data->gpu_metrics_table; 2823 SmuMetrics_t metrics; 2824 uint32_t fan_speed_rpm; 2825 int ret; 2826 2827 ret = vega12_get_metrics_table(hwmgr, &metrics, true); 2828 if (ret) 2829 return ret; 2830 2831 vega12_init_gpu_metrics_v1_0(gpu_metrics); 2832 2833 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2834 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2835 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2836 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2837 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2838 2839 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2840 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2841 2842 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2843 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2844 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2845 2846 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2847 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2848 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2849 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2850 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2851 2852 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2853 2854 vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); 2855 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; 2856 2857 gpu_metrics->pcie_link_width = 2858 vega12_get_current_pcie_link_width(hwmgr); 2859 gpu_metrics->pcie_link_speed = 2860 vega12_get_current_pcie_link_speed(hwmgr); 2861 2862 *table = (void *)gpu_metrics; 2863 2864 return sizeof(struct gpu_metrics_v1_0); 2865 } 2866 2867 static const struct pp_hwmgr_func vega12_hwmgr_funcs = { 2868 .backend_init = vega12_hwmgr_backend_init, 2869 .backend_fini = vega12_hwmgr_backend_fini, 2870 .asic_setup = vega12_setup_asic_task, 2871 .dynamic_state_management_enable = vega12_enable_dpm_tasks, 2872 .dynamic_state_management_disable = vega12_disable_dpm_tasks, 2873 .patch_boot_state = vega12_patch_boot_state, 2874 .get_sclk = vega12_dpm_get_sclk, 2875 .get_mclk = vega12_dpm_get_mclk, 2876 .notify_smc_display_config_after_ps_adjustment = 2877 vega12_notify_smc_display_config_after_ps_adjustment, 2878 .force_dpm_level = vega12_dpm_force_dpm_level, 2879 .stop_thermal_controller = vega12_thermal_stop_thermal_controller, 2880 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info, 2881 .reset_fan_speed_to_default = 2882 vega12_fan_ctrl_reset_fan_speed_to_default, 2883 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm, 2884 .set_fan_control_mode = vega12_set_fan_control_mode, 2885 .get_fan_control_mode = vega12_get_fan_control_mode, 2886 .read_sensor = vega12_read_sensor, 2887 .get_dal_power_level = vega12_get_dal_power_level, 2888 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency, 2889 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage, 2890 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges, 2891 .display_clock_voltage_request = vega12_display_clock_voltage_request, 2892 .force_clock_level = vega12_force_clock_level, 2893 .print_clock_levels = vega12_print_clock_levels, 2894 .apply_clocks_adjust_rules = 2895 vega12_apply_clocks_adjust_rules, 2896 .pre_display_config_changed = 2897 vega12_pre_display_configuration_changed_task, 2898 .display_config_changed = vega12_display_configuration_changed_task, 2899 .powergate_uvd = vega12_power_gate_uvd, 2900 .powergate_vce = vega12_power_gate_vce, 2901 .check_smc_update_required_for_display_configuration = 2902 vega12_check_smc_update_required_for_display_configuration, 2903 .power_off_asic = vega12_power_off_asic, 2904 .disable_smc_firmware_ctf = vega12_thermal_disable_alert, 2905 #if 0 2906 .set_power_profile_state = vega12_set_power_profile_state, 2907 .get_sclk_od = vega12_get_sclk_od, 2908 .set_sclk_od = vega12_set_sclk_od, 2909 .get_mclk_od = vega12_get_mclk_od, 2910 .set_mclk_od = vega12_set_mclk_od, 2911 #endif 2912 .notify_cac_buffer_info = vega12_notify_cac_buffer_info, 2913 .get_thermal_temperature_range = vega12_get_thermal_temperature_range, 2914 .register_irq_handlers = smu9_register_irq_handlers, 2915 .start_thermal_controller = vega12_start_thermal_controller, 2916 .powergate_gfx = vega12_gfx_off_control, 2917 .get_performance_level = vega12_get_performance_level, 2918 .get_asic_baco_capability = smu9_baco_get_capability, 2919 .get_asic_baco_state = smu9_baco_get_state, 2920 .set_asic_baco_state = vega12_baco_set_state, 2921 .get_ppfeature_status = vega12_get_ppfeature_status, 2922 .set_ppfeature_status = vega12_set_ppfeature_status, 2923 .set_mp1_state = vega12_set_mp1_state, 2924 .get_gpu_metrics = vega12_get_gpu_metrics, 2925 }; 2926 2927 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) 2928 { 2929 hwmgr->hwmgr_func = &vega12_hwmgr_funcs; 2930 hwmgr->pptable_func = &vega12_pptable_funcs; 2931 2932 return 0; 2933 } 2934