1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/fb.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "vega12_smumgr.h" 32 #include "hardwaremanager.h" 33 #include "ppatomfwctrl.h" 34 #include "atomfirmware.h" 35 #include "cgs_common.h" 36 #include "vega12_inc.h" 37 #include "pppcielanes.h" 38 #include "vega12_hwmgr.h" 39 #include "vega12_processpptables.h" 40 #include "vega12_pptable.h" 41 #include "vega12_thermal.h" 42 #include "vega12_ppsmc.h" 43 #include "pp_debug.h" 44 #include "amd_pcie_helpers.h" 45 #include "ppinterrupt.h" 46 #include "pp_overdriver.h" 47 #include "pp_thermal.h" 48 #include "vega12_baco.h" 49 50 #define smnPCIE_LC_SPEED_CNTL 0x11140290 51 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 52 53 #define LINK_WIDTH_MAX 6 54 #define LINK_SPEED_MAX 3 55 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 56 static const int link_speed[] = {25, 50, 80, 160}; 57 58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 59 enum pp_clock_type type, uint32_t mask); 60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 61 uint32_t *clock, 62 PPCLK_e clock_select, 63 bool max); 64 65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) 66 { 67 struct vega12_hwmgr *data = 68 (struct vega12_hwmgr *)(hwmgr->backend); 69 70 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT; 71 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT; 72 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT; 73 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT; 74 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT; 75 76 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT; 77 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 78 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 79 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 80 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 81 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 82 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 83 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 84 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 85 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 86 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 87 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 88 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 89 90 data->registry_data.disallowed_features = 0x0; 91 data->registry_data.od_state_in_dc_support = 0; 92 data->registry_data.thermal_support = 1; 93 data->registry_data.skip_baco_hardware = 0; 94 95 data->registry_data.log_avfs_param = 0; 96 data->registry_data.sclk_throttle_low_notification = 1; 97 data->registry_data.force_dpm_high = 0; 98 data->registry_data.stable_pstate_sclk_dpm_percentage = 75; 99 100 data->registry_data.didt_support = 0; 101 if (data->registry_data.didt_support) { 102 data->registry_data.didt_mode = 6; 103 data->registry_data.sq_ramping_support = 1; 104 data->registry_data.db_ramping_support = 0; 105 data->registry_data.td_ramping_support = 0; 106 data->registry_data.tcp_ramping_support = 0; 107 data->registry_data.dbr_ramping_support = 0; 108 data->registry_data.edc_didt_support = 1; 109 data->registry_data.gc_didt_support = 0; 110 data->registry_data.psm_didt_support = 0; 111 } 112 113 data->registry_data.pcie_lane_override = 0xff; 114 data->registry_data.pcie_speed_override = 0xff; 115 data->registry_data.pcie_clock_override = 0xffffffff; 116 data->registry_data.regulator_hot_gpio_support = 1; 117 data->registry_data.ac_dc_switch_gpio_support = 0; 118 data->registry_data.quick_transition_support = 0; 119 data->registry_data.zrpm_start_temp = 0xffff; 120 data->registry_data.zrpm_stop_temp = 0xffff; 121 data->registry_data.odn_feature_enable = 1; 122 data->registry_data.disable_water_mark = 0; 123 data->registry_data.disable_pp_tuning = 0; 124 data->registry_data.disable_xlpp_tuning = 0; 125 data->registry_data.disable_workload_policy = 0; 126 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; 127 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; 128 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; 129 data->registry_data.force_workload_policy_mask = 0; 130 data->registry_data.disable_3d_fs_detection = 0; 131 data->registry_data.fps_support = 1; 132 data->registry_data.disable_auto_wattman = 1; 133 data->registry_data.auto_wattman_debug = 0; 134 data->registry_data.auto_wattman_sample_period = 100; 135 data->registry_data.auto_wattman_threshold = 50; 136 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 137 } 138 139 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) 140 { 141 struct vega12_hwmgr *data = 142 (struct vega12_hwmgr *)(hwmgr->backend); 143 struct amdgpu_device *adev = hwmgr->adev; 144 145 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE) 146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 147 PHM_PlatformCaps_ControlVDDCI); 148 149 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 150 PHM_PlatformCaps_TablelessHardwareInterface); 151 152 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 153 PHM_PlatformCaps_EnableSMU7ThermalManagement); 154 155 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) { 156 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 157 PHM_PlatformCaps_UVDPowerGating); 158 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 159 PHM_PlatformCaps_UVDDynamicPowerGating); 160 } 161 162 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 163 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 164 PHM_PlatformCaps_VCEPowerGating); 165 166 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 167 PHM_PlatformCaps_UnTabledHardwareInterface); 168 169 if (data->registry_data.odn_feature_enable) 170 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 171 PHM_PlatformCaps_ODNinACSupport); 172 else { 173 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 174 PHM_PlatformCaps_OD6inACSupport); 175 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 176 PHM_PlatformCaps_OD6PlusinACSupport); 177 } 178 179 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 180 PHM_PlatformCaps_ActivityReporting); 181 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 182 PHM_PlatformCaps_FanSpeedInTableIsRPM); 183 184 if (data->registry_data.od_state_in_dc_support) { 185 if (data->registry_data.odn_feature_enable) 186 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 187 PHM_PlatformCaps_ODNinDCSupport); 188 else { 189 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 190 PHM_PlatformCaps_OD6inDCSupport); 191 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 192 PHM_PlatformCaps_OD6PlusinDCSupport); 193 } 194 } 195 196 if (data->registry_data.thermal_support 197 && data->registry_data.fuzzy_fan_control_support 198 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax) 199 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 200 PHM_PlatformCaps_ODFuzzyFanControlSupport); 201 202 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 203 PHM_PlatformCaps_DynamicPowerManagement); 204 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 205 PHM_PlatformCaps_SMC); 206 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 207 PHM_PlatformCaps_ThermalPolicyDelay); 208 209 if (data->registry_data.force_dpm_high) 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_ExclusiveModeAlwaysHigh); 212 213 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 214 PHM_PlatformCaps_DynamicUVDState); 215 216 if (data->registry_data.sclk_throttle_low_notification) 217 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 218 PHM_PlatformCaps_SclkThrottleLowNotification); 219 220 /* power tune caps */ 221 /* assume disabled */ 222 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 223 PHM_PlatformCaps_PowerContainment); 224 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 225 PHM_PlatformCaps_DiDtSupport); 226 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 227 PHM_PlatformCaps_SQRamping); 228 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 229 PHM_PlatformCaps_DBRamping); 230 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 231 PHM_PlatformCaps_TDRamping); 232 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 233 PHM_PlatformCaps_TCPRamping); 234 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 235 PHM_PlatformCaps_DBRRamping); 236 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 237 PHM_PlatformCaps_DiDtEDCEnable); 238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 239 PHM_PlatformCaps_GCEDC); 240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 241 PHM_PlatformCaps_PSM); 242 243 if (data->registry_data.didt_support) { 244 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 245 if (data->registry_data.sq_ramping_support) 246 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 247 if (data->registry_data.db_ramping_support) 248 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 249 if (data->registry_data.td_ramping_support) 250 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 251 if (data->registry_data.tcp_ramping_support) 252 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 253 if (data->registry_data.dbr_ramping_support) 254 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 255 if (data->registry_data.edc_didt_support) 256 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 257 if (data->registry_data.gc_didt_support) 258 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 259 if (data->registry_data.psm_didt_support) 260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 261 } 262 263 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 264 PHM_PlatformCaps_RegulatorHot); 265 266 if (data->registry_data.ac_dc_switch_gpio_support) { 267 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 268 PHM_PlatformCaps_AutomaticDCTransition); 269 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 270 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 271 } 272 273 if (data->registry_data.quick_transition_support) { 274 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 275 PHM_PlatformCaps_AutomaticDCTransition); 276 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 277 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 278 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 279 PHM_PlatformCaps_Falcon_QuickTransition); 280 } 281 282 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) { 283 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 284 PHM_PlatformCaps_LowestUclkReservedForUlv); 285 if (data->lowest_uclk_reserved_for_ulv == 1) 286 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 287 PHM_PlatformCaps_LowestUclkReservedForUlv); 288 } 289 290 if (data->registry_data.custom_fan_support) 291 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 292 PHM_PlatformCaps_CustomFanControlSupport); 293 294 return 0; 295 } 296 297 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) 298 { 299 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 300 struct amdgpu_device *adev = hwmgr->adev; 301 uint32_t top32, bottom32; 302 int i; 303 304 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 305 FEATURE_DPM_PREFETCHER_BIT; 306 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 307 FEATURE_DPM_GFXCLK_BIT; 308 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 309 FEATURE_DPM_UCLK_BIT; 310 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 311 FEATURE_DPM_SOCCLK_BIT; 312 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 313 FEATURE_DPM_UVD_BIT; 314 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 315 FEATURE_DPM_VCE_BIT; 316 data->smu_features[GNLD_ULV].smu_feature_id = 317 FEATURE_ULV_BIT; 318 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 319 FEATURE_DPM_MP0CLK_BIT; 320 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 321 FEATURE_DPM_LINK_BIT; 322 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 323 FEATURE_DPM_DCEFCLK_BIT; 324 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 325 FEATURE_DS_GFXCLK_BIT; 326 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 327 FEATURE_DS_SOCCLK_BIT; 328 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 329 FEATURE_DS_LCLK_BIT; 330 data->smu_features[GNLD_PPT].smu_feature_id = 331 FEATURE_PPT_BIT; 332 data->smu_features[GNLD_TDC].smu_feature_id = 333 FEATURE_TDC_BIT; 334 data->smu_features[GNLD_THERMAL].smu_feature_id = 335 FEATURE_THERMAL_BIT; 336 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 337 FEATURE_GFX_PER_CU_CG_BIT; 338 data->smu_features[GNLD_RM].smu_feature_id = 339 FEATURE_RM_BIT; 340 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 341 FEATURE_DS_DCEFCLK_BIT; 342 data->smu_features[GNLD_ACDC].smu_feature_id = 343 FEATURE_ACDC_BIT; 344 data->smu_features[GNLD_VR0HOT].smu_feature_id = 345 FEATURE_VR0HOT_BIT; 346 data->smu_features[GNLD_VR1HOT].smu_feature_id = 347 FEATURE_VR1HOT_BIT; 348 data->smu_features[GNLD_FW_CTF].smu_feature_id = 349 FEATURE_FW_CTF_BIT; 350 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 351 FEATURE_LED_DISPLAY_BIT; 352 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 353 FEATURE_FAN_CONTROL_BIT; 354 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 355 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; 356 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; 357 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 358 359 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 360 data->smu_features[i].smu_feature_bitmap = 361 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); 362 data->smu_features[i].allowed = 363 ((data->registry_data.disallowed_features >> i) & 1) ? 364 false : true; 365 } 366 367 /* Get the SN to turn into a Unique ID */ 368 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 369 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 370 371 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 372 } 373 374 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 375 { 376 return 0; 377 } 378 379 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 380 { 381 kfree(hwmgr->backend); 382 hwmgr->backend = NULL; 383 384 return 0; 385 } 386 387 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 388 { 389 int result = 0; 390 struct vega12_hwmgr *data; 391 struct amdgpu_device *adev = hwmgr->adev; 392 393 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL); 394 if (data == NULL) 395 return -ENOMEM; 396 397 hwmgr->backend = data; 398 399 vega12_set_default_registry_data(hwmgr); 400 401 data->disable_dpm_mask = 0xff; 402 data->workload_mask = 0xff; 403 404 /* need to set voltage control types before EVV patching */ 405 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE; 406 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; 407 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE; 408 409 data->water_marks_bitmap = 0; 410 data->avfs_exist = false; 411 412 vega12_set_features_platform_caps(hwmgr); 413 414 vega12_init_dpm_defaults(hwmgr); 415 416 /* Parse pptable data read from VBIOS */ 417 vega12_set_private_data_based_on_pptable(hwmgr); 418 419 data->is_tlu_enabled = false; 420 421 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 422 VEGA12_MAX_HARDWARE_POWERLEVELS; 423 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 424 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 425 426 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 427 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 428 hwmgr->platform_descriptor.clockStep.engineClock = 500; 429 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 430 431 data->total_active_cus = adev->gfx.cu_info.number; 432 /* Setup default Overdrive Fan control settings */ 433 data->odn_fan_table.target_fan_speed = 434 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 435 data->odn_fan_table.target_temperature = 436 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature; 437 data->odn_fan_table.min_performance_clock = 438 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit; 439 data->odn_fan_table.min_fan_limit = 440 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * 441 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 442 443 if (hwmgr->feature_mask & PP_GFXOFF_MASK) 444 data->gfxoff_controlled_by_driver = true; 445 else 446 data->gfxoff_controlled_by_driver = false; 447 448 return result; 449 } 450 451 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) 452 { 453 struct vega12_hwmgr *data = 454 (struct vega12_hwmgr *)(hwmgr->backend); 455 456 data->low_sclk_interrupt_threshold = 0; 457 458 return 0; 459 } 460 461 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) 462 { 463 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), 464 "Failed to init sclk threshold!", 465 return -EINVAL); 466 467 return 0; 468 } 469 470 /* 471 * @fn vega12_init_dpm_state 472 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 473 * 474 * @param dpm_state - the address of the DPM Table to initiailize. 475 * @return None. 476 */ 477 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) 478 { 479 dpm_state->soft_min_level = 0x0; 480 dpm_state->soft_max_level = 0xffff; 481 dpm_state->hard_min_level = 0x0; 482 dpm_state->hard_max_level = 0xffff; 483 } 484 485 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr) 486 { 487 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 488 struct vega12_hwmgr *data = 489 (struct vega12_hwmgr *)(hwmgr->backend); 490 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; 491 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 492 int i; 493 int ret; 494 495 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 496 pcie_gen = 3; 497 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 498 pcie_gen = 2; 499 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 500 pcie_gen = 1; 501 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 502 pcie_gen = 0; 503 504 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 505 pcie_width = 6; 506 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 507 pcie_width = 5; 508 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 509 pcie_width = 4; 510 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 511 pcie_width = 3; 512 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 513 pcie_width = 2; 514 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 515 pcie_width = 1; 516 517 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 518 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 519 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 520 */ 521 for (i = 0; i < NUM_LINK_LEVELS; i++) { 522 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : 523 pp_table->PcieGenSpeed[i]; 524 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : 525 pp_table->PcieLaneCount[i]; 526 527 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != 528 pp_table->PcieLaneCount[i]) { 529 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; 530 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 531 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 532 NULL); 533 PP_ASSERT_WITH_CODE(!ret, 534 "[OverridePcieParameters] Attempt to override pcie params failed!", 535 return ret); 536 } 537 538 /* update the pptable */ 539 pp_table->PcieGenSpeed[i] = pcie_gen_arg; 540 pp_table->PcieLaneCount[i] = pcie_width_arg; 541 } 542 543 /* override to the highest if it's disabled from ppfeaturmask */ 544 if (data->registry_data.pcie_dpm_key_disabled) { 545 for (i = 0; i < NUM_LINK_LEVELS; i++) { 546 smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; 547 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 548 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 549 NULL); 550 PP_ASSERT_WITH_CODE(!ret, 551 "[OverridePcieParameters] Attempt to override pcie params failed!", 552 return ret); 553 554 pp_table->PcieGenSpeed[i] = pcie_gen; 555 pp_table->PcieLaneCount[i] = pcie_width; 556 } 557 ret = vega12_enable_smc_features(hwmgr, 558 false, 559 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); 560 PP_ASSERT_WITH_CODE(!ret, 561 "Attempt to Disable DPM LINK Failed!", 562 return ret); 563 data->smu_features[GNLD_DPM_LINK].enabled = false; 564 data->smu_features[GNLD_DPM_LINK].supported = false; 565 } 566 return 0; 567 } 568 569 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 570 PPCLK_e clk_id, uint32_t *num_of_levels) 571 { 572 int ret = 0; 573 574 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 575 PPSMC_MSG_GetDpmFreqByIndex, 576 (clk_id << 16 | 0xFF), 577 num_of_levels); 578 PP_ASSERT_WITH_CODE(!ret, 579 "[GetNumOfDpmLevel] failed to get dpm levels!", 580 return ret); 581 582 return ret; 583 } 584 585 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 586 PPCLK_e clkID, uint32_t index, uint32_t *clock) 587 { 588 /* 589 *SMU expects the Clock ID to be in the top 16 bits. 590 *Lower 16 bits specify the level 591 */ 592 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 593 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index), 594 clock) == 0, 595 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", 596 return -EINVAL); 597 598 return 0; 599 } 600 601 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, 602 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) 603 { 604 int ret = 0; 605 uint32_t i, num_of_levels, clk; 606 607 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); 608 PP_ASSERT_WITH_CODE(!ret, 609 "[SetupSingleDpmTable] failed to get clk levels!", 610 return ret); 611 612 dpm_table->count = num_of_levels; 613 614 for (i = 0; i < num_of_levels; i++) { 615 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); 616 PP_ASSERT_WITH_CODE(!ret, 617 "[SetupSingleDpmTable] failed to get clk of specific level!", 618 return ret); 619 dpm_table->dpm_levels[i].value = clk; 620 dpm_table->dpm_levels[i].enabled = true; 621 } 622 623 return ret; 624 } 625 626 /* 627 * This function is to initialize all DPM state tables 628 * for SMU based on the dependency table. 629 * Dynamic state patching function will then trim these 630 * state tables to the allowed range based 631 * on the power policy or external client requests, 632 * such as UVD request, etc. 633 */ 634 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 635 { 636 637 struct vega12_hwmgr *data = 638 (struct vega12_hwmgr *)(hwmgr->backend); 639 struct vega12_single_dpm_table *dpm_table; 640 int ret = 0; 641 642 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 643 644 /* socclk */ 645 dpm_table = &(data->dpm_table.soc_table); 646 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 647 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); 648 PP_ASSERT_WITH_CODE(!ret, 649 "[SetupDefaultDpmTable] failed to get socclk dpm levels!", 650 return ret); 651 } else { 652 dpm_table->count = 1; 653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 654 } 655 vega12_init_dpm_state(&(dpm_table->dpm_state)); 656 657 /* gfxclk */ 658 dpm_table = &(data->dpm_table.gfx_table); 659 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 660 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 661 PP_ASSERT_WITH_CODE(!ret, 662 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", 663 return ret); 664 } else { 665 dpm_table->count = 1; 666 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 667 } 668 vega12_init_dpm_state(&(dpm_table->dpm_state)); 669 670 /* memclk */ 671 dpm_table = &(data->dpm_table.mem_table); 672 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 673 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); 674 PP_ASSERT_WITH_CODE(!ret, 675 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", 676 return ret); 677 } else { 678 dpm_table->count = 1; 679 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 680 } 681 vega12_init_dpm_state(&(dpm_table->dpm_state)); 682 683 /* eclk */ 684 dpm_table = &(data->dpm_table.eclk_table); 685 if (data->smu_features[GNLD_DPM_VCE].enabled) { 686 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); 687 PP_ASSERT_WITH_CODE(!ret, 688 "[SetupDefaultDpmTable] failed to get eclk dpm levels!", 689 return ret); 690 } else { 691 dpm_table->count = 1; 692 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 693 } 694 vega12_init_dpm_state(&(dpm_table->dpm_state)); 695 696 /* vclk */ 697 dpm_table = &(data->dpm_table.vclk_table); 698 if (data->smu_features[GNLD_DPM_UVD].enabled) { 699 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); 700 PP_ASSERT_WITH_CODE(!ret, 701 "[SetupDefaultDpmTable] failed to get vclk dpm levels!", 702 return ret); 703 } else { 704 dpm_table->count = 1; 705 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 706 } 707 vega12_init_dpm_state(&(dpm_table->dpm_state)); 708 709 /* dclk */ 710 dpm_table = &(data->dpm_table.dclk_table); 711 if (data->smu_features[GNLD_DPM_UVD].enabled) { 712 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); 713 PP_ASSERT_WITH_CODE(!ret, 714 "[SetupDefaultDpmTable] failed to get dclk dpm levels!", 715 return ret); 716 } else { 717 dpm_table->count = 1; 718 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 719 } 720 vega12_init_dpm_state(&(dpm_table->dpm_state)); 721 722 /* dcefclk */ 723 dpm_table = &(data->dpm_table.dcef_table); 724 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 725 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); 726 PP_ASSERT_WITH_CODE(!ret, 727 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", 728 return ret); 729 } else { 730 dpm_table->count = 1; 731 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 732 } 733 vega12_init_dpm_state(&(dpm_table->dpm_state)); 734 735 /* pixclk */ 736 dpm_table = &(data->dpm_table.pixel_table); 737 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 738 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); 739 PP_ASSERT_WITH_CODE(!ret, 740 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", 741 return ret); 742 } else 743 dpm_table->count = 0; 744 vega12_init_dpm_state(&(dpm_table->dpm_state)); 745 746 /* dispclk */ 747 dpm_table = &(data->dpm_table.display_table); 748 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 749 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); 750 PP_ASSERT_WITH_CODE(!ret, 751 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", 752 return ret); 753 } else 754 dpm_table->count = 0; 755 vega12_init_dpm_state(&(dpm_table->dpm_state)); 756 757 /* phyclk */ 758 dpm_table = &(data->dpm_table.phy_table); 759 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 760 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); 761 PP_ASSERT_WITH_CODE(!ret, 762 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", 763 return ret); 764 } else 765 dpm_table->count = 0; 766 vega12_init_dpm_state(&(dpm_table->dpm_state)); 767 768 /* save a copy of the default DPM table */ 769 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 770 sizeof(struct vega12_dpm_table)); 771 772 return 0; 773 } 774 775 #if 0 776 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) 777 { 778 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 779 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 780 uint32_t min_level; 781 782 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; 783 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; 784 785 /* Optimize compute power profile: Use only highest 786 * 2 power levels (if more than 2 are available) 787 */ 788 if (dpm_table->count > 2) 789 min_level = dpm_table->count - 2; 790 else if (dpm_table->count == 2) 791 min_level = 1; 792 else 793 min_level = 0; 794 795 hwmgr->default_compute_power_profile.min_sclk = 796 dpm_table->dpm_levels[min_level].value; 797 798 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; 799 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; 800 801 return 0; 802 } 803 #endif 804 805 /** 806 * vega12_init_smc_table - Initializes the SMC table and uploads it 807 * 808 * @hwmgr: the address of the powerplay hardware manager. 809 * return: always 0 810 */ 811 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) 812 { 813 int result; 814 struct vega12_hwmgr *data = 815 (struct vega12_hwmgr *)(hwmgr->backend); 816 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 817 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 818 struct phm_ppt_v3_information *pptable_information = 819 (struct phm_ppt_v3_information *)hwmgr->pptable; 820 821 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 822 if (!result) { 823 data->vbios_boot_state.vddc = boot_up_values.usVddc; 824 data->vbios_boot_state.vddci = boot_up_values.usVddci; 825 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 826 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 827 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 828 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 829 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 830 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; 831 data->vbios_boot_state.eclock = boot_up_values.ulEClk; 832 data->vbios_boot_state.dclock = boot_up_values.ulDClk; 833 data->vbios_boot_state.vclock = boot_up_values.ulVClk; 834 smum_send_msg_to_smc_with_parameter(hwmgr, 835 PPSMC_MSG_SetMinDeepSleepDcefclk, 836 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 837 NULL); 838 } 839 840 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 841 842 result = smum_smc_table_manager(hwmgr, 843 (uint8_t *)pp_table, TABLE_PPTABLE, false); 844 PP_ASSERT_WITH_CODE(!result, 845 "Failed to upload PPtable!", return result); 846 847 return 0; 848 } 849 850 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr) 851 { 852 uint32_t result; 853 854 PP_ASSERT_WITH_CODE( 855 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0, 856 "[Run_ACG_BTC] Attempt to run ACG BTC failed!", 857 return -EINVAL); 858 859 PP_ASSERT_WITH_CODE(result == 1, 860 "Failed to run ACG BTC!", return -EINVAL); 861 862 return 0; 863 } 864 865 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) 866 { 867 struct vega12_hwmgr *data = 868 (struct vega12_hwmgr *)(hwmgr->backend); 869 int i; 870 uint32_t allowed_features_low = 0, allowed_features_high = 0; 871 872 for (i = 0; i < GNLD_FEATURES_MAX; i++) 873 if (data->smu_features[i].allowed) 874 data->smu_features[i].smu_feature_id > 31 ? 875 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) : 876 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF)); 877 878 PP_ASSERT_WITH_CODE( 879 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, 880 NULL) == 0, 881 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!", 882 return -1); 883 884 PP_ASSERT_WITH_CODE( 885 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, 886 NULL) == 0, 887 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", 888 return -1); 889 890 return 0; 891 } 892 893 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) 894 { 895 struct vega12_hwmgr *data = 896 (struct vega12_hwmgr *)(hwmgr->backend); 897 898 data->uvd_power_gated = true; 899 data->vce_power_gated = true; 900 901 if (data->smu_features[GNLD_DPM_UVD].enabled) 902 data->uvd_power_gated = false; 903 904 if (data->smu_features[GNLD_DPM_VCE].enabled) 905 data->vce_power_gated = false; 906 } 907 908 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) 909 { 910 struct vega12_hwmgr *data = 911 (struct vega12_hwmgr *)(hwmgr->backend); 912 uint64_t features_enabled; 913 int i; 914 bool enabled; 915 916 PP_ASSERT_WITH_CODE( 917 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0, 918 "[EnableAllSMUFeatures] Failed to enable all smu features!", 919 return -1); 920 921 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 922 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 923 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 924 data->smu_features[i].enabled = enabled; 925 data->smu_features[i].supported = enabled; 926 } 927 } 928 929 vega12_init_powergate_state(hwmgr); 930 931 return 0; 932 } 933 934 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) 935 { 936 struct vega12_hwmgr *data = 937 (struct vega12_hwmgr *)(hwmgr->backend); 938 uint64_t features_enabled; 939 int i; 940 bool enabled; 941 942 PP_ASSERT_WITH_CODE( 943 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0, 944 "[DisableAllSMUFeatures] Failed to disable all smu features!", 945 return -1); 946 947 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 948 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 949 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 950 data->smu_features[i].enabled = enabled; 951 data->smu_features[i].supported = enabled; 952 } 953 } 954 955 return 0; 956 } 957 958 static int vega12_odn_initialize_default_settings( 959 struct pp_hwmgr *hwmgr) 960 { 961 return 0; 962 } 963 964 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 965 uint32_t adjust_percent) 966 { 967 return smum_send_msg_to_smc_with_parameter(hwmgr, 968 PPSMC_MSG_OverDriveSetPercentage, adjust_percent, 969 NULL); 970 } 971 972 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) 973 { 974 int adjust_percent, result = 0; 975 976 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 977 adjust_percent = 978 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? 979 hwmgr->platform_descriptor.TDPAdjustment : 980 (-1 * hwmgr->platform_descriptor.TDPAdjustment); 981 result = vega12_set_overdrive_target_percentage(hwmgr, 982 (uint32_t)adjust_percent); 983 } 984 return result; 985 } 986 987 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, 988 PPCLK_e clkid, struct vega12_clock_range *clock) 989 { 990 /* AC Max */ 991 PP_ASSERT_WITH_CODE( 992 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16), 993 &(clock->ACMax)) == 0, 994 "[GetClockRanges] Failed to get max ac clock from SMC!", 995 return -EINVAL); 996 997 /* AC Min */ 998 PP_ASSERT_WITH_CODE( 999 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16), 1000 &(clock->ACMin)) == 0, 1001 "[GetClockRanges] Failed to get min ac clock from SMC!", 1002 return -EINVAL); 1003 1004 /* DC Max */ 1005 PP_ASSERT_WITH_CODE( 1006 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16), 1007 &(clock->DCMax)) == 0, 1008 "[GetClockRanges] Failed to get max dc clock from SMC!", 1009 return -EINVAL); 1010 1011 return 0; 1012 } 1013 1014 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) 1015 { 1016 struct vega12_hwmgr *data = 1017 (struct vega12_hwmgr *)(hwmgr->backend); 1018 uint32_t i; 1019 1020 for (i = 0; i < PPCLK_COUNT; i++) 1021 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, 1022 i, &(data->clk_range[i])), 1023 "Failed to get clk range from SMC!", 1024 return -EINVAL); 1025 1026 return 0; 1027 } 1028 1029 static void vega12_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1030 { 1031 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1032 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 1033 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 1034 1035 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && 1036 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL) { 1037 hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 1038 hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 1039 } else { 1040 hwmgr->pstate_sclk = gfx_dpm_table->dpm_levels[0].value; 1041 hwmgr->pstate_mclk = mem_dpm_table->dpm_levels[0].value; 1042 } 1043 1044 hwmgr->pstate_sclk_peak = gfx_dpm_table->dpm_levels[gfx_dpm_table->count].value; 1045 hwmgr->pstate_mclk_peak = mem_dpm_table->dpm_levels[mem_dpm_table->count].value; 1046 } 1047 1048 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1049 { 1050 int tmp_result, result = 0; 1051 1052 smum_send_msg_to_smc_with_parameter(hwmgr, 1053 PPSMC_MSG_NumOfDisplays, 0, NULL); 1054 1055 result = vega12_set_allowed_featuresmask(hwmgr); 1056 PP_ASSERT_WITH_CODE(result == 0, 1057 "[EnableDPMTasks] Failed to set allowed featuresmask!\n", 1058 return result); 1059 1060 tmp_result = vega12_init_smc_table(hwmgr); 1061 PP_ASSERT_WITH_CODE(!tmp_result, 1062 "Failed to initialize SMC table!", 1063 result = tmp_result); 1064 1065 tmp_result = vega12_run_acg_btc(hwmgr); 1066 PP_ASSERT_WITH_CODE(!tmp_result, 1067 "Failed to run ACG BTC!", 1068 result = tmp_result); 1069 1070 result = vega12_enable_all_smu_features(hwmgr); 1071 PP_ASSERT_WITH_CODE(!result, 1072 "Failed to enable all smu features!", 1073 return result); 1074 1075 result = vega12_override_pcie_parameters(hwmgr); 1076 PP_ASSERT_WITH_CODE(!result, 1077 "[EnableDPMTasks] Failed to override pcie parameters!", 1078 return result); 1079 1080 tmp_result = vega12_power_control_set_level(hwmgr); 1081 PP_ASSERT_WITH_CODE(!tmp_result, 1082 "Failed to power control set level!", 1083 result = tmp_result); 1084 1085 result = vega12_get_all_clock_ranges(hwmgr); 1086 PP_ASSERT_WITH_CODE(!result, 1087 "Failed to get all clock ranges!", 1088 return result); 1089 1090 result = vega12_odn_initialize_default_settings(hwmgr); 1091 PP_ASSERT_WITH_CODE(!result, 1092 "Failed to power control set level!", 1093 return result); 1094 1095 result = vega12_setup_default_dpm_tables(hwmgr); 1096 PP_ASSERT_WITH_CODE(!result, 1097 "Failed to setup default DPM tables!", 1098 return result); 1099 1100 vega12_populate_umdpstate_clocks(hwmgr); 1101 1102 return result; 1103 } 1104 1105 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, 1106 struct pp_hw_power_state *hw_ps) 1107 { 1108 return 0; 1109 } 1110 1111 static uint32_t vega12_find_lowest_dpm_level( 1112 struct vega12_single_dpm_table *table) 1113 { 1114 uint32_t i; 1115 1116 for (i = 0; i < table->count; i++) { 1117 if (table->dpm_levels[i].enabled) 1118 break; 1119 } 1120 1121 if (i >= table->count) { 1122 i = 0; 1123 table->dpm_levels[i].enabled = true; 1124 } 1125 1126 return i; 1127 } 1128 1129 static uint32_t vega12_find_highest_dpm_level( 1130 struct vega12_single_dpm_table *table) 1131 { 1132 int32_t i = 0; 1133 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, 1134 "[FindHighestDPMLevel] DPM Table has too many entries!", 1135 return MAX_REGULAR_DPM_NUMBER - 1); 1136 1137 for (i = table->count - 1; i >= 0; i--) { 1138 if (table->dpm_levels[i].enabled) 1139 break; 1140 } 1141 1142 if (i < 0) { 1143 i = 0; 1144 table->dpm_levels[i].enabled = true; 1145 } 1146 1147 return (uint32_t)i; 1148 } 1149 1150 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) 1151 { 1152 struct vega12_hwmgr *data = hwmgr->backend; 1153 uint32_t min_freq; 1154 int ret = 0; 1155 1156 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1157 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1158 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1159 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1160 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), 1161 NULL)), 1162 "Failed to set soft min gfxclk !", 1163 return ret); 1164 } 1165 1166 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1167 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1168 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1169 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1170 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1171 NULL)), 1172 "Failed to set soft min memclk !", 1173 return ret); 1174 1175 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; 1176 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1177 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1178 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1179 NULL)), 1180 "Failed to set hard min memclk !", 1181 return ret); 1182 } 1183 1184 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1185 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1186 1187 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1188 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1189 (PPCLK_VCLK << 16) | (min_freq & 0xffff), 1190 NULL)), 1191 "Failed to set soft min vclk!", 1192 return ret); 1193 1194 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1195 1196 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1197 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1198 (PPCLK_DCLK << 16) | (min_freq & 0xffff), 1199 NULL)), 1200 "Failed to set soft min dclk!", 1201 return ret); 1202 } 1203 1204 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1205 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1206 1207 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1208 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1209 (PPCLK_ECLK << 16) | (min_freq & 0xffff), 1210 NULL)), 1211 "Failed to set soft min eclk!", 1212 return ret); 1213 } 1214 1215 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1216 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1217 1218 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1219 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1220 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), 1221 NULL)), 1222 "Failed to set soft min socclk!", 1223 return ret); 1224 } 1225 1226 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1227 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; 1228 1229 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1230 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1231 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), 1232 NULL)), 1233 "Failed to set hard min dcefclk!", 1234 return ret); 1235 } 1236 1237 return ret; 1238 1239 } 1240 1241 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 1242 { 1243 struct vega12_hwmgr *data = hwmgr->backend; 1244 uint32_t max_freq; 1245 int ret = 0; 1246 1247 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1248 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1249 1250 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1251 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1252 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), 1253 NULL)), 1254 "Failed to set soft max gfxclk!", 1255 return ret); 1256 } 1257 1258 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1259 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1260 1261 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1262 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1263 (PPCLK_UCLK << 16) | (max_freq & 0xffff), 1264 NULL)), 1265 "Failed to set soft max memclk!", 1266 return ret); 1267 } 1268 1269 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1270 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1271 1272 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1273 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1274 (PPCLK_VCLK << 16) | (max_freq & 0xffff), 1275 NULL)), 1276 "Failed to set soft max vclk!", 1277 return ret); 1278 1279 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1280 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1281 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1282 (PPCLK_DCLK << 16) | (max_freq & 0xffff), 1283 NULL)), 1284 "Failed to set soft max dclk!", 1285 return ret); 1286 } 1287 1288 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1289 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1290 1291 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1292 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1293 (PPCLK_ECLK << 16) | (max_freq & 0xffff), 1294 NULL)), 1295 "Failed to set soft max eclk!", 1296 return ret); 1297 } 1298 1299 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1300 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1301 1302 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1303 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1304 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), 1305 NULL)), 1306 "Failed to set soft max socclk!", 1307 return ret); 1308 } 1309 1310 return ret; 1311 } 1312 1313 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 1314 { 1315 struct vega12_hwmgr *data = 1316 (struct vega12_hwmgr *)(hwmgr->backend); 1317 1318 if (data->smu_features[GNLD_DPM_VCE].supported) { 1319 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 1320 enable, 1321 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 1322 "Attempt to Enable/Disable DPM VCE Failed!", 1323 return -1); 1324 data->smu_features[GNLD_DPM_VCE].enabled = enable; 1325 } 1326 1327 return 0; 1328 } 1329 1330 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 1331 { 1332 struct vega12_hwmgr *data = 1333 (struct vega12_hwmgr *)(hwmgr->backend); 1334 uint32_t gfx_clk; 1335 1336 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1337 return -1; 1338 1339 if (low) 1340 PP_ASSERT_WITH_CODE( 1341 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0, 1342 "[GetSclks]: fail to get min PPCLK_GFXCLK\n", 1343 return -1); 1344 else 1345 PP_ASSERT_WITH_CODE( 1346 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0, 1347 "[GetSclks]: fail to get max PPCLK_GFXCLK\n", 1348 return -1); 1349 1350 return (gfx_clk * 100); 1351 } 1352 1353 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 1354 { 1355 struct vega12_hwmgr *data = 1356 (struct vega12_hwmgr *)(hwmgr->backend); 1357 uint32_t mem_clk; 1358 1359 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1360 return -1; 1361 1362 if (low) 1363 PP_ASSERT_WITH_CODE( 1364 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, 1365 "[GetMclks]: fail to get min PPCLK_UCLK\n", 1366 return -1); 1367 else 1368 PP_ASSERT_WITH_CODE( 1369 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, 1370 "[GetMclks]: fail to get max PPCLK_UCLK\n", 1371 return -1); 1372 1373 return (mem_clk * 100); 1374 } 1375 1376 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, 1377 SmuMetrics_t *metrics_table, 1378 bool bypass_cache) 1379 { 1380 struct vega12_hwmgr *data = 1381 (struct vega12_hwmgr *)(hwmgr->backend); 1382 int ret = 0; 1383 1384 if (bypass_cache || 1385 !data->metrics_time || 1386 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { 1387 ret = smum_smc_table_manager(hwmgr, 1388 (uint8_t *)(&data->metrics_table), 1389 TABLE_SMU_METRICS, 1390 true); 1391 if (ret) { 1392 pr_info("Failed to export SMU metrics table!\n"); 1393 return ret; 1394 } 1395 data->metrics_time = jiffies; 1396 } 1397 1398 if (metrics_table) 1399 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); 1400 1401 return ret; 1402 } 1403 1404 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) 1405 { 1406 SmuMetrics_t metrics_table; 1407 int ret = 0; 1408 1409 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1410 if (ret) 1411 return ret; 1412 1413 *query = metrics_table.CurrSocketPower << 8; 1414 1415 return ret; 1416 } 1417 1418 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) 1419 { 1420 uint32_t gfx_clk = 0; 1421 1422 *gfx_freq = 0; 1423 1424 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 1425 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16), 1426 &gfx_clk) == 0, 1427 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!", 1428 return -EINVAL); 1429 1430 *gfx_freq = gfx_clk * 100; 1431 1432 return 0; 1433 } 1434 1435 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) 1436 { 1437 uint32_t mem_clk = 0; 1438 1439 *mclk_freq = 0; 1440 1441 PP_ASSERT_WITH_CODE( 1442 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16), 1443 &mem_clk) == 0, 1444 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!", 1445 return -EINVAL); 1446 1447 *mclk_freq = mem_clk * 100; 1448 1449 return 0; 1450 } 1451 1452 static int vega12_get_current_activity_percent( 1453 struct pp_hwmgr *hwmgr, 1454 int idx, 1455 uint32_t *activity_percent) 1456 { 1457 SmuMetrics_t metrics_table; 1458 int ret = 0; 1459 1460 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1461 if (ret) 1462 return ret; 1463 1464 switch (idx) { 1465 case AMDGPU_PP_SENSOR_GPU_LOAD: 1466 *activity_percent = metrics_table.AverageGfxActivity; 1467 break; 1468 case AMDGPU_PP_SENSOR_MEM_LOAD: 1469 *activity_percent = metrics_table.AverageUclkActivity; 1470 break; 1471 default: 1472 pr_err("Invalid index for retrieving clock activity\n"); 1473 return -EINVAL; 1474 } 1475 1476 return ret; 1477 } 1478 1479 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1480 void *value, int *size) 1481 { 1482 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1483 SmuMetrics_t metrics_table; 1484 int ret = 0; 1485 1486 switch (idx) { 1487 case AMDGPU_PP_SENSOR_GFX_SCLK: 1488 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); 1489 if (!ret) 1490 *size = 4; 1491 break; 1492 case AMDGPU_PP_SENSOR_GFX_MCLK: 1493 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); 1494 if (!ret) 1495 *size = 4; 1496 break; 1497 case AMDGPU_PP_SENSOR_GPU_LOAD: 1498 case AMDGPU_PP_SENSOR_MEM_LOAD: 1499 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); 1500 if (!ret) 1501 *size = 4; 1502 break; 1503 case AMDGPU_PP_SENSOR_GPU_TEMP: 1504 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); 1505 *size = 4; 1506 break; 1507 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1508 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1509 if (ret) 1510 return ret; 1511 1512 *((uint32_t *)value) = metrics_table.TemperatureHotspot * 1513 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1514 *size = 4; 1515 break; 1516 case AMDGPU_PP_SENSOR_MEM_TEMP: 1517 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1518 if (ret) 1519 return ret; 1520 1521 *((uint32_t *)value) = metrics_table.TemperatureHBM * 1522 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1523 *size = 4; 1524 break; 1525 case AMDGPU_PP_SENSOR_UVD_POWER: 1526 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 1527 *size = 4; 1528 break; 1529 case AMDGPU_PP_SENSOR_VCE_POWER: 1530 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 1531 *size = 4; 1532 break; 1533 case AMDGPU_PP_SENSOR_GPU_POWER: 1534 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); 1535 if (!ret) 1536 *size = 4; 1537 break; 1538 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 1539 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value); 1540 if (!ret) 1541 *size = 8; 1542 break; 1543 default: 1544 ret = -EOPNOTSUPP; 1545 break; 1546 } 1547 return ret; 1548 } 1549 1550 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, 1551 bool has_disp) 1552 { 1553 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1554 1555 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1556 return smum_send_msg_to_smc_with_parameter(hwmgr, 1557 PPSMC_MSG_SetUclkFastSwitch, 1558 has_disp ? 1 : 0, 1559 NULL); 1560 1561 return 0; 1562 } 1563 1564 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 1565 struct pp_display_clock_request *clock_req) 1566 { 1567 int result = 0; 1568 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1569 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1570 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1571 PPCLK_e clk_select = 0; 1572 uint32_t clk_request = 0; 1573 1574 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1575 switch (clk_type) { 1576 case amd_pp_dcef_clock: 1577 clk_select = PPCLK_DCEFCLK; 1578 break; 1579 case amd_pp_disp_clock: 1580 clk_select = PPCLK_DISPCLK; 1581 break; 1582 case amd_pp_pixel_clock: 1583 clk_select = PPCLK_PIXCLK; 1584 break; 1585 case amd_pp_phy_clock: 1586 clk_select = PPCLK_PHYCLK; 1587 break; 1588 default: 1589 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 1590 result = -1; 1591 break; 1592 } 1593 1594 if (!result) { 1595 clk_request = (clk_select << 16) | clk_freq; 1596 result = smum_send_msg_to_smc_with_parameter(hwmgr, 1597 PPSMC_MSG_SetHardMinByFreq, 1598 clk_request, 1599 NULL); 1600 } 1601 } 1602 1603 return result; 1604 } 1605 1606 static int vega12_notify_smc_display_config_after_ps_adjustment( 1607 struct pp_hwmgr *hwmgr) 1608 { 1609 struct vega12_hwmgr *data = 1610 (struct vega12_hwmgr *)(hwmgr->backend); 1611 struct PP_Clocks min_clocks = {0}; 1612 struct pp_display_clock_request clock_req; 1613 1614 if ((hwmgr->display_config->num_display > 1) && 1615 !hwmgr->display_config->multi_monitor_in_sync && 1616 !hwmgr->display_config->nb_pstate_switch_disable) 1617 vega12_notify_smc_display_change(hwmgr, false); 1618 else 1619 vega12_notify_smc_display_change(hwmgr, true); 1620 1621 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 1622 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 1623 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 1624 1625 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { 1626 clock_req.clock_type = amd_pp_dcef_clock; 1627 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; 1628 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { 1629 if (data->smu_features[GNLD_DS_DCEFCLK].supported) 1630 PP_ASSERT_WITH_CODE( 1631 !smum_send_msg_to_smc_with_parameter( 1632 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 1633 min_clocks.dcefClockInSR /100, 1634 NULL), 1635 "Attempt to set divider for DCEFCLK Failed!", 1636 return -1); 1637 } else { 1638 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 1639 } 1640 } 1641 1642 return 0; 1643 } 1644 1645 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) 1646 { 1647 struct vega12_hwmgr *data = 1648 (struct vega12_hwmgr *)(hwmgr->backend); 1649 1650 uint32_t soft_level; 1651 1652 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 1653 1654 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1655 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1656 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1657 1658 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table)); 1659 1660 data->dpm_table.mem_table.dpm_state.soft_min_level = 1661 data->dpm_table.mem_table.dpm_state.soft_max_level = 1662 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1663 1664 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1665 "Failed to upload boot level to highest!", 1666 return -1); 1667 1668 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1669 "Failed to upload dpm max level to highest!", 1670 return -1); 1671 1672 return 0; 1673 } 1674 1675 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) 1676 { 1677 struct vega12_hwmgr *data = 1678 (struct vega12_hwmgr *)(hwmgr->backend); 1679 uint32_t soft_level; 1680 1681 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 1682 1683 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1684 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1685 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1686 1687 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 1688 1689 data->dpm_table.mem_table.dpm_state.soft_min_level = 1690 data->dpm_table.mem_table.dpm_state.soft_max_level = 1691 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1692 1693 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1694 "Failed to upload boot level to highest!", 1695 return -1); 1696 1697 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1698 "Failed to upload dpm max level to highest!", 1699 return -1); 1700 1701 return 0; 1702 1703 } 1704 1705 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 1706 { 1707 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1708 "Failed to upload DPM Bootup Levels!", 1709 return -1); 1710 1711 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1712 "Failed to upload DPM Max Levels!", 1713 return -1); 1714 1715 return 0; 1716 } 1717 1718 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 1719 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 1720 { 1721 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1722 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 1723 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 1724 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); 1725 1726 *sclk_mask = 0; 1727 *mclk_mask = 0; 1728 *soc_mask = 0; 1729 1730 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && 1731 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL && 1732 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) { 1733 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; 1734 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; 1735 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; 1736 } 1737 1738 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 1739 *sclk_mask = 0; 1740 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 1741 *mclk_mask = 0; 1742 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 1743 *sclk_mask = gfx_dpm_table->count - 1; 1744 *mclk_mask = mem_dpm_table->count - 1; 1745 *soc_mask = soc_dpm_table->count - 1; 1746 } 1747 1748 return 0; 1749 } 1750 1751 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 1752 { 1753 switch (mode) { 1754 case AMD_FAN_CTRL_NONE: 1755 break; 1756 case AMD_FAN_CTRL_MANUAL: 1757 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1758 vega12_fan_ctrl_stop_smc_fan_control(hwmgr); 1759 break; 1760 case AMD_FAN_CTRL_AUTO: 1761 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1762 vega12_fan_ctrl_start_smc_fan_control(hwmgr); 1763 break; 1764 default: 1765 break; 1766 } 1767 } 1768 1769 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 1770 enum amd_dpm_forced_level level) 1771 { 1772 int ret = 0; 1773 uint32_t sclk_mask = 0; 1774 uint32_t mclk_mask = 0; 1775 uint32_t soc_mask = 0; 1776 1777 switch (level) { 1778 case AMD_DPM_FORCED_LEVEL_HIGH: 1779 ret = vega12_force_dpm_highest(hwmgr); 1780 break; 1781 case AMD_DPM_FORCED_LEVEL_LOW: 1782 ret = vega12_force_dpm_lowest(hwmgr); 1783 break; 1784 case AMD_DPM_FORCED_LEVEL_AUTO: 1785 ret = vega12_unforce_dpm_levels(hwmgr); 1786 break; 1787 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1788 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1789 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1790 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1791 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 1792 if (ret) 1793 return ret; 1794 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 1795 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); 1796 break; 1797 case AMD_DPM_FORCED_LEVEL_MANUAL: 1798 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1799 default: 1800 break; 1801 } 1802 1803 return ret; 1804 } 1805 1806 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) 1807 { 1808 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1809 1810 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 1811 return AMD_FAN_CTRL_MANUAL; 1812 else 1813 return AMD_FAN_CTRL_AUTO; 1814 } 1815 1816 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, 1817 struct amd_pp_simple_clock_info *info) 1818 { 1819 #if 0 1820 struct phm_ppt_v2_information *table_info = 1821 (struct phm_ppt_v2_information *)hwmgr->pptable; 1822 struct phm_clock_and_voltage_limits *max_limits = 1823 &table_info->max_clock_voltage_on_ac; 1824 1825 info->engine_max_clock = max_limits->sclk; 1826 info->memory_max_clock = max_limits->mclk; 1827 #endif 1828 return 0; 1829 } 1830 1831 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 1832 uint32_t *clock, 1833 PPCLK_e clock_select, 1834 bool max) 1835 { 1836 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1837 1838 if (max) 1839 *clock = data->clk_range[clock_select].ACMax; 1840 else 1841 *clock = data->clk_range[clock_select].ACMin; 1842 1843 return 0; 1844 } 1845 1846 static int vega12_get_sclks(struct pp_hwmgr *hwmgr, 1847 struct pp_clock_levels_with_latency *clocks) 1848 { 1849 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1850 uint32_t ucount; 1851 int i; 1852 struct vega12_single_dpm_table *dpm_table; 1853 1854 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1855 return -1; 1856 1857 dpm_table = &(data->dpm_table.gfx_table); 1858 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1859 MAX_NUM_CLOCKS : dpm_table->count; 1860 1861 for (i = 0; i < ucount; i++) { 1862 clocks->data[i].clocks_in_khz = 1863 dpm_table->dpm_levels[i].value * 1000; 1864 1865 clocks->data[i].latency_in_us = 0; 1866 } 1867 1868 clocks->num_levels = ucount; 1869 1870 return 0; 1871 } 1872 1873 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, 1874 uint32_t clock) 1875 { 1876 return 25; 1877 } 1878 1879 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, 1880 struct pp_clock_levels_with_latency *clocks) 1881 { 1882 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1883 uint32_t ucount; 1884 int i; 1885 struct vega12_single_dpm_table *dpm_table; 1886 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1887 return -1; 1888 1889 dpm_table = &(data->dpm_table.mem_table); 1890 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1891 MAX_NUM_CLOCKS : dpm_table->count; 1892 1893 for (i = 0; i < ucount; i++) { 1894 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; 1895 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; 1896 clocks->data[i].latency_in_us = 1897 data->mclk_latency_table.entries[i].latency = 1898 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); 1899 } 1900 1901 clocks->num_levels = data->mclk_latency_table.count = ucount; 1902 1903 return 0; 1904 } 1905 1906 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, 1907 struct pp_clock_levels_with_latency *clocks) 1908 { 1909 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1910 uint32_t ucount; 1911 int i; 1912 struct vega12_single_dpm_table *dpm_table; 1913 1914 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) 1915 return -1; 1916 1917 1918 dpm_table = &(data->dpm_table.dcef_table); 1919 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1920 MAX_NUM_CLOCKS : dpm_table->count; 1921 1922 for (i = 0; i < ucount; i++) { 1923 clocks->data[i].clocks_in_khz = 1924 dpm_table->dpm_levels[i].value * 1000; 1925 1926 clocks->data[i].latency_in_us = 0; 1927 } 1928 1929 clocks->num_levels = ucount; 1930 1931 return 0; 1932 } 1933 1934 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, 1935 struct pp_clock_levels_with_latency *clocks) 1936 { 1937 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1938 uint32_t ucount; 1939 int i; 1940 struct vega12_single_dpm_table *dpm_table; 1941 1942 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) 1943 return -1; 1944 1945 1946 dpm_table = &(data->dpm_table.soc_table); 1947 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1948 MAX_NUM_CLOCKS : dpm_table->count; 1949 1950 for (i = 0; i < ucount; i++) { 1951 clocks->data[i].clocks_in_khz = 1952 dpm_table->dpm_levels[i].value * 1000; 1953 1954 clocks->data[i].latency_in_us = 0; 1955 } 1956 1957 clocks->num_levels = ucount; 1958 1959 return 0; 1960 1961 } 1962 1963 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 1964 enum amd_pp_clock_type type, 1965 struct pp_clock_levels_with_latency *clocks) 1966 { 1967 int ret; 1968 1969 switch (type) { 1970 case amd_pp_sys_clock: 1971 ret = vega12_get_sclks(hwmgr, clocks); 1972 break; 1973 case amd_pp_mem_clock: 1974 ret = vega12_get_memclocks(hwmgr, clocks); 1975 break; 1976 case amd_pp_dcef_clock: 1977 ret = vega12_get_dcefclocks(hwmgr, clocks); 1978 break; 1979 case amd_pp_soc_clock: 1980 ret = vega12_get_socclocks(hwmgr, clocks); 1981 break; 1982 default: 1983 return -EINVAL; 1984 } 1985 1986 return ret; 1987 } 1988 1989 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 1990 enum amd_pp_clock_type type, 1991 struct pp_clock_levels_with_voltage *clocks) 1992 { 1993 clocks->num_levels = 0; 1994 1995 return 0; 1996 } 1997 1998 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 1999 void *clock_ranges) 2000 { 2001 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2002 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 2003 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 2004 2005 if (!data->registry_data.disable_water_mark && 2006 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2007 data->smu_features[GNLD_DPM_SOCCLK].supported) { 2008 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 2009 data->water_marks_bitmap |= WaterMarksExist; 2010 data->water_marks_bitmap &= ~WaterMarksLoaded; 2011 } 2012 2013 return 0; 2014 } 2015 2016 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 2017 enum pp_clock_type type, uint32_t mask) 2018 { 2019 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2020 uint32_t soft_min_level, soft_max_level, hard_min_level; 2021 int ret = 0; 2022 2023 switch (type) { 2024 case PP_SCLK: 2025 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2026 soft_max_level = mask ? (fls(mask) - 1) : 0; 2027 2028 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2029 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2030 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2031 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2032 2033 ret = vega12_upload_dpm_min_level(hwmgr); 2034 PP_ASSERT_WITH_CODE(!ret, 2035 "Failed to upload boot level to lowest!", 2036 return ret); 2037 2038 ret = vega12_upload_dpm_max_level(hwmgr); 2039 PP_ASSERT_WITH_CODE(!ret, 2040 "Failed to upload dpm max level to highest!", 2041 return ret); 2042 break; 2043 2044 case PP_MCLK: 2045 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2046 soft_max_level = mask ? (fls(mask) - 1) : 0; 2047 2048 data->dpm_table.mem_table.dpm_state.soft_min_level = 2049 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2050 data->dpm_table.mem_table.dpm_state.soft_max_level = 2051 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2052 2053 ret = vega12_upload_dpm_min_level(hwmgr); 2054 PP_ASSERT_WITH_CODE(!ret, 2055 "Failed to upload boot level to lowest!", 2056 return ret); 2057 2058 ret = vega12_upload_dpm_max_level(hwmgr); 2059 PP_ASSERT_WITH_CODE(!ret, 2060 "Failed to upload dpm max level to highest!", 2061 return ret); 2062 2063 break; 2064 2065 case PP_SOCCLK: 2066 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2067 soft_max_level = mask ? (fls(mask) - 1) : 0; 2068 2069 if (soft_max_level >= data->dpm_table.soc_table.count) { 2070 pr_err("Clock level specified %d is over max allowed %d\n", 2071 soft_max_level, 2072 data->dpm_table.soc_table.count - 1); 2073 return -EINVAL; 2074 } 2075 2076 data->dpm_table.soc_table.dpm_state.soft_min_level = 2077 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2078 data->dpm_table.soc_table.dpm_state.soft_max_level = 2079 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2080 2081 ret = vega12_upload_dpm_min_level(hwmgr); 2082 PP_ASSERT_WITH_CODE(!ret, 2083 "Failed to upload boot level to lowest!", 2084 return ret); 2085 2086 ret = vega12_upload_dpm_max_level(hwmgr); 2087 PP_ASSERT_WITH_CODE(!ret, 2088 "Failed to upload dpm max level to highest!", 2089 return ret); 2090 2091 break; 2092 2093 case PP_DCEFCLK: 2094 hard_min_level = mask ? (ffs(mask) - 1) : 0; 2095 2096 if (hard_min_level >= data->dpm_table.dcef_table.count) { 2097 pr_err("Clock level specified %d is over max allowed %d\n", 2098 hard_min_level, 2099 data->dpm_table.dcef_table.count - 1); 2100 return -EINVAL; 2101 } 2102 2103 data->dpm_table.dcef_table.dpm_state.hard_min_level = 2104 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; 2105 2106 ret = vega12_upload_dpm_min_level(hwmgr); 2107 PP_ASSERT_WITH_CODE(!ret, 2108 "Failed to upload boot level to lowest!", 2109 return ret); 2110 2111 //TODO: Setting DCEFCLK max dpm level is not supported 2112 2113 break; 2114 2115 case PP_PCIE: 2116 break; 2117 2118 default: 2119 break; 2120 } 2121 2122 return 0; 2123 } 2124 2125 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 2126 { 2127 static const char *ppfeature_name[] = { 2128 "DPM_PREFETCHER", 2129 "GFXCLK_DPM", 2130 "UCLK_DPM", 2131 "SOCCLK_DPM", 2132 "UVD_DPM", 2133 "VCE_DPM", 2134 "ULV", 2135 "MP0CLK_DPM", 2136 "LINK_DPM", 2137 "DCEFCLK_DPM", 2138 "GFXCLK_DS", 2139 "SOCCLK_DS", 2140 "LCLK_DS", 2141 "PPT", 2142 "TDC", 2143 "THERMAL", 2144 "GFX_PER_CU_CG", 2145 "RM", 2146 "DCEFCLK_DS", 2147 "ACDC", 2148 "VR0HOT", 2149 "VR1HOT", 2150 "FW_CTF", 2151 "LED_DISPLAY", 2152 "FAN_CONTROL", 2153 "DIDT", 2154 "GFXOFF", 2155 "CG", 2156 "ACG"}; 2157 static const char *output_title[] = { 2158 "FEATURES", 2159 "BITMASK", 2160 "ENABLEMENT"}; 2161 uint64_t features_enabled; 2162 int i; 2163 int ret = 0; 2164 int size = 0; 2165 2166 phm_get_sysfs_buf(&buf, &size); 2167 2168 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2169 PP_ASSERT_WITH_CODE(!ret, 2170 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 2171 return ret); 2172 2173 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 2174 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 2175 output_title[0], 2176 output_title[1], 2177 output_title[2]); 2178 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 2179 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 2180 ppfeature_name[i], 2181 1ULL << i, 2182 (features_enabled & (1ULL << i)) ? "Y" : "N"); 2183 } 2184 2185 return size; 2186 } 2187 2188 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 2189 { 2190 uint64_t features_enabled; 2191 uint64_t features_to_enable; 2192 uint64_t features_to_disable; 2193 int ret = 0; 2194 2195 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 2196 return -EINVAL; 2197 2198 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2199 if (ret) 2200 return ret; 2201 2202 features_to_disable = 2203 features_enabled & ~new_ppfeature_masks; 2204 features_to_enable = 2205 ~features_enabled & new_ppfeature_masks; 2206 2207 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 2208 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 2209 2210 if (features_to_disable) { 2211 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable); 2212 if (ret) 2213 return ret; 2214 } 2215 2216 if (features_to_enable) { 2217 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable); 2218 if (ret) 2219 return ret; 2220 } 2221 2222 return 0; 2223 } 2224 2225 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 2226 { 2227 struct amdgpu_device *adev = hwmgr->adev; 2228 2229 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2230 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2231 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2232 } 2233 2234 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) 2235 { 2236 uint32_t width_level; 2237 2238 width_level = vega12_get_current_pcie_link_width_level(hwmgr); 2239 if (width_level > LINK_WIDTH_MAX) 2240 width_level = 0; 2241 2242 return link_width[width_level]; 2243 } 2244 2245 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 2246 { 2247 struct amdgpu_device *adev = hwmgr->adev; 2248 2249 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2250 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2251 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2252 } 2253 2254 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) 2255 { 2256 uint32_t speed_level; 2257 2258 speed_level = vega12_get_current_pcie_link_speed_level(hwmgr); 2259 if (speed_level > LINK_SPEED_MAX) 2260 speed_level = 0; 2261 2262 return link_speed[speed_level]; 2263 } 2264 2265 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 2266 enum pp_clock_type type, char *buf) 2267 { 2268 int i, now, size = 0; 2269 struct pp_clock_levels_with_latency clocks; 2270 2271 switch (type) { 2272 case PP_SCLK: 2273 PP_ASSERT_WITH_CODE( 2274 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0, 2275 "Attempt to get current gfx clk Failed!", 2276 return -1); 2277 2278 PP_ASSERT_WITH_CODE( 2279 vega12_get_sclks(hwmgr, &clocks) == 0, 2280 "Attempt to get gfx clk levels Failed!", 2281 return -1); 2282 for (i = 0; i < clocks.num_levels; i++) 2283 size += sprintf(buf + size, "%d: %uMhz %s\n", 2284 i, clocks.data[i].clocks_in_khz / 1000, 2285 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2286 break; 2287 2288 case PP_MCLK: 2289 PP_ASSERT_WITH_CODE( 2290 vega12_get_current_mclk_freq(hwmgr, &now) == 0, 2291 "Attempt to get current mclk freq Failed!", 2292 return -1); 2293 2294 PP_ASSERT_WITH_CODE( 2295 vega12_get_memclocks(hwmgr, &clocks) == 0, 2296 "Attempt to get memory clk levels Failed!", 2297 return -1); 2298 for (i = 0; i < clocks.num_levels; i++) 2299 size += sprintf(buf + size, "%d: %uMhz %s\n", 2300 i, clocks.data[i].clocks_in_khz / 1000, 2301 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2302 break; 2303 2304 case PP_SOCCLK: 2305 PP_ASSERT_WITH_CODE( 2306 smum_send_msg_to_smc_with_parameter(hwmgr, 2307 PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16), 2308 &now) == 0, 2309 "Attempt to get Current SOCCLK Frequency Failed!", 2310 return -EINVAL); 2311 2312 PP_ASSERT_WITH_CODE( 2313 vega12_get_socclocks(hwmgr, &clocks) == 0, 2314 "Attempt to get soc clk levels Failed!", 2315 return -1); 2316 for (i = 0; i < clocks.num_levels; i++) 2317 size += sprintf(buf + size, "%d: %uMhz %s\n", 2318 i, clocks.data[i].clocks_in_khz / 1000, 2319 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2320 break; 2321 2322 case PP_DCEFCLK: 2323 PP_ASSERT_WITH_CODE( 2324 smum_send_msg_to_smc_with_parameter(hwmgr, 2325 PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16), 2326 &now) == 0, 2327 "Attempt to get Current DCEFCLK Frequency Failed!", 2328 return -EINVAL); 2329 2330 PP_ASSERT_WITH_CODE( 2331 vega12_get_dcefclocks(hwmgr, &clocks) == 0, 2332 "Attempt to get dcef clk levels Failed!", 2333 return -1); 2334 for (i = 0; i < clocks.num_levels; i++) 2335 size += sprintf(buf + size, "%d: %uMhz %s\n", 2336 i, clocks.data[i].clocks_in_khz / 1000, 2337 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2338 break; 2339 2340 case PP_PCIE: 2341 break; 2342 2343 default: 2344 break; 2345 } 2346 return size; 2347 } 2348 2349 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 2350 { 2351 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2352 struct vega12_single_dpm_table *dpm_table; 2353 bool vblank_too_short = false; 2354 bool disable_mclk_switching; 2355 uint32_t i, latency; 2356 2357 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 2358 !hwmgr->display_config->multi_monitor_in_sync) || 2359 vblank_too_short; 2360 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 2361 2362 /* gfxclk */ 2363 dpm_table = &(data->dpm_table.gfx_table); 2364 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2365 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2366 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2367 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2368 2369 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2370 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { 2371 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2372 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2373 } 2374 2375 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2376 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2377 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2378 } 2379 2380 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2381 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2382 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2383 } 2384 } 2385 2386 /* memclk */ 2387 dpm_table = &(data->dpm_table.mem_table); 2388 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2389 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2390 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2391 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2392 2393 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2394 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { 2395 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2396 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2397 } 2398 2399 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 2400 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2401 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2402 } 2403 2404 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2405 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2406 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2407 } 2408 } 2409 2410 /* honour DAL's UCLK Hardmin */ 2411 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) 2412 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; 2413 2414 /* Hardmin is dependent on displayconfig */ 2415 if (disable_mclk_switching) { 2416 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2417 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { 2418 if (data->mclk_latency_table.entries[i].latency <= latency) { 2419 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { 2420 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; 2421 break; 2422 } 2423 } 2424 } 2425 } 2426 2427 if (hwmgr->display_config->nb_pstate_switch_disable) 2428 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2429 2430 /* vclk */ 2431 dpm_table = &(data->dpm_table.vclk_table); 2432 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2433 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2434 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2435 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2436 2437 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2438 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2439 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2440 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2441 } 2442 2443 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2444 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2445 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2446 } 2447 } 2448 2449 /* dclk */ 2450 dpm_table = &(data->dpm_table.dclk_table); 2451 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2452 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2453 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2454 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2455 2456 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2457 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2458 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2459 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2460 } 2461 2462 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2463 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2464 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2465 } 2466 } 2467 2468 /* socclk */ 2469 dpm_table = &(data->dpm_table.soc_table); 2470 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2471 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2472 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2473 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2474 2475 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2476 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { 2477 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2478 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2479 } 2480 2481 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2482 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2483 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2484 } 2485 } 2486 2487 /* eclk */ 2488 dpm_table = &(data->dpm_table.eclk_table); 2489 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2490 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2491 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2492 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2493 2494 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2495 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { 2496 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2497 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2498 } 2499 2500 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2501 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2502 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2503 } 2504 } 2505 2506 return 0; 2507 } 2508 2509 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, 2510 struct vega12_single_dpm_table *dpm_table) 2511 { 2512 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2513 int ret = 0; 2514 2515 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 2516 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 2517 "[SetUclkToHightestDpmLevel] Dpm table has no entry!", 2518 return -EINVAL); 2519 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, 2520 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", 2521 return -EINVAL); 2522 2523 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2524 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2525 PPSMC_MSG_SetHardMinByFreq, 2526 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, 2527 NULL)), 2528 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", 2529 return ret); 2530 } 2531 2532 return ret; 2533 } 2534 2535 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2536 { 2537 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2538 int ret = 0; 2539 2540 smum_send_msg_to_smc_with_parameter(hwmgr, 2541 PPSMC_MSG_NumOfDisplays, 0, 2542 NULL); 2543 2544 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr, 2545 &data->dpm_table.mem_table); 2546 2547 return ret; 2548 } 2549 2550 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2551 { 2552 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2553 int result = 0; 2554 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 2555 2556 if ((data->water_marks_bitmap & WaterMarksExist) && 2557 !(data->water_marks_bitmap & WaterMarksLoaded)) { 2558 result = smum_smc_table_manager(hwmgr, 2559 (uint8_t *)wm_table, TABLE_WATERMARKS, false); 2560 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 2561 data->water_marks_bitmap |= WaterMarksLoaded; 2562 } 2563 2564 if ((data->water_marks_bitmap & WaterMarksExist) && 2565 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2566 data->smu_features[GNLD_DPM_SOCCLK].supported) 2567 smum_send_msg_to_smc_with_parameter(hwmgr, 2568 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 2569 NULL); 2570 2571 return result; 2572 } 2573 2574 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 2575 { 2576 struct vega12_hwmgr *data = 2577 (struct vega12_hwmgr *)(hwmgr->backend); 2578 2579 if (data->smu_features[GNLD_DPM_UVD].supported) { 2580 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 2581 enable, 2582 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 2583 "Attempt to Enable/Disable DPM UVD Failed!", 2584 return -1); 2585 data->smu_features[GNLD_DPM_UVD].enabled = enable; 2586 } 2587 2588 return 0; 2589 } 2590 2591 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 2592 { 2593 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2594 2595 if (data->vce_power_gated == bgate) 2596 return; 2597 2598 data->vce_power_gated = bgate; 2599 vega12_enable_disable_vce_dpm(hwmgr, !bgate); 2600 } 2601 2602 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 2603 { 2604 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2605 2606 if (data->uvd_power_gated == bgate) 2607 return; 2608 2609 data->uvd_power_gated = bgate; 2610 vega12_enable_disable_uvd_dpm(hwmgr, !bgate); 2611 } 2612 2613 static bool 2614 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 2615 { 2616 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2617 bool is_update_required = false; 2618 2619 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 2620 is_update_required = true; 2621 2622 if (data->registry_data.gfx_clk_deep_sleep_support) { 2623 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 2624 is_update_required = true; 2625 } 2626 2627 return is_update_required; 2628 } 2629 2630 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 2631 { 2632 int tmp_result, result = 0; 2633 2634 tmp_result = vega12_disable_all_smu_features(hwmgr); 2635 PP_ASSERT_WITH_CODE((tmp_result == 0), 2636 "Failed to disable all smu features!", result = tmp_result); 2637 2638 return result; 2639 } 2640 2641 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) 2642 { 2643 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2644 int result; 2645 2646 result = vega12_disable_dpm_tasks(hwmgr); 2647 PP_ASSERT_WITH_CODE((0 == result), 2648 "[disable_dpm_tasks] Failed to disable DPM!", 2649 ); 2650 data->water_marks_bitmap &= ~(WaterMarksLoaded); 2651 2652 return result; 2653 } 2654 2655 #if 0 2656 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr, 2657 uint32_t *sclk_idx, uint32_t *mclk_idx, 2658 uint32_t min_sclk, uint32_t min_mclk) 2659 { 2660 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2661 struct vega12_dpm_table *dpm_table = &(data->dpm_table); 2662 uint32_t i; 2663 2664 for (i = 0; i < dpm_table->gfx_table.count; i++) { 2665 if (dpm_table->gfx_table.dpm_levels[i].enabled && 2666 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { 2667 *sclk_idx = i; 2668 break; 2669 } 2670 } 2671 2672 for (i = 0; i < dpm_table->mem_table.count; i++) { 2673 if (dpm_table->mem_table.dpm_levels[i].enabled && 2674 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { 2675 *mclk_idx = i; 2676 break; 2677 } 2678 } 2679 } 2680 #endif 2681 2682 #if 0 2683 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr, 2684 struct amd_pp_profile *request) 2685 { 2686 return 0; 2687 } 2688 2689 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) 2690 { 2691 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2692 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 2693 struct vega12_single_dpm_table *golden_sclk_table = 2694 &(data->golden_dpm_table.gfx_table); 2695 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 2696 int golden_value = golden_sclk_table->dpm_levels 2697 [golden_sclk_table->count - 1].value; 2698 2699 value -= golden_value; 2700 value = DIV_ROUND_UP(value * 100, golden_value); 2701 2702 return value; 2703 } 2704 2705 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2706 { 2707 return 0; 2708 } 2709 2710 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) 2711 { 2712 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2713 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 2714 struct vega12_single_dpm_table *golden_mclk_table = 2715 &(data->golden_dpm_table.mem_table); 2716 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 2717 int golden_value = golden_mclk_table->dpm_levels 2718 [golden_mclk_table->count - 1].value; 2719 2720 value -= golden_value; 2721 value = DIV_ROUND_UP(value * 100, golden_value); 2722 2723 return value; 2724 } 2725 2726 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2727 { 2728 return 0; 2729 } 2730 #endif 2731 2732 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 2733 uint32_t virtual_addr_low, 2734 uint32_t virtual_addr_hi, 2735 uint32_t mc_addr_low, 2736 uint32_t mc_addr_hi, 2737 uint32_t size) 2738 { 2739 smum_send_msg_to_smc_with_parameter(hwmgr, 2740 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 2741 virtual_addr_hi, 2742 NULL); 2743 smum_send_msg_to_smc_with_parameter(hwmgr, 2744 PPSMC_MSG_SetSystemVirtualDramAddrLow, 2745 virtual_addr_low, 2746 NULL); 2747 smum_send_msg_to_smc_with_parameter(hwmgr, 2748 PPSMC_MSG_DramLogSetDramAddrHigh, 2749 mc_addr_hi, 2750 NULL); 2751 2752 smum_send_msg_to_smc_with_parameter(hwmgr, 2753 PPSMC_MSG_DramLogSetDramAddrLow, 2754 mc_addr_low, 2755 NULL); 2756 2757 smum_send_msg_to_smc_with_parameter(hwmgr, 2758 PPSMC_MSG_DramLogSetDramSize, 2759 size, 2760 NULL); 2761 return 0; 2762 } 2763 2764 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 2765 struct PP_TemperatureRange *thermal_data) 2766 { 2767 struct vega12_hwmgr *data = 2768 (struct vega12_hwmgr *)(hwmgr->backend); 2769 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2770 2771 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 2772 2773 thermal_data->max = pp_table->TedgeLimit * 2774 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2775 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 2776 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2777 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 2778 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2779 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2780 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2781 thermal_data->mem_crit_max = pp_table->ThbmLimit * 2782 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2783 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 2784 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2785 2786 return 0; 2787 } 2788 2789 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) 2790 { 2791 struct vega12_hwmgr *data = 2792 (struct vega12_hwmgr *)(hwmgr->backend); 2793 int ret = 0; 2794 2795 if (data->gfxoff_controlled_by_driver) 2796 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL); 2797 2798 return ret; 2799 } 2800 2801 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) 2802 { 2803 struct vega12_hwmgr *data = 2804 (struct vega12_hwmgr *)(hwmgr->backend); 2805 int ret = 0; 2806 2807 if (data->gfxoff_controlled_by_driver) 2808 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL); 2809 2810 return ret; 2811 } 2812 2813 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) 2814 { 2815 if (enable) 2816 return vega12_enable_gfx_off(hwmgr); 2817 else 2818 return vega12_disable_gfx_off(hwmgr); 2819 } 2820 2821 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 2822 PHM_PerformanceLevelDesignation designation, uint32_t index, 2823 PHM_PerformanceLevel *level) 2824 { 2825 return 0; 2826 } 2827 2828 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr, 2829 enum pp_mp1_state mp1_state) 2830 { 2831 uint16_t msg; 2832 int ret; 2833 2834 switch (mp1_state) { 2835 case PP_MP1_STATE_UNLOAD: 2836 msg = PPSMC_MSG_PrepareMp1ForUnload; 2837 break; 2838 case PP_MP1_STATE_SHUTDOWN: 2839 case PP_MP1_STATE_RESET: 2840 case PP_MP1_STATE_NONE: 2841 default: 2842 return 0; 2843 } 2844 2845 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 2846 "[PrepareMp1] Failed!", 2847 return ret); 2848 2849 return 0; 2850 } 2851 2852 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) 2853 { 2854 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); 2855 2856 gpu_metrics->common_header.structure_size = 2857 sizeof(struct gpu_metrics_v1_0); 2858 gpu_metrics->common_header.format_revision = 1; 2859 gpu_metrics->common_header.content_revision = 0; 2860 2861 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2862 } 2863 2864 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr, 2865 void **table) 2866 { 2867 struct vega12_hwmgr *data = 2868 (struct vega12_hwmgr *)(hwmgr->backend); 2869 struct gpu_metrics_v1_0 *gpu_metrics = 2870 &data->gpu_metrics_table; 2871 SmuMetrics_t metrics; 2872 uint32_t fan_speed_rpm; 2873 int ret; 2874 2875 ret = vega12_get_metrics_table(hwmgr, &metrics, true); 2876 if (ret) 2877 return ret; 2878 2879 vega12_init_gpu_metrics_v1_0(gpu_metrics); 2880 2881 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2882 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2883 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2884 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2885 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2886 2887 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2888 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2889 2890 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2891 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2892 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2893 2894 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2895 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2896 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2897 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2898 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2899 2900 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2901 2902 vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); 2903 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; 2904 2905 gpu_metrics->pcie_link_width = 2906 vega12_get_current_pcie_link_width(hwmgr); 2907 gpu_metrics->pcie_link_speed = 2908 vega12_get_current_pcie_link_speed(hwmgr); 2909 2910 *table = (void *)gpu_metrics; 2911 2912 return sizeof(struct gpu_metrics_v1_0); 2913 } 2914 2915 static const struct pp_hwmgr_func vega12_hwmgr_funcs = { 2916 .backend_init = vega12_hwmgr_backend_init, 2917 .backend_fini = vega12_hwmgr_backend_fini, 2918 .asic_setup = vega12_setup_asic_task, 2919 .dynamic_state_management_enable = vega12_enable_dpm_tasks, 2920 .dynamic_state_management_disable = vega12_disable_dpm_tasks, 2921 .patch_boot_state = vega12_patch_boot_state, 2922 .get_sclk = vega12_dpm_get_sclk, 2923 .get_mclk = vega12_dpm_get_mclk, 2924 .notify_smc_display_config_after_ps_adjustment = 2925 vega12_notify_smc_display_config_after_ps_adjustment, 2926 .force_dpm_level = vega12_dpm_force_dpm_level, 2927 .stop_thermal_controller = vega12_thermal_stop_thermal_controller, 2928 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info, 2929 .reset_fan_speed_to_default = 2930 vega12_fan_ctrl_reset_fan_speed_to_default, 2931 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm, 2932 .set_fan_control_mode = vega12_set_fan_control_mode, 2933 .get_fan_control_mode = vega12_get_fan_control_mode, 2934 .read_sensor = vega12_read_sensor, 2935 .get_dal_power_level = vega12_get_dal_power_level, 2936 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency, 2937 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage, 2938 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges, 2939 .display_clock_voltage_request = vega12_display_clock_voltage_request, 2940 .force_clock_level = vega12_force_clock_level, 2941 .print_clock_levels = vega12_print_clock_levels, 2942 .apply_clocks_adjust_rules = 2943 vega12_apply_clocks_adjust_rules, 2944 .pre_display_config_changed = 2945 vega12_pre_display_configuration_changed_task, 2946 .display_config_changed = vega12_display_configuration_changed_task, 2947 .powergate_uvd = vega12_power_gate_uvd, 2948 .powergate_vce = vega12_power_gate_vce, 2949 .check_smc_update_required_for_display_configuration = 2950 vega12_check_smc_update_required_for_display_configuration, 2951 .power_off_asic = vega12_power_off_asic, 2952 .disable_smc_firmware_ctf = vega12_thermal_disable_alert, 2953 #if 0 2954 .set_power_profile_state = vega12_set_power_profile_state, 2955 .get_sclk_od = vega12_get_sclk_od, 2956 .set_sclk_od = vega12_set_sclk_od, 2957 .get_mclk_od = vega12_get_mclk_od, 2958 .set_mclk_od = vega12_set_mclk_od, 2959 #endif 2960 .notify_cac_buffer_info = vega12_notify_cac_buffer_info, 2961 .get_thermal_temperature_range = vega12_get_thermal_temperature_range, 2962 .register_irq_handlers = smu9_register_irq_handlers, 2963 .start_thermal_controller = vega12_start_thermal_controller, 2964 .powergate_gfx = vega12_gfx_off_control, 2965 .get_performance_level = vega12_get_performance_level, 2966 .get_asic_baco_capability = smu9_baco_get_capability, 2967 .get_asic_baco_state = smu9_baco_get_state, 2968 .set_asic_baco_state = vega12_baco_set_state, 2969 .get_ppfeature_status = vega12_get_ppfeature_status, 2970 .set_ppfeature_status = vega12_set_ppfeature_status, 2971 .set_mp1_state = vega12_set_mp1_state, 2972 .get_gpu_metrics = vega12_get_gpu_metrics, 2973 }; 2974 2975 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) 2976 { 2977 hwmgr->hwmgr_func = &vega12_hwmgr_funcs; 2978 hwmgr->pptable_func = &vega12_pptable_funcs; 2979 2980 return 0; 2981 } 2982