1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/slab.h> 27 28 #include "hwmgr.h" 29 #include "amd_powerplay.h" 30 #include "vega12_smumgr.h" 31 #include "hardwaremanager.h" 32 #include "ppatomfwctrl.h" 33 #include "atomfirmware.h" 34 #include "cgs_common.h" 35 #include "vega12_inc.h" 36 #include "pppcielanes.h" 37 #include "vega12_hwmgr.h" 38 #include "vega12_processpptables.h" 39 #include "vega12_pptable.h" 40 #include "vega12_thermal.h" 41 #include "vega12_ppsmc.h" 42 #include "pp_debug.h" 43 #include "amd_pcie_helpers.h" 44 #include "ppinterrupt.h" 45 #include "pp_overdriver.h" 46 #include "pp_thermal.h" 47 #include "vega12_baco.h" 48 49 #define smnPCIE_LC_SPEED_CNTL 0x11140290 50 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 51 52 #define LINK_WIDTH_MAX 6 53 #define LINK_SPEED_MAX 3 54 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; 55 static const int link_speed[] = {25, 50, 80, 160}; 56 57 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 58 enum pp_clock_type type, uint32_t mask); 59 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 60 uint32_t *clock, 61 PPCLK_e clock_select, 62 bool max); 63 64 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) 65 { 66 struct vega12_hwmgr *data = 67 (struct vega12_hwmgr *)(hwmgr->backend); 68 69 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT; 70 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT; 71 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT; 72 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT; 73 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT; 74 75 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT; 76 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 77 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 78 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 79 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 80 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 81 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 82 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 83 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 84 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 85 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 86 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 87 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT; 88 89 data->registry_data.disallowed_features = 0x0; 90 data->registry_data.od_state_in_dc_support = 0; 91 data->registry_data.thermal_support = 1; 92 data->registry_data.skip_baco_hardware = 0; 93 94 data->registry_data.log_avfs_param = 0; 95 data->registry_data.sclk_throttle_low_notification = 1; 96 data->registry_data.force_dpm_high = 0; 97 data->registry_data.stable_pstate_sclk_dpm_percentage = 75; 98 99 data->registry_data.didt_support = 0; 100 if (data->registry_data.didt_support) { 101 data->registry_data.didt_mode = 6; 102 data->registry_data.sq_ramping_support = 1; 103 data->registry_data.db_ramping_support = 0; 104 data->registry_data.td_ramping_support = 0; 105 data->registry_data.tcp_ramping_support = 0; 106 data->registry_data.dbr_ramping_support = 0; 107 data->registry_data.edc_didt_support = 1; 108 data->registry_data.gc_didt_support = 0; 109 data->registry_data.psm_didt_support = 0; 110 } 111 112 data->registry_data.pcie_lane_override = 0xff; 113 data->registry_data.pcie_speed_override = 0xff; 114 data->registry_data.pcie_clock_override = 0xffffffff; 115 data->registry_data.regulator_hot_gpio_support = 1; 116 data->registry_data.ac_dc_switch_gpio_support = 0; 117 data->registry_data.quick_transition_support = 0; 118 data->registry_data.zrpm_start_temp = 0xffff; 119 data->registry_data.zrpm_stop_temp = 0xffff; 120 data->registry_data.odn_feature_enable = 1; 121 data->registry_data.disable_water_mark = 0; 122 data->registry_data.disable_pp_tuning = 0; 123 data->registry_data.disable_xlpp_tuning = 0; 124 data->registry_data.disable_workload_policy = 0; 125 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F; 126 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919; 127 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A; 128 data->registry_data.force_workload_policy_mask = 0; 129 data->registry_data.disable_3d_fs_detection = 0; 130 data->registry_data.fps_support = 1; 131 data->registry_data.disable_auto_wattman = 1; 132 data->registry_data.auto_wattman_debug = 0; 133 data->registry_data.auto_wattman_sample_period = 100; 134 data->registry_data.auto_wattman_threshold = 50; 135 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 136 } 137 138 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) 139 { 140 struct vega12_hwmgr *data = 141 (struct vega12_hwmgr *)(hwmgr->backend); 142 struct amdgpu_device *adev = hwmgr->adev; 143 144 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE) 145 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 146 PHM_PlatformCaps_ControlVDDCI); 147 148 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 149 PHM_PlatformCaps_TablelessHardwareInterface); 150 151 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 152 PHM_PlatformCaps_EnableSMU7ThermalManagement); 153 154 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) { 155 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 156 PHM_PlatformCaps_UVDPowerGating); 157 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 158 PHM_PlatformCaps_UVDDynamicPowerGating); 159 } 160 161 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 162 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 163 PHM_PlatformCaps_VCEPowerGating); 164 165 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 166 PHM_PlatformCaps_UnTabledHardwareInterface); 167 168 if (data->registry_data.odn_feature_enable) 169 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 170 PHM_PlatformCaps_ODNinACSupport); 171 else { 172 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 173 PHM_PlatformCaps_OD6inACSupport); 174 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 175 PHM_PlatformCaps_OD6PlusinACSupport); 176 } 177 178 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 179 PHM_PlatformCaps_ActivityReporting); 180 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 181 PHM_PlatformCaps_FanSpeedInTableIsRPM); 182 183 if (data->registry_data.od_state_in_dc_support) { 184 if (data->registry_data.odn_feature_enable) 185 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 186 PHM_PlatformCaps_ODNinDCSupport); 187 else { 188 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 189 PHM_PlatformCaps_OD6inDCSupport); 190 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 191 PHM_PlatformCaps_OD6PlusinDCSupport); 192 } 193 } 194 195 if (data->registry_data.thermal_support 196 && data->registry_data.fuzzy_fan_control_support 197 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax) 198 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 199 PHM_PlatformCaps_ODFuzzyFanControlSupport); 200 201 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 202 PHM_PlatformCaps_DynamicPowerManagement); 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_SMC); 205 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 206 PHM_PlatformCaps_ThermalPolicyDelay); 207 208 if (data->registry_data.force_dpm_high) 209 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 210 PHM_PlatformCaps_ExclusiveModeAlwaysHigh); 211 212 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 213 PHM_PlatformCaps_DynamicUVDState); 214 215 if (data->registry_data.sclk_throttle_low_notification) 216 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 217 PHM_PlatformCaps_SclkThrottleLowNotification); 218 219 /* power tune caps */ 220 /* assume disabled */ 221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 222 PHM_PlatformCaps_PowerContainment); 223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 224 PHM_PlatformCaps_DiDtSupport); 225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 226 PHM_PlatformCaps_SQRamping); 227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_DBRamping); 229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 230 PHM_PlatformCaps_TDRamping); 231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 232 PHM_PlatformCaps_TCPRamping); 233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_DBRRamping); 235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 236 PHM_PlatformCaps_DiDtEDCEnable); 237 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 238 PHM_PlatformCaps_GCEDC); 239 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 240 PHM_PlatformCaps_PSM); 241 242 if (data->registry_data.didt_support) { 243 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 244 if (data->registry_data.sq_ramping_support) 245 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 246 if (data->registry_data.db_ramping_support) 247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 248 if (data->registry_data.td_ramping_support) 249 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 250 if (data->registry_data.tcp_ramping_support) 251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 252 if (data->registry_data.dbr_ramping_support) 253 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 254 if (data->registry_data.edc_didt_support) 255 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 256 if (data->registry_data.gc_didt_support) 257 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 258 if (data->registry_data.psm_didt_support) 259 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 260 } 261 262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 263 PHM_PlatformCaps_RegulatorHot); 264 265 if (data->registry_data.ac_dc_switch_gpio_support) { 266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 267 PHM_PlatformCaps_AutomaticDCTransition); 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 270 } 271 272 if (data->registry_data.quick_transition_support) { 273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 274 PHM_PlatformCaps_AutomaticDCTransition); 275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme); 277 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 278 PHM_PlatformCaps_Falcon_QuickTransition); 279 } 280 281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) { 282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 283 PHM_PlatformCaps_LowestUclkReservedForUlv); 284 if (data->lowest_uclk_reserved_for_ulv == 1) 285 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 286 PHM_PlatformCaps_LowestUclkReservedForUlv); 287 } 288 289 if (data->registry_data.custom_fan_support) 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_CustomFanControlSupport); 292 293 return 0; 294 } 295 296 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) 297 { 298 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 299 struct amdgpu_device *adev = hwmgr->adev; 300 uint32_t top32, bottom32; 301 int i; 302 303 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 304 FEATURE_DPM_PREFETCHER_BIT; 305 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 306 FEATURE_DPM_GFXCLK_BIT; 307 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 308 FEATURE_DPM_UCLK_BIT; 309 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 310 FEATURE_DPM_SOCCLK_BIT; 311 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 312 FEATURE_DPM_UVD_BIT; 313 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 314 FEATURE_DPM_VCE_BIT; 315 data->smu_features[GNLD_ULV].smu_feature_id = 316 FEATURE_ULV_BIT; 317 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 318 FEATURE_DPM_MP0CLK_BIT; 319 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 320 FEATURE_DPM_LINK_BIT; 321 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 322 FEATURE_DPM_DCEFCLK_BIT; 323 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 324 FEATURE_DS_GFXCLK_BIT; 325 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 326 FEATURE_DS_SOCCLK_BIT; 327 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 328 FEATURE_DS_LCLK_BIT; 329 data->smu_features[GNLD_PPT].smu_feature_id = 330 FEATURE_PPT_BIT; 331 data->smu_features[GNLD_TDC].smu_feature_id = 332 FEATURE_TDC_BIT; 333 data->smu_features[GNLD_THERMAL].smu_feature_id = 334 FEATURE_THERMAL_BIT; 335 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 336 FEATURE_GFX_PER_CU_CG_BIT; 337 data->smu_features[GNLD_RM].smu_feature_id = 338 FEATURE_RM_BIT; 339 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 340 FEATURE_DS_DCEFCLK_BIT; 341 data->smu_features[GNLD_ACDC].smu_feature_id = 342 FEATURE_ACDC_BIT; 343 data->smu_features[GNLD_VR0HOT].smu_feature_id = 344 FEATURE_VR0HOT_BIT; 345 data->smu_features[GNLD_VR1HOT].smu_feature_id = 346 FEATURE_VR1HOT_BIT; 347 data->smu_features[GNLD_FW_CTF].smu_feature_id = 348 FEATURE_FW_CTF_BIT; 349 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 350 FEATURE_LED_DISPLAY_BIT; 351 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 352 FEATURE_FAN_CONTROL_BIT; 353 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 354 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT; 355 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT; 356 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 357 358 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 359 data->smu_features[i].smu_feature_bitmap = 360 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id); 361 data->smu_features[i].allowed = 362 ((data->registry_data.disallowed_features >> i) & 1) ? 363 false : true; 364 } 365 366 /* Get the SN to turn into a Unique ID */ 367 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 368 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 369 370 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 371 } 372 373 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 374 { 375 return 0; 376 } 377 378 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 379 { 380 kfree(hwmgr->backend); 381 hwmgr->backend = NULL; 382 383 return 0; 384 } 385 386 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 387 { 388 int result = 0; 389 struct vega12_hwmgr *data; 390 struct amdgpu_device *adev = hwmgr->adev; 391 392 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL); 393 if (data == NULL) 394 return -ENOMEM; 395 396 hwmgr->backend = data; 397 398 vega12_set_default_registry_data(hwmgr); 399 400 data->disable_dpm_mask = 0xff; 401 data->workload_mask = 0xff; 402 403 /* need to set voltage control types before EVV patching */ 404 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE; 405 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE; 406 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE; 407 408 data->water_marks_bitmap = 0; 409 data->avfs_exist = false; 410 411 vega12_set_features_platform_caps(hwmgr); 412 413 vega12_init_dpm_defaults(hwmgr); 414 415 /* Parse pptable data read from VBIOS */ 416 vega12_set_private_data_based_on_pptable(hwmgr); 417 418 data->is_tlu_enabled = false; 419 420 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 421 VEGA12_MAX_HARDWARE_POWERLEVELS; 422 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 423 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 424 425 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 426 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 427 hwmgr->platform_descriptor.clockStep.engineClock = 500; 428 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 429 430 data->total_active_cus = adev->gfx.cu_info.number; 431 /* Setup default Overdrive Fan control settings */ 432 data->odn_fan_table.target_fan_speed = 433 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 434 data->odn_fan_table.target_temperature = 435 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature; 436 data->odn_fan_table.min_performance_clock = 437 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit; 438 data->odn_fan_table.min_fan_limit = 439 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit * 440 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 441 442 if (hwmgr->feature_mask & PP_GFXOFF_MASK) 443 data->gfxoff_controlled_by_driver = true; 444 else 445 data->gfxoff_controlled_by_driver = false; 446 447 return result; 448 } 449 450 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) 451 { 452 struct vega12_hwmgr *data = 453 (struct vega12_hwmgr *)(hwmgr->backend); 454 455 data->low_sclk_interrupt_threshold = 0; 456 457 return 0; 458 } 459 460 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) 461 { 462 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr), 463 "Failed to init sclk threshold!", 464 return -EINVAL); 465 466 return 0; 467 } 468 469 /* 470 * @fn vega12_init_dpm_state 471 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 472 * 473 * @param dpm_state - the address of the DPM Table to initiailize. 474 * @return None. 475 */ 476 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) 477 { 478 dpm_state->soft_min_level = 0x0; 479 dpm_state->soft_max_level = 0xffff; 480 dpm_state->hard_min_level = 0x0; 481 dpm_state->hard_max_level = 0xffff; 482 } 483 484 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr) 485 { 486 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 487 struct vega12_hwmgr *data = 488 (struct vega12_hwmgr *)(hwmgr->backend); 489 uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg; 490 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 491 int i; 492 int ret; 493 494 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 495 pcie_gen = 3; 496 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 497 pcie_gen = 2; 498 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 499 pcie_gen = 1; 500 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 501 pcie_gen = 0; 502 503 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 504 pcie_width = 6; 505 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 506 pcie_width = 5; 507 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 508 pcie_width = 4; 509 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 510 pcie_width = 3; 511 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 512 pcie_width = 2; 513 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 514 pcie_width = 1; 515 516 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1 517 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4 518 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32 519 */ 520 for (i = 0; i < NUM_LINK_LEVELS; i++) { 521 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen : 522 pp_table->PcieGenSpeed[i]; 523 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width : 524 pp_table->PcieLaneCount[i]; 525 526 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg != 527 pp_table->PcieLaneCount[i]) { 528 smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg; 529 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 530 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 531 NULL); 532 PP_ASSERT_WITH_CODE(!ret, 533 "[OverridePcieParameters] Attempt to override pcie params failed!", 534 return ret); 535 } 536 537 /* update the pptable */ 538 pp_table->PcieGenSpeed[i] = pcie_gen_arg; 539 pp_table->PcieLaneCount[i] = pcie_width_arg; 540 } 541 542 /* override to the highest if it's disabled from ppfeaturmask */ 543 if (data->registry_data.pcie_dpm_key_disabled) { 544 for (i = 0; i < NUM_LINK_LEVELS; i++) { 545 smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width; 546 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 547 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg, 548 NULL); 549 PP_ASSERT_WITH_CODE(!ret, 550 "[OverridePcieParameters] Attempt to override pcie params failed!", 551 return ret); 552 553 pp_table->PcieGenSpeed[i] = pcie_gen; 554 pp_table->PcieLaneCount[i] = pcie_width; 555 } 556 ret = vega12_enable_smc_features(hwmgr, 557 false, 558 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap); 559 PP_ASSERT_WITH_CODE(!ret, 560 "Attempt to Disable DPM LINK Failed!", 561 return ret); 562 data->smu_features[GNLD_DPM_LINK].enabled = false; 563 data->smu_features[GNLD_DPM_LINK].supported = false; 564 } 565 return 0; 566 } 567 568 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, 569 PPCLK_e clk_id, uint32_t *num_of_levels) 570 { 571 int ret = 0; 572 573 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 574 PPSMC_MSG_GetDpmFreqByIndex, 575 (clk_id << 16 | 0xFF), 576 num_of_levels); 577 PP_ASSERT_WITH_CODE(!ret, 578 "[GetNumOfDpmLevel] failed to get dpm levels!", 579 return ret); 580 581 return ret; 582 } 583 584 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, 585 PPCLK_e clkID, uint32_t index, uint32_t *clock) 586 { 587 /* 588 *SMU expects the Clock ID to be in the top 16 bits. 589 *Lower 16 bits specify the level 590 */ 591 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 592 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index), 593 clock) == 0, 594 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", 595 return -EINVAL); 596 597 return 0; 598 } 599 600 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, 601 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) 602 { 603 int ret = 0; 604 uint32_t i, num_of_levels, clk; 605 606 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels); 607 PP_ASSERT_WITH_CODE(!ret, 608 "[SetupSingleDpmTable] failed to get clk levels!", 609 return ret); 610 611 dpm_table->count = num_of_levels; 612 613 for (i = 0; i < num_of_levels; i++) { 614 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk); 615 PP_ASSERT_WITH_CODE(!ret, 616 "[SetupSingleDpmTable] failed to get clk of specific level!", 617 return ret); 618 dpm_table->dpm_levels[i].value = clk; 619 dpm_table->dpm_levels[i].enabled = true; 620 } 621 622 return ret; 623 } 624 625 /* 626 * This function is to initialize all DPM state tables 627 * for SMU based on the dependency table. 628 * Dynamic state patching function will then trim these 629 * state tables to the allowed range based 630 * on the power policy or external client requests, 631 * such as UVD request, etc. 632 */ 633 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 634 { 635 636 struct vega12_hwmgr *data = 637 (struct vega12_hwmgr *)(hwmgr->backend); 638 struct vega12_single_dpm_table *dpm_table; 639 int ret = 0; 640 641 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); 642 643 /* socclk */ 644 dpm_table = &(data->dpm_table.soc_table); 645 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 646 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); 647 PP_ASSERT_WITH_CODE(!ret, 648 "[SetupDefaultDpmTable] failed to get socclk dpm levels!", 649 return ret); 650 } else { 651 dpm_table->count = 1; 652 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; 653 } 654 vega12_init_dpm_state(&(dpm_table->dpm_state)); 655 656 /* gfxclk */ 657 dpm_table = &(data->dpm_table.gfx_table); 658 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 659 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); 660 PP_ASSERT_WITH_CODE(!ret, 661 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!", 662 return ret); 663 } else { 664 dpm_table->count = 1; 665 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; 666 } 667 vega12_init_dpm_state(&(dpm_table->dpm_state)); 668 669 /* memclk */ 670 dpm_table = &(data->dpm_table.mem_table); 671 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 672 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); 673 PP_ASSERT_WITH_CODE(!ret, 674 "[SetupDefaultDpmTable] failed to get memclk dpm levels!", 675 return ret); 676 } else { 677 dpm_table->count = 1; 678 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100; 679 } 680 vega12_init_dpm_state(&(dpm_table->dpm_state)); 681 682 /* eclk */ 683 dpm_table = &(data->dpm_table.eclk_table); 684 if (data->smu_features[GNLD_DPM_VCE].enabled) { 685 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK); 686 PP_ASSERT_WITH_CODE(!ret, 687 "[SetupDefaultDpmTable] failed to get eclk dpm levels!", 688 return ret); 689 } else { 690 dpm_table->count = 1; 691 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100; 692 } 693 vega12_init_dpm_state(&(dpm_table->dpm_state)); 694 695 /* vclk */ 696 dpm_table = &(data->dpm_table.vclk_table); 697 if (data->smu_features[GNLD_DPM_UVD].enabled) { 698 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK); 699 PP_ASSERT_WITH_CODE(!ret, 700 "[SetupDefaultDpmTable] failed to get vclk dpm levels!", 701 return ret); 702 } else { 703 dpm_table->count = 1; 704 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100; 705 } 706 vega12_init_dpm_state(&(dpm_table->dpm_state)); 707 708 /* dclk */ 709 dpm_table = &(data->dpm_table.dclk_table); 710 if (data->smu_features[GNLD_DPM_UVD].enabled) { 711 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK); 712 PP_ASSERT_WITH_CODE(!ret, 713 "[SetupDefaultDpmTable] failed to get dclk dpm levels!", 714 return ret); 715 } else { 716 dpm_table->count = 1; 717 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100; 718 } 719 vega12_init_dpm_state(&(dpm_table->dpm_state)); 720 721 /* dcefclk */ 722 dpm_table = &(data->dpm_table.dcef_table); 723 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 724 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK); 725 PP_ASSERT_WITH_CODE(!ret, 726 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!", 727 return ret); 728 } else { 729 dpm_table->count = 1; 730 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100; 731 } 732 vega12_init_dpm_state(&(dpm_table->dpm_state)); 733 734 /* pixclk */ 735 dpm_table = &(data->dpm_table.pixel_table); 736 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 737 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK); 738 PP_ASSERT_WITH_CODE(!ret, 739 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!", 740 return ret); 741 } else 742 dpm_table->count = 0; 743 vega12_init_dpm_state(&(dpm_table->dpm_state)); 744 745 /* dispclk */ 746 dpm_table = &(data->dpm_table.display_table); 747 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 748 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); 749 PP_ASSERT_WITH_CODE(!ret, 750 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!", 751 return ret); 752 } else 753 dpm_table->count = 0; 754 vega12_init_dpm_state(&(dpm_table->dpm_state)); 755 756 /* phyclk */ 757 dpm_table = &(data->dpm_table.phy_table); 758 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 759 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK); 760 PP_ASSERT_WITH_CODE(!ret, 761 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!", 762 return ret); 763 } else 764 dpm_table->count = 0; 765 vega12_init_dpm_state(&(dpm_table->dpm_state)); 766 767 /* save a copy of the default DPM table */ 768 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 769 sizeof(struct vega12_dpm_table)); 770 771 return 0; 772 } 773 774 #if 0 775 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) 776 { 777 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 778 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 779 uint32_t min_level; 780 781 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; 782 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; 783 784 /* Optimize compute power profile: Use only highest 785 * 2 power levels (if more than 2 are available) 786 */ 787 if (dpm_table->count > 2) 788 min_level = dpm_table->count - 2; 789 else if (dpm_table->count == 2) 790 min_level = 1; 791 else 792 min_level = 0; 793 794 hwmgr->default_compute_power_profile.min_sclk = 795 dpm_table->dpm_levels[min_level].value; 796 797 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; 798 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; 799 800 return 0; 801 } 802 #endif 803 804 /** 805 * vega12_init_smc_table - Initializes the SMC table and uploads it 806 * 807 * @hwmgr: the address of the powerplay hardware manager. 808 * return: always 0 809 */ 810 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) 811 { 812 int result; 813 struct vega12_hwmgr *data = 814 (struct vega12_hwmgr *)(hwmgr->backend); 815 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 816 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 817 struct phm_ppt_v3_information *pptable_information = 818 (struct phm_ppt_v3_information *)hwmgr->pptable; 819 820 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 821 if (!result) { 822 data->vbios_boot_state.vddc = boot_up_values.usVddc; 823 data->vbios_boot_state.vddci = boot_up_values.usVddci; 824 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 825 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 826 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 827 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 828 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 829 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID; 830 data->vbios_boot_state.eclock = boot_up_values.ulEClk; 831 data->vbios_boot_state.dclock = boot_up_values.ulDClk; 832 data->vbios_boot_state.vclock = boot_up_values.ulVClk; 833 smum_send_msg_to_smc_with_parameter(hwmgr, 834 PPSMC_MSG_SetMinDeepSleepDcefclk, 835 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 836 NULL); 837 } 838 839 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t)); 840 841 result = smum_smc_table_manager(hwmgr, 842 (uint8_t *)pp_table, TABLE_PPTABLE, false); 843 PP_ASSERT_WITH_CODE(!result, 844 "Failed to upload PPtable!", return result); 845 846 return 0; 847 } 848 849 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr) 850 { 851 uint32_t result; 852 853 PP_ASSERT_WITH_CODE( 854 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0, 855 "[Run_ACG_BTC] Attempt to run ACG BTC failed!", 856 return -EINVAL); 857 858 PP_ASSERT_WITH_CODE(result == 1, 859 "Failed to run ACG BTC!", return -EINVAL); 860 861 return 0; 862 } 863 864 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) 865 { 866 struct vega12_hwmgr *data = 867 (struct vega12_hwmgr *)(hwmgr->backend); 868 int i; 869 uint32_t allowed_features_low = 0, allowed_features_high = 0; 870 871 for (i = 0; i < GNLD_FEATURES_MAX; i++) 872 if (data->smu_features[i].allowed) 873 data->smu_features[i].smu_feature_id > 31 ? 874 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) : 875 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF)); 876 877 PP_ASSERT_WITH_CODE( 878 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high, 879 NULL) == 0, 880 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!", 881 return -1); 882 883 PP_ASSERT_WITH_CODE( 884 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low, 885 NULL) == 0, 886 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!", 887 return -1); 888 889 return 0; 890 } 891 892 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) 893 { 894 struct vega12_hwmgr *data = 895 (struct vega12_hwmgr *)(hwmgr->backend); 896 897 data->uvd_power_gated = true; 898 data->vce_power_gated = true; 899 900 if (data->smu_features[GNLD_DPM_UVD].enabled) 901 data->uvd_power_gated = false; 902 903 if (data->smu_features[GNLD_DPM_VCE].enabled) 904 data->vce_power_gated = false; 905 } 906 907 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) 908 { 909 struct vega12_hwmgr *data = 910 (struct vega12_hwmgr *)(hwmgr->backend); 911 uint64_t features_enabled; 912 int i; 913 bool enabled; 914 915 PP_ASSERT_WITH_CODE( 916 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0, 917 "[EnableAllSMUFeatures] Failed to enable all smu features!", 918 return -1); 919 920 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 921 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 922 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 923 data->smu_features[i].enabled = enabled; 924 data->smu_features[i].supported = enabled; 925 } 926 } 927 928 vega12_init_powergate_state(hwmgr); 929 930 return 0; 931 } 932 933 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) 934 { 935 struct vega12_hwmgr *data = 936 (struct vega12_hwmgr *)(hwmgr->backend); 937 uint64_t features_enabled; 938 int i; 939 bool enabled; 940 941 PP_ASSERT_WITH_CODE( 942 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0, 943 "[DisableAllSMUFeatures] Failed to disable all smu features!", 944 return -1); 945 946 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) { 947 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 948 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false; 949 data->smu_features[i].enabled = enabled; 950 data->smu_features[i].supported = enabled; 951 } 952 } 953 954 return 0; 955 } 956 957 static int vega12_odn_initialize_default_settings( 958 struct pp_hwmgr *hwmgr) 959 { 960 return 0; 961 } 962 963 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 964 uint32_t adjust_percent) 965 { 966 return smum_send_msg_to_smc_with_parameter(hwmgr, 967 PPSMC_MSG_OverDriveSetPercentage, adjust_percent, 968 NULL); 969 } 970 971 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) 972 { 973 int adjust_percent, result = 0; 974 975 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 976 adjust_percent = 977 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? 978 hwmgr->platform_descriptor.TDPAdjustment : 979 (-1 * hwmgr->platform_descriptor.TDPAdjustment); 980 result = vega12_set_overdrive_target_percentage(hwmgr, 981 (uint32_t)adjust_percent); 982 } 983 return result; 984 } 985 986 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, 987 PPCLK_e clkid, struct vega12_clock_range *clock) 988 { 989 /* AC Max */ 990 PP_ASSERT_WITH_CODE( 991 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16), 992 &(clock->ACMax)) == 0, 993 "[GetClockRanges] Failed to get max ac clock from SMC!", 994 return -EINVAL); 995 996 /* AC Min */ 997 PP_ASSERT_WITH_CODE( 998 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16), 999 &(clock->ACMin)) == 0, 1000 "[GetClockRanges] Failed to get min ac clock from SMC!", 1001 return -EINVAL); 1002 1003 /* DC Max */ 1004 PP_ASSERT_WITH_CODE( 1005 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16), 1006 &(clock->DCMax)) == 0, 1007 "[GetClockRanges] Failed to get max dc clock from SMC!", 1008 return -EINVAL); 1009 1010 return 0; 1011 } 1012 1013 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) 1014 { 1015 struct vega12_hwmgr *data = 1016 (struct vega12_hwmgr *)(hwmgr->backend); 1017 uint32_t i; 1018 1019 for (i = 0; i < PPCLK_COUNT; i++) 1020 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr, 1021 i, &(data->clk_range[i])), 1022 "Failed to get clk range from SMC!", 1023 return -EINVAL); 1024 1025 return 0; 1026 } 1027 1028 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1029 { 1030 int tmp_result, result = 0; 1031 1032 smum_send_msg_to_smc_with_parameter(hwmgr, 1033 PPSMC_MSG_NumOfDisplays, 0, NULL); 1034 1035 result = vega12_set_allowed_featuresmask(hwmgr); 1036 PP_ASSERT_WITH_CODE(result == 0, 1037 "[EnableDPMTasks] Failed to set allowed featuresmask!\n", 1038 return result); 1039 1040 tmp_result = vega12_init_smc_table(hwmgr); 1041 PP_ASSERT_WITH_CODE(!tmp_result, 1042 "Failed to initialize SMC table!", 1043 result = tmp_result); 1044 1045 tmp_result = vega12_run_acg_btc(hwmgr); 1046 PP_ASSERT_WITH_CODE(!tmp_result, 1047 "Failed to run ACG BTC!", 1048 result = tmp_result); 1049 1050 result = vega12_enable_all_smu_features(hwmgr); 1051 PP_ASSERT_WITH_CODE(!result, 1052 "Failed to enable all smu features!", 1053 return result); 1054 1055 result = vega12_override_pcie_parameters(hwmgr); 1056 PP_ASSERT_WITH_CODE(!result, 1057 "[EnableDPMTasks] Failed to override pcie parameters!", 1058 return result); 1059 1060 tmp_result = vega12_power_control_set_level(hwmgr); 1061 PP_ASSERT_WITH_CODE(!tmp_result, 1062 "Failed to power control set level!", 1063 result = tmp_result); 1064 1065 result = vega12_get_all_clock_ranges(hwmgr); 1066 PP_ASSERT_WITH_CODE(!result, 1067 "Failed to get all clock ranges!", 1068 return result); 1069 1070 result = vega12_odn_initialize_default_settings(hwmgr); 1071 PP_ASSERT_WITH_CODE(!result, 1072 "Failed to power control set level!", 1073 return result); 1074 1075 result = vega12_setup_default_dpm_tables(hwmgr); 1076 PP_ASSERT_WITH_CODE(!result, 1077 "Failed to setup default DPM tables!", 1078 return result); 1079 return result; 1080 } 1081 1082 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, 1083 struct pp_hw_power_state *hw_ps) 1084 { 1085 return 0; 1086 } 1087 1088 static uint32_t vega12_find_lowest_dpm_level( 1089 struct vega12_single_dpm_table *table) 1090 { 1091 uint32_t i; 1092 1093 for (i = 0; i < table->count; i++) { 1094 if (table->dpm_levels[i].enabled) 1095 break; 1096 } 1097 1098 if (i >= table->count) { 1099 i = 0; 1100 table->dpm_levels[i].enabled = true; 1101 } 1102 1103 return i; 1104 } 1105 1106 static uint32_t vega12_find_highest_dpm_level( 1107 struct vega12_single_dpm_table *table) 1108 { 1109 int32_t i = 0; 1110 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER, 1111 "[FindHighestDPMLevel] DPM Table has too many entries!", 1112 return MAX_REGULAR_DPM_NUMBER - 1); 1113 1114 for (i = table->count - 1; i >= 0; i--) { 1115 if (table->dpm_levels[i].enabled) 1116 break; 1117 } 1118 1119 if (i < 0) { 1120 i = 0; 1121 table->dpm_levels[i].enabled = true; 1122 } 1123 1124 return (uint32_t)i; 1125 } 1126 1127 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) 1128 { 1129 struct vega12_hwmgr *data = hwmgr->backend; 1130 uint32_t min_freq; 1131 int ret = 0; 1132 1133 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1134 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; 1135 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1136 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1137 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff), 1138 NULL)), 1139 "Failed to set soft min gfxclk !", 1140 return ret); 1141 } 1142 1143 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1144 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; 1145 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1146 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1147 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1148 NULL)), 1149 "Failed to set soft min memclk !", 1150 return ret); 1151 1152 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; 1153 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1154 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1155 (PPCLK_UCLK << 16) | (min_freq & 0xffff), 1156 NULL)), 1157 "Failed to set hard min memclk !", 1158 return ret); 1159 } 1160 1161 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1162 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; 1163 1164 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1165 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1166 (PPCLK_VCLK << 16) | (min_freq & 0xffff), 1167 NULL)), 1168 "Failed to set soft min vclk!", 1169 return ret); 1170 1171 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; 1172 1173 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1174 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1175 (PPCLK_DCLK << 16) | (min_freq & 0xffff), 1176 NULL)), 1177 "Failed to set soft min dclk!", 1178 return ret); 1179 } 1180 1181 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1182 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; 1183 1184 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1185 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1186 (PPCLK_ECLK << 16) | (min_freq & 0xffff), 1187 NULL)), 1188 "Failed to set soft min eclk!", 1189 return ret); 1190 } 1191 1192 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1193 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; 1194 1195 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1196 hwmgr, PPSMC_MSG_SetSoftMinByFreq, 1197 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff), 1198 NULL)), 1199 "Failed to set soft min socclk!", 1200 return ret); 1201 } 1202 1203 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1204 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level; 1205 1206 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1207 hwmgr, PPSMC_MSG_SetHardMinByFreq, 1208 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff), 1209 NULL)), 1210 "Failed to set hard min dcefclk!", 1211 return ret); 1212 } 1213 1214 return ret; 1215 1216 } 1217 1218 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 1219 { 1220 struct vega12_hwmgr *data = hwmgr->backend; 1221 uint32_t max_freq; 1222 int ret = 0; 1223 1224 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { 1225 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; 1226 1227 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1228 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1229 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff), 1230 NULL)), 1231 "Failed to set soft max gfxclk!", 1232 return ret); 1233 } 1234 1235 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 1236 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; 1237 1238 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1239 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1240 (PPCLK_UCLK << 16) | (max_freq & 0xffff), 1241 NULL)), 1242 "Failed to set soft max memclk!", 1243 return ret); 1244 } 1245 1246 if (data->smu_features[GNLD_DPM_UVD].enabled) { 1247 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; 1248 1249 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1250 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1251 (PPCLK_VCLK << 16) | (max_freq & 0xffff), 1252 NULL)), 1253 "Failed to set soft max vclk!", 1254 return ret); 1255 1256 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; 1257 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1258 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1259 (PPCLK_DCLK << 16) | (max_freq & 0xffff), 1260 NULL)), 1261 "Failed to set soft max dclk!", 1262 return ret); 1263 } 1264 1265 if (data->smu_features[GNLD_DPM_VCE].enabled) { 1266 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; 1267 1268 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1269 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1270 (PPCLK_ECLK << 16) | (max_freq & 0xffff), 1271 NULL)), 1272 "Failed to set soft max eclk!", 1273 return ret); 1274 } 1275 1276 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { 1277 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; 1278 1279 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( 1280 hwmgr, PPSMC_MSG_SetSoftMaxByFreq, 1281 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff), 1282 NULL)), 1283 "Failed to set soft max socclk!", 1284 return ret); 1285 } 1286 1287 return ret; 1288 } 1289 1290 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 1291 { 1292 struct vega12_hwmgr *data = 1293 (struct vega12_hwmgr *)(hwmgr->backend); 1294 1295 if (data->smu_features[GNLD_DPM_VCE].supported) { 1296 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 1297 enable, 1298 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 1299 "Attempt to Enable/Disable DPM VCE Failed!", 1300 return -1); 1301 data->smu_features[GNLD_DPM_VCE].enabled = enable; 1302 } 1303 1304 return 0; 1305 } 1306 1307 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 1308 { 1309 struct vega12_hwmgr *data = 1310 (struct vega12_hwmgr *)(hwmgr->backend); 1311 uint32_t gfx_clk; 1312 1313 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1314 return -1; 1315 1316 if (low) 1317 PP_ASSERT_WITH_CODE( 1318 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0, 1319 "[GetSclks]: fail to get min PPCLK_GFXCLK\n", 1320 return -1); 1321 else 1322 PP_ASSERT_WITH_CODE( 1323 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0, 1324 "[GetSclks]: fail to get max PPCLK_GFXCLK\n", 1325 return -1); 1326 1327 return (gfx_clk * 100); 1328 } 1329 1330 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 1331 { 1332 struct vega12_hwmgr *data = 1333 (struct vega12_hwmgr *)(hwmgr->backend); 1334 uint32_t mem_clk; 1335 1336 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1337 return -1; 1338 1339 if (low) 1340 PP_ASSERT_WITH_CODE( 1341 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, 1342 "[GetMclks]: fail to get min PPCLK_UCLK\n", 1343 return -1); 1344 else 1345 PP_ASSERT_WITH_CODE( 1346 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, 1347 "[GetMclks]: fail to get max PPCLK_UCLK\n", 1348 return -1); 1349 1350 return (mem_clk * 100); 1351 } 1352 1353 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, 1354 SmuMetrics_t *metrics_table, 1355 bool bypass_cache) 1356 { 1357 struct vega12_hwmgr *data = 1358 (struct vega12_hwmgr *)(hwmgr->backend); 1359 int ret = 0; 1360 1361 if (bypass_cache || 1362 !data->metrics_time || 1363 time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) { 1364 ret = smum_smc_table_manager(hwmgr, 1365 (uint8_t *)(&data->metrics_table), 1366 TABLE_SMU_METRICS, 1367 true); 1368 if (ret) { 1369 pr_info("Failed to export SMU metrics table!\n"); 1370 return ret; 1371 } 1372 data->metrics_time = jiffies; 1373 } 1374 1375 if (metrics_table) 1376 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t)); 1377 1378 return ret; 1379 } 1380 1381 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) 1382 { 1383 SmuMetrics_t metrics_table; 1384 int ret = 0; 1385 1386 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1387 if (ret) 1388 return ret; 1389 1390 *query = metrics_table.CurrSocketPower << 8; 1391 1392 return ret; 1393 } 1394 1395 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) 1396 { 1397 uint32_t gfx_clk = 0; 1398 1399 *gfx_freq = 0; 1400 1401 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, 1402 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16), 1403 &gfx_clk) == 0, 1404 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!", 1405 return -EINVAL); 1406 1407 *gfx_freq = gfx_clk * 100; 1408 1409 return 0; 1410 } 1411 1412 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) 1413 { 1414 uint32_t mem_clk = 0; 1415 1416 *mclk_freq = 0; 1417 1418 PP_ASSERT_WITH_CODE( 1419 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16), 1420 &mem_clk) == 0, 1421 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!", 1422 return -EINVAL); 1423 1424 *mclk_freq = mem_clk * 100; 1425 1426 return 0; 1427 } 1428 1429 static int vega12_get_current_activity_percent( 1430 struct pp_hwmgr *hwmgr, 1431 int idx, 1432 uint32_t *activity_percent) 1433 { 1434 SmuMetrics_t metrics_table; 1435 int ret = 0; 1436 1437 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1438 if (ret) 1439 return ret; 1440 1441 switch (idx) { 1442 case AMDGPU_PP_SENSOR_GPU_LOAD: 1443 *activity_percent = metrics_table.AverageGfxActivity; 1444 break; 1445 case AMDGPU_PP_SENSOR_MEM_LOAD: 1446 *activity_percent = metrics_table.AverageUclkActivity; 1447 break; 1448 default: 1449 pr_err("Invalid index for retrieving clock activity\n"); 1450 return -EINVAL; 1451 } 1452 1453 return ret; 1454 } 1455 1456 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1457 void *value, int *size) 1458 { 1459 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1460 SmuMetrics_t metrics_table; 1461 int ret = 0; 1462 1463 switch (idx) { 1464 case AMDGPU_PP_SENSOR_GFX_SCLK: 1465 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value); 1466 if (!ret) 1467 *size = 4; 1468 break; 1469 case AMDGPU_PP_SENSOR_GFX_MCLK: 1470 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value); 1471 if (!ret) 1472 *size = 4; 1473 break; 1474 case AMDGPU_PP_SENSOR_GPU_LOAD: 1475 case AMDGPU_PP_SENSOR_MEM_LOAD: 1476 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value); 1477 if (!ret) 1478 *size = 4; 1479 break; 1480 case AMDGPU_PP_SENSOR_GPU_TEMP: 1481 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr); 1482 *size = 4; 1483 break; 1484 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 1485 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1486 if (ret) 1487 return ret; 1488 1489 *((uint32_t *)value) = metrics_table.TemperatureHotspot * 1490 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1491 *size = 4; 1492 break; 1493 case AMDGPU_PP_SENSOR_MEM_TEMP: 1494 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false); 1495 if (ret) 1496 return ret; 1497 1498 *((uint32_t *)value) = metrics_table.TemperatureHBM * 1499 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1500 *size = 4; 1501 break; 1502 case AMDGPU_PP_SENSOR_UVD_POWER: 1503 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 1504 *size = 4; 1505 break; 1506 case AMDGPU_PP_SENSOR_VCE_POWER: 1507 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 1508 *size = 4; 1509 break; 1510 case AMDGPU_PP_SENSOR_GPU_POWER: 1511 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value); 1512 if (!ret) 1513 *size = 4; 1514 break; 1515 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 1516 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value); 1517 if (!ret) 1518 *size = 8; 1519 break; 1520 default: 1521 ret = -EOPNOTSUPP; 1522 break; 1523 } 1524 return ret; 1525 } 1526 1527 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, 1528 bool has_disp) 1529 { 1530 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1531 1532 if (data->smu_features[GNLD_DPM_UCLK].enabled) 1533 return smum_send_msg_to_smc_with_parameter(hwmgr, 1534 PPSMC_MSG_SetUclkFastSwitch, 1535 has_disp ? 1 : 0, 1536 NULL); 1537 1538 return 0; 1539 } 1540 1541 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 1542 struct pp_display_clock_request *clock_req) 1543 { 1544 int result = 0; 1545 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1546 enum amd_pp_clock_type clk_type = clock_req->clock_type; 1547 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 1548 PPCLK_e clk_select = 0; 1549 uint32_t clk_request = 0; 1550 1551 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) { 1552 switch (clk_type) { 1553 case amd_pp_dcef_clock: 1554 clk_select = PPCLK_DCEFCLK; 1555 break; 1556 case amd_pp_disp_clock: 1557 clk_select = PPCLK_DISPCLK; 1558 break; 1559 case amd_pp_pixel_clock: 1560 clk_select = PPCLK_PIXCLK; 1561 break; 1562 case amd_pp_phy_clock: 1563 clk_select = PPCLK_PHYCLK; 1564 break; 1565 default: 1566 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 1567 result = -1; 1568 break; 1569 } 1570 1571 if (!result) { 1572 clk_request = (clk_select << 16) | clk_freq; 1573 result = smum_send_msg_to_smc_with_parameter(hwmgr, 1574 PPSMC_MSG_SetHardMinByFreq, 1575 clk_request, 1576 NULL); 1577 } 1578 } 1579 1580 return result; 1581 } 1582 1583 static int vega12_notify_smc_display_config_after_ps_adjustment( 1584 struct pp_hwmgr *hwmgr) 1585 { 1586 struct vega12_hwmgr *data = 1587 (struct vega12_hwmgr *)(hwmgr->backend); 1588 struct PP_Clocks min_clocks = {0}; 1589 struct pp_display_clock_request clock_req; 1590 1591 if ((hwmgr->display_config->num_display > 1) && 1592 !hwmgr->display_config->multi_monitor_in_sync && 1593 !hwmgr->display_config->nb_pstate_switch_disable) 1594 vega12_notify_smc_display_change(hwmgr, false); 1595 else 1596 vega12_notify_smc_display_change(hwmgr, true); 1597 1598 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 1599 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 1600 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 1601 1602 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) { 1603 clock_req.clock_type = amd_pp_dcef_clock; 1604 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10; 1605 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) { 1606 if (data->smu_features[GNLD_DS_DCEFCLK].supported) 1607 PP_ASSERT_WITH_CODE( 1608 !smum_send_msg_to_smc_with_parameter( 1609 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 1610 min_clocks.dcefClockInSR /100, 1611 NULL), 1612 "Attempt to set divider for DCEFCLK Failed!", 1613 return -1); 1614 } else { 1615 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 1616 } 1617 } 1618 1619 return 0; 1620 } 1621 1622 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) 1623 { 1624 struct vega12_hwmgr *data = 1625 (struct vega12_hwmgr *)(hwmgr->backend); 1626 1627 uint32_t soft_level; 1628 1629 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 1630 1631 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1632 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1633 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1634 1635 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table)); 1636 1637 data->dpm_table.mem_table.dpm_state.soft_min_level = 1638 data->dpm_table.mem_table.dpm_state.soft_max_level = 1639 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1640 1641 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1642 "Failed to upload boot level to highest!", 1643 return -1); 1644 1645 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1646 "Failed to upload dpm max level to highest!", 1647 return -1); 1648 1649 return 0; 1650 } 1651 1652 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) 1653 { 1654 struct vega12_hwmgr *data = 1655 (struct vega12_hwmgr *)(hwmgr->backend); 1656 uint32_t soft_level; 1657 1658 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 1659 1660 data->dpm_table.gfx_table.dpm_state.soft_min_level = 1661 data->dpm_table.gfx_table.dpm_state.soft_max_level = 1662 data->dpm_table.gfx_table.dpm_levels[soft_level].value; 1663 1664 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 1665 1666 data->dpm_table.mem_table.dpm_state.soft_min_level = 1667 data->dpm_table.mem_table.dpm_state.soft_max_level = 1668 data->dpm_table.mem_table.dpm_levels[soft_level].value; 1669 1670 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1671 "Failed to upload boot level to highest!", 1672 return -1); 1673 1674 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1675 "Failed to upload dpm max level to highest!", 1676 return -1); 1677 1678 return 0; 1679 1680 } 1681 1682 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 1683 { 1684 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr), 1685 "Failed to upload DPM Bootup Levels!", 1686 return -1); 1687 1688 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr), 1689 "Failed to upload DPM Max Levels!", 1690 return -1); 1691 1692 return 0; 1693 } 1694 1695 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 1696 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 1697 { 1698 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1699 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table); 1700 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table); 1701 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table); 1702 1703 *sclk_mask = 0; 1704 *mclk_mask = 0; 1705 *soc_mask = 0; 1706 1707 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL && 1708 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL && 1709 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) { 1710 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; 1711 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; 1712 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; 1713 } 1714 1715 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 1716 *sclk_mask = 0; 1717 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 1718 *mclk_mask = 0; 1719 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 1720 *sclk_mask = gfx_dpm_table->count - 1; 1721 *mclk_mask = mem_dpm_table->count - 1; 1722 *soc_mask = soc_dpm_table->count - 1; 1723 } 1724 1725 return 0; 1726 } 1727 1728 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 1729 { 1730 switch (mode) { 1731 case AMD_FAN_CTRL_NONE: 1732 break; 1733 case AMD_FAN_CTRL_MANUAL: 1734 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1735 vega12_fan_ctrl_stop_smc_fan_control(hwmgr); 1736 break; 1737 case AMD_FAN_CTRL_AUTO: 1738 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 1739 vega12_fan_ctrl_start_smc_fan_control(hwmgr); 1740 break; 1741 default: 1742 break; 1743 } 1744 } 1745 1746 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 1747 enum amd_dpm_forced_level level) 1748 { 1749 int ret = 0; 1750 uint32_t sclk_mask = 0; 1751 uint32_t mclk_mask = 0; 1752 uint32_t soc_mask = 0; 1753 1754 switch (level) { 1755 case AMD_DPM_FORCED_LEVEL_HIGH: 1756 ret = vega12_force_dpm_highest(hwmgr); 1757 break; 1758 case AMD_DPM_FORCED_LEVEL_LOW: 1759 ret = vega12_force_dpm_lowest(hwmgr); 1760 break; 1761 case AMD_DPM_FORCED_LEVEL_AUTO: 1762 ret = vega12_unforce_dpm_levels(hwmgr); 1763 break; 1764 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1765 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1766 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 1767 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1768 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 1769 if (ret) 1770 return ret; 1771 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 1772 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); 1773 break; 1774 case AMD_DPM_FORCED_LEVEL_MANUAL: 1775 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1776 default: 1777 break; 1778 } 1779 1780 return ret; 1781 } 1782 1783 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) 1784 { 1785 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1786 1787 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 1788 return AMD_FAN_CTRL_MANUAL; 1789 else 1790 return AMD_FAN_CTRL_AUTO; 1791 } 1792 1793 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, 1794 struct amd_pp_simple_clock_info *info) 1795 { 1796 #if 0 1797 struct phm_ppt_v2_information *table_info = 1798 (struct phm_ppt_v2_information *)hwmgr->pptable; 1799 struct phm_clock_and_voltage_limits *max_limits = 1800 &table_info->max_clock_voltage_on_ac; 1801 1802 info->engine_max_clock = max_limits->sclk; 1803 info->memory_max_clock = max_limits->mclk; 1804 #endif 1805 return 0; 1806 } 1807 1808 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, 1809 uint32_t *clock, 1810 PPCLK_e clock_select, 1811 bool max) 1812 { 1813 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1814 1815 if (max) 1816 *clock = data->clk_range[clock_select].ACMax; 1817 else 1818 *clock = data->clk_range[clock_select].ACMin; 1819 1820 return 0; 1821 } 1822 1823 static int vega12_get_sclks(struct pp_hwmgr *hwmgr, 1824 struct pp_clock_levels_with_latency *clocks) 1825 { 1826 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1827 uint32_t ucount; 1828 int i; 1829 struct vega12_single_dpm_table *dpm_table; 1830 1831 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled) 1832 return -1; 1833 1834 dpm_table = &(data->dpm_table.gfx_table); 1835 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1836 MAX_NUM_CLOCKS : dpm_table->count; 1837 1838 for (i = 0; i < ucount; i++) { 1839 clocks->data[i].clocks_in_khz = 1840 dpm_table->dpm_levels[i].value * 1000; 1841 1842 clocks->data[i].latency_in_us = 0; 1843 } 1844 1845 clocks->num_levels = ucount; 1846 1847 return 0; 1848 } 1849 1850 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, 1851 uint32_t clock) 1852 { 1853 return 25; 1854 } 1855 1856 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, 1857 struct pp_clock_levels_with_latency *clocks) 1858 { 1859 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1860 uint32_t ucount; 1861 int i; 1862 struct vega12_single_dpm_table *dpm_table; 1863 if (!data->smu_features[GNLD_DPM_UCLK].enabled) 1864 return -1; 1865 1866 dpm_table = &(data->dpm_table.mem_table); 1867 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1868 MAX_NUM_CLOCKS : dpm_table->count; 1869 1870 for (i = 0; i < ucount; i++) { 1871 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000; 1872 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; 1873 clocks->data[i].latency_in_us = 1874 data->mclk_latency_table.entries[i].latency = 1875 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value); 1876 } 1877 1878 clocks->num_levels = data->mclk_latency_table.count = ucount; 1879 1880 return 0; 1881 } 1882 1883 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, 1884 struct pp_clock_levels_with_latency *clocks) 1885 { 1886 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1887 uint32_t ucount; 1888 int i; 1889 struct vega12_single_dpm_table *dpm_table; 1890 1891 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled) 1892 return -1; 1893 1894 1895 dpm_table = &(data->dpm_table.dcef_table); 1896 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1897 MAX_NUM_CLOCKS : dpm_table->count; 1898 1899 for (i = 0; i < ucount; i++) { 1900 clocks->data[i].clocks_in_khz = 1901 dpm_table->dpm_levels[i].value * 1000; 1902 1903 clocks->data[i].latency_in_us = 0; 1904 } 1905 1906 clocks->num_levels = ucount; 1907 1908 return 0; 1909 } 1910 1911 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, 1912 struct pp_clock_levels_with_latency *clocks) 1913 { 1914 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1915 uint32_t ucount; 1916 int i; 1917 struct vega12_single_dpm_table *dpm_table; 1918 1919 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled) 1920 return -1; 1921 1922 1923 dpm_table = &(data->dpm_table.soc_table); 1924 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ? 1925 MAX_NUM_CLOCKS : dpm_table->count; 1926 1927 for (i = 0; i < ucount; i++) { 1928 clocks->data[i].clocks_in_khz = 1929 dpm_table->dpm_levels[i].value * 1000; 1930 1931 clocks->data[i].latency_in_us = 0; 1932 } 1933 1934 clocks->num_levels = ucount; 1935 1936 return 0; 1937 1938 } 1939 1940 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 1941 enum amd_pp_clock_type type, 1942 struct pp_clock_levels_with_latency *clocks) 1943 { 1944 int ret; 1945 1946 switch (type) { 1947 case amd_pp_sys_clock: 1948 ret = vega12_get_sclks(hwmgr, clocks); 1949 break; 1950 case amd_pp_mem_clock: 1951 ret = vega12_get_memclocks(hwmgr, clocks); 1952 break; 1953 case amd_pp_dcef_clock: 1954 ret = vega12_get_dcefclocks(hwmgr, clocks); 1955 break; 1956 case amd_pp_soc_clock: 1957 ret = vega12_get_socclocks(hwmgr, clocks); 1958 break; 1959 default: 1960 return -EINVAL; 1961 } 1962 1963 return ret; 1964 } 1965 1966 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 1967 enum amd_pp_clock_type type, 1968 struct pp_clock_levels_with_voltage *clocks) 1969 { 1970 clocks->num_levels = 0; 1971 1972 return 0; 1973 } 1974 1975 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 1976 void *clock_ranges) 1977 { 1978 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1979 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 1980 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 1981 1982 if (!data->registry_data.disable_water_mark && 1983 data->smu_features[GNLD_DPM_DCEFCLK].supported && 1984 data->smu_features[GNLD_DPM_SOCCLK].supported) { 1985 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 1986 data->water_marks_bitmap |= WaterMarksExist; 1987 data->water_marks_bitmap &= ~WaterMarksLoaded; 1988 } 1989 1990 return 0; 1991 } 1992 1993 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, 1994 enum pp_clock_type type, uint32_t mask) 1995 { 1996 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 1997 uint32_t soft_min_level, soft_max_level, hard_min_level; 1998 int ret = 0; 1999 2000 switch (type) { 2001 case PP_SCLK: 2002 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2003 soft_max_level = mask ? (fls(mask) - 1) : 0; 2004 2005 data->dpm_table.gfx_table.dpm_state.soft_min_level = 2006 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value; 2007 data->dpm_table.gfx_table.dpm_state.soft_max_level = 2008 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value; 2009 2010 ret = vega12_upload_dpm_min_level(hwmgr); 2011 PP_ASSERT_WITH_CODE(!ret, 2012 "Failed to upload boot level to lowest!", 2013 return ret); 2014 2015 ret = vega12_upload_dpm_max_level(hwmgr); 2016 PP_ASSERT_WITH_CODE(!ret, 2017 "Failed to upload dpm max level to highest!", 2018 return ret); 2019 break; 2020 2021 case PP_MCLK: 2022 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2023 soft_max_level = mask ? (fls(mask) - 1) : 0; 2024 2025 data->dpm_table.mem_table.dpm_state.soft_min_level = 2026 data->dpm_table.mem_table.dpm_levels[soft_min_level].value; 2027 data->dpm_table.mem_table.dpm_state.soft_max_level = 2028 data->dpm_table.mem_table.dpm_levels[soft_max_level].value; 2029 2030 ret = vega12_upload_dpm_min_level(hwmgr); 2031 PP_ASSERT_WITH_CODE(!ret, 2032 "Failed to upload boot level to lowest!", 2033 return ret); 2034 2035 ret = vega12_upload_dpm_max_level(hwmgr); 2036 PP_ASSERT_WITH_CODE(!ret, 2037 "Failed to upload dpm max level to highest!", 2038 return ret); 2039 2040 break; 2041 2042 case PP_SOCCLK: 2043 soft_min_level = mask ? (ffs(mask) - 1) : 0; 2044 soft_max_level = mask ? (fls(mask) - 1) : 0; 2045 2046 if (soft_max_level >= data->dpm_table.soc_table.count) { 2047 pr_err("Clock level specified %d is over max allowed %d\n", 2048 soft_max_level, 2049 data->dpm_table.soc_table.count - 1); 2050 return -EINVAL; 2051 } 2052 2053 data->dpm_table.soc_table.dpm_state.soft_min_level = 2054 data->dpm_table.soc_table.dpm_levels[soft_min_level].value; 2055 data->dpm_table.soc_table.dpm_state.soft_max_level = 2056 data->dpm_table.soc_table.dpm_levels[soft_max_level].value; 2057 2058 ret = vega12_upload_dpm_min_level(hwmgr); 2059 PP_ASSERT_WITH_CODE(!ret, 2060 "Failed to upload boot level to lowest!", 2061 return ret); 2062 2063 ret = vega12_upload_dpm_max_level(hwmgr); 2064 PP_ASSERT_WITH_CODE(!ret, 2065 "Failed to upload dpm max level to highest!", 2066 return ret); 2067 2068 break; 2069 2070 case PP_DCEFCLK: 2071 hard_min_level = mask ? (ffs(mask) - 1) : 0; 2072 2073 if (hard_min_level >= data->dpm_table.dcef_table.count) { 2074 pr_err("Clock level specified %d is over max allowed %d\n", 2075 hard_min_level, 2076 data->dpm_table.dcef_table.count - 1); 2077 return -EINVAL; 2078 } 2079 2080 data->dpm_table.dcef_table.dpm_state.hard_min_level = 2081 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value; 2082 2083 ret = vega12_upload_dpm_min_level(hwmgr); 2084 PP_ASSERT_WITH_CODE(!ret, 2085 "Failed to upload boot level to lowest!", 2086 return ret); 2087 2088 //TODO: Setting DCEFCLK max dpm level is not supported 2089 2090 break; 2091 2092 case PP_PCIE: 2093 break; 2094 2095 default: 2096 break; 2097 } 2098 2099 return 0; 2100 } 2101 2102 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 2103 { 2104 static const char *ppfeature_name[] = { 2105 "DPM_PREFETCHER", 2106 "GFXCLK_DPM", 2107 "UCLK_DPM", 2108 "SOCCLK_DPM", 2109 "UVD_DPM", 2110 "VCE_DPM", 2111 "ULV", 2112 "MP0CLK_DPM", 2113 "LINK_DPM", 2114 "DCEFCLK_DPM", 2115 "GFXCLK_DS", 2116 "SOCCLK_DS", 2117 "LCLK_DS", 2118 "PPT", 2119 "TDC", 2120 "THERMAL", 2121 "GFX_PER_CU_CG", 2122 "RM", 2123 "DCEFCLK_DS", 2124 "ACDC", 2125 "VR0HOT", 2126 "VR1HOT", 2127 "FW_CTF", 2128 "LED_DISPLAY", 2129 "FAN_CONTROL", 2130 "DIDT", 2131 "GFXOFF", 2132 "CG", 2133 "ACG"}; 2134 static const char *output_title[] = { 2135 "FEATURES", 2136 "BITMASK", 2137 "ENABLEMENT"}; 2138 uint64_t features_enabled; 2139 int i; 2140 int ret = 0; 2141 int size = 0; 2142 2143 phm_get_sysfs_buf(&buf, &size); 2144 2145 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2146 PP_ASSERT_WITH_CODE(!ret, 2147 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 2148 return ret); 2149 2150 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 2151 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 2152 output_title[0], 2153 output_title[1], 2154 output_title[2]); 2155 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 2156 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 2157 ppfeature_name[i], 2158 1ULL << i, 2159 (features_enabled & (1ULL << i)) ? "Y" : "N"); 2160 } 2161 2162 return size; 2163 } 2164 2165 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 2166 { 2167 uint64_t features_enabled; 2168 uint64_t features_to_enable; 2169 uint64_t features_to_disable; 2170 int ret = 0; 2171 2172 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 2173 return -EINVAL; 2174 2175 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled); 2176 if (ret) 2177 return ret; 2178 2179 features_to_disable = 2180 features_enabled & ~new_ppfeature_masks; 2181 features_to_enable = 2182 ~features_enabled & new_ppfeature_masks; 2183 2184 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 2185 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 2186 2187 if (features_to_disable) { 2188 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable); 2189 if (ret) 2190 return ret; 2191 } 2192 2193 if (features_to_enable) { 2194 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable); 2195 if (ret) 2196 return ret; 2197 } 2198 2199 return 0; 2200 } 2201 2202 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 2203 { 2204 struct amdgpu_device *adev = hwmgr->adev; 2205 2206 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 2207 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 2208 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 2209 } 2210 2211 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) 2212 { 2213 uint32_t width_level; 2214 2215 width_level = vega12_get_current_pcie_link_width_level(hwmgr); 2216 if (width_level > LINK_WIDTH_MAX) 2217 width_level = 0; 2218 2219 return link_width[width_level]; 2220 } 2221 2222 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 2223 { 2224 struct amdgpu_device *adev = hwmgr->adev; 2225 2226 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 2227 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 2228 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 2229 } 2230 2231 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) 2232 { 2233 uint32_t speed_level; 2234 2235 speed_level = vega12_get_current_pcie_link_speed_level(hwmgr); 2236 if (speed_level > LINK_SPEED_MAX) 2237 speed_level = 0; 2238 2239 return link_speed[speed_level]; 2240 } 2241 2242 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, 2243 enum pp_clock_type type, char *buf) 2244 { 2245 int i, now, size = 0; 2246 struct pp_clock_levels_with_latency clocks; 2247 2248 switch (type) { 2249 case PP_SCLK: 2250 PP_ASSERT_WITH_CODE( 2251 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0, 2252 "Attempt to get current gfx clk Failed!", 2253 return -1); 2254 2255 PP_ASSERT_WITH_CODE( 2256 vega12_get_sclks(hwmgr, &clocks) == 0, 2257 "Attempt to get gfx clk levels Failed!", 2258 return -1); 2259 for (i = 0; i < clocks.num_levels; i++) 2260 size += sprintf(buf + size, "%d: %uMhz %s\n", 2261 i, clocks.data[i].clocks_in_khz / 1000, 2262 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2263 break; 2264 2265 case PP_MCLK: 2266 PP_ASSERT_WITH_CODE( 2267 vega12_get_current_mclk_freq(hwmgr, &now) == 0, 2268 "Attempt to get current mclk freq Failed!", 2269 return -1); 2270 2271 PP_ASSERT_WITH_CODE( 2272 vega12_get_memclocks(hwmgr, &clocks) == 0, 2273 "Attempt to get memory clk levels Failed!", 2274 return -1); 2275 for (i = 0; i < clocks.num_levels; i++) 2276 size += sprintf(buf + size, "%d: %uMhz %s\n", 2277 i, clocks.data[i].clocks_in_khz / 1000, 2278 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); 2279 break; 2280 2281 case PP_SOCCLK: 2282 PP_ASSERT_WITH_CODE( 2283 smum_send_msg_to_smc_with_parameter(hwmgr, 2284 PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16), 2285 &now) == 0, 2286 "Attempt to get Current SOCCLK Frequency Failed!", 2287 return -EINVAL); 2288 2289 PP_ASSERT_WITH_CODE( 2290 vega12_get_socclocks(hwmgr, &clocks) == 0, 2291 "Attempt to get soc clk levels Failed!", 2292 return -1); 2293 for (i = 0; i < clocks.num_levels; i++) 2294 size += sprintf(buf + size, "%d: %uMhz %s\n", 2295 i, clocks.data[i].clocks_in_khz / 1000, 2296 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2297 break; 2298 2299 case PP_DCEFCLK: 2300 PP_ASSERT_WITH_CODE( 2301 smum_send_msg_to_smc_with_parameter(hwmgr, 2302 PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16), 2303 &now) == 0, 2304 "Attempt to get Current DCEFCLK Frequency Failed!", 2305 return -EINVAL); 2306 2307 PP_ASSERT_WITH_CODE( 2308 vega12_get_dcefclocks(hwmgr, &clocks) == 0, 2309 "Attempt to get dcef clk levels Failed!", 2310 return -1); 2311 for (i = 0; i < clocks.num_levels; i++) 2312 size += sprintf(buf + size, "%d: %uMhz %s\n", 2313 i, clocks.data[i].clocks_in_khz / 1000, 2314 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); 2315 break; 2316 2317 case PP_PCIE: 2318 break; 2319 2320 default: 2321 break; 2322 } 2323 return size; 2324 } 2325 2326 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 2327 { 2328 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2329 struct vega12_single_dpm_table *dpm_table; 2330 bool vblank_too_short = false; 2331 bool disable_mclk_switching; 2332 uint32_t i, latency; 2333 2334 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 2335 !hwmgr->display_config->multi_monitor_in_sync) || 2336 vblank_too_short; 2337 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 2338 2339 /* gfxclk */ 2340 dpm_table = &(data->dpm_table.gfx_table); 2341 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2342 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2343 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2344 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2345 2346 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2347 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) { 2348 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2349 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value; 2350 } 2351 2352 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2353 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2354 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2355 } 2356 2357 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2358 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2359 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2360 } 2361 } 2362 2363 /* memclk */ 2364 dpm_table = &(data->dpm_table.mem_table); 2365 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2366 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2367 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2368 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2369 2370 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2371 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) { 2372 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2373 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value; 2374 } 2375 2376 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 2377 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2378 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value; 2379 } 2380 2381 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2382 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2383 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2384 } 2385 } 2386 2387 /* honour DAL's UCLK Hardmin */ 2388 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100)) 2389 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100; 2390 2391 /* Hardmin is dependent on displayconfig */ 2392 if (disable_mclk_switching) { 2393 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2394 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { 2395 if (data->mclk_latency_table.entries[i].latency <= latency) { 2396 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) { 2397 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value; 2398 break; 2399 } 2400 } 2401 } 2402 } 2403 2404 if (hwmgr->display_config->nb_pstate_switch_disable) 2405 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2406 2407 /* vclk */ 2408 dpm_table = &(data->dpm_table.vclk_table); 2409 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2410 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2411 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2412 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2413 2414 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2415 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2416 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2417 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2418 } 2419 2420 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2421 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2422 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2423 } 2424 } 2425 2426 /* dclk */ 2427 dpm_table = &(data->dpm_table.dclk_table); 2428 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2429 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2430 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2431 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2432 2433 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2434 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) { 2435 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2436 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value; 2437 } 2438 2439 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2440 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2441 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2442 } 2443 } 2444 2445 /* socclk */ 2446 dpm_table = &(data->dpm_table.soc_table); 2447 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2448 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2449 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2450 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2451 2452 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2453 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) { 2454 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2455 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value; 2456 } 2457 2458 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2459 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2460 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2461 } 2462 } 2463 2464 /* eclk */ 2465 dpm_table = &(data->dpm_table.eclk_table); 2466 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value; 2467 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2468 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value; 2469 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2470 2471 if (PP_CAP(PHM_PlatformCaps_UMDPState)) { 2472 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) { 2473 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2474 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value; 2475 } 2476 2477 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 2478 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2479 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2480 } 2481 } 2482 2483 return 0; 2484 } 2485 2486 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, 2487 struct vega12_single_dpm_table *dpm_table) 2488 { 2489 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2490 int ret = 0; 2491 2492 if (data->smu_features[GNLD_DPM_UCLK].enabled) { 2493 PP_ASSERT_WITH_CODE(dpm_table->count > 0, 2494 "[SetUclkToHightestDpmLevel] Dpm table has no entry!", 2495 return -EINVAL); 2496 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, 2497 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!", 2498 return -EINVAL); 2499 2500 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value; 2501 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr, 2502 PPSMC_MSG_SetHardMinByFreq, 2503 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level, 2504 NULL)), 2505 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!", 2506 return ret); 2507 } 2508 2509 return ret; 2510 } 2511 2512 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2513 { 2514 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2515 int ret = 0; 2516 2517 smum_send_msg_to_smc_with_parameter(hwmgr, 2518 PPSMC_MSG_NumOfDisplays, 0, 2519 NULL); 2520 2521 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr, 2522 &data->dpm_table.mem_table); 2523 2524 return ret; 2525 } 2526 2527 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 2528 { 2529 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2530 int result = 0; 2531 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 2532 2533 if ((data->water_marks_bitmap & WaterMarksExist) && 2534 !(data->water_marks_bitmap & WaterMarksLoaded)) { 2535 result = smum_smc_table_manager(hwmgr, 2536 (uint8_t *)wm_table, TABLE_WATERMARKS, false); 2537 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 2538 data->water_marks_bitmap |= WaterMarksLoaded; 2539 } 2540 2541 if ((data->water_marks_bitmap & WaterMarksExist) && 2542 data->smu_features[GNLD_DPM_DCEFCLK].supported && 2543 data->smu_features[GNLD_DPM_SOCCLK].supported) 2544 smum_send_msg_to_smc_with_parameter(hwmgr, 2545 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 2546 NULL); 2547 2548 return result; 2549 } 2550 2551 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 2552 { 2553 struct vega12_hwmgr *data = 2554 (struct vega12_hwmgr *)(hwmgr->backend); 2555 2556 if (data->smu_features[GNLD_DPM_UVD].supported) { 2557 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr, 2558 enable, 2559 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 2560 "Attempt to Enable/Disable DPM UVD Failed!", 2561 return -1); 2562 data->smu_features[GNLD_DPM_UVD].enabled = enable; 2563 } 2564 2565 return 0; 2566 } 2567 2568 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 2569 { 2570 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2571 2572 if (data->vce_power_gated == bgate) 2573 return; 2574 2575 data->vce_power_gated = bgate; 2576 vega12_enable_disable_vce_dpm(hwmgr, !bgate); 2577 } 2578 2579 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 2580 { 2581 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2582 2583 if (data->uvd_power_gated == bgate) 2584 return; 2585 2586 data->uvd_power_gated = bgate; 2587 vega12_enable_disable_uvd_dpm(hwmgr, !bgate); 2588 } 2589 2590 static bool 2591 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 2592 { 2593 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2594 bool is_update_required = false; 2595 2596 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 2597 is_update_required = true; 2598 2599 if (data->registry_data.gfx_clk_deep_sleep_support) { 2600 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 2601 is_update_required = true; 2602 } 2603 2604 return is_update_required; 2605 } 2606 2607 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 2608 { 2609 int tmp_result, result = 0; 2610 2611 tmp_result = vega12_disable_all_smu_features(hwmgr); 2612 PP_ASSERT_WITH_CODE((tmp_result == 0), 2613 "Failed to disable all smu features!", result = tmp_result); 2614 2615 return result; 2616 } 2617 2618 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) 2619 { 2620 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2621 int result; 2622 2623 result = vega12_disable_dpm_tasks(hwmgr); 2624 PP_ASSERT_WITH_CODE((0 == result), 2625 "[disable_dpm_tasks] Failed to disable DPM!", 2626 ); 2627 data->water_marks_bitmap &= ~(WaterMarksLoaded); 2628 2629 return result; 2630 } 2631 2632 #if 0 2633 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr, 2634 uint32_t *sclk_idx, uint32_t *mclk_idx, 2635 uint32_t min_sclk, uint32_t min_mclk) 2636 { 2637 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2638 struct vega12_dpm_table *dpm_table = &(data->dpm_table); 2639 uint32_t i; 2640 2641 for (i = 0; i < dpm_table->gfx_table.count; i++) { 2642 if (dpm_table->gfx_table.dpm_levels[i].enabled && 2643 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { 2644 *sclk_idx = i; 2645 break; 2646 } 2647 } 2648 2649 for (i = 0; i < dpm_table->mem_table.count; i++) { 2650 if (dpm_table->mem_table.dpm_levels[i].enabled && 2651 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { 2652 *mclk_idx = i; 2653 break; 2654 } 2655 } 2656 } 2657 #endif 2658 2659 #if 0 2660 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr, 2661 struct amd_pp_profile *request) 2662 { 2663 return 0; 2664 } 2665 2666 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) 2667 { 2668 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2669 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 2670 struct vega12_single_dpm_table *golden_sclk_table = 2671 &(data->golden_dpm_table.gfx_table); 2672 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 2673 int golden_value = golden_sclk_table->dpm_levels 2674 [golden_sclk_table->count - 1].value; 2675 2676 value -= golden_value; 2677 value = DIV_ROUND_UP(value * 100, golden_value); 2678 2679 return value; 2680 } 2681 2682 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2683 { 2684 return 0; 2685 } 2686 2687 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) 2688 { 2689 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); 2690 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 2691 struct vega12_single_dpm_table *golden_mclk_table = 2692 &(data->golden_dpm_table.mem_table); 2693 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 2694 int golden_value = golden_mclk_table->dpm_levels 2695 [golden_mclk_table->count - 1].value; 2696 2697 value -= golden_value; 2698 value = DIV_ROUND_UP(value * 100, golden_value); 2699 2700 return value; 2701 } 2702 2703 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 2704 { 2705 return 0; 2706 } 2707 #endif 2708 2709 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 2710 uint32_t virtual_addr_low, 2711 uint32_t virtual_addr_hi, 2712 uint32_t mc_addr_low, 2713 uint32_t mc_addr_hi, 2714 uint32_t size) 2715 { 2716 smum_send_msg_to_smc_with_parameter(hwmgr, 2717 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 2718 virtual_addr_hi, 2719 NULL); 2720 smum_send_msg_to_smc_with_parameter(hwmgr, 2721 PPSMC_MSG_SetSystemVirtualDramAddrLow, 2722 virtual_addr_low, 2723 NULL); 2724 smum_send_msg_to_smc_with_parameter(hwmgr, 2725 PPSMC_MSG_DramLogSetDramAddrHigh, 2726 mc_addr_hi, 2727 NULL); 2728 2729 smum_send_msg_to_smc_with_parameter(hwmgr, 2730 PPSMC_MSG_DramLogSetDramAddrLow, 2731 mc_addr_low, 2732 NULL); 2733 2734 smum_send_msg_to_smc_with_parameter(hwmgr, 2735 PPSMC_MSG_DramLogSetDramSize, 2736 size, 2737 NULL); 2738 return 0; 2739 } 2740 2741 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 2742 struct PP_TemperatureRange *thermal_data) 2743 { 2744 struct vega12_hwmgr *data = 2745 (struct vega12_hwmgr *)(hwmgr->backend); 2746 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2747 2748 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 2749 2750 thermal_data->max = pp_table->TedgeLimit * 2751 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2752 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 2753 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2754 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 2755 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2756 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 2757 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2758 thermal_data->mem_crit_max = pp_table->ThbmLimit * 2759 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2760 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 2761 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 2762 2763 return 0; 2764 } 2765 2766 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) 2767 { 2768 struct vega12_hwmgr *data = 2769 (struct vega12_hwmgr *)(hwmgr->backend); 2770 int ret = 0; 2771 2772 if (data->gfxoff_controlled_by_driver) 2773 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL); 2774 2775 return ret; 2776 } 2777 2778 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) 2779 { 2780 struct vega12_hwmgr *data = 2781 (struct vega12_hwmgr *)(hwmgr->backend); 2782 int ret = 0; 2783 2784 if (data->gfxoff_controlled_by_driver) 2785 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL); 2786 2787 return ret; 2788 } 2789 2790 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) 2791 { 2792 if (enable) 2793 return vega12_enable_gfx_off(hwmgr); 2794 else 2795 return vega12_disable_gfx_off(hwmgr); 2796 } 2797 2798 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 2799 PHM_PerformanceLevelDesignation designation, uint32_t index, 2800 PHM_PerformanceLevel *level) 2801 { 2802 return 0; 2803 } 2804 2805 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr, 2806 enum pp_mp1_state mp1_state) 2807 { 2808 uint16_t msg; 2809 int ret; 2810 2811 switch (mp1_state) { 2812 case PP_MP1_STATE_UNLOAD: 2813 msg = PPSMC_MSG_PrepareMp1ForUnload; 2814 break; 2815 case PP_MP1_STATE_SHUTDOWN: 2816 case PP_MP1_STATE_RESET: 2817 case PP_MP1_STATE_NONE: 2818 default: 2819 return 0; 2820 } 2821 2822 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 2823 "[PrepareMp1] Failed!", 2824 return ret); 2825 2826 return 0; 2827 } 2828 2829 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) 2830 { 2831 memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0)); 2832 2833 gpu_metrics->common_header.structure_size = 2834 sizeof(struct gpu_metrics_v1_0); 2835 gpu_metrics->common_header.format_revision = 1; 2836 gpu_metrics->common_header.content_revision = 0; 2837 2838 gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); 2839 } 2840 2841 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr, 2842 void **table) 2843 { 2844 struct vega12_hwmgr *data = 2845 (struct vega12_hwmgr *)(hwmgr->backend); 2846 struct gpu_metrics_v1_0 *gpu_metrics = 2847 &data->gpu_metrics_table; 2848 SmuMetrics_t metrics; 2849 uint32_t fan_speed_rpm; 2850 int ret; 2851 2852 ret = vega12_get_metrics_table(hwmgr, &metrics, true); 2853 if (ret) 2854 return ret; 2855 2856 vega12_init_gpu_metrics_v1_0(gpu_metrics); 2857 2858 gpu_metrics->temperature_edge = metrics.TemperatureEdge; 2859 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; 2860 gpu_metrics->temperature_mem = metrics.TemperatureHBM; 2861 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; 2862 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem; 2863 2864 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; 2865 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; 2866 2867 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency; 2868 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency; 2869 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency; 2870 2871 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; 2872 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; 2873 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; 2874 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK]; 2875 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK]; 2876 2877 gpu_metrics->throttle_status = metrics.ThrottlerStatus; 2878 2879 vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm); 2880 gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm; 2881 2882 gpu_metrics->pcie_link_width = 2883 vega12_get_current_pcie_link_width(hwmgr); 2884 gpu_metrics->pcie_link_speed = 2885 vega12_get_current_pcie_link_speed(hwmgr); 2886 2887 *table = (void *)gpu_metrics; 2888 2889 return sizeof(struct gpu_metrics_v1_0); 2890 } 2891 2892 static const struct pp_hwmgr_func vega12_hwmgr_funcs = { 2893 .backend_init = vega12_hwmgr_backend_init, 2894 .backend_fini = vega12_hwmgr_backend_fini, 2895 .asic_setup = vega12_setup_asic_task, 2896 .dynamic_state_management_enable = vega12_enable_dpm_tasks, 2897 .dynamic_state_management_disable = vega12_disable_dpm_tasks, 2898 .patch_boot_state = vega12_patch_boot_state, 2899 .get_sclk = vega12_dpm_get_sclk, 2900 .get_mclk = vega12_dpm_get_mclk, 2901 .notify_smc_display_config_after_ps_adjustment = 2902 vega12_notify_smc_display_config_after_ps_adjustment, 2903 .force_dpm_level = vega12_dpm_force_dpm_level, 2904 .stop_thermal_controller = vega12_thermal_stop_thermal_controller, 2905 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info, 2906 .reset_fan_speed_to_default = 2907 vega12_fan_ctrl_reset_fan_speed_to_default, 2908 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm, 2909 .set_fan_control_mode = vega12_set_fan_control_mode, 2910 .get_fan_control_mode = vega12_get_fan_control_mode, 2911 .read_sensor = vega12_read_sensor, 2912 .get_dal_power_level = vega12_get_dal_power_level, 2913 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency, 2914 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage, 2915 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges, 2916 .display_clock_voltage_request = vega12_display_clock_voltage_request, 2917 .force_clock_level = vega12_force_clock_level, 2918 .print_clock_levels = vega12_print_clock_levels, 2919 .apply_clocks_adjust_rules = 2920 vega12_apply_clocks_adjust_rules, 2921 .pre_display_config_changed = 2922 vega12_pre_display_configuration_changed_task, 2923 .display_config_changed = vega12_display_configuration_changed_task, 2924 .powergate_uvd = vega12_power_gate_uvd, 2925 .powergate_vce = vega12_power_gate_vce, 2926 .check_smc_update_required_for_display_configuration = 2927 vega12_check_smc_update_required_for_display_configuration, 2928 .power_off_asic = vega12_power_off_asic, 2929 .disable_smc_firmware_ctf = vega12_thermal_disable_alert, 2930 #if 0 2931 .set_power_profile_state = vega12_set_power_profile_state, 2932 .get_sclk_od = vega12_get_sclk_od, 2933 .set_sclk_od = vega12_set_sclk_od, 2934 .get_mclk_od = vega12_get_mclk_od, 2935 .set_mclk_od = vega12_set_mclk_od, 2936 #endif 2937 .notify_cac_buffer_info = vega12_notify_cac_buffer_info, 2938 .get_thermal_temperature_range = vega12_get_thermal_temperature_range, 2939 .register_irq_handlers = smu9_register_irq_handlers, 2940 .start_thermal_controller = vega12_start_thermal_controller, 2941 .powergate_gfx = vega12_gfx_off_control, 2942 .get_performance_level = vega12_get_performance_level, 2943 .get_asic_baco_capability = smu9_baco_get_capability, 2944 .get_asic_baco_state = smu9_baco_get_state, 2945 .set_asic_baco_state = vega12_baco_set_state, 2946 .get_ppfeature_status = vega12_get_ppfeature_status, 2947 .set_ppfeature_status = vega12_set_ppfeature_status, 2948 .set_mp1_state = vega12_set_mp1_state, 2949 .get_gpu_metrics = vega12_get_gpu_metrics, 2950 }; 2951 2952 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) 2953 { 2954 hwmgr->hwmgr_func = &vega12_hwmgr_funcs; 2955 hwmgr->pptable_func = &vega12_pptable_funcs; 2956 2957 return 0; 2958 } 2959