1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "vega10_thermal.h" 25 #include "vega10_hwmgr.h" 26 #include "vega10_smumgr.h" 27 #include "vega10_ppsmc.h" 28 #include "vega10_inc.h" 29 #include "soc15_common.h" 30 #include "pp_debug.h" 31 32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) 33 { 34 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm); 35 return 0; 36 } 37 38 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, 39 struct phm_fan_speed_info *fan_speed_info) 40 { 41 42 if (hwmgr->thermal_controller.fanInfo.bNoFan) 43 return 0; 44 45 fan_speed_info->supports_percent_read = true; 46 fan_speed_info->supports_percent_write = true; 47 fan_speed_info->min_percent = 0; 48 fan_speed_info->max_percent = 100; 49 50 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && 51 hwmgr->thermal_controller.fanInfo. 52 ucTachometerPulsesPerRevolution) { 53 fan_speed_info->supports_rpm_read = true; 54 fan_speed_info->supports_rpm_write = true; 55 fan_speed_info->min_rpm = 56 hwmgr->thermal_controller.fanInfo.ulMinRPM; 57 fan_speed_info->max_rpm = 58 hwmgr->thermal_controller.fanInfo.ulMaxRPM; 59 } else { 60 fan_speed_info->min_rpm = 0; 61 fan_speed_info->max_rpm = 0; 62 } 63 64 return 0; 65 } 66 67 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, 68 uint32_t *speed) 69 { 70 uint32_t current_rpm; 71 uint32_t percent = 0; 72 73 if (hwmgr->thermal_controller.fanInfo.bNoFan) 74 return 0; 75 76 if (vega10_get_current_rpm(hwmgr, ¤t_rpm)) 77 return -1; 78 79 if (hwmgr->thermal_controller. 80 advanceFanControlParameters.usMaxFanRPM != 0) 81 percent = current_rpm * 100 / 82 hwmgr->thermal_controller. 83 advanceFanControlParameters.usMaxFanRPM; 84 85 *speed = percent > 100 ? 100 : percent; 86 87 return 0; 88 } 89 90 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 91 { 92 struct amdgpu_device *adev = hwmgr->adev; 93 struct vega10_hwmgr *data = hwmgr->backend; 94 uint32_t tach_period; 95 uint32_t crystal_clock_freq; 96 int result = 0; 97 98 if (hwmgr->thermal_controller.fanInfo.bNoFan) 99 return -1; 100 101 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 102 result = vega10_get_current_rpm(hwmgr, speed); 103 } else { 104 tach_period = 105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), 106 CG_TACH_STATUS, 107 TACH_PERIOD); 108 109 if (tach_period == 0) 110 return -EINVAL; 111 112 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 113 114 *speed = 60 * crystal_clock_freq * 10000 / tach_period; 115 } 116 117 return result; 118 } 119 120 /** 121 * Set Fan Speed Control to static mode, 122 * so that the user can decide what speed to use. 123 * @param hwmgr the address of the powerplay hardware manager. 124 * mode the fan control mode, 0 default, 1 by percent, 5, by RPM 125 * @exception Should always succeed. 126 */ 127 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 128 { 129 struct amdgpu_device *adev = hwmgr->adev; 130 131 if (hwmgr->fan_ctrl_is_in_default_mode) { 132 hwmgr->fan_ctrl_default_mode = 133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 134 CG_FDO_CTRL2, FDO_PWM_MODE); 135 hwmgr->tmin = 136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 137 CG_FDO_CTRL2, TMIN); 138 hwmgr->fan_ctrl_is_in_default_mode = false; 139 } 140 141 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 143 CG_FDO_CTRL2, TMIN, 0)); 144 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 146 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 147 148 return 0; 149 } 150 151 /** 152 * Reset Fan Speed Control to default mode. 153 * @param hwmgr the address of the powerplay hardware manager. 154 * @exception Should always succeed. 155 */ 156 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) 157 { 158 struct amdgpu_device *adev = hwmgr->adev; 159 160 if (!hwmgr->fan_ctrl_is_in_default_mode) { 161 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 163 CG_FDO_CTRL2, FDO_PWM_MODE, 164 hwmgr->fan_ctrl_default_mode)); 165 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 167 CG_FDO_CTRL2, TMIN, 168 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT)); 169 hwmgr->fan_ctrl_is_in_default_mode = true; 170 } 171 172 return 0; 173 } 174 175 /** 176 * @fn vega10_enable_fan_control_feature 177 * @brief Enables the SMC Fan Control Feature. 178 * 179 * @param hwmgr - the address of the powerplay hardware manager. 180 * @return 0 on success. -1 otherwise. 181 */ 182 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) 183 { 184 struct vega10_hwmgr *data = hwmgr->backend; 185 186 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 187 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( 188 hwmgr, true, 189 data->smu_features[GNLD_FAN_CONTROL]. 190 smu_feature_bitmap), 191 "Attempt to Enable FAN CONTROL feature Failed!", 192 return -1); 193 data->smu_features[GNLD_FAN_CONTROL].enabled = true; 194 } 195 196 return 0; 197 } 198 199 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr) 200 { 201 struct vega10_hwmgr *data = hwmgr->backend; 202 203 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 204 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( 205 hwmgr, false, 206 data->smu_features[GNLD_FAN_CONTROL]. 207 smu_feature_bitmap), 208 "Attempt to Enable FAN CONTROL feature Failed!", 209 return -1); 210 data->smu_features[GNLD_FAN_CONTROL].enabled = false; 211 } 212 213 return 0; 214 } 215 216 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) 217 { 218 if (hwmgr->thermal_controller.fanInfo.bNoFan) 219 return -1; 220 221 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr), 222 "Attempt to Enable SMC FAN CONTROL Feature Failed!", 223 return -1); 224 225 return 0; 226 } 227 228 229 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) 230 { 231 struct vega10_hwmgr *data = hwmgr->backend; 232 233 if (hwmgr->thermal_controller.fanInfo.bNoFan) 234 return -1; 235 236 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 237 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr), 238 "Attempt to Disable SMC FAN CONTROL Feature Failed!", 239 return -1); 240 } 241 return 0; 242 } 243 244 /** 245 * Set Fan Speed in percent. 246 * @param hwmgr the address of the powerplay hardware manager. 247 * @param speed is the percentage value (0% - 100%) to be set. 248 * @exception Fails is the 100% setting appears to be 0. 249 */ 250 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, 251 uint32_t speed) 252 { 253 struct amdgpu_device *adev = hwmgr->adev; 254 uint32_t duty100; 255 uint32_t duty; 256 uint64_t tmp64; 257 258 if (hwmgr->thermal_controller.fanInfo.bNoFan) 259 return 0; 260 261 if (speed > 100) 262 speed = 100; 263 264 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 265 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 266 267 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 268 CG_FDO_CTRL1, FMAX_DUTY100); 269 270 if (duty100 == 0) 271 return -EINVAL; 272 273 tmp64 = (uint64_t)speed * duty100; 274 do_div(tmp64, 100); 275 duty = (uint32_t)tmp64; 276 277 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 278 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 279 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 280 281 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); 282 } 283 284 /** 285 * Reset Fan Speed to default. 286 * @param hwmgr the address of the powerplay hardware manager. 287 * @exception Always succeeds. 288 */ 289 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) 290 { 291 if (hwmgr->thermal_controller.fanInfo.bNoFan) 292 return 0; 293 294 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 295 return vega10_fan_ctrl_start_smc_fan_control(hwmgr); 296 else 297 return vega10_fan_ctrl_set_default_mode(hwmgr); 298 } 299 300 /** 301 * Set Fan Speed in RPM. 302 * @param hwmgr the address of the powerplay hardware manager. 303 * @param speed is the percentage value (min - max) to be set. 304 * @exception Fails is the speed not lie between min and max. 305 */ 306 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) 307 { 308 struct amdgpu_device *adev = hwmgr->adev; 309 uint32_t tach_period; 310 uint32_t crystal_clock_freq; 311 int result = 0; 312 313 if (hwmgr->thermal_controller.fanInfo.bNoFan || 314 speed == 0 || 315 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || 316 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) 317 return -1; 318 319 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 320 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 321 322 if (!result) { 323 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 324 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 325 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 326 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 327 CG_TACH_CTRL, TARGET_PERIOD, 328 tach_period)); 329 } 330 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); 331 } 332 333 /** 334 * Reads the remote temperature from the SIslands thermal controller. 335 * 336 * @param hwmgr The address of the hardware manager. 337 */ 338 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 339 { 340 struct amdgpu_device *adev = hwmgr->adev; 341 int temp; 342 343 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); 344 345 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 346 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; 347 348 temp = temp & 0x1ff; 349 350 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 351 352 return temp; 353 } 354 355 /** 356 * Set the requested temperature range for high and low alert signals 357 * 358 * @param hwmgr The address of the hardware manager. 359 * @param range Temperature range to be programmed for 360 * high and low alert signals 361 * @exception PP_Result_BadInput if the input data is not valid. 362 */ 363 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, 364 struct PP_TemperatureRange *range) 365 { 366 struct phm_ppt_v2_information *pp_table_info = 367 (struct phm_ppt_v2_information *)(hwmgr->pptable); 368 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table; 369 struct amdgpu_device *adev = hwmgr->adev; 370 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP; 371 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP; 372 uint32_t val; 373 374 /* compare them in unit celsius degree */ 375 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) 376 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 377 378 /* 379 * As a common sense, usSoftwareShutdownTemp should be bigger 380 * than ThotspotLimit. For any invalid usSoftwareShutdownTemp, 381 * we will just use the max possible setting VEGA10_THERMAL_MAXIMUM_ALERT_TEMP 382 * to avoid false alarms. 383 */ 384 if ((tdp_table->usSoftwareShutdownTemp > 385 range->hotspot_crit_max / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)) { 386 if (high > tdp_table->usSoftwareShutdownTemp) 387 high = tdp_table->usSoftwareShutdownTemp; 388 } 389 390 if (low > high) 391 return -EINVAL; 392 393 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 394 395 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 396 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 397 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high); 398 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low); 399 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) & 400 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) & 401 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK); 402 403 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 404 405 return 0; 406 } 407 408 /** 409 * Programs thermal controller one-time setting registers 410 * 411 * @param hwmgr The address of the hardware manager. 412 */ 413 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) 414 { 415 struct amdgpu_device *adev = hwmgr->adev; 416 417 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { 418 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 419 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 420 CG_TACH_CTRL, EDGE_PER_REV, 421 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1)); 422 } 423 424 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 425 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 426 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); 427 428 return 0; 429 } 430 431 /** 432 * Enable thermal alerts on the RV770 thermal controller. 433 * 434 * @param hwmgr The address of the hardware manager. 435 */ 436 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) 437 { 438 struct amdgpu_device *adev = hwmgr->adev; 439 struct vega10_hwmgr *data = hwmgr->backend; 440 uint32_t val = 0; 441 442 if (data->smu_features[GNLD_FW_CTF].supported) { 443 if (data->smu_features[GNLD_FW_CTF].enabled) 444 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n"); 445 446 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 447 true, 448 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), 449 "Attempt to Enable FW CTF feature Failed!", 450 return -1); 451 data->smu_features[GNLD_FW_CTF].enabled = true; 452 } 453 454 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 455 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 456 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 457 458 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 459 460 return 0; 461 } 462 463 /** 464 * Disable thermal alerts on the RV770 thermal controller. 465 * @param hwmgr The address of the hardware manager. 466 */ 467 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) 468 { 469 struct amdgpu_device *adev = hwmgr->adev; 470 struct vega10_hwmgr *data = hwmgr->backend; 471 472 if (data->smu_features[GNLD_FW_CTF].supported) { 473 if (!data->smu_features[GNLD_FW_CTF].enabled) 474 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n"); 475 476 477 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 478 false, 479 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), 480 "Attempt to disable FW CTF feature Failed!", 481 return -1); 482 data->smu_features[GNLD_FW_CTF].enabled = false; 483 } 484 485 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 486 487 return 0; 488 } 489 490 /** 491 * Uninitialize the thermal controller. 492 * Currently just disables alerts. 493 * @param hwmgr The address of the hardware manager. 494 */ 495 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) 496 { 497 int result = vega10_thermal_disable_alert(hwmgr); 498 499 if (!hwmgr->thermal_controller.fanInfo.bNoFan) 500 vega10_fan_ctrl_set_default_mode(hwmgr); 501 502 return result; 503 } 504 505 /** 506 * Set up the fan table to control the fan using the SMC. 507 * @param hwmgr the address of the powerplay hardware manager. 508 * @param pInput the pointer to input data 509 * @param pOutput the pointer to output data 510 * @param pStorage the pointer to temporary storage 511 * @param Result the last failure code 512 * @return result from set temperature range routine 513 */ 514 static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 515 { 516 int ret; 517 struct vega10_hwmgr *data = hwmgr->backend; 518 PPTable_t *table = &(data->smc_state_table.pp_table); 519 520 if (!data->smu_features[GNLD_FAN_CONTROL].supported) 521 return 0; 522 523 table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller. 524 advanceFanControlParameters.usMaxFanRPM; 525 table->FanThrottlingRpm = hwmgr->thermal_controller. 526 advanceFanControlParameters.usFanRPMMaxLimit; 527 table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller. 528 advanceFanControlParameters.ulMinFanSCLKAcousticLimit); 529 table->FanTargetTemperature = hwmgr->thermal_controller. 530 advanceFanControlParameters.usTMax; 531 532 smum_send_msg_to_smc_with_parameter(hwmgr, 533 PPSMC_MSG_SetFanTemperatureTarget, 534 (uint32_t)table->FanTargetTemperature, 535 NULL); 536 537 table->FanPwmMin = hwmgr->thermal_controller. 538 advanceFanControlParameters.usPWMMin * 255 / 100; 539 table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller. 540 advanceFanControlParameters.ulTargetGfxClk); 541 table->FanGainEdge = hwmgr->thermal_controller. 542 advanceFanControlParameters.usFanGainEdge; 543 table->FanGainHotspot = hwmgr->thermal_controller. 544 advanceFanControlParameters.usFanGainHotspot; 545 table->FanGainLiquid = hwmgr->thermal_controller. 546 advanceFanControlParameters.usFanGainLiquid; 547 table->FanGainVrVddc = hwmgr->thermal_controller. 548 advanceFanControlParameters.usFanGainVrVddc; 549 table->FanGainVrMvdd = hwmgr->thermal_controller. 550 advanceFanControlParameters.usFanGainVrMvdd; 551 table->FanGainPlx = hwmgr->thermal_controller. 552 advanceFanControlParameters.usFanGainPlx; 553 table->FanGainHbm = hwmgr->thermal_controller. 554 advanceFanControlParameters.usFanGainHbm; 555 table->FanZeroRpmEnable = hwmgr->thermal_controller. 556 advanceFanControlParameters.ucEnableZeroRPM; 557 table->FanStopTemp = hwmgr->thermal_controller. 558 advanceFanControlParameters.usZeroRPMStopTemperature; 559 table->FanStartTemp = hwmgr->thermal_controller. 560 advanceFanControlParameters.usZeroRPMStartTemperature; 561 562 ret = smum_smc_table_manager(hwmgr, 563 (uint8_t *)(&(data->smc_state_table.pp_table)), 564 PPTABLE, false); 565 if (ret) 566 pr_info("Failed to update Fan Control Table in PPTable!"); 567 568 return ret; 569 } 570 571 int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) 572 { 573 struct vega10_hwmgr *data = hwmgr->backend; 574 PPTable_t *table = &(data->smc_state_table.pp_table); 575 int ret; 576 577 if (!data->smu_features[GNLD_FAN_CONTROL].supported) 578 return 0; 579 580 if (!hwmgr->thermal_controller.advanceFanControlParameters. 581 usMGpuThrottlingRPMLimit) 582 return 0; 583 584 table->FanThrottlingRpm = hwmgr->thermal_controller. 585 advanceFanControlParameters.usMGpuThrottlingRPMLimit; 586 587 ret = smum_smc_table_manager(hwmgr, 588 (uint8_t *)(&(data->smc_state_table.pp_table)), 589 PPTABLE, false); 590 if (ret) { 591 pr_info("Failed to update fan control table in pptable!"); 592 return ret; 593 } 594 595 ret = vega10_disable_fan_control_feature(hwmgr); 596 if (ret) { 597 pr_info("Attempt to disable SMC fan control feature failed!"); 598 return ret; 599 } 600 601 ret = vega10_enable_fan_control_feature(hwmgr); 602 if (ret) 603 pr_info("Attempt to enable SMC fan control feature failed!"); 604 605 return ret; 606 } 607 608 /** 609 * Start the fan control on the SMC. 610 * @param hwmgr the address of the powerplay hardware manager. 611 * @param pInput the pointer to input data 612 * @param pOutput the pointer to output data 613 * @param pStorage the pointer to temporary storage 614 * @param Result the last failure code 615 * @return result from set temperature range routine 616 */ 617 static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) 618 { 619 /* If the fantable setup has failed we could have disabled 620 * PHM_PlatformCaps_MicrocodeFanControl even after 621 * this function was included in the table. 622 * Make sure that we still think controlling the fan is OK. 623 */ 624 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 625 vega10_fan_ctrl_start_smc_fan_control(hwmgr); 626 627 return 0; 628 } 629 630 631 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr, 632 struct PP_TemperatureRange *range) 633 { 634 int ret = 0; 635 636 if (range == NULL) 637 return -EINVAL; 638 639 vega10_thermal_initialize(hwmgr); 640 ret = vega10_thermal_set_temperature_range(hwmgr, range); 641 if (ret) 642 return -EINVAL; 643 644 vega10_thermal_enable_alert(hwmgr); 645 /* We should restrict performance levels to low before we halt the SMC. 646 * On the other hand we are still in boot state when we do this 647 * so it would be pointless. 648 * If this assumption changes we have to revisit this table. 649 */ 650 ret = vega10_thermal_setup_fan_table(hwmgr); 651 if (ret) 652 return -EINVAL; 653 654 vega10_thermal_start_smc_fan_control(hwmgr); 655 656 return 0; 657 }; 658 659 660 661 662 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) 663 { 664 if (!hwmgr->thermal_controller.fanInfo.bNoFan) { 665 vega10_fan_ctrl_set_default_mode(hwmgr); 666 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 667 } 668 return 0; 669 } 670