1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "vega10_thermal.h" 25 #include "vega10_hwmgr.h" 26 #include "vega10_smumgr.h" 27 #include "vega10_ppsmc.h" 28 #include "vega10_inc.h" 29 #include "soc15_common.h" 30 #include "pp_debug.h" 31 32 static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) 33 { 34 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm); 35 return 0; 36 } 37 38 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, 39 struct phm_fan_speed_info *fan_speed_info) 40 { 41 42 if (hwmgr->thermal_controller.fanInfo.bNoFan) 43 return 0; 44 45 fan_speed_info->supports_percent_read = true; 46 fan_speed_info->supports_percent_write = true; 47 fan_speed_info->min_percent = 0; 48 fan_speed_info->max_percent = 100; 49 50 if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && 51 hwmgr->thermal_controller.fanInfo. 52 ucTachometerPulsesPerRevolution) { 53 fan_speed_info->supports_rpm_read = true; 54 fan_speed_info->supports_rpm_write = true; 55 fan_speed_info->min_rpm = 56 hwmgr->thermal_controller.fanInfo.ulMinRPM; 57 fan_speed_info->max_rpm = 58 hwmgr->thermal_controller.fanInfo.ulMaxRPM; 59 } else { 60 fan_speed_info->min_rpm = 0; 61 fan_speed_info->max_rpm = 0; 62 } 63 64 return 0; 65 } 66 67 int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, 68 uint32_t *speed) 69 { 70 uint32_t current_rpm; 71 uint32_t percent = 0; 72 73 if (hwmgr->thermal_controller.fanInfo.bNoFan) 74 return 0; 75 76 if (vega10_get_current_rpm(hwmgr, ¤t_rpm)) 77 return -1; 78 79 if (hwmgr->thermal_controller. 80 advanceFanControlParameters.usMaxFanRPM != 0) 81 percent = current_rpm * 100 / 82 hwmgr->thermal_controller. 83 advanceFanControlParameters.usMaxFanRPM; 84 85 *speed = percent > 100 ? 100 : percent; 86 87 return 0; 88 } 89 90 int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 91 { 92 struct amdgpu_device *adev = hwmgr->adev; 93 struct vega10_hwmgr *data = hwmgr->backend; 94 uint32_t tach_period; 95 uint32_t crystal_clock_freq; 96 int result = 0; 97 98 if (hwmgr->thermal_controller.fanInfo.bNoFan) 99 return -1; 100 101 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 102 result = vega10_get_current_rpm(hwmgr, speed); 103 } else { 104 tach_period = 105 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS), 106 CG_TACH_STATUS, 107 TACH_PERIOD); 108 109 if (tach_period == 0) 110 return -EINVAL; 111 112 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 113 114 *speed = 60 * crystal_clock_freq * 10000 / tach_period; 115 } 116 117 return result; 118 } 119 120 /** 121 * vega10_fan_ctrl_set_static_mode - Set Fan Speed Control to static mode, 122 * so that the user can decide what speed to use. 123 * @hwmgr: the address of the powerplay hardware manager. 124 * @mode: the fan control mode, 0 default, 1 by percent, 5, by RPM 125 * Exception: Should always succeed. 126 */ 127 int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 128 { 129 struct amdgpu_device *adev = hwmgr->adev; 130 131 if (hwmgr->fan_ctrl_is_in_default_mode) { 132 hwmgr->fan_ctrl_default_mode = 133 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 134 CG_FDO_CTRL2, FDO_PWM_MODE); 135 hwmgr->tmin = 136 REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 137 CG_FDO_CTRL2, TMIN); 138 hwmgr->fan_ctrl_is_in_default_mode = false; 139 } 140 141 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 142 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 143 CG_FDO_CTRL2, TMIN, 0)); 144 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 145 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 146 CG_FDO_CTRL2, FDO_PWM_MODE, mode)); 147 148 return 0; 149 } 150 151 /** 152 * vega10_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode. 153 * @hwmgr: the address of the powerplay hardware manager. 154 * Exception: Should always succeed. 155 */ 156 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) 157 { 158 struct amdgpu_device *adev = hwmgr->adev; 159 160 if (!hwmgr->fan_ctrl_is_in_default_mode) { 161 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 162 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 163 CG_FDO_CTRL2, FDO_PWM_MODE, 164 hwmgr->fan_ctrl_default_mode)); 165 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 166 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 167 CG_FDO_CTRL2, TMIN, 168 hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT)); 169 hwmgr->fan_ctrl_is_in_default_mode = true; 170 } 171 172 return 0; 173 } 174 175 /** 176 * vega10_enable_fan_control_feature - Enables the SMC Fan Control Feature. 177 * 178 * @hwmgr: the address of the powerplay hardware manager. 179 * Return: 0 on success. -1 otherwise. 180 */ 181 static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr) 182 { 183 struct vega10_hwmgr *data = hwmgr->backend; 184 185 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 186 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( 187 hwmgr, true, 188 data->smu_features[GNLD_FAN_CONTROL]. 189 smu_feature_bitmap), 190 "Attempt to Enable FAN CONTROL feature Failed!", 191 return -1); 192 data->smu_features[GNLD_FAN_CONTROL].enabled = true; 193 } 194 195 return 0; 196 } 197 198 static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr) 199 { 200 struct vega10_hwmgr *data = hwmgr->backend; 201 202 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 203 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features( 204 hwmgr, false, 205 data->smu_features[GNLD_FAN_CONTROL]. 206 smu_feature_bitmap), 207 "Attempt to Enable FAN CONTROL feature Failed!", 208 return -1); 209 data->smu_features[GNLD_FAN_CONTROL].enabled = false; 210 } 211 212 return 0; 213 } 214 215 int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) 216 { 217 if (hwmgr->thermal_controller.fanInfo.bNoFan) 218 return -1; 219 220 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr), 221 "Attempt to Enable SMC FAN CONTROL Feature Failed!", 222 return -1); 223 224 return 0; 225 } 226 227 228 int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) 229 { 230 struct vega10_hwmgr *data = hwmgr->backend; 231 232 if (hwmgr->thermal_controller.fanInfo.bNoFan) 233 return -1; 234 235 if (data->smu_features[GNLD_FAN_CONTROL].supported) { 236 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr), 237 "Attempt to Disable SMC FAN CONTROL Feature Failed!", 238 return -1); 239 } 240 return 0; 241 } 242 243 /** 244 * vega10_fan_ctrl_set_fan_speed_percent - Set Fan Speed in percent. 245 * @hwmgr: the address of the powerplay hardware manager. 246 * @speed: is the percentage value (0% - 100%) to be set. 247 * Exception: Fails is the 100% setting appears to be 0. 248 */ 249 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, 250 uint32_t speed) 251 { 252 struct amdgpu_device *adev = hwmgr->adev; 253 uint32_t duty100; 254 uint32_t duty; 255 uint64_t tmp64; 256 257 if (hwmgr->thermal_controller.fanInfo.bNoFan) 258 return 0; 259 260 if (speed > 100) 261 speed = 100; 262 263 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 264 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 265 266 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1), 267 CG_FDO_CTRL1, FMAX_DUTY100); 268 269 if (duty100 == 0) 270 return -EINVAL; 271 272 tmp64 = (uint64_t)speed * duty100; 273 do_div(tmp64, 100); 274 duty = (uint32_t)tmp64; 275 276 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0, 277 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0), 278 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty)); 279 280 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); 281 } 282 283 /** 284 * vega10_fan_ctrl_reset_fan_speed_to_default - Reset Fan Speed to default. 285 * @hwmgr: the address of the powerplay hardware manager. 286 * Exception: Always succeeds. 287 */ 288 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) 289 { 290 if (hwmgr->thermal_controller.fanInfo.bNoFan) 291 return 0; 292 293 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 294 return vega10_fan_ctrl_start_smc_fan_control(hwmgr); 295 else 296 return vega10_fan_ctrl_set_default_mode(hwmgr); 297 } 298 299 /** 300 * vega10_fan_ctrl_set_fan_speed_rpm - Set Fan Speed in RPM. 301 * @hwmgr: the address of the powerplay hardware manager. 302 * @speed: is the percentage value (min - max) to be set. 303 * Exception: Fails is the speed not lie between min and max. 304 */ 305 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) 306 { 307 struct amdgpu_device *adev = hwmgr->adev; 308 uint32_t tach_period; 309 uint32_t crystal_clock_freq; 310 int result = 0; 311 312 if (hwmgr->thermal_controller.fanInfo.bNoFan || 313 speed == 0 || 314 (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || 315 (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) 316 return -1; 317 318 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 319 result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 320 321 if (!result) { 322 crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 323 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); 324 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 325 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 326 CG_TACH_CTRL, TARGET_PERIOD, 327 tach_period)); 328 } 329 return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM); 330 } 331 332 /** 333 * vega10_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller. 334 * 335 * @hwmgr: The address of the hardware manager. 336 */ 337 int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 338 { 339 struct amdgpu_device *adev = hwmgr->adev; 340 int temp; 341 342 temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS); 343 344 temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 345 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; 346 347 temp = temp & 0x1ff; 348 349 temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 350 351 return temp; 352 } 353 354 /** 355 * vega10_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals 356 * 357 * @hwmgr: The address of the hardware manager. 358 * @range: Temperature range to be programmed for 359 * high and low alert signals 360 * Exception: PP_Result_BadInput if the input data is not valid. 361 */ 362 static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, 363 struct PP_TemperatureRange *range) 364 { 365 struct phm_ppt_v2_information *pp_table_info = 366 (struct phm_ppt_v2_information *)(hwmgr->pptable); 367 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table; 368 struct amdgpu_device *adev = hwmgr->adev; 369 int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP; 370 int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP; 371 uint32_t val; 372 373 /* compare them in unit celsius degree */ 374 if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) 375 low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 376 377 /* 378 * As a common sense, usSoftwareShutdownTemp should be bigger 379 * than ThotspotLimit. For any invalid usSoftwareShutdownTemp, 380 * we will just use the max possible setting VEGA10_THERMAL_MAXIMUM_ALERT_TEMP 381 * to avoid false alarms. 382 */ 383 if ((tdp_table->usSoftwareShutdownTemp > 384 range->hotspot_crit_max / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)) { 385 if (high > tdp_table->usSoftwareShutdownTemp) 386 high = tdp_table->usSoftwareShutdownTemp; 387 } 388 389 if (low > high) 390 return -EINVAL; 391 392 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL); 393 394 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5); 395 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1); 396 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high); 397 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low); 398 val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) & 399 (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) & 400 (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK); 401 402 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val); 403 404 return 0; 405 } 406 407 /** 408 * vega10_thermal_initialize - Programs thermal controller one-time setting registers 409 * 410 * @hwmgr: The address of the hardware manager. 411 */ 412 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr) 413 { 414 struct amdgpu_device *adev = hwmgr->adev; 415 416 if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { 417 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL, 418 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL), 419 CG_TACH_CTRL, EDGE_PER_REV, 420 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1)); 421 } 422 423 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2, 424 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2), 425 CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28)); 426 427 return 0; 428 } 429 430 /** 431 * vega10_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller. 432 * 433 * @hwmgr: The address of the hardware manager. 434 */ 435 static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr) 436 { 437 struct amdgpu_device *adev = hwmgr->adev; 438 struct vega10_hwmgr *data = hwmgr->backend; 439 uint32_t val = 0; 440 441 if (data->smu_features[GNLD_FW_CTF].supported) { 442 if (data->smu_features[GNLD_FW_CTF].enabled) 443 printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n"); 444 445 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 446 true, 447 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), 448 "Attempt to Enable FW CTF feature Failed!", 449 return -1); 450 data->smu_features[GNLD_FW_CTF].enabled = true; 451 } 452 453 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT); 454 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT); 455 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT); 456 457 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val); 458 459 return 0; 460 } 461 462 /** 463 * vega10_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller. 464 * @hwmgr: The address of the hardware manager. 465 */ 466 int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr) 467 { 468 struct amdgpu_device *adev = hwmgr->adev; 469 struct vega10_hwmgr *data = hwmgr->backend; 470 471 if (data->smu_features[GNLD_FW_CTF].supported) { 472 if (!data->smu_features[GNLD_FW_CTF].enabled) 473 printk("[Thermal_EnableAlert] FW CTF Already disabled!\n"); 474 475 476 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 477 false, 478 data->smu_features[GNLD_FW_CTF].smu_feature_bitmap), 479 "Attempt to disable FW CTF feature Failed!", 480 return -1); 481 data->smu_features[GNLD_FW_CTF].enabled = false; 482 } 483 484 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0); 485 486 return 0; 487 } 488 489 /** 490 * vega10_thermal_stop_thermal_controller - Uninitialize the thermal controller. 491 * Currently just disables alerts. 492 * @hwmgr: The address of the hardware manager. 493 */ 494 int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) 495 { 496 int result = vega10_thermal_disable_alert(hwmgr); 497 498 if (!hwmgr->thermal_controller.fanInfo.bNoFan) 499 vega10_fan_ctrl_set_default_mode(hwmgr); 500 501 return result; 502 } 503 504 /** 505 * vega10_thermal_setup_fan_table - Set up the fan table to control the fan using the SMC. 506 * @hwmgr: the address of the powerplay hardware manager. 507 * Return: result from set temperature range routine 508 */ 509 static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 510 { 511 int ret; 512 struct vega10_hwmgr *data = hwmgr->backend; 513 PPTable_t *table = &(data->smc_state_table.pp_table); 514 515 if (!data->smu_features[GNLD_FAN_CONTROL].supported) 516 return 0; 517 518 table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller. 519 advanceFanControlParameters.usMaxFanRPM; 520 table->FanThrottlingRpm = hwmgr->thermal_controller. 521 advanceFanControlParameters.usFanRPMMaxLimit; 522 table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller. 523 advanceFanControlParameters.ulMinFanSCLKAcousticLimit); 524 table->FanTargetTemperature = hwmgr->thermal_controller. 525 advanceFanControlParameters.usTMax; 526 527 smum_send_msg_to_smc_with_parameter(hwmgr, 528 PPSMC_MSG_SetFanTemperatureTarget, 529 (uint32_t)table->FanTargetTemperature, 530 NULL); 531 532 table->FanPwmMin = hwmgr->thermal_controller. 533 advanceFanControlParameters.usPWMMin * 255 / 100; 534 table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller. 535 advanceFanControlParameters.ulTargetGfxClk); 536 table->FanGainEdge = hwmgr->thermal_controller. 537 advanceFanControlParameters.usFanGainEdge; 538 table->FanGainHotspot = hwmgr->thermal_controller. 539 advanceFanControlParameters.usFanGainHotspot; 540 table->FanGainLiquid = hwmgr->thermal_controller. 541 advanceFanControlParameters.usFanGainLiquid; 542 table->FanGainVrVddc = hwmgr->thermal_controller. 543 advanceFanControlParameters.usFanGainVrVddc; 544 table->FanGainVrMvdd = hwmgr->thermal_controller. 545 advanceFanControlParameters.usFanGainVrMvdd; 546 table->FanGainPlx = hwmgr->thermal_controller. 547 advanceFanControlParameters.usFanGainPlx; 548 table->FanGainHbm = hwmgr->thermal_controller. 549 advanceFanControlParameters.usFanGainHbm; 550 table->FanZeroRpmEnable = hwmgr->thermal_controller. 551 advanceFanControlParameters.ucEnableZeroRPM; 552 table->FanStopTemp = hwmgr->thermal_controller. 553 advanceFanControlParameters.usZeroRPMStopTemperature; 554 table->FanStartTemp = hwmgr->thermal_controller. 555 advanceFanControlParameters.usZeroRPMStartTemperature; 556 557 ret = smum_smc_table_manager(hwmgr, 558 (uint8_t *)(&(data->smc_state_table.pp_table)), 559 PPTABLE, false); 560 if (ret) 561 pr_info("Failed to update Fan Control Table in PPTable!"); 562 563 return ret; 564 } 565 566 int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr) 567 { 568 struct vega10_hwmgr *data = hwmgr->backend; 569 PPTable_t *table = &(data->smc_state_table.pp_table); 570 int ret; 571 572 if (!data->smu_features[GNLD_FAN_CONTROL].supported) 573 return 0; 574 575 if (!hwmgr->thermal_controller.advanceFanControlParameters. 576 usMGpuThrottlingRPMLimit) 577 return 0; 578 579 table->FanThrottlingRpm = hwmgr->thermal_controller. 580 advanceFanControlParameters.usMGpuThrottlingRPMLimit; 581 582 ret = smum_smc_table_manager(hwmgr, 583 (uint8_t *)(&(data->smc_state_table.pp_table)), 584 PPTABLE, false); 585 if (ret) { 586 pr_info("Failed to update fan control table in pptable!"); 587 return ret; 588 } 589 590 ret = vega10_disable_fan_control_feature(hwmgr); 591 if (ret) { 592 pr_info("Attempt to disable SMC fan control feature failed!"); 593 return ret; 594 } 595 596 ret = vega10_enable_fan_control_feature(hwmgr); 597 if (ret) 598 pr_info("Attempt to enable SMC fan control feature failed!"); 599 600 return ret; 601 } 602 603 /** 604 * vega10_thermal_start_smc_fan_control - Start the fan control on the SMC. 605 * @hwmgr: the address of the powerplay hardware manager. 606 * Return: result from set temperature range routine 607 */ 608 static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr) 609 { 610 /* If the fantable setup has failed we could have disabled 611 * PHM_PlatformCaps_MicrocodeFanControl even after 612 * this function was included in the table. 613 * Make sure that we still think controlling the fan is OK. 614 */ 615 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 616 vega10_fan_ctrl_start_smc_fan_control(hwmgr); 617 618 return 0; 619 } 620 621 622 int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr, 623 struct PP_TemperatureRange *range) 624 { 625 int ret = 0; 626 627 if (range == NULL) 628 return -EINVAL; 629 630 vega10_thermal_initialize(hwmgr); 631 ret = vega10_thermal_set_temperature_range(hwmgr, range); 632 if (ret) 633 return -EINVAL; 634 635 vega10_thermal_enable_alert(hwmgr); 636 /* We should restrict performance levels to low before we halt the SMC. 637 * On the other hand we are still in boot state when we do this 638 * so it would be pointless. 639 * If this assumption changes we have to revisit this table. 640 */ 641 ret = vega10_thermal_setup_fan_table(hwmgr); 642 if (ret) 643 return -EINVAL; 644 645 vega10_thermal_start_smc_fan_control(hwmgr); 646 647 return 0; 648 }; 649 650 651 652 653 int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) 654 { 655 if (!hwmgr->thermal_controller.fanInfo.bNoFan) { 656 vega10_fan_ctrl_set_default_mode(hwmgr); 657 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 658 } 659 return 0; 660 } 661