1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/slab.h> 26 #include <linux/fb.h> 27 28 #include "vega10_processpptables.h" 29 #include "ppatomfwctrl.h" 30 #include "atomfirmware.h" 31 #include "pp_debug.h" 32 #include "cgs_common.h" 33 #include "vega10_pptable.h" 34 35 #define NUM_DSPCLK_LEVELS 8 36 #define VEGA10_ENGINECLOCK_HARDMAX 198000 37 38 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, 39 enum phm_platform_caps cap) 40 { 41 if (enable) 42 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); 43 else 44 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); 45 } 46 47 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) 48 { 49 int index = GetIndexIntoMasterDataTable(powerplayinfo); 50 51 u16 size; 52 u8 frev, crev; 53 const void *table_address = hwmgr->soft_pp_table; 54 55 if (!table_address) { 56 table_address = (ATOM_Vega10_POWERPLAYTABLE *) 57 smu_atom_get_data_table(hwmgr->adev, index, 58 &size, &frev, &crev); 59 60 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ 61 hwmgr->soft_pp_table_size = size; 62 } 63 64 return table_address; 65 } 66 67 static int check_powerplay_tables( 68 struct pp_hwmgr *hwmgr, 69 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) 70 { 71 const ATOM_Vega10_State_Array *state_arrays; 72 73 state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) + 74 le16_to_cpu(powerplay_table->usStateArrayOffset)); 75 76 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= 77 ATOM_Vega10_TABLE_REVISION_VEGA10), 78 "Unsupported PPTable format!", return -1); 79 PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset, 80 "State table is not set!", return -1); 81 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, 82 "Invalid PowerPlay Table!", return -1); 83 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, 84 "Invalid PowerPlay Table!", return -1); 85 86 return 0; 87 } 88 89 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) 90 { 91 set_hw_cap( 92 hwmgr, 93 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY), 94 PHM_PlatformCaps_PowerPlaySupport); 95 96 set_hw_cap( 97 hwmgr, 98 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), 99 PHM_PlatformCaps_BiosPowerSourceControl); 100 101 set_hw_cap( 102 hwmgr, 103 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC), 104 PHM_PlatformCaps_AutomaticDCTransition); 105 106 set_hw_cap( 107 hwmgr, 108 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO), 109 PHM_PlatformCaps_BACO); 110 111 set_hw_cap( 112 hwmgr, 113 0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL), 114 PHM_PlatformCaps_CombinePCCWithThermalSignal); 115 116 return 0; 117 } 118 119 static int init_thermal_controller( 120 struct pp_hwmgr *hwmgr, 121 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) 122 { 123 const ATOM_Vega10_Thermal_Controller *thermal_controller; 124 const Vega10_PPTable_Generic_SubTable_Header *header; 125 const ATOM_Vega10_Fan_Table *fan_table_v1; 126 const ATOM_Vega10_Fan_Table_V2 *fan_table_v2; 127 const ATOM_Vega10_Fan_Table_V3 *fan_table_v3; 128 129 thermal_controller = (ATOM_Vega10_Thermal_Controller *) 130 (((unsigned long)powerplay_table) + 131 le16_to_cpu(powerplay_table->usThermalControllerOffset)); 132 133 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0), 134 "Thermal controller table not set!", return -EINVAL); 135 136 hwmgr->thermal_controller.ucType = thermal_controller->ucType; 137 hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine; 138 hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress; 139 140 hwmgr->thermal_controller.fanInfo.bNoFan = 141 (0 != (thermal_controller->ucFanParameters & 142 ATOM_VEGA10_PP_FANPARAMETERS_NOFAN)); 143 144 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = 145 thermal_controller->ucFanParameters & 146 ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 147 148 hwmgr->thermal_controller.fanInfo.ulMinRPM = 149 thermal_controller->ucFanMinRPM * 100UL; 150 hwmgr->thermal_controller.fanInfo.ulMaxRPM = 151 thermal_controller->ucFanMaxRPM * 100UL; 152 153 hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay 154 = 100000; 155 156 set_hw_cap( 157 hwmgr, 158 ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, 159 PHM_PlatformCaps_ThermalController); 160 161 if (!powerplay_table->usFanTableOffset) 162 return 0; 163 164 header = (const Vega10_PPTable_Generic_SubTable_Header *) 165 (((unsigned long)powerplay_table) + 166 le16_to_cpu(powerplay_table->usFanTableOffset)); 167 168 if (header->ucRevId == 10) { 169 fan_table_v1 = (ATOM_Vega10_Fan_Table *)header; 170 171 PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8), 172 "Invalid Input Fan Table!", return -EINVAL); 173 174 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 175 PHM_PlatformCaps_MicrocodeFanControl); 176 177 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 178 le16_to_cpu(fan_table_v1->usFanOutputSensitivity); 179 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 180 le16_to_cpu(fan_table_v1->usFanRPMMax); 181 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 182 le16_to_cpu(fan_table_v1->usThrottlingRPM); 183 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = 184 le16_to_cpu(fan_table_v1->usFanAcousticLimit); 185 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 186 le16_to_cpu(fan_table_v1->usTargetTemperature); 187 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = 188 le16_to_cpu(fan_table_v1->usMinimumPWMLimit); 189 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = 190 le16_to_cpu(fan_table_v1->usTargetGfxClk); 191 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = 192 le16_to_cpu(fan_table_v1->usFanGainEdge); 193 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = 194 le16_to_cpu(fan_table_v1->usFanGainHotspot); 195 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = 196 le16_to_cpu(fan_table_v1->usFanGainLiquid); 197 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = 198 le16_to_cpu(fan_table_v1->usFanGainVrVddc); 199 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = 200 le16_to_cpu(fan_table_v1->usFanGainVrMvdd); 201 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = 202 le16_to_cpu(fan_table_v1->usFanGainPlx); 203 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = 204 le16_to_cpu(fan_table_v1->usFanGainHbm); 205 206 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = 207 fan_table_v1->ucEnableZeroRPM; 208 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = 209 le16_to_cpu(fan_table_v1->usFanStopTemperature); 210 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = 211 le16_to_cpu(fan_table_v1->usFanStartTemperature); 212 } else if (header->ucRevId == 0xb) { 213 fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header; 214 215 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = 216 fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 217 hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL; 218 hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL; 219 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 220 PHM_PlatformCaps_MicrocodeFanControl); 221 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 222 le16_to_cpu(fan_table_v2->usFanOutputSensitivity); 223 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 224 fan_table_v2->ucFanMaxRPM * 100UL; 225 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 226 le16_to_cpu(fan_table_v2->usThrottlingRPM); 227 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = 228 le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm); 229 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 230 le16_to_cpu(fan_table_v2->usTargetTemperature); 231 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = 232 le16_to_cpu(fan_table_v2->usMinimumPWMLimit); 233 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = 234 le16_to_cpu(fan_table_v2->usTargetGfxClk); 235 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = 236 le16_to_cpu(fan_table_v2->usFanGainEdge); 237 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = 238 le16_to_cpu(fan_table_v2->usFanGainHotspot); 239 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = 240 le16_to_cpu(fan_table_v2->usFanGainLiquid); 241 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = 242 le16_to_cpu(fan_table_v2->usFanGainVrVddc); 243 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = 244 le16_to_cpu(fan_table_v2->usFanGainVrMvdd); 245 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = 246 le16_to_cpu(fan_table_v2->usFanGainPlx); 247 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = 248 le16_to_cpu(fan_table_v2->usFanGainHbm); 249 250 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = 251 fan_table_v2->ucEnableZeroRPM; 252 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = 253 le16_to_cpu(fan_table_v2->usFanStopTemperature); 254 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = 255 le16_to_cpu(fan_table_v2->usFanStartTemperature); 256 } else if (header->ucRevId > 0xb) { 257 fan_table_v3 = (ATOM_Vega10_Fan_Table_V3 *)header; 258 259 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution = 260 fan_table_v3->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK; 261 hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v3->ucFanMinRPM * 100UL; 262 hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v3->ucFanMaxRPM * 100UL; 263 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 264 PHM_PlatformCaps_MicrocodeFanControl); 265 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity = 266 le16_to_cpu(fan_table_v3->usFanOutputSensitivity); 267 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 268 fan_table_v3->ucFanMaxRPM * 100UL; 269 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 270 le16_to_cpu(fan_table_v3->usThrottlingRPM); 271 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit = 272 le16_to_cpu(fan_table_v3->usFanAcousticLimitRpm); 273 hwmgr->thermal_controller.advanceFanControlParameters.usTMax = 274 le16_to_cpu(fan_table_v3->usTargetTemperature); 275 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin = 276 le16_to_cpu(fan_table_v3->usMinimumPWMLimit); 277 hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk = 278 le16_to_cpu(fan_table_v3->usTargetGfxClk); 279 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge = 280 le16_to_cpu(fan_table_v3->usFanGainEdge); 281 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot = 282 le16_to_cpu(fan_table_v3->usFanGainHotspot); 283 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid = 284 le16_to_cpu(fan_table_v3->usFanGainLiquid); 285 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc = 286 le16_to_cpu(fan_table_v3->usFanGainVrVddc); 287 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd = 288 le16_to_cpu(fan_table_v3->usFanGainVrMvdd); 289 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx = 290 le16_to_cpu(fan_table_v3->usFanGainPlx); 291 hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm = 292 le16_to_cpu(fan_table_v3->usFanGainHbm); 293 294 hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM = 295 fan_table_v3->ucEnableZeroRPM; 296 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature = 297 le16_to_cpu(fan_table_v3->usFanStopTemperature); 298 hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature = 299 le16_to_cpu(fan_table_v3->usFanStartTemperature); 300 hwmgr->thermal_controller.advanceFanControlParameters.usMGpuThrottlingRPMLimit = 301 le16_to_cpu(fan_table_v3->usMGpuThrottlingRPM); 302 } 303 304 return 0; 305 } 306 307 static int init_over_drive_limits( 308 struct pp_hwmgr *hwmgr, 309 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) 310 { 311 const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = 312 (const ATOM_Vega10_GFXCLK_Dependency_Table *) 313 (((unsigned long) powerplay_table) + 314 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); 315 bool is_acg_enabled = false; 316 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2; 317 318 if (gfxclk_dep_table->ucRevId == 1) { 319 patom_record_v2 = 320 (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; 321 is_acg_enabled = 322 (bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable; 323 } 324 325 if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX && 326 !is_acg_enabled) 327 hwmgr->platform_descriptor.overdriveLimit.engineClock = 328 VEGA10_ENGINECLOCK_HARDMAX; 329 else 330 hwmgr->platform_descriptor.overdriveLimit.engineClock = 331 le32_to_cpu(powerplay_table->ulMaxODEngineClock); 332 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 333 le32_to_cpu(powerplay_table->ulMaxODMemoryClock); 334 335 hwmgr->platform_descriptor.minOverdriveVDDC = 0; 336 hwmgr->platform_descriptor.maxOverdriveVDDC = 0; 337 hwmgr->platform_descriptor.overdriveVDDCStep = 0; 338 339 return 0; 340 } 341 342 static int get_mm_clock_voltage_table( 343 struct pp_hwmgr *hwmgr, 344 phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table, 345 const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table) 346 { 347 uint32_t i; 348 const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record; 349 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table; 350 351 PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0), 352 "Invalid PowerPlay Table!", return -1); 353 354 mm_table = kzalloc(struct_size(mm_table, entries, mm_dependency_table->ucNumEntries), 355 GFP_KERNEL); 356 if (!mm_table) 357 return -ENOMEM; 358 359 mm_table->count = mm_dependency_table->ucNumEntries; 360 361 for (i = 0; i < mm_dependency_table->ucNumEntries; i++) { 362 mm_dependency_record = &mm_dependency_table->entries[i]; 363 mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd; 364 mm_table->entries[i].samclock = 365 le32_to_cpu(mm_dependency_record->ulPSPClk); 366 mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk); 367 mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk); 368 mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk); 369 } 370 371 *vega10_mm_table = mm_table; 372 373 return 0; 374 } 375 376 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda) 377 { 378 switch(line){ 379 case Vega10_I2CLineID_DDC1: 380 *scl = Vega10_I2C_DDC1CLK; 381 *sda = Vega10_I2C_DDC1DATA; 382 break; 383 case Vega10_I2CLineID_DDC2: 384 *scl = Vega10_I2C_DDC2CLK; 385 *sda = Vega10_I2C_DDC2DATA; 386 break; 387 case Vega10_I2CLineID_DDC3: 388 *scl = Vega10_I2C_DDC3CLK; 389 *sda = Vega10_I2C_DDC3DATA; 390 break; 391 case Vega10_I2CLineID_DDC4: 392 *scl = Vega10_I2C_DDC4CLK; 393 *sda = Vega10_I2C_DDC4DATA; 394 break; 395 case Vega10_I2CLineID_DDC5: 396 *scl = Vega10_I2C_DDC5CLK; 397 *sda = Vega10_I2C_DDC5DATA; 398 break; 399 case Vega10_I2CLineID_DDC6: 400 *scl = Vega10_I2C_DDC6CLK; 401 *sda = Vega10_I2C_DDC6DATA; 402 break; 403 case Vega10_I2CLineID_SCLSDA: 404 *scl = Vega10_I2C_SCL; 405 *sda = Vega10_I2C_SDA; 406 break; 407 case Vega10_I2CLineID_DDCVGA: 408 *scl = Vega10_I2C_DDCVGACLK; 409 *sda = Vega10_I2C_DDCVGADATA; 410 break; 411 default: 412 *scl = 0; 413 *sda = 0; 414 break; 415 } 416 } 417 418 static int get_tdp_table( 419 struct pp_hwmgr *hwmgr, 420 struct phm_tdp_table **info_tdp_table, 421 const Vega10_PPTable_Generic_SubTable_Header *table) 422 { 423 uint32_t table_size; 424 struct phm_tdp_table *tdp_table; 425 uint8_t scl; 426 uint8_t sda; 427 const ATOM_Vega10_PowerTune_Table *power_tune_table; 428 const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2; 429 const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3; 430 431 table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table); 432 433 tdp_table = kzalloc(table_size, GFP_KERNEL); 434 435 if (!tdp_table) 436 return -ENOMEM; 437 438 if (table->ucRevId == 5) { 439 power_tune_table = (ATOM_Vega10_PowerTune_Table *)table; 440 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit); 441 tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit); 442 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit); 443 tdp_table->usSoftwareShutdownTemp = 444 le16_to_cpu(power_tune_table->usSoftwareShutdownTemp); 445 tdp_table->usTemperatureLimitTedge = 446 le16_to_cpu(power_tune_table->usTemperatureLimitTedge); 447 tdp_table->usTemperatureLimitHotspot = 448 le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot); 449 tdp_table->usTemperatureLimitLiquid1 = 450 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1); 451 tdp_table->usTemperatureLimitLiquid2 = 452 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2); 453 tdp_table->usTemperatureLimitHBM = 454 le16_to_cpu(power_tune_table->usTemperatureLimitHBM); 455 tdp_table->usTemperatureLimitVrVddc = 456 le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc); 457 tdp_table->usTemperatureLimitVrMvdd = 458 le16_to_cpu(power_tune_table->usTemperatureLimitVrMem); 459 tdp_table->usTemperatureLimitPlx = 460 le16_to_cpu(power_tune_table->usTemperatureLimitPlx); 461 tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address; 462 tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address; 463 tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL; 464 tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA; 465 tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address; 466 tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL; 467 tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA; 468 tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address; 469 tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL; 470 tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA; 471 hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance); 472 } else if (table->ucRevId == 6) { 473 power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table; 474 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit); 475 tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit); 476 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit); 477 tdp_table->usSoftwareShutdownTemp = 478 le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp); 479 tdp_table->usTemperatureLimitTedge = 480 le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge); 481 tdp_table->usTemperatureLimitHotspot = 482 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot); 483 tdp_table->usTemperatureLimitLiquid1 = 484 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1); 485 tdp_table->usTemperatureLimitLiquid2 = 486 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2); 487 tdp_table->usTemperatureLimitHBM = 488 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM); 489 tdp_table->usTemperatureLimitVrVddc = 490 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc); 491 tdp_table->usTemperatureLimitVrMvdd = 492 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem); 493 tdp_table->usTemperatureLimitPlx = 494 le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx); 495 tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address; 496 tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address; 497 498 get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda); 499 500 tdp_table->ucLiquid_I2C_Line = scl; 501 tdp_table->ucLiquid_I2C_LineSDA = sda; 502 503 tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address; 504 505 get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda); 506 507 tdp_table->ucVr_I2C_Line = scl; 508 tdp_table->ucVr_I2C_LineSDA = sda; 509 tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address; 510 511 get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda); 512 513 tdp_table->ucPlx_I2C_Line = scl; 514 tdp_table->ucPlx_I2C_LineSDA = sda; 515 516 hwmgr->platform_descriptor.LoadLineSlope = 517 le16_to_cpu(power_tune_table_v2->usLoadLineResistance); 518 } else { 519 power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table; 520 tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v3->usSocketPowerLimit); 521 tdp_table->usTDC = le16_to_cpu(power_tune_table_v3->usTdcLimit); 522 tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v3->usEdcLimit); 523 tdp_table->usSoftwareShutdownTemp = le16_to_cpu(power_tune_table_v3->usSoftwareShutdownTemp); 524 tdp_table->usTemperatureLimitTedge = le16_to_cpu(power_tune_table_v3->usTemperatureLimitTedge); 525 tdp_table->usTemperatureLimitHotspot = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHotSpot); 526 tdp_table->usTemperatureLimitLiquid1 = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid1); 527 tdp_table->usTemperatureLimitLiquid2 = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid2); 528 tdp_table->usTemperatureLimitHBM = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHBM); 529 tdp_table->usTemperatureLimitVrVddc = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrSoc); 530 tdp_table->usTemperatureLimitVrMvdd = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrMem); 531 tdp_table->usTemperatureLimitPlx = le16_to_cpu(power_tune_table_v3->usTemperatureLimitPlx); 532 tdp_table->ucLiquid1_I2C_address = power_tune_table_v3->ucLiquid1_I2C_address; 533 tdp_table->ucLiquid2_I2C_address = power_tune_table_v3->ucLiquid2_I2C_address; 534 tdp_table->usBoostStartTemperature = le16_to_cpu(power_tune_table_v3->usBoostStartTemperature); 535 tdp_table->usBoostStopTemperature = le16_to_cpu(power_tune_table_v3->usBoostStopTemperature); 536 tdp_table->ulBoostClock = le32_to_cpu(power_tune_table_v3->ulBoostClock); 537 538 get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda); 539 540 tdp_table->ucLiquid_I2C_Line = scl; 541 tdp_table->ucLiquid_I2C_LineSDA = sda; 542 543 tdp_table->ucVr_I2C_address = power_tune_table_v3->ucVr_I2C_address; 544 545 get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda); 546 547 tdp_table->ucVr_I2C_Line = scl; 548 tdp_table->ucVr_I2C_LineSDA = sda; 549 550 tdp_table->ucPlx_I2C_address = power_tune_table_v3->ucPlx_I2C_address; 551 552 get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda); 553 554 tdp_table->ucPlx_I2C_Line = scl; 555 tdp_table->ucPlx_I2C_LineSDA = sda; 556 557 hwmgr->platform_descriptor.LoadLineSlope = 558 le16_to_cpu(power_tune_table_v3->usLoadLineResistance); 559 } 560 561 *info_tdp_table = tdp_table; 562 563 return 0; 564 } 565 566 static int get_socclk_voltage_dependency_table( 567 struct pp_hwmgr *hwmgr, 568 phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table, 569 const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table) 570 { 571 uint32_t i; 572 phm_ppt_v1_clock_voltage_dependency_table *clk_table; 573 574 PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries, 575 "Invalid PowerPlay Table!", return -1); 576 577 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), 578 GFP_KERNEL); 579 if (!clk_table) 580 return -ENOMEM; 581 582 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; 583 584 for (i = 0; i < clk_dep_table->ucNumEntries; i++) { 585 clk_table->entries[i].vddInd = 586 clk_dep_table->entries[i].ucVddInd; 587 clk_table->entries[i].clk = 588 le32_to_cpu(clk_dep_table->entries[i].ulClk); 589 } 590 591 *pp_vega10_clk_dep_table = clk_table; 592 593 return 0; 594 } 595 596 static int get_mclk_voltage_dependency_table( 597 struct pp_hwmgr *hwmgr, 598 phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table, 599 const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table) 600 { 601 uint32_t i; 602 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; 603 604 PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries, 605 "Invalid PowerPlay Table!", return -1); 606 607 mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries), 608 GFP_KERNEL); 609 if (!mclk_table) 610 return -ENOMEM; 611 612 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; 613 614 for (i = 0; i < mclk_dep_table->ucNumEntries; i++) { 615 mclk_table->entries[i].vddInd = 616 mclk_dep_table->entries[i].ucVddInd; 617 mclk_table->entries[i].vddciInd = 618 mclk_dep_table->entries[i].ucVddciInd; 619 mclk_table->entries[i].mvddInd = 620 mclk_dep_table->entries[i].ucVddMemInd; 621 mclk_table->entries[i].clk = 622 le32_to_cpu(mclk_dep_table->entries[i].ulMemClk); 623 } 624 625 *pp_vega10_mclk_dep_table = mclk_table; 626 627 return 0; 628 } 629 630 static int get_gfxclk_voltage_dependency_table( 631 struct pp_hwmgr *hwmgr, 632 struct phm_ppt_v1_clock_voltage_dependency_table 633 **pp_vega10_clk_dep_table, 634 const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table) 635 { 636 uint32_t i; 637 struct phm_ppt_v1_clock_voltage_dependency_table 638 *clk_table; 639 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2; 640 641 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), 642 "Invalid PowerPlay Table!", return -1); 643 644 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), 645 GFP_KERNEL); 646 if (!clk_table) 647 return -ENOMEM; 648 649 clk_table->count = clk_dep_table->ucNumEntries; 650 651 if (clk_dep_table->ucRevId == 0) { 652 for (i = 0; i < clk_table->count; i++) { 653 clk_table->entries[i].vddInd = 654 clk_dep_table->entries[i].ucVddInd; 655 clk_table->entries[i].clk = 656 le32_to_cpu(clk_dep_table->entries[i].ulClk); 657 clk_table->entries[i].cks_enable = 658 (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000) 659 >> 15) == 0) ? 1 : 0; 660 clk_table->entries[i].cks_voffset = 661 le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F; 662 clk_table->entries[i].sclk_offset = 663 le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset); 664 } 665 } else if (clk_dep_table->ucRevId == 1) { 666 patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries; 667 for (i = 0; i < clk_table->count; i++) { 668 clk_table->entries[i].vddInd = 669 patom_record_v2->ucVddInd; 670 clk_table->entries[i].clk = 671 le32_to_cpu(patom_record_v2->ulClk); 672 clk_table->entries[i].cks_enable = 673 (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000) 674 >> 15) == 0) ? 1 : 0; 675 clk_table->entries[i].cks_voffset = 676 le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F; 677 clk_table->entries[i].sclk_offset = 678 le16_to_cpu(patom_record_v2->usAVFSOffset); 679 patom_record_v2++; 680 } 681 } else { 682 kfree(clk_table); 683 PP_ASSERT_WITH_CODE(false, 684 "Unsupported GFXClockDependencyTable Revision!", 685 return -EINVAL); 686 } 687 688 *pp_vega10_clk_dep_table = clk_table; 689 690 return 0; 691 } 692 693 static int get_pix_clk_voltage_dependency_table( 694 struct pp_hwmgr *hwmgr, 695 struct phm_ppt_v1_clock_voltage_dependency_table 696 **pp_vega10_clk_dep_table, 697 const ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table) 698 { 699 uint32_t i; 700 struct phm_ppt_v1_clock_voltage_dependency_table 701 *clk_table; 702 703 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), 704 "Invalid PowerPlay Table!", return -1); 705 706 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), 707 GFP_KERNEL); 708 if (!clk_table) 709 return -ENOMEM; 710 711 clk_table->count = clk_dep_table->ucNumEntries; 712 713 for (i = 0; i < clk_table->count; i++) { 714 clk_table->entries[i].vddInd = 715 clk_dep_table->entries[i].ucVddInd; 716 clk_table->entries[i].clk = 717 le32_to_cpu(clk_dep_table->entries[i].ulClk); 718 } 719 720 *pp_vega10_clk_dep_table = clk_table; 721 722 return 0; 723 } 724 725 static int get_dcefclk_voltage_dependency_table( 726 struct pp_hwmgr *hwmgr, 727 struct phm_ppt_v1_clock_voltage_dependency_table 728 **pp_vega10_clk_dep_table, 729 const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table) 730 { 731 uint32_t i; 732 uint8_t num_entries; 733 struct phm_ppt_v1_clock_voltage_dependency_table 734 *clk_table; 735 uint32_t dev_id; 736 uint32_t rev_id; 737 struct amdgpu_device *adev = hwmgr->adev; 738 739 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0), 740 "Invalid PowerPlay Table!", return -1); 741 742 /* 743 * workaround needed to add another DPM level for pioneer cards 744 * as VBIOS is locked down. 745 * This DPM level was added to support 3DPM monitors @ 4K120Hz 746 * 747 */ 748 dev_id = adev->pdev->device; 749 rev_id = adev->pdev->revision; 750 751 if (dev_id == 0x6863 && rev_id == 0 && 752 clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000) 753 num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ? 754 NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1; 755 else 756 num_entries = clk_dep_table->ucNumEntries; 757 758 759 clk_table = kzalloc(struct_size(clk_table, entries, num_entries), 760 GFP_KERNEL); 761 if (!clk_table) 762 return -ENOMEM; 763 764 clk_table->count = (uint32_t)num_entries; 765 766 for (i = 0; i < clk_dep_table->ucNumEntries; i++) { 767 clk_table->entries[i].vddInd = 768 clk_dep_table->entries[i].ucVddInd; 769 clk_table->entries[i].clk = 770 le32_to_cpu(clk_dep_table->entries[i].ulClk); 771 } 772 773 if (i < num_entries) { 774 clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd; 775 clk_table->entries[i].clk = 90000; 776 } 777 778 *pp_vega10_clk_dep_table = clk_table; 779 780 return 0; 781 } 782 783 static int get_pcie_table(struct pp_hwmgr *hwmgr, 784 struct phm_ppt_v1_pcie_table **vega10_pcie_table, 785 const Vega10_PPTable_Generic_SubTable_Header *table) 786 { 787 uint32_t table_size, i, pcie_count; 788 struct phm_ppt_v1_pcie_table *pcie_table; 789 struct phm_ppt_v2_information *table_info = 790 (struct phm_ppt_v2_information *)(hwmgr->pptable); 791 const ATOM_Vega10_PCIE_Table *atom_pcie_table = 792 (ATOM_Vega10_PCIE_Table *)table; 793 794 PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries, 795 "Invalid PowerPlay Table!", 796 return 0); 797 798 table_size = sizeof(uint32_t) + 799 sizeof(struct phm_ppt_v1_pcie_record) * 800 atom_pcie_table->ucNumEntries; 801 802 pcie_table = kzalloc(table_size, GFP_KERNEL); 803 804 if (!pcie_table) 805 return -ENOMEM; 806 807 pcie_count = table_info->vdd_dep_on_sclk->count; 808 if (atom_pcie_table->ucNumEntries <= pcie_count) 809 pcie_count = atom_pcie_table->ucNumEntries; 810 else 811 pr_info("Number of Pcie Entries exceed the number of" 812 " GFXCLK Dpm Levels!" 813 " Disregarding the excess entries...\n"); 814 815 pcie_table->count = pcie_count; 816 817 for (i = 0; i < pcie_count; i++) { 818 pcie_table->entries[i].gen_speed = 819 atom_pcie_table->entries[i].ucPCIEGenSpeed; 820 pcie_table->entries[i].lane_width = 821 atom_pcie_table->entries[i].ucPCIELaneWidth; 822 pcie_table->entries[i].pcie_sclk = 823 atom_pcie_table->entries[i].ulLCLK; 824 } 825 826 *vega10_pcie_table = pcie_table; 827 828 return 0; 829 } 830 831 static int get_hard_limits( 832 struct pp_hwmgr *hwmgr, 833 struct phm_clock_and_voltage_limits *limits, 834 const ATOM_Vega10_Hard_Limit_Table *limit_table) 835 { 836 PP_ASSERT_WITH_CODE(limit_table->ucNumEntries, 837 "Invalid PowerPlay Table!", return -1); 838 839 /* currently we always take entries[0] parameters */ 840 limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit); 841 limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit); 842 limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit); 843 limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit); 844 limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit); 845 limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit); 846 847 return 0; 848 } 849 850 static int get_valid_clk( 851 struct pp_hwmgr *hwmgr, 852 struct phm_clock_array **clk_table, 853 const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table) 854 { 855 uint32_t i; 856 struct phm_clock_array *table; 857 858 PP_ASSERT_WITH_CODE(clk_volt_pp_table->count, 859 "Invalid PowerPlay Table!", return -1); 860 861 table = kzalloc(struct_size(table, values, clk_volt_pp_table->count), 862 GFP_KERNEL); 863 if (!table) 864 return -ENOMEM; 865 866 table->count = (uint32_t)clk_volt_pp_table->count; 867 868 for (i = 0; i < table->count; i++) 869 table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk; 870 871 *clk_table = table; 872 873 return 0; 874 } 875 876 static int init_powerplay_extended_tables( 877 struct pp_hwmgr *hwmgr, 878 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) 879 { 880 int result = 0; 881 struct phm_ppt_v2_information *pp_table_info = 882 (struct phm_ppt_v2_information *)(hwmgr->pptable); 883 884 const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table = 885 (const ATOM_Vega10_MM_Dependency_Table *) 886 (((unsigned long) powerplay_table) + 887 le16_to_cpu(powerplay_table->usMMDependencyTableOffset)); 888 const Vega10_PPTable_Generic_SubTable_Header *power_tune_table = 889 (const Vega10_PPTable_Generic_SubTable_Header *) 890 (((unsigned long) powerplay_table) + 891 le16_to_cpu(powerplay_table->usPowerTuneTableOffset)); 892 const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = 893 (const ATOM_Vega10_SOCCLK_Dependency_Table *) 894 (((unsigned long) powerplay_table) + 895 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); 896 const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = 897 (const ATOM_Vega10_GFXCLK_Dependency_Table *) 898 (((unsigned long) powerplay_table) + 899 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); 900 const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table = 901 (const ATOM_Vega10_DCEFCLK_Dependency_Table *) 902 (((unsigned long) powerplay_table) + 903 le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset)); 904 const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = 905 (const ATOM_Vega10_MCLK_Dependency_Table *) 906 (((unsigned long) powerplay_table) + 907 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 908 const ATOM_Vega10_Hard_Limit_Table *hard_limits = 909 (const ATOM_Vega10_Hard_Limit_Table *) 910 (((unsigned long) powerplay_table) + 911 le16_to_cpu(powerplay_table->usHardLimitTableOffset)); 912 const Vega10_PPTable_Generic_SubTable_Header *pcie_table = 913 (const Vega10_PPTable_Generic_SubTable_Header *) 914 (((unsigned long) powerplay_table) + 915 le16_to_cpu(powerplay_table->usPCIETableOffset)); 916 const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table = 917 (const ATOM_Vega10_PIXCLK_Dependency_Table *) 918 (((unsigned long) powerplay_table) + 919 le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset)); 920 const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table = 921 (const ATOM_Vega10_PHYCLK_Dependency_Table *) 922 (((unsigned long) powerplay_table) + 923 le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset)); 924 const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table = 925 (const ATOM_Vega10_DISPCLK_Dependency_Table *) 926 (((unsigned long) powerplay_table) + 927 le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset)); 928 929 pp_table_info->vdd_dep_on_socclk = NULL; 930 pp_table_info->vdd_dep_on_sclk = NULL; 931 pp_table_info->vdd_dep_on_mclk = NULL; 932 pp_table_info->vdd_dep_on_dcefclk = NULL; 933 pp_table_info->mm_dep_table = NULL; 934 pp_table_info->tdp_table = NULL; 935 pp_table_info->vdd_dep_on_pixclk = NULL; 936 pp_table_info->vdd_dep_on_phyclk = NULL; 937 pp_table_info->vdd_dep_on_dispclk = NULL; 938 939 if (powerplay_table->usMMDependencyTableOffset) 940 result = get_mm_clock_voltage_table(hwmgr, 941 &pp_table_info->mm_dep_table, 942 mm_dependency_table); 943 944 if (!result && powerplay_table->usPowerTuneTableOffset) 945 result = get_tdp_table(hwmgr, 946 &pp_table_info->tdp_table, 947 power_tune_table); 948 949 if (!result && powerplay_table->usSocclkDependencyTableOffset) 950 result = get_socclk_voltage_dependency_table(hwmgr, 951 &pp_table_info->vdd_dep_on_socclk, 952 socclk_dep_table); 953 954 if (!result && powerplay_table->usGfxclkDependencyTableOffset) 955 result = get_gfxclk_voltage_dependency_table(hwmgr, 956 &pp_table_info->vdd_dep_on_sclk, 957 gfxclk_dep_table); 958 959 if (!result && powerplay_table->usPixclkDependencyTableOffset) 960 result = get_pix_clk_voltage_dependency_table(hwmgr, 961 &pp_table_info->vdd_dep_on_pixclk, 962 (const ATOM_Vega10_PIXCLK_Dependency_Table*) 963 pixclk_dep_table); 964 965 if (!result && powerplay_table->usPhyClkDependencyTableOffset) 966 result = get_pix_clk_voltage_dependency_table(hwmgr, 967 &pp_table_info->vdd_dep_on_phyclk, 968 (const ATOM_Vega10_PIXCLK_Dependency_Table *) 969 phyclk_dep_table); 970 971 if (!result && powerplay_table->usDispClkDependencyTableOffset) 972 result = get_pix_clk_voltage_dependency_table(hwmgr, 973 &pp_table_info->vdd_dep_on_dispclk, 974 (const ATOM_Vega10_PIXCLK_Dependency_Table *) 975 dispclk_dep_table); 976 977 if (!result && powerplay_table->usDcefclkDependencyTableOffset) 978 result = get_dcefclk_voltage_dependency_table(hwmgr, 979 &pp_table_info->vdd_dep_on_dcefclk, 980 dcefclk_dep_table); 981 982 if (!result && powerplay_table->usMclkDependencyTableOffset) 983 result = get_mclk_voltage_dependency_table(hwmgr, 984 &pp_table_info->vdd_dep_on_mclk, 985 mclk_dep_table); 986 987 if (!result && powerplay_table->usPCIETableOffset) 988 result = get_pcie_table(hwmgr, 989 &pp_table_info->pcie_table, 990 pcie_table); 991 992 if (!result && powerplay_table->usHardLimitTableOffset) 993 result = get_hard_limits(hwmgr, 994 &pp_table_info->max_clock_voltage_on_dc, 995 hard_limits); 996 997 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = 998 pp_table_info->max_clock_voltage_on_dc.sclk; 999 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = 1000 pp_table_info->max_clock_voltage_on_dc.mclk; 1001 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = 1002 pp_table_info->max_clock_voltage_on_dc.vddc; 1003 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = 1004 pp_table_info->max_clock_voltage_on_dc.vddci; 1005 1006 if (!result && 1007 pp_table_info->vdd_dep_on_socclk && 1008 pp_table_info->vdd_dep_on_socclk->count) 1009 result = get_valid_clk(hwmgr, 1010 &pp_table_info->valid_socclk_values, 1011 pp_table_info->vdd_dep_on_socclk); 1012 1013 if (!result && 1014 pp_table_info->vdd_dep_on_sclk && 1015 pp_table_info->vdd_dep_on_sclk->count) 1016 result = get_valid_clk(hwmgr, 1017 &pp_table_info->valid_sclk_values, 1018 pp_table_info->vdd_dep_on_sclk); 1019 1020 if (!result && 1021 pp_table_info->vdd_dep_on_dcefclk && 1022 pp_table_info->vdd_dep_on_dcefclk->count) 1023 result = get_valid_clk(hwmgr, 1024 &pp_table_info->valid_dcefclk_values, 1025 pp_table_info->vdd_dep_on_dcefclk); 1026 1027 if (!result && 1028 pp_table_info->vdd_dep_on_mclk && 1029 pp_table_info->vdd_dep_on_mclk->count) 1030 result = get_valid_clk(hwmgr, 1031 &pp_table_info->valid_mclk_values, 1032 pp_table_info->vdd_dep_on_mclk); 1033 1034 return result; 1035 } 1036 1037 static int get_vddc_lookup_table( 1038 struct pp_hwmgr *hwmgr, 1039 phm_ppt_v1_voltage_lookup_table **lookup_table, 1040 const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables, 1041 uint32_t max_levels) 1042 { 1043 uint32_t table_size, i; 1044 phm_ppt_v1_voltage_lookup_table *table; 1045 1046 PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0), 1047 "Invalid SOC_VDDD Lookup Table!", return 1); 1048 1049 table_size = sizeof(uint32_t) + 1050 sizeof(phm_ppt_v1_voltage_lookup_record) * max_levels; 1051 1052 table = kzalloc(table_size, GFP_KERNEL); 1053 1054 if (table == NULL) 1055 return -ENOMEM; 1056 1057 table->count = vddc_lookup_pp_tables->ucNumEntries; 1058 1059 for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++) 1060 table->entries[i].us_vdd = 1061 le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd); 1062 1063 *lookup_table = table; 1064 1065 return 0; 1066 } 1067 1068 static int init_dpm_2_parameters( 1069 struct pp_hwmgr *hwmgr, 1070 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table) 1071 { 1072 int result = 0; 1073 struct phm_ppt_v2_information *pp_table_info = 1074 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1075 uint32_t disable_power_control = 0; 1076 1077 pp_table_info->us_ulv_voltage_offset = 1078 le16_to_cpu(powerplay_table->usUlvVoltageOffset); 1079 1080 pp_table_info->us_ulv_smnclk_did = 1081 le16_to_cpu(powerplay_table->usUlvSmnclkDid); 1082 pp_table_info->us_ulv_mp1clk_did = 1083 le16_to_cpu(powerplay_table->usUlvMp1clkDid); 1084 pp_table_info->us_ulv_gfxclk_bypass = 1085 le16_to_cpu(powerplay_table->usUlvGfxclkBypass); 1086 pp_table_info->us_gfxclk_slew_rate = 1087 le16_to_cpu(powerplay_table->usGfxclkSlewRate); 1088 pp_table_info->uc_gfx_dpm_voltage_mode = 1089 le16_to_cpu(powerplay_table->ucGfxVoltageMode); 1090 pp_table_info->uc_soc_dpm_voltage_mode = 1091 le16_to_cpu(powerplay_table->ucSocVoltageMode); 1092 pp_table_info->uc_uclk_dpm_voltage_mode = 1093 le16_to_cpu(powerplay_table->ucUclkVoltageMode); 1094 pp_table_info->uc_uvd_dpm_voltage_mode = 1095 le16_to_cpu(powerplay_table->ucUvdVoltageMode); 1096 pp_table_info->uc_vce_dpm_voltage_mode = 1097 le16_to_cpu(powerplay_table->ucVceVoltageMode); 1098 pp_table_info->uc_mp0_dpm_voltage_mode = 1099 le16_to_cpu(powerplay_table->ucMp0VoltageMode); 1100 pp_table_info->uc_dcef_dpm_voltage_mode = 1101 le16_to_cpu(powerplay_table->ucDcefVoltageMode); 1102 1103 pp_table_info->ppm_parameter_table = NULL; 1104 pp_table_info->vddc_lookup_table = NULL; 1105 pp_table_info->vddmem_lookup_table = NULL; 1106 pp_table_info->vddci_lookup_table = NULL; 1107 1108 /* TDP limits */ 1109 hwmgr->platform_descriptor.TDPODLimit = 1110 le16_to_cpu(powerplay_table->usPowerControlLimit); 1111 hwmgr->platform_descriptor.TDPAdjustment = 0; 1112 hwmgr->platform_descriptor.VidAdjustment = 0; 1113 hwmgr->platform_descriptor.VidAdjustmentPolarity = 0; 1114 hwmgr->platform_descriptor.VidMinLimit = 0; 1115 hwmgr->platform_descriptor.VidMaxLimit = 1500000; 1116 hwmgr->platform_descriptor.VidStep = 6250; 1117 1118 disable_power_control = 0; 1119 if (!disable_power_control) { 1120 /* enable TDP overdrive (PowerControl) feature as well if supported */ 1121 if (hwmgr->platform_descriptor.TDPODLimit) 1122 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1123 PHM_PlatformCaps_PowerControl); 1124 } 1125 1126 if (powerplay_table->usVddcLookupTableOffset) { 1127 const ATOM_Vega10_Voltage_Lookup_Table *vddc_table = 1128 (ATOM_Vega10_Voltage_Lookup_Table *) 1129 (((unsigned long)powerplay_table) + 1130 le16_to_cpu(powerplay_table->usVddcLookupTableOffset)); 1131 result = get_vddc_lookup_table(hwmgr, 1132 &pp_table_info->vddc_lookup_table, vddc_table, 8); 1133 } 1134 1135 if (powerplay_table->usVddmemLookupTableOffset) { 1136 const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table = 1137 (ATOM_Vega10_Voltage_Lookup_Table *) 1138 (((unsigned long)powerplay_table) + 1139 le16_to_cpu(powerplay_table->usVddmemLookupTableOffset)); 1140 result = get_vddc_lookup_table(hwmgr, 1141 &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4); 1142 } 1143 1144 if (powerplay_table->usVddciLookupTableOffset) { 1145 const ATOM_Vega10_Voltage_Lookup_Table *vddci_table = 1146 (ATOM_Vega10_Voltage_Lookup_Table *) 1147 (((unsigned long)powerplay_table) + 1148 le16_to_cpu(powerplay_table->usVddciLookupTableOffset)); 1149 result = get_vddc_lookup_table(hwmgr, 1150 &pp_table_info->vddci_lookup_table, vddci_table, 4); 1151 } 1152 1153 return result; 1154 } 1155 1156 int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr) 1157 { 1158 int result = 0; 1159 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table; 1160 1161 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL); 1162 1163 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), 1164 "Failed to allocate hwmgr->pptable!", return -ENOMEM); 1165 1166 powerplay_table = get_powerplay_table(hwmgr); 1167 1168 PP_ASSERT_WITH_CODE((powerplay_table != NULL), 1169 "Missing PowerPlay Table!", return -1); 1170 1171 result = check_powerplay_tables(hwmgr, powerplay_table); 1172 1173 PP_ASSERT_WITH_CODE((result == 0), 1174 "check_powerplay_tables failed", return result); 1175 1176 result = set_platform_caps(hwmgr, 1177 le32_to_cpu(powerplay_table->ulPlatformCaps)); 1178 1179 PP_ASSERT_WITH_CODE((result == 0), 1180 "set_platform_caps failed", return result); 1181 1182 result = init_thermal_controller(hwmgr, powerplay_table); 1183 1184 PP_ASSERT_WITH_CODE((result == 0), 1185 "init_thermal_controller failed", return result); 1186 1187 result = init_over_drive_limits(hwmgr, powerplay_table); 1188 1189 PP_ASSERT_WITH_CODE((result == 0), 1190 "init_over_drive_limits failed", return result); 1191 1192 result = init_powerplay_extended_tables(hwmgr, powerplay_table); 1193 1194 PP_ASSERT_WITH_CODE((result == 0), 1195 "init_powerplay_extended_tables failed", return result); 1196 1197 result = init_dpm_2_parameters(hwmgr, powerplay_table); 1198 1199 PP_ASSERT_WITH_CODE((result == 0), 1200 "init_dpm_2_parameters failed", return result); 1201 1202 return result; 1203 } 1204 1205 static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) 1206 { 1207 struct phm_ppt_v2_information *pp_table_info = 1208 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1209 1210 kfree(pp_table_info->vdd_dep_on_sclk); 1211 pp_table_info->vdd_dep_on_sclk = NULL; 1212 1213 kfree(pp_table_info->vdd_dep_on_mclk); 1214 pp_table_info->vdd_dep_on_mclk = NULL; 1215 1216 kfree(pp_table_info->valid_mclk_values); 1217 pp_table_info->valid_mclk_values = NULL; 1218 1219 kfree(pp_table_info->valid_sclk_values); 1220 pp_table_info->valid_sclk_values = NULL; 1221 1222 kfree(pp_table_info->vddc_lookup_table); 1223 pp_table_info->vddc_lookup_table = NULL; 1224 1225 kfree(pp_table_info->vddmem_lookup_table); 1226 pp_table_info->vddmem_lookup_table = NULL; 1227 1228 kfree(pp_table_info->vddci_lookup_table); 1229 pp_table_info->vddci_lookup_table = NULL; 1230 1231 kfree(pp_table_info->ppm_parameter_table); 1232 pp_table_info->ppm_parameter_table = NULL; 1233 1234 kfree(pp_table_info->mm_dep_table); 1235 pp_table_info->mm_dep_table = NULL; 1236 1237 kfree(pp_table_info->cac_dtp_table); 1238 pp_table_info->cac_dtp_table = NULL; 1239 1240 kfree(hwmgr->dyn_state.cac_dtp_table); 1241 hwmgr->dyn_state.cac_dtp_table = NULL; 1242 1243 kfree(pp_table_info->tdp_table); 1244 pp_table_info->tdp_table = NULL; 1245 1246 kfree(hwmgr->pptable); 1247 hwmgr->pptable = NULL; 1248 1249 return 0; 1250 } 1251 1252 const struct pp_table_func vega10_pptable_funcs = { 1253 .pptable_init = vega10_pp_tables_initialize, 1254 .pptable_fini = vega10_pp_tables_uninitialize, 1255 }; 1256 1257 int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) 1258 { 1259 const ATOM_Vega10_State_Array *state_arrays; 1260 const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr); 1261 1262 PP_ASSERT_WITH_CODE((pp_table != NULL), 1263 "Missing PowerPlay Table!", return -1); 1264 PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >= 1265 ATOM_Vega10_TABLE_REVISION_VEGA10), 1266 "Incorrect PowerPlay table revision!", return -1); 1267 1268 state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) + 1269 le16_to_cpu(pp_table->usStateArrayOffset)); 1270 1271 return (uint32_t)(state_arrays->ucNumEntries); 1272 } 1273 1274 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, 1275 uint16_t classification, uint16_t classification2) 1276 { 1277 uint32_t result = 0; 1278 1279 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) 1280 result |= PP_StateClassificationFlag_Boot; 1281 1282 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) 1283 result |= PP_StateClassificationFlag_Thermal; 1284 1285 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) 1286 result |= PP_StateClassificationFlag_LimitedPowerSource; 1287 1288 if (classification & ATOM_PPLIB_CLASSIFICATION_REST) 1289 result |= PP_StateClassificationFlag_Rest; 1290 1291 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) 1292 result |= PP_StateClassificationFlag_Forced; 1293 1294 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) 1295 result |= PP_StateClassificationFlag_ACPI; 1296 1297 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) 1298 result |= PP_StateClassificationFlag_LimitedPowerSource_2; 1299 1300 return result; 1301 } 1302 1303 int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, 1304 uint32_t entry_index, struct pp_power_state *power_state, 1305 int (*call_back_func)(struct pp_hwmgr *, void *, 1306 struct pp_power_state *, void *, uint32_t)) 1307 { 1308 int result = 0; 1309 const ATOM_Vega10_State_Array *state_arrays; 1310 const ATOM_Vega10_State *state_entry; 1311 const ATOM_Vega10_POWERPLAYTABLE *pp_table = 1312 get_powerplay_table(hwmgr); 1313 1314 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", 1315 return -1;); 1316 power_state->classification.bios_index = entry_index; 1317 1318 if (pp_table->sHeader.format_revision >= 1319 ATOM_Vega10_TABLE_REVISION_VEGA10) { 1320 state_arrays = (ATOM_Vega10_State_Array *) 1321 (((unsigned long)pp_table) + 1322 le16_to_cpu(pp_table->usStateArrayOffset)); 1323 1324 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, 1325 "Invalid PowerPlay Table State Array Offset.", 1326 return -1); 1327 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, 1328 "Invalid PowerPlay Table State Array.", 1329 return -1); 1330 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), 1331 "Invalid PowerPlay Table State Array Entry.", 1332 return -1); 1333 1334 state_entry = &(state_arrays->states[entry_index]); 1335 1336 result = call_back_func(hwmgr, (void *)state_entry, power_state, 1337 (void *)pp_table, 1338 make_classification_flags(hwmgr, 1339 le16_to_cpu(state_entry->usClassification), 1340 le16_to_cpu(state_entry->usClassification2))); 1341 } 1342 1343 if (!result && (power_state->classification.flags & 1344 PP_StateClassificationFlag_Boot)) 1345 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); 1346 1347 return result; 1348 } 1349 1350 int vega10_baco_set_cap(struct pp_hwmgr *hwmgr) 1351 { 1352 int result = 0; 1353 1354 const ATOM_Vega10_POWERPLAYTABLE *powerplay_table; 1355 1356 powerplay_table = get_powerplay_table(hwmgr); 1357 1358 PP_ASSERT_WITH_CODE((powerplay_table != NULL), 1359 "Missing PowerPlay Table!", return -1); 1360 1361 result = check_powerplay_tables(hwmgr, powerplay_table); 1362 1363 PP_ASSERT_WITH_CODE((result == 0), 1364 "check_powerplay_tables failed", return result); 1365 1366 set_hw_cap( 1367 hwmgr, 1368 0 != (le32_to_cpu(powerplay_table->ulPlatformCaps) & ATOM_VEGA10_PP_PLATFORM_CAP_BACO), 1369 PHM_PlatformCaps_BACO); 1370 return result; 1371 } 1372 1373