1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/fb.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include <linux/slab.h> 29 30 #include "hwmgr.h" 31 #include "amd_powerplay.h" 32 #include "hardwaremanager.h" 33 #include "ppatomfwctrl.h" 34 #include "atomfirmware.h" 35 #include "cgs_common.h" 36 #include "vega10_powertune.h" 37 #include "smu9.h" 38 #include "smu9_driver_if.h" 39 #include "vega10_inc.h" 40 #include "soc15_common.h" 41 #include "pppcielanes.h" 42 #include "vega10_hwmgr.h" 43 #include "vega10_smumgr.h" 44 #include "vega10_processpptables.h" 45 #include "vega10_pptable.h" 46 #include "vega10_thermal.h" 47 #include "pp_debug.h" 48 #include "amd_pcie_helpers.h" 49 #include "ppinterrupt.h" 50 #include "pp_overdriver.h" 51 #include "pp_thermal.h" 52 #include "vega10_baco.h" 53 54 #include "smuio/smuio_9_0_offset.h" 55 #include "smuio/smuio_9_0_sh_mask.h" 56 57 #define smnPCIE_LC_SPEED_CNTL 0x11140290 58 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 59 60 #define HBM_MEMORY_CHANNEL_WIDTH 128 61 62 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; 63 64 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 65 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 66 67 //DF_CS_AON0_DramBaseAddress0 68 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 69 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 70 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 71 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 72 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 73 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 74 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 75 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 76 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 77 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 78 79 typedef enum { 80 CLK_SMNCLK = 0, 81 CLK_SOCCLK, 82 CLK_MP0CLK, 83 CLK_MP1CLK, 84 CLK_LCLK, 85 CLK_DCEFCLK, 86 CLK_VCLK, 87 CLK_DCLK, 88 CLK_ECLK, 89 CLK_UCLK, 90 CLK_GFXCLK, 91 CLK_COUNT, 92 } CLOCK_ID_e; 93 94 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic); 95 96 static struct vega10_power_state *cast_phw_vega10_power_state( 97 struct pp_hw_power_state *hw_ps) 98 { 99 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 100 "Invalid Powerstate Type!", 101 return NULL;); 102 103 return (struct vega10_power_state *)hw_ps; 104 } 105 106 static const struct vega10_power_state *cast_const_phw_vega10_power_state( 107 const struct pp_hw_power_state *hw_ps) 108 { 109 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 110 "Invalid Powerstate Type!", 111 return NULL;); 112 113 return (const struct vega10_power_state *)hw_ps; 114 } 115 116 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) 117 { 118 struct vega10_hwmgr *data = hwmgr->backend; 119 120 data->registry_data.sclk_dpm_key_disabled = 121 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 122 data->registry_data.socclk_dpm_key_disabled = 123 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; 124 data->registry_data.mclk_dpm_key_disabled = 125 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 126 data->registry_data.pcie_dpm_key_disabled = 127 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; 128 129 data->registry_data.dcefclk_dpm_key_disabled = 130 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; 131 132 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { 133 data->registry_data.power_containment_support = 1; 134 data->registry_data.enable_pkg_pwr_tracking_feature = 1; 135 data->registry_data.enable_tdc_limit_feature = 1; 136 } 137 138 data->registry_data.clock_stretcher_support = 139 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; 140 141 data->registry_data.ulv_support = 142 hwmgr->feature_mask & PP_ULV_MASK ? true : false; 143 144 data->registry_data.sclk_deep_sleep_support = 145 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; 146 147 data->registry_data.disable_water_mark = 0; 148 149 data->registry_data.fan_control_support = 1; 150 data->registry_data.thermal_support = 1; 151 data->registry_data.fw_ctf_enabled = 1; 152 153 data->registry_data.avfs_support = 154 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; 155 data->registry_data.led_dpm_enabled = 1; 156 157 data->registry_data.vr0hot_enabled = 1; 158 data->registry_data.vr1hot_enabled = 1; 159 data->registry_data.regulator_hot_gpio_support = 1; 160 161 data->registry_data.didt_support = 1; 162 if (data->registry_data.didt_support) { 163 data->registry_data.didt_mode = 6; 164 data->registry_data.sq_ramping_support = 1; 165 data->registry_data.db_ramping_support = 0; 166 data->registry_data.td_ramping_support = 0; 167 data->registry_data.tcp_ramping_support = 0; 168 data->registry_data.dbr_ramping_support = 0; 169 data->registry_data.edc_didt_support = 1; 170 data->registry_data.gc_didt_support = 0; 171 data->registry_data.psm_didt_support = 0; 172 } 173 174 data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; 175 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 176 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 177 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 178 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 179 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 180 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 181 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 182 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 183 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 184 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 185 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 186 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 187 188 data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT; 189 data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT; 190 data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT; 191 data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT; 192 } 193 194 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) 195 { 196 struct vega10_hwmgr *data = hwmgr->backend; 197 struct phm_ppt_v2_information *table_info = 198 (struct phm_ppt_v2_information *)hwmgr->pptable; 199 struct amdgpu_device *adev = hwmgr->adev; 200 201 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 202 PHM_PlatformCaps_SclkDeepSleep); 203 204 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 205 PHM_PlatformCaps_DynamicPatchPowerState); 206 207 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) 208 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 209 PHM_PlatformCaps_ControlVDDCI); 210 211 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 212 PHM_PlatformCaps_EnableSMU7ThermalManagement); 213 214 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 215 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 216 PHM_PlatformCaps_UVDPowerGating); 217 218 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 219 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 220 PHM_PlatformCaps_VCEPowerGating); 221 222 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 223 PHM_PlatformCaps_UnTabledHardwareInterface); 224 225 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 226 PHM_PlatformCaps_FanSpeedInTableIsRPM); 227 228 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 229 PHM_PlatformCaps_ODFuzzyFanControlSupport); 230 231 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 232 PHM_PlatformCaps_DynamicPowerManagement); 233 234 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 235 PHM_PlatformCaps_SMC); 236 237 /* power tune caps */ 238 /* assume disabled */ 239 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 240 PHM_PlatformCaps_PowerContainment); 241 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 242 PHM_PlatformCaps_DiDtSupport); 243 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 244 PHM_PlatformCaps_SQRamping); 245 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 246 PHM_PlatformCaps_DBRamping); 247 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 248 PHM_PlatformCaps_TDRamping); 249 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 250 PHM_PlatformCaps_TCPRamping); 251 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 252 PHM_PlatformCaps_DBRRamping); 253 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 254 PHM_PlatformCaps_DiDtEDCEnable); 255 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 256 PHM_PlatformCaps_GCEDC); 257 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 258 PHM_PlatformCaps_PSM); 259 260 if (data->registry_data.didt_support) { 261 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 262 if (data->registry_data.sq_ramping_support) 263 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 264 if (data->registry_data.db_ramping_support) 265 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 266 if (data->registry_data.td_ramping_support) 267 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 268 if (data->registry_data.tcp_ramping_support) 269 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 270 if (data->registry_data.dbr_ramping_support) 271 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 272 if (data->registry_data.edc_didt_support) 273 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 274 if (data->registry_data.gc_didt_support) 275 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 276 if (data->registry_data.psm_didt_support) 277 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 278 } 279 280 if (data->registry_data.power_containment_support) 281 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 282 PHM_PlatformCaps_PowerContainment); 283 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 284 PHM_PlatformCaps_CAC); 285 286 if (table_info->tdp_table->usClockStretchAmount && 287 data->registry_data.clock_stretcher_support) 288 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 289 PHM_PlatformCaps_ClockStretcher); 290 291 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 292 PHM_PlatformCaps_RegulatorHot); 293 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 294 PHM_PlatformCaps_AutomaticDCTransition); 295 296 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 297 PHM_PlatformCaps_UVDDPM); 298 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 299 PHM_PlatformCaps_VCEDPM); 300 301 return 0; 302 } 303 304 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 305 { 306 struct vega10_hwmgr *data = hwmgr->backend; 307 struct phm_ppt_v2_information *table_info = 308 (struct phm_ppt_v2_information *)(hwmgr->pptable); 309 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 310 struct vega10_odn_vddc_lookup_table *od_lookup_table; 311 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 312 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3]; 313 struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3]; 314 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 315 uint32_t i; 316 int result; 317 318 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 319 if (!result) { 320 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc; 321 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc; 322 } 323 324 od_lookup_table = &odn_table->vddc_lookup_table; 325 vddc_lookup_table = table_info->vddc_lookup_table; 326 327 for (i = 0; i < vddc_lookup_table->count; i++) 328 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd; 329 330 od_lookup_table->count = vddc_lookup_table->count; 331 332 dep_table[0] = table_info->vdd_dep_on_sclk; 333 dep_table[1] = table_info->vdd_dep_on_mclk; 334 dep_table[2] = table_info->vdd_dep_on_socclk; 335 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; 336 od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk; 337 od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk; 338 339 for (i = 0; i < 3; i++) 340 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]); 341 342 if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000) 343 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc; 344 if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000) 345 odn_table->min_vddc = dep_table[0]->entries[0].vddc; 346 347 i = od_table[2]->count - 1; 348 od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ? 349 hwmgr->platform_descriptor.overdriveLimit.memoryClock : 350 od_table[2]->entries[i].clk; 351 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? 352 odn_table->max_vddc : 353 od_table[2]->entries[i].vddc; 354 355 return 0; 356 } 357 358 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) 359 { 360 struct vega10_hwmgr *data = hwmgr->backend; 361 int i; 362 uint32_t sub_vendor_id, hw_revision; 363 uint32_t top32, bottom32; 364 struct amdgpu_device *adev = hwmgr->adev; 365 366 vega10_initialize_power_tune_defaults(hwmgr); 367 368 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 369 data->smu_features[i].smu_feature_id = 0xffff; 370 data->smu_features[i].smu_feature_bitmap = 1 << i; 371 data->smu_features[i].enabled = false; 372 data->smu_features[i].supported = false; 373 } 374 375 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 376 FEATURE_DPM_PREFETCHER_BIT; 377 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 378 FEATURE_DPM_GFXCLK_BIT; 379 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 380 FEATURE_DPM_UCLK_BIT; 381 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 382 FEATURE_DPM_SOCCLK_BIT; 383 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 384 FEATURE_DPM_UVD_BIT; 385 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 386 FEATURE_DPM_VCE_BIT; 387 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 388 FEATURE_DPM_MP0CLK_BIT; 389 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 390 FEATURE_DPM_LINK_BIT; 391 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 392 FEATURE_DPM_DCEFCLK_BIT; 393 data->smu_features[GNLD_ULV].smu_feature_id = 394 FEATURE_ULV_BIT; 395 data->smu_features[GNLD_AVFS].smu_feature_id = 396 FEATURE_AVFS_BIT; 397 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 398 FEATURE_DS_GFXCLK_BIT; 399 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 400 FEATURE_DS_SOCCLK_BIT; 401 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 402 FEATURE_DS_LCLK_BIT; 403 data->smu_features[GNLD_PPT].smu_feature_id = 404 FEATURE_PPT_BIT; 405 data->smu_features[GNLD_TDC].smu_feature_id = 406 FEATURE_TDC_BIT; 407 data->smu_features[GNLD_THERMAL].smu_feature_id = 408 FEATURE_THERMAL_BIT; 409 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 410 FEATURE_GFX_PER_CU_CG_BIT; 411 data->smu_features[GNLD_RM].smu_feature_id = 412 FEATURE_RM_BIT; 413 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 414 FEATURE_DS_DCEFCLK_BIT; 415 data->smu_features[GNLD_ACDC].smu_feature_id = 416 FEATURE_ACDC_BIT; 417 data->smu_features[GNLD_VR0HOT].smu_feature_id = 418 FEATURE_VR0HOT_BIT; 419 data->smu_features[GNLD_VR1HOT].smu_feature_id = 420 FEATURE_VR1HOT_BIT; 421 data->smu_features[GNLD_FW_CTF].smu_feature_id = 422 FEATURE_FW_CTF_BIT; 423 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 424 FEATURE_LED_DISPLAY_BIT; 425 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 426 FEATURE_FAN_CONTROL_BIT; 427 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 428 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 429 data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; 430 431 if (!data->registry_data.prefetcher_dpm_key_disabled) 432 data->smu_features[GNLD_DPM_PREFETCHER].supported = true; 433 434 if (!data->registry_data.sclk_dpm_key_disabled) 435 data->smu_features[GNLD_DPM_GFXCLK].supported = true; 436 437 if (!data->registry_data.mclk_dpm_key_disabled) 438 data->smu_features[GNLD_DPM_UCLK].supported = true; 439 440 if (!data->registry_data.socclk_dpm_key_disabled) 441 data->smu_features[GNLD_DPM_SOCCLK].supported = true; 442 443 if (PP_CAP(PHM_PlatformCaps_UVDDPM)) 444 data->smu_features[GNLD_DPM_UVD].supported = true; 445 446 if (PP_CAP(PHM_PlatformCaps_VCEDPM)) 447 data->smu_features[GNLD_DPM_VCE].supported = true; 448 449 data->smu_features[GNLD_DPM_LINK].supported = true; 450 451 if (!data->registry_data.dcefclk_dpm_key_disabled) 452 data->smu_features[GNLD_DPM_DCEFCLK].supported = true; 453 454 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && 455 data->registry_data.sclk_deep_sleep_support) { 456 data->smu_features[GNLD_DS_GFXCLK].supported = true; 457 data->smu_features[GNLD_DS_SOCCLK].supported = true; 458 data->smu_features[GNLD_DS_LCLK].supported = true; 459 data->smu_features[GNLD_DS_DCEFCLK].supported = true; 460 } 461 462 if (data->registry_data.enable_pkg_pwr_tracking_feature) 463 data->smu_features[GNLD_PPT].supported = true; 464 465 if (data->registry_data.enable_tdc_limit_feature) 466 data->smu_features[GNLD_TDC].supported = true; 467 468 if (data->registry_data.thermal_support) 469 data->smu_features[GNLD_THERMAL].supported = true; 470 471 if (data->registry_data.fan_control_support) 472 data->smu_features[GNLD_FAN_CONTROL].supported = true; 473 474 if (data->registry_data.fw_ctf_enabled) 475 data->smu_features[GNLD_FW_CTF].supported = true; 476 477 if (data->registry_data.avfs_support) 478 data->smu_features[GNLD_AVFS].supported = true; 479 480 if (data->registry_data.led_dpm_enabled) 481 data->smu_features[GNLD_LED_DISPLAY].supported = true; 482 483 if (data->registry_data.vr1hot_enabled) 484 data->smu_features[GNLD_VR1HOT].supported = true; 485 486 if (data->registry_data.vr0hot_enabled) 487 data->smu_features[GNLD_VR0HOT].supported = true; 488 489 smum_send_msg_to_smc(hwmgr, 490 PPSMC_MSG_GetSmuVersion, 491 &hwmgr->smu_version); 492 /* ACG firmware has major version 5 */ 493 if ((hwmgr->smu_version & 0xff000000) == 0x5000000) 494 data->smu_features[GNLD_ACG].supported = true; 495 if (data->registry_data.didt_support) 496 data->smu_features[GNLD_DIDT].supported = true; 497 498 hw_revision = adev->pdev->revision; 499 sub_vendor_id = adev->pdev->subsystem_vendor; 500 501 if ((hwmgr->chip_id == 0x6862 || 502 hwmgr->chip_id == 0x6861 || 503 hwmgr->chip_id == 0x6868) && 504 (hw_revision == 0) && 505 (sub_vendor_id != 0x1002)) 506 data->smu_features[GNLD_PCC_LIMIT].supported = true; 507 508 /* Get the SN to turn into a Unique ID */ 509 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 510 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 511 512 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 513 } 514 515 #ifdef PPLIB_VEGA10_EVV_SUPPORT 516 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, 517 phm_ppt_v1_voltage_lookup_table *lookup_table, 518 uint16_t virtual_voltage_id, int32_t *socclk) 519 { 520 uint8_t entry_id; 521 uint8_t voltage_id; 522 struct phm_ppt_v2_information *table_info = 523 (struct phm_ppt_v2_information *)(hwmgr->pptable); 524 525 PP_ASSERT_WITH_CODE(lookup_table->count != 0, 526 "Lookup table is empty", 527 return -EINVAL); 528 529 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */ 530 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { 531 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd; 532 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) 533 break; 534 } 535 536 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, 537 "Can't find requested voltage id in vdd_dep_on_socclk table!", 538 return -EINVAL); 539 540 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk; 541 542 return 0; 543 } 544 545 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 546 /** 547 * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. 548 * 549 * @hwmgr: the address of the powerplay hardware manager. 550 * return: always 0. 551 */ 552 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) 553 { 554 struct vega10_hwmgr *data = hwmgr->backend; 555 uint16_t vv_id; 556 uint32_t vddc = 0; 557 uint16_t i, j; 558 uint32_t sclk = 0; 559 struct phm_ppt_v2_information *table_info = 560 (struct phm_ppt_v2_information *)hwmgr->pptable; 561 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = 562 table_info->vdd_dep_on_socclk; 563 int result; 564 565 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) { 566 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 567 568 if (!vega10_get_socclk_for_voltage_evv(hwmgr, 569 table_info->vddc_lookup_table, vv_id, &sclk)) { 570 if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { 571 for (j = 1; j < socclk_table->count; j++) { 572 if (socclk_table->entries[j].clk == sclk && 573 socclk_table->entries[j].cks_enable == 0) { 574 sclk += 5000; 575 break; 576 } 577 } 578 } 579 580 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, 581 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), 582 "Error retrieving EVV voltage value!", 583 continue); 584 585 586 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ 587 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), 588 "Invalid VDDC value", result = -EINVAL;); 589 590 /* the voltage should not be zero nor equal to leakage ID */ 591 if (vddc != 0 && vddc != vv_id) { 592 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); 593 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 594 data->vddc_leakage.count++; 595 } 596 } 597 } 598 599 return 0; 600 } 601 602 /** 603 * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value. 604 * 605 * @hwmgr: the address of the powerplay hardware manager. 606 * @voltage: pointer to changing voltage 607 * @leakage_table: pointer to leakage table 608 */ 609 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, 610 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table) 611 { 612 uint32_t index; 613 614 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 615 for (index = 0; index < leakage_table->count; index++) { 616 /* if this voltage matches a leakage voltage ID */ 617 /* patch with actual leakage voltage */ 618 if (leakage_table->leakage_id[index] == *voltage) { 619 *voltage = leakage_table->actual_voltage[index]; 620 break; 621 } 622 } 623 624 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 625 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 626 } 627 628 /** 629 * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 630 * 631 * @hwmgr: the address of the powerplay hardware manager. 632 * @lookup_table: pointer to voltage lookup table 633 * @leakage_table: pointer to leakage table 634 * return: always 0 635 */ 636 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 637 phm_ppt_v1_voltage_lookup_table *lookup_table, 638 struct vega10_leakage_voltage *leakage_table) 639 { 640 uint32_t i; 641 642 for (i = 0; i < lookup_table->count; i++) 643 vega10_patch_with_vdd_leakage(hwmgr, 644 &lookup_table->entries[i].us_vdd, leakage_table); 645 646 return 0; 647 } 648 649 static int vega10_patch_clock_voltage_limits_with_vddc_leakage( 650 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table, 651 uint16_t *vddc) 652 { 653 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 654 655 return 0; 656 } 657 #endif 658 659 static int vega10_patch_voltage_dependency_tables_with_lookup_table( 660 struct pp_hwmgr *hwmgr) 661 { 662 uint8_t entry_id, voltage_id; 663 unsigned i; 664 struct phm_ppt_v2_information *table_info = 665 (struct phm_ppt_v2_information *)(hwmgr->pptable); 666 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 667 table_info->mm_dep_table; 668 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 669 table_info->vdd_dep_on_mclk; 670 671 for (i = 0; i < 6; i++) { 672 struct phm_ppt_v1_clock_voltage_dependency_table *vdt; 673 switch (i) { 674 case 0: vdt = table_info->vdd_dep_on_socclk; break; 675 case 1: vdt = table_info->vdd_dep_on_sclk; break; 676 case 2: vdt = table_info->vdd_dep_on_dcefclk; break; 677 case 3: vdt = table_info->vdd_dep_on_pixclk; break; 678 case 4: vdt = table_info->vdd_dep_on_dispclk; break; 679 case 5: vdt = table_info->vdd_dep_on_phyclk; break; 680 } 681 682 for (entry_id = 0; entry_id < vdt->count; entry_id++) { 683 voltage_id = vdt->entries[entry_id].vddInd; 684 vdt->entries[entry_id].vddc = 685 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 686 } 687 } 688 689 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 690 voltage_id = mm_table->entries[entry_id].vddcInd; 691 mm_table->entries[entry_id].vddc = 692 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 693 } 694 695 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 696 voltage_id = mclk_table->entries[entry_id].vddInd; 697 mclk_table->entries[entry_id].vddc = 698 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 699 voltage_id = mclk_table->entries[entry_id].vddciInd; 700 mclk_table->entries[entry_id].vddci = 701 table_info->vddci_lookup_table->entries[voltage_id].us_vdd; 702 voltage_id = mclk_table->entries[entry_id].mvddInd; 703 mclk_table->entries[entry_id].mvdd = 704 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; 705 } 706 707 708 return 0; 709 710 } 711 712 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, 713 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 714 { 715 uint32_t table_size, i, j; 716 717 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, 718 "Lookup table is empty", return -EINVAL); 719 720 table_size = lookup_table->count; 721 722 /* Sorting voltages */ 723 for (i = 0; i < table_size - 1; i++) { 724 for (j = i + 1; j > 0; j--) { 725 if (lookup_table->entries[j].us_vdd < 726 lookup_table->entries[j - 1].us_vdd) { 727 swap(lookup_table->entries[j - 1], 728 lookup_table->entries[j]); 729 } 730 } 731 } 732 733 return 0; 734 } 735 736 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) 737 { 738 int result = 0; 739 int tmp_result; 740 struct phm_ppt_v2_information *table_info = 741 (struct phm_ppt_v2_information *)(hwmgr->pptable); 742 #ifdef PPLIB_VEGA10_EVV_SUPPORT 743 struct vega10_hwmgr *data = hwmgr->backend; 744 745 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr, 746 table_info->vddc_lookup_table, &(data->vddc_leakage)); 747 if (tmp_result) 748 result = tmp_result; 749 750 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 751 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 752 if (tmp_result) 753 result = tmp_result; 754 #endif 755 756 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 757 if (tmp_result) 758 result = tmp_result; 759 760 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 761 if (tmp_result) 762 result = tmp_result; 763 764 return result; 765 } 766 767 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 768 { 769 struct phm_ppt_v2_information *table_info = 770 (struct phm_ppt_v2_information *)(hwmgr->pptable); 771 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 772 table_info->vdd_dep_on_socclk; 773 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 774 table_info->vdd_dep_on_mclk; 775 776 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, 777 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); 778 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 779 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); 780 781 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 782 "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); 783 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 784 "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); 785 786 table_info->max_clock_voltage_on_ac.sclk = 787 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 788 table_info->max_clock_voltage_on_ac.mclk = 789 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 790 table_info->max_clock_voltage_on_ac.vddc = 791 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 792 table_info->max_clock_voltage_on_ac.vddci = 793 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 794 795 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 796 table_info->max_clock_voltage_on_ac.sclk; 797 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 798 table_info->max_clock_voltage_on_ac.mclk; 799 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 800 table_info->max_clock_voltage_on_ac.vddc; 801 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = 802 table_info->max_clock_voltage_on_ac.vddci; 803 804 return 0; 805 } 806 807 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 808 { 809 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 810 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 811 812 kfree(hwmgr->backend); 813 hwmgr->backend = NULL; 814 815 return 0; 816 } 817 818 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 819 { 820 int result = 0; 821 struct vega10_hwmgr *data; 822 uint32_t config_telemetry = 0; 823 struct pp_atomfwctrl_voltage_table vol_table; 824 struct amdgpu_device *adev = hwmgr->adev; 825 826 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); 827 if (data == NULL) 828 return -ENOMEM; 829 830 hwmgr->backend = data; 831 832 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 833 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 834 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 835 836 vega10_set_default_registry_data(hwmgr); 837 data->disable_dpm_mask = 0xff; 838 839 /* need to set voltage control types before EVV patching */ 840 data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE; 841 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; 842 data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE; 843 844 /* VDDCR_SOC */ 845 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 846 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { 847 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 848 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2, 849 &vol_table)) { 850 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) | 851 (vol_table.telemetry_offset & 0xff); 852 data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 853 } 854 } else { 855 kfree(hwmgr->backend); 856 hwmgr->backend = NULL; 857 PP_ASSERT_WITH_CODE(false, 858 "VDDCR_SOC is not SVID2!", 859 return -1); 860 } 861 862 /* MVDDC */ 863 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 864 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) { 865 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 866 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2, 867 &vol_table)) { 868 config_telemetry |= 869 ((vol_table.telemetry_slope << 24) & 0xff000000) | 870 ((vol_table.telemetry_offset << 16) & 0xff0000); 871 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 872 } 873 } 874 875 /* VDDCI_MEM */ 876 if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { 877 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 878 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 879 data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; 880 } 881 882 data->config_telemetry = config_telemetry; 883 884 vega10_set_features_platform_caps(hwmgr); 885 886 vega10_init_dpm_defaults(hwmgr); 887 888 #ifdef PPLIB_VEGA10_EVV_SUPPORT 889 /* Get leakage voltage based on leakage ID. */ 890 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), 891 "Get EVV Voltage Failed. Abort Driver loading!", 892 return -1); 893 #endif 894 895 /* Patch our voltage dependency table with actual leakage voltage 896 * We need to perform leakage translation before it's used by other functions 897 */ 898 vega10_complete_dependency_tables(hwmgr); 899 900 /* Parse pptable data read from VBIOS */ 901 vega10_set_private_data_based_on_pptable(hwmgr); 902 903 data->is_tlu_enabled = false; 904 905 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 906 VEGA10_MAX_HARDWARE_POWERLEVELS; 907 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 908 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 909 910 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 911 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 912 hwmgr->platform_descriptor.clockStep.engineClock = 500; 913 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 914 915 data->total_active_cus = adev->gfx.cu_info.number; 916 if (!hwmgr->not_vf) 917 return result; 918 919 /* Setup default Overdrive Fan control settings */ 920 data->odn_fan_table.target_fan_speed = 921 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 922 data->odn_fan_table.target_temperature = 923 hwmgr->thermal_controller. 924 advanceFanControlParameters.ucTargetTemperature; 925 data->odn_fan_table.min_performance_clock = 926 hwmgr->thermal_controller.advanceFanControlParameters. 927 ulMinFanSCLKAcousticLimit; 928 data->odn_fan_table.min_fan_limit = 929 hwmgr->thermal_controller. 930 advanceFanControlParameters.usFanPWMMinLimit * 931 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 932 933 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & 934 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> 935 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 936 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), 937 "Mem Channel Index Exceeded maximum!", 938 return -EINVAL); 939 940 return result; 941 } 942 943 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) 944 { 945 struct vega10_hwmgr *data = hwmgr->backend; 946 947 data->low_sclk_interrupt_threshold = 0; 948 949 return 0; 950 } 951 952 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr) 953 { 954 struct vega10_hwmgr *data = hwmgr->backend; 955 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 956 957 struct pp_atomfwctrl_voltage_table table; 958 uint8_t i, j; 959 uint32_t mask = 0; 960 uint32_t tmp; 961 int32_t ret = 0; 962 963 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM, 964 VOLTAGE_OBJ_GPIO_LUT, &table); 965 966 if (!ret) { 967 tmp = table.mask_low; 968 for (i = 0, j = 0; i < 32; i++) { 969 if (tmp & 1) { 970 mask |= (uint32_t)(i << (8 * j)); 971 if (++j >= 3) 972 break; 973 } 974 tmp >>= 1; 975 } 976 } 977 978 pp_table->LedPin0 = (uint8_t)(mask & 0xff); 979 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); 980 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); 981 return 0; 982 } 983 984 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) 985 { 986 if (!hwmgr->not_vf) 987 return 0; 988 989 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), 990 "Failed to init sclk threshold!", 991 return -EINVAL); 992 993 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), 994 "Failed to set up led dpm config!", 995 return -EINVAL); 996 997 smum_send_msg_to_smc_with_parameter(hwmgr, 998 PPSMC_MSG_NumOfDisplays, 999 0, 1000 NULL); 1001 1002 return 0; 1003 } 1004 1005 /** 1006 * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values. 1007 * 1008 * @hwmgr: the address of the powerplay hardware manager. 1009 * @vol_table: the pointer to changing voltage table 1010 * return: 0 in success 1011 */ 1012 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr, 1013 struct pp_atomfwctrl_voltage_table *vol_table) 1014 { 1015 uint32_t i, j; 1016 uint16_t vvalue; 1017 bool found = false; 1018 struct pp_atomfwctrl_voltage_table *table; 1019 1020 PP_ASSERT_WITH_CODE(vol_table, 1021 "Voltage Table empty.", return -EINVAL); 1022 table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table), 1023 GFP_KERNEL); 1024 1025 if (!table) 1026 return -ENOMEM; 1027 1028 table->mask_low = vol_table->mask_low; 1029 table->phase_delay = vol_table->phase_delay; 1030 1031 for (i = 0; i < vol_table->count; i++) { 1032 vvalue = vol_table->entries[i].value; 1033 found = false; 1034 1035 for (j = 0; j < table->count; j++) { 1036 if (vvalue == table->entries[j].value) { 1037 found = true; 1038 break; 1039 } 1040 } 1041 1042 if (!found) { 1043 table->entries[table->count].value = vvalue; 1044 table->entries[table->count].smio_low = 1045 vol_table->entries[i].smio_low; 1046 table->count++; 1047 } 1048 } 1049 1050 memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table)); 1051 kfree(table); 1052 1053 return 0; 1054 } 1055 1056 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr, 1057 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1058 struct pp_atomfwctrl_voltage_table *vol_table) 1059 { 1060 int i; 1061 1062 PP_ASSERT_WITH_CODE(dep_table->count, 1063 "Voltage Dependency Table empty.", 1064 return -EINVAL); 1065 1066 vol_table->mask_low = 0; 1067 vol_table->phase_delay = 0; 1068 vol_table->count = dep_table->count; 1069 1070 for (i = 0; i < vol_table->count; i++) { 1071 vol_table->entries[i].value = dep_table->entries[i].mvdd; 1072 vol_table->entries[i].smio_low = 0; 1073 } 1074 1075 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, 1076 vol_table), 1077 "Failed to trim MVDD Table!", 1078 return -1); 1079 1080 return 0; 1081 } 1082 1083 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr, 1084 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1085 struct pp_atomfwctrl_voltage_table *vol_table) 1086 { 1087 uint32_t i; 1088 1089 PP_ASSERT_WITH_CODE(dep_table->count, 1090 "Voltage Dependency Table empty.", 1091 return -EINVAL); 1092 1093 vol_table->mask_low = 0; 1094 vol_table->phase_delay = 0; 1095 vol_table->count = dep_table->count; 1096 1097 for (i = 0; i < dep_table->count; i++) { 1098 vol_table->entries[i].value = dep_table->entries[i].vddci; 1099 vol_table->entries[i].smio_low = 0; 1100 } 1101 1102 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), 1103 "Failed to trim VDDCI table.", 1104 return -1); 1105 1106 return 0; 1107 } 1108 1109 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr, 1110 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1111 struct pp_atomfwctrl_voltage_table *vol_table) 1112 { 1113 int i; 1114 1115 PP_ASSERT_WITH_CODE(dep_table->count, 1116 "Voltage Dependency Table empty.", 1117 return -EINVAL); 1118 1119 vol_table->mask_low = 0; 1120 vol_table->phase_delay = 0; 1121 vol_table->count = dep_table->count; 1122 1123 for (i = 0; i < vol_table->count; i++) { 1124 vol_table->entries[i].value = dep_table->entries[i].vddc; 1125 vol_table->entries[i].smio_low = 0; 1126 } 1127 1128 return 0; 1129 } 1130 1131 /* ---- Voltage Tables ---- 1132 * If the voltage table would be bigger than 1133 * what will fit into the state table on 1134 * the SMC keep only the higher entries. 1135 */ 1136 static void vega10_trim_voltage_table_to_fit_state_table( 1137 struct pp_hwmgr *hwmgr, 1138 uint32_t max_vol_steps, 1139 struct pp_atomfwctrl_voltage_table *vol_table) 1140 { 1141 unsigned int i, diff; 1142 1143 if (vol_table->count <= max_vol_steps) 1144 return; 1145 1146 diff = vol_table->count - max_vol_steps; 1147 1148 for (i = 0; i < max_vol_steps; i++) 1149 vol_table->entries[i] = vol_table->entries[i + diff]; 1150 1151 vol_table->count = max_vol_steps; 1152 } 1153 1154 /** 1155 * vega10_construct_voltage_tables - Create Voltage Tables. 1156 * 1157 * @hwmgr: the address of the powerplay hardware manager. 1158 * return: always 0 1159 */ 1160 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr) 1161 { 1162 struct vega10_hwmgr *data = hwmgr->backend; 1163 struct phm_ppt_v2_information *table_info = 1164 (struct phm_ppt_v2_information *)hwmgr->pptable; 1165 int result; 1166 1167 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1168 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1169 result = vega10_get_mvdd_voltage_table(hwmgr, 1170 table_info->vdd_dep_on_mclk, 1171 &(data->mvdd_voltage_table)); 1172 PP_ASSERT_WITH_CODE(!result, 1173 "Failed to retrieve MVDDC table!", 1174 return result); 1175 } 1176 1177 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1178 result = vega10_get_vddci_voltage_table(hwmgr, 1179 table_info->vdd_dep_on_mclk, 1180 &(data->vddci_voltage_table)); 1181 PP_ASSERT_WITH_CODE(!result, 1182 "Failed to retrieve VDDCI_MEM table!", 1183 return result); 1184 } 1185 1186 if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1187 data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1188 result = vega10_get_vdd_voltage_table(hwmgr, 1189 table_info->vdd_dep_on_sclk, 1190 &(data->vddc_voltage_table)); 1191 PP_ASSERT_WITH_CODE(!result, 1192 "Failed to retrieve VDDCR_SOC table!", 1193 return result); 1194 } 1195 1196 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16, 1197 "Too many voltage values for VDDC. Trimming to fit state table.", 1198 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1199 16, &(data->vddc_voltage_table))); 1200 1201 PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16, 1202 "Too many voltage values for VDDCI. Trimming to fit state table.", 1203 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1204 16, &(data->vddci_voltage_table))); 1205 1206 PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16, 1207 "Too many voltage values for MVDD. Trimming to fit state table.", 1208 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1209 16, &(data->mvdd_voltage_table))); 1210 1211 1212 return 0; 1213 } 1214 1215 /* 1216 * vega10_init_dpm_state 1217 * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 1218 * 1219 * @dpm_state: - the address of the DPM Table to initiailize. 1220 * return: None. 1221 */ 1222 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state) 1223 { 1224 dpm_state->soft_min_level = 0xff; 1225 dpm_state->soft_max_level = 0xff; 1226 dpm_state->hard_min_level = 0xff; 1227 dpm_state->hard_max_level = 0xff; 1228 } 1229 1230 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, 1231 struct vega10_single_dpm_table *dpm_table, 1232 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) 1233 { 1234 int i; 1235 1236 dpm_table->count = 0; 1237 1238 for (i = 0; i < dep_table->count; i++) { 1239 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= 1240 dep_table->entries[i].clk) { 1241 dpm_table->dpm_levels[dpm_table->count].value = 1242 dep_table->entries[i].clk; 1243 dpm_table->dpm_levels[dpm_table->count].enabled = true; 1244 dpm_table->count++; 1245 } 1246 } 1247 } 1248 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 1249 { 1250 struct vega10_hwmgr *data = hwmgr->backend; 1251 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); 1252 struct phm_ppt_v2_information *table_info = 1253 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1254 struct phm_ppt_v1_pcie_table *bios_pcie_table = 1255 table_info->pcie_table; 1256 uint32_t i; 1257 1258 PP_ASSERT_WITH_CODE(bios_pcie_table->count, 1259 "Incorrect number of PCIE States from VBIOS!", 1260 return -1); 1261 1262 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1263 if (data->registry_data.pcieSpeedOverride) 1264 pcie_table->pcie_gen[i] = 1265 data->registry_data.pcieSpeedOverride; 1266 else 1267 pcie_table->pcie_gen[i] = 1268 bios_pcie_table->entries[i].gen_speed; 1269 1270 if (data->registry_data.pcieLaneOverride) 1271 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1272 data->registry_data.pcieLaneOverride); 1273 else 1274 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1275 bios_pcie_table->entries[i].lane_width); 1276 if (data->registry_data.pcieClockOverride) 1277 pcie_table->lclk[i] = 1278 data->registry_data.pcieClockOverride; 1279 else 1280 pcie_table->lclk[i] = 1281 bios_pcie_table->entries[i].pcie_sclk; 1282 } 1283 1284 pcie_table->count = NUM_LINK_LEVELS; 1285 1286 return 0; 1287 } 1288 1289 /* 1290 * This function is to initialize all DPM state tables 1291 * for SMU based on the dependency table. 1292 * Dynamic state patching function will then trim these 1293 * state tables to the allowed range based 1294 * on the power policy or external client requests, 1295 * such as UVD request, etc. 1296 */ 1297 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1298 { 1299 struct vega10_hwmgr *data = hwmgr->backend; 1300 struct phm_ppt_v2_information *table_info = 1301 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1302 struct vega10_single_dpm_table *dpm_table; 1303 uint32_t i; 1304 1305 struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table = 1306 table_info->vdd_dep_on_socclk; 1307 struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table = 1308 table_info->vdd_dep_on_sclk; 1309 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 1310 table_info->vdd_dep_on_mclk; 1311 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table = 1312 table_info->mm_dep_table; 1313 struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table = 1314 table_info->vdd_dep_on_dcefclk; 1315 struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table = 1316 table_info->vdd_dep_on_pixclk; 1317 struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table = 1318 table_info->vdd_dep_on_dispclk; 1319 struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table = 1320 table_info->vdd_dep_on_phyclk; 1321 1322 PP_ASSERT_WITH_CODE(dep_soc_table, 1323 "SOCCLK dependency table is missing. This table is mandatory", 1324 return -EINVAL); 1325 PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1, 1326 "SOCCLK dependency table is empty. This table is mandatory", 1327 return -EINVAL); 1328 1329 PP_ASSERT_WITH_CODE(dep_gfx_table, 1330 "GFXCLK dependency table is missing. This table is mandatory", 1331 return -EINVAL); 1332 PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1, 1333 "GFXCLK dependency table is empty. This table is mandatory", 1334 return -EINVAL); 1335 1336 PP_ASSERT_WITH_CODE(dep_mclk_table, 1337 "MCLK dependency table is missing. This table is mandatory", 1338 return -EINVAL); 1339 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 1340 "MCLK dependency table has to have is missing. This table is mandatory", 1341 return -EINVAL); 1342 1343 /* Initialize Sclk DPM table based on allow Sclk values */ 1344 dpm_table = &(data->dpm_table.soc_table); 1345 vega10_setup_default_single_dpm_table(hwmgr, 1346 dpm_table, 1347 dep_soc_table); 1348 1349 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1350 1351 dpm_table = &(data->dpm_table.gfx_table); 1352 vega10_setup_default_single_dpm_table(hwmgr, 1353 dpm_table, 1354 dep_gfx_table); 1355 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 1356 hwmgr->platform_descriptor.overdriveLimit.engineClock = 1357 dpm_table->dpm_levels[dpm_table->count-1].value; 1358 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1359 1360 /* Initialize Mclk DPM table based on allow Mclk values */ 1361 data->dpm_table.mem_table.count = 0; 1362 dpm_table = &(data->dpm_table.mem_table); 1363 vega10_setup_default_single_dpm_table(hwmgr, 1364 dpm_table, 1365 dep_mclk_table); 1366 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 1367 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 1368 dpm_table->dpm_levels[dpm_table->count-1].value; 1369 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1370 1371 data->dpm_table.eclk_table.count = 0; 1372 dpm_table = &(data->dpm_table.eclk_table); 1373 for (i = 0; i < dep_mm_table->count; i++) { 1374 if (i == 0 || dpm_table->dpm_levels 1375 [dpm_table->count - 1].value <= 1376 dep_mm_table->entries[i].eclk) { 1377 dpm_table->dpm_levels[dpm_table->count].value = 1378 dep_mm_table->entries[i].eclk; 1379 dpm_table->dpm_levels[dpm_table->count].enabled = 1380 (i == 0) ? true : false; 1381 dpm_table->count++; 1382 } 1383 } 1384 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1385 1386 data->dpm_table.vclk_table.count = 0; 1387 data->dpm_table.dclk_table.count = 0; 1388 dpm_table = &(data->dpm_table.vclk_table); 1389 for (i = 0; i < dep_mm_table->count; i++) { 1390 if (i == 0 || dpm_table->dpm_levels 1391 [dpm_table->count - 1].value <= 1392 dep_mm_table->entries[i].vclk) { 1393 dpm_table->dpm_levels[dpm_table->count].value = 1394 dep_mm_table->entries[i].vclk; 1395 dpm_table->dpm_levels[dpm_table->count].enabled = 1396 (i == 0) ? true : false; 1397 dpm_table->count++; 1398 } 1399 } 1400 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1401 1402 dpm_table = &(data->dpm_table.dclk_table); 1403 for (i = 0; i < dep_mm_table->count; i++) { 1404 if (i == 0 || dpm_table->dpm_levels 1405 [dpm_table->count - 1].value <= 1406 dep_mm_table->entries[i].dclk) { 1407 dpm_table->dpm_levels[dpm_table->count].value = 1408 dep_mm_table->entries[i].dclk; 1409 dpm_table->dpm_levels[dpm_table->count].enabled = 1410 (i == 0) ? true : false; 1411 dpm_table->count++; 1412 } 1413 } 1414 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1415 1416 /* Assume there is no headless Vega10 for now */ 1417 dpm_table = &(data->dpm_table.dcef_table); 1418 vega10_setup_default_single_dpm_table(hwmgr, 1419 dpm_table, 1420 dep_dcef_table); 1421 1422 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1423 1424 dpm_table = &(data->dpm_table.pixel_table); 1425 vega10_setup_default_single_dpm_table(hwmgr, 1426 dpm_table, 1427 dep_pix_table); 1428 1429 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1430 1431 dpm_table = &(data->dpm_table.display_table); 1432 vega10_setup_default_single_dpm_table(hwmgr, 1433 dpm_table, 1434 dep_disp_table); 1435 1436 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1437 1438 dpm_table = &(data->dpm_table.phy_table); 1439 vega10_setup_default_single_dpm_table(hwmgr, 1440 dpm_table, 1441 dep_phy_table); 1442 1443 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1444 1445 vega10_setup_default_pcie_table(hwmgr); 1446 1447 /* Zero out the saved copy of the CUSTOM profile 1448 * This will be checked when trying to set the profile 1449 * and will require that new values be passed in 1450 */ 1451 data->custom_profile_mode[0] = 0; 1452 data->custom_profile_mode[1] = 0; 1453 data->custom_profile_mode[2] = 0; 1454 data->custom_profile_mode[3] = 0; 1455 1456 /* save a copy of the default DPM table */ 1457 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1458 sizeof(struct vega10_dpm_table)); 1459 1460 return 0; 1461 } 1462 1463 /* 1464 * vega10_populate_ulv_state 1465 * Function to provide parameters for Utral Low Voltage state to SMC. 1466 * 1467 * @hwmgr: - the address of the hardware manager. 1468 * return: Always 0. 1469 */ 1470 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr) 1471 { 1472 struct vega10_hwmgr *data = hwmgr->backend; 1473 struct phm_ppt_v2_information *table_info = 1474 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1475 1476 data->smc_state_table.pp_table.UlvOffsetVid = 1477 (uint8_t)table_info->us_ulv_voltage_offset; 1478 1479 data->smc_state_table.pp_table.UlvSmnclkDid = 1480 (uint8_t)(table_info->us_ulv_smnclk_did); 1481 data->smc_state_table.pp_table.UlvMp1clkDid = 1482 (uint8_t)(table_info->us_ulv_mp1clk_did); 1483 data->smc_state_table.pp_table.UlvGfxclkBypass = 1484 (uint8_t)(table_info->us_ulv_gfxclk_bypass); 1485 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = 1486 (uint8_t)(data->vddc_voltage_table.psi0_enable); 1487 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = 1488 (uint8_t)(data->vddc_voltage_table.psi1_enable); 1489 1490 return 0; 1491 } 1492 1493 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, 1494 uint32_t lclock, uint8_t *curr_lclk_did) 1495 { 1496 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1497 1498 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1499 hwmgr, 1500 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1501 lclock, ÷rs), 1502 "Failed to get LCLK clock settings from VBIOS!", 1503 return -1); 1504 1505 *curr_lclk_did = dividers.ulDid; 1506 1507 return 0; 1508 } 1509 1510 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr) 1511 { 1512 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 1513 struct vega10_hwmgr *data = 1514 (struct vega10_hwmgr *)(hwmgr->backend); 1515 uint32_t pcie_gen = 0, pcie_width = 0; 1516 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1517 int i; 1518 1519 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1520 pcie_gen = 3; 1521 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1522 pcie_gen = 2; 1523 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1524 pcie_gen = 1; 1525 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1526 pcie_gen = 0; 1527 1528 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1529 pcie_width = 6; 1530 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1531 pcie_width = 5; 1532 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1533 pcie_width = 4; 1534 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1535 pcie_width = 3; 1536 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1537 pcie_width = 2; 1538 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1539 pcie_width = 1; 1540 1541 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1542 if (pp_table->PcieGenSpeed[i] > pcie_gen) 1543 pp_table->PcieGenSpeed[i] = pcie_gen; 1544 1545 if (pp_table->PcieLaneCount[i] > pcie_width) 1546 pp_table->PcieLaneCount[i] = pcie_width; 1547 } 1548 1549 if (data->registry_data.pcie_dpm_key_disabled) { 1550 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1551 pp_table->PcieGenSpeed[i] = pcie_gen; 1552 pp_table->PcieLaneCount[i] = pcie_width; 1553 } 1554 } 1555 1556 return 0; 1557 } 1558 1559 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) 1560 { 1561 int result = -1; 1562 struct vega10_hwmgr *data = hwmgr->backend; 1563 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1564 struct vega10_pcie_table *pcie_table = 1565 &(data->dpm_table.pcie_table); 1566 uint32_t i, j; 1567 1568 for (i = 0; i < pcie_table->count; i++) { 1569 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i]; 1570 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; 1571 1572 result = vega10_populate_single_lclk_level(hwmgr, 1573 pcie_table->lclk[i], &(pp_table->LclkDid[i])); 1574 if (result) { 1575 pr_info("Populate LClock Level %d Failed!\n", i); 1576 return result; 1577 } 1578 } 1579 1580 j = i - 1; 1581 while (i < NUM_LINK_LEVELS) { 1582 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j]; 1583 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; 1584 1585 result = vega10_populate_single_lclk_level(hwmgr, 1586 pcie_table->lclk[j], &(pp_table->LclkDid[i])); 1587 if (result) { 1588 pr_info("Populate LClock Level %d Failed!\n", i); 1589 return result; 1590 } 1591 i++; 1592 } 1593 1594 return result; 1595 } 1596 1597 /** 1598 * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure 1599 * using the provided engine clock 1600 * 1601 * @hwmgr: the address of the hardware manager 1602 * @gfx_clock: the GFX clock to use to populate the structure. 1603 * @current_gfxclk_level: location in PPTable for the SMC GFXCLK structure. 1604 * @acg_freq: ACG frequenty to return (MHz) 1605 */ 1606 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, 1607 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, 1608 uint32_t *acg_freq) 1609 { 1610 struct phm_ppt_v2_information *table_info = 1611 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1612 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk; 1613 struct vega10_hwmgr *data = hwmgr->backend; 1614 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1615 uint32_t gfx_max_clock = 1616 hwmgr->platform_descriptor.overdriveLimit.engineClock; 1617 uint32_t i = 0; 1618 1619 if (hwmgr->od_enabled) 1620 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1621 &(data->odn_dpm_table.vdd_dep_on_sclk); 1622 else 1623 dep_on_sclk = table_info->vdd_dep_on_sclk; 1624 1625 PP_ASSERT_WITH_CODE(dep_on_sclk, 1626 "Invalid SOC_VDD-GFX_CLK Dependency Table!", 1627 return -EINVAL); 1628 1629 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 1630 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; 1631 else { 1632 for (i = 0; i < dep_on_sclk->count; i++) { 1633 if (dep_on_sclk->entries[i].clk == gfx_clock) 1634 break; 1635 } 1636 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, 1637 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", 1638 return -EINVAL); 1639 } 1640 1641 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1642 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, 1643 gfx_clock, ÷rs), 1644 "Failed to get GFX Clock settings from VBIOS!", 1645 return -EINVAL); 1646 1647 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */ 1648 current_gfxclk_level->FbMult = 1649 cpu_to_le32(dividers.ulPll_fb_mult); 1650 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ 1651 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; 1652 current_gfxclk_level->SsFbMult = 1653 cpu_to_le32(dividers.ulPll_ss_fbsmult); 1654 current_gfxclk_level->SsSlewFrac = 1655 cpu_to_le16(dividers.usPll_ss_slew_frac); 1656 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); 1657 1658 *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ 1659 1660 return 0; 1661 } 1662 1663 /** 1664 * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure 1665 * using the provided clock. 1666 * 1667 * @hwmgr: the address of the hardware manager. 1668 * @soc_clock: the SOC clock to use to populate the structure. 1669 * @current_soc_did: DFS divider to pass back to caller 1670 * @current_vol_index: index of current VDD to pass back to caller 1671 * return: 0 on success 1672 */ 1673 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, 1674 uint32_t soc_clock, uint8_t *current_soc_did, 1675 uint8_t *current_vol_index) 1676 { 1677 struct vega10_hwmgr *data = hwmgr->backend; 1678 struct phm_ppt_v2_information *table_info = 1679 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1680 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc; 1681 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1682 uint32_t i; 1683 1684 if (hwmgr->od_enabled) { 1685 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1686 &data->odn_dpm_table.vdd_dep_on_socclk; 1687 for (i = 0; i < dep_on_soc->count; i++) { 1688 if (dep_on_soc->entries[i].clk >= soc_clock) 1689 break; 1690 } 1691 } else { 1692 dep_on_soc = table_info->vdd_dep_on_socclk; 1693 for (i = 0; i < dep_on_soc->count; i++) { 1694 if (dep_on_soc->entries[i].clk == soc_clock) 1695 break; 1696 } 1697 } 1698 1699 PP_ASSERT_WITH_CODE(dep_on_soc->count > i, 1700 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table", 1701 return -EINVAL); 1702 1703 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1704 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1705 soc_clock, ÷rs), 1706 "Failed to get SOC Clock settings from VBIOS!", 1707 return -EINVAL); 1708 1709 *current_soc_did = (uint8_t)dividers.ulDid; 1710 *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd); 1711 return 0; 1712 } 1713 1714 /** 1715 * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure 1716 * based on the trimmed allowed dpm engine clock states 1717 * 1718 * @hwmgr: the address of the hardware manager 1719 */ 1720 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 1721 { 1722 struct vega10_hwmgr *data = hwmgr->backend; 1723 struct phm_ppt_v2_information *table_info = 1724 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1725 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1726 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 1727 int result = 0; 1728 uint32_t i, j; 1729 1730 for (i = 0; i < dpm_table->count; i++) { 1731 result = vega10_populate_single_gfx_level(hwmgr, 1732 dpm_table->dpm_levels[i].value, 1733 &(pp_table->GfxclkLevel[i]), 1734 &(pp_table->AcgFreqTable[i])); 1735 if (result) 1736 return result; 1737 } 1738 1739 j = i - 1; 1740 while (i < NUM_GFXCLK_DPM_LEVELS) { 1741 result = vega10_populate_single_gfx_level(hwmgr, 1742 dpm_table->dpm_levels[j].value, 1743 &(pp_table->GfxclkLevel[i]), 1744 &(pp_table->AcgFreqTable[i])); 1745 if (result) 1746 return result; 1747 i++; 1748 } 1749 1750 pp_table->GfxclkSlewRate = 1751 cpu_to_le16(table_info->us_gfxclk_slew_rate); 1752 1753 dpm_table = &(data->dpm_table.soc_table); 1754 for (i = 0; i < dpm_table->count; i++) { 1755 result = vega10_populate_single_soc_level(hwmgr, 1756 dpm_table->dpm_levels[i].value, 1757 &(pp_table->SocclkDid[i]), 1758 &(pp_table->SocDpmVoltageIndex[i])); 1759 if (result) 1760 return result; 1761 } 1762 1763 j = i - 1; 1764 while (i < NUM_SOCCLK_DPM_LEVELS) { 1765 result = vega10_populate_single_soc_level(hwmgr, 1766 dpm_table->dpm_levels[j].value, 1767 &(pp_table->SocclkDid[i]), 1768 &(pp_table->SocDpmVoltageIndex[i])); 1769 if (result) 1770 return result; 1771 i++; 1772 } 1773 1774 return result; 1775 } 1776 1777 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr) 1778 { 1779 struct vega10_hwmgr *data = hwmgr->backend; 1780 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1781 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 1782 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 1783 1784 uint8_t soc_vid = 0; 1785 uint32_t i, max_vddc_level; 1786 1787 if (hwmgr->od_enabled) 1788 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table; 1789 else 1790 vddc_lookup_table = table_info->vddc_lookup_table; 1791 1792 max_vddc_level = vddc_lookup_table->count; 1793 for (i = 0; i < max_vddc_level; i++) { 1794 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd); 1795 pp_table->SocVid[i] = soc_vid; 1796 } 1797 while (i < MAX_REGULAR_DPM_NUMBER) { 1798 pp_table->SocVid[i] = soc_vid; 1799 i++; 1800 } 1801 } 1802 1803 /* 1804 * Populates single SMC GFXCLK structure using the provided clock. 1805 * 1806 * @hwmgr: the address of the hardware manager. 1807 * @mem_clock: the memory clock to use to populate the structure. 1808 * return: 0 on success.. 1809 */ 1810 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, 1811 uint32_t mem_clock, uint8_t *current_mem_vid, 1812 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind) 1813 { 1814 struct vega10_hwmgr *data = hwmgr->backend; 1815 struct phm_ppt_v2_information *table_info = 1816 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1817 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk; 1818 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1819 uint32_t mem_max_clock = 1820 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 1821 uint32_t i = 0; 1822 1823 if (hwmgr->od_enabled) 1824 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1825 &data->odn_dpm_table.vdd_dep_on_mclk; 1826 else 1827 dep_on_mclk = table_info->vdd_dep_on_mclk; 1828 1829 PP_ASSERT_WITH_CODE(dep_on_mclk, 1830 "Invalid SOC_VDD-UCLK Dependency Table!", 1831 return -EINVAL); 1832 1833 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 1834 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; 1835 } else { 1836 for (i = 0; i < dep_on_mclk->count; i++) { 1837 if (dep_on_mclk->entries[i].clk == mem_clock) 1838 break; 1839 } 1840 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, 1841 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", 1842 return -EINVAL); 1843 } 1844 1845 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1846 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), 1847 "Failed to get UCLK settings from VBIOS!", 1848 return -1); 1849 1850 *current_mem_vid = 1851 (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd)); 1852 *current_mem_soc_vind = 1853 (uint8_t)(dep_on_mclk->entries[i].vddInd); 1854 current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); 1855 current_memclk_level->Did = (uint8_t)(dividers.ulDid); 1856 1857 PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1, 1858 "Invalid Divider ID!", 1859 return -EINVAL); 1860 1861 return 0; 1862 } 1863 1864 /** 1865 * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure 1866 * based on the trimmed allowed dpm memory clock states. 1867 * 1868 * @hwmgr: the address of the hardware manager. 1869 * return: PP_Result_OK on success. 1870 */ 1871 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1872 { 1873 struct vega10_hwmgr *data = hwmgr->backend; 1874 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1875 struct vega10_single_dpm_table *dpm_table = 1876 &(data->dpm_table.mem_table); 1877 int result = 0; 1878 uint32_t i, j; 1879 1880 for (i = 0; i < dpm_table->count; i++) { 1881 result = vega10_populate_single_memory_level(hwmgr, 1882 dpm_table->dpm_levels[i].value, 1883 &(pp_table->MemVid[i]), 1884 &(pp_table->UclkLevel[i]), 1885 &(pp_table->MemSocVoltageIndex[i])); 1886 if (result) 1887 return result; 1888 } 1889 1890 j = i - 1; 1891 while (i < NUM_UCLK_DPM_LEVELS) { 1892 result = vega10_populate_single_memory_level(hwmgr, 1893 dpm_table->dpm_levels[j].value, 1894 &(pp_table->MemVid[i]), 1895 &(pp_table->UclkLevel[i]), 1896 &(pp_table->MemSocVoltageIndex[i])); 1897 if (result) 1898 return result; 1899 i++; 1900 } 1901 1902 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); 1903 pp_table->MemoryChannelWidth = 1904 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * 1905 channel_number[data->mem_channels]); 1906 1907 pp_table->LowestUclkReservedForUlv = 1908 (uint8_t)(data->lowest_uclk_reserved_for_ulv); 1909 1910 return result; 1911 } 1912 1913 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr, 1914 DSPCLK_e disp_clock) 1915 { 1916 struct vega10_hwmgr *data = hwmgr->backend; 1917 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1918 struct phm_ppt_v2_information *table_info = 1919 (struct phm_ppt_v2_information *) 1920 (hwmgr->pptable); 1921 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1922 uint32_t i; 1923 uint16_t clk = 0, vddc = 0; 1924 uint8_t vid = 0; 1925 1926 switch (disp_clock) { 1927 case DSPCLK_DCEFCLK: 1928 dep_table = table_info->vdd_dep_on_dcefclk; 1929 break; 1930 case DSPCLK_DISPCLK: 1931 dep_table = table_info->vdd_dep_on_dispclk; 1932 break; 1933 case DSPCLK_PIXCLK: 1934 dep_table = table_info->vdd_dep_on_pixclk; 1935 break; 1936 case DSPCLK_PHYCLK: 1937 dep_table = table_info->vdd_dep_on_phyclk; 1938 break; 1939 default: 1940 return -1; 1941 } 1942 1943 PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS, 1944 "Number Of Entries Exceeded maximum!", 1945 return -1); 1946 1947 for (i = 0; i < dep_table->count; i++) { 1948 clk = (uint16_t)(dep_table->entries[i].clk / 100); 1949 vddc = table_info->vddc_lookup_table-> 1950 entries[dep_table->entries[i].vddInd].us_vdd; 1951 vid = (uint8_t)convert_to_vid(vddc); 1952 pp_table->DisplayClockTable[disp_clock][i].Freq = 1953 cpu_to_le16(clk); 1954 pp_table->DisplayClockTable[disp_clock][i].Vid = 1955 cpu_to_le16(vid); 1956 } 1957 1958 while (i < NUM_DSPCLK_LEVELS) { 1959 pp_table->DisplayClockTable[disp_clock][i].Freq = 1960 cpu_to_le16(clk); 1961 pp_table->DisplayClockTable[disp_clock][i].Vid = 1962 cpu_to_le16(vid); 1963 i++; 1964 } 1965 1966 return 0; 1967 } 1968 1969 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr) 1970 { 1971 uint32_t i; 1972 1973 for (i = 0; i < DSPCLK_COUNT; i++) { 1974 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), 1975 "Failed to populate Clock in DisplayClockTable!", 1976 return -1); 1977 } 1978 1979 return 0; 1980 } 1981 1982 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, 1983 uint32_t eclock, uint8_t *current_eclk_did, 1984 uint8_t *current_soc_vol) 1985 { 1986 struct phm_ppt_v2_information *table_info = 1987 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1988 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 1989 table_info->mm_dep_table; 1990 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1991 uint32_t i; 1992 1993 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1994 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1995 eclock, ÷rs), 1996 "Failed to get ECLK clock settings from VBIOS!", 1997 return -1); 1998 1999 *current_eclk_did = (uint8_t)dividers.ulDid; 2000 2001 for (i = 0; i < dep_table->count; i++) { 2002 if (dep_table->entries[i].eclk == eclock) 2003 *current_soc_vol = dep_table->entries[i].vddcInd; 2004 } 2005 2006 return 0; 2007 } 2008 2009 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr) 2010 { 2011 struct vega10_hwmgr *data = hwmgr->backend; 2012 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2013 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); 2014 int result = -EINVAL; 2015 uint32_t i, j; 2016 2017 for (i = 0; i < dpm_table->count; i++) { 2018 result = vega10_populate_single_eclock_level(hwmgr, 2019 dpm_table->dpm_levels[i].value, 2020 &(pp_table->EclkDid[i]), 2021 &(pp_table->VceDpmVoltageIndex[i])); 2022 if (result) 2023 return result; 2024 } 2025 2026 j = i - 1; 2027 while (i < NUM_VCE_DPM_LEVELS) { 2028 result = vega10_populate_single_eclock_level(hwmgr, 2029 dpm_table->dpm_levels[j].value, 2030 &(pp_table->EclkDid[i]), 2031 &(pp_table->VceDpmVoltageIndex[i])); 2032 if (result) 2033 return result; 2034 i++; 2035 } 2036 2037 return result; 2038 } 2039 2040 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr, 2041 uint32_t vclock, uint8_t *current_vclk_did) 2042 { 2043 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2044 2045 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2046 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2047 vclock, ÷rs), 2048 "Failed to get VCLK clock settings from VBIOS!", 2049 return -EINVAL); 2050 2051 *current_vclk_did = (uint8_t)dividers.ulDid; 2052 2053 return 0; 2054 } 2055 2056 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, 2057 uint32_t dclock, uint8_t *current_dclk_did) 2058 { 2059 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2060 2061 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2062 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2063 dclock, ÷rs), 2064 "Failed to get DCLK clock settings from VBIOS!", 2065 return -EINVAL); 2066 2067 *current_dclk_did = (uint8_t)dividers.ulDid; 2068 2069 return 0; 2070 } 2071 2072 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) 2073 { 2074 struct vega10_hwmgr *data = hwmgr->backend; 2075 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2076 struct vega10_single_dpm_table *vclk_dpm_table = 2077 &(data->dpm_table.vclk_table); 2078 struct vega10_single_dpm_table *dclk_dpm_table = 2079 &(data->dpm_table.dclk_table); 2080 struct phm_ppt_v2_information *table_info = 2081 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2082 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 2083 table_info->mm_dep_table; 2084 int result = -EINVAL; 2085 uint32_t i, j; 2086 2087 for (i = 0; i < vclk_dpm_table->count; i++) { 2088 result = vega10_populate_single_vclock_level(hwmgr, 2089 vclk_dpm_table->dpm_levels[i].value, 2090 &(pp_table->VclkDid[i])); 2091 if (result) 2092 return result; 2093 } 2094 2095 j = i - 1; 2096 while (i < NUM_UVD_DPM_LEVELS) { 2097 result = vega10_populate_single_vclock_level(hwmgr, 2098 vclk_dpm_table->dpm_levels[j].value, 2099 &(pp_table->VclkDid[i])); 2100 if (result) 2101 return result; 2102 i++; 2103 } 2104 2105 for (i = 0; i < dclk_dpm_table->count; i++) { 2106 result = vega10_populate_single_dclock_level(hwmgr, 2107 dclk_dpm_table->dpm_levels[i].value, 2108 &(pp_table->DclkDid[i])); 2109 if (result) 2110 return result; 2111 } 2112 2113 j = i - 1; 2114 while (i < NUM_UVD_DPM_LEVELS) { 2115 result = vega10_populate_single_dclock_level(hwmgr, 2116 dclk_dpm_table->dpm_levels[j].value, 2117 &(pp_table->DclkDid[i])); 2118 if (result) 2119 return result; 2120 i++; 2121 } 2122 2123 for (i = 0; i < dep_table->count; i++) { 2124 if (dep_table->entries[i].vclk == 2125 vclk_dpm_table->dpm_levels[i].value && 2126 dep_table->entries[i].dclk == 2127 dclk_dpm_table->dpm_levels[i].value) 2128 pp_table->UvdDpmVoltageIndex[i] = 2129 dep_table->entries[i].vddcInd; 2130 else 2131 return -1; 2132 } 2133 2134 j = i - 1; 2135 while (i < NUM_UVD_DPM_LEVELS) { 2136 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd; 2137 i++; 2138 } 2139 2140 return 0; 2141 } 2142 2143 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) 2144 { 2145 struct vega10_hwmgr *data = hwmgr->backend; 2146 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2147 struct phm_ppt_v2_information *table_info = 2148 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2149 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2150 table_info->vdd_dep_on_sclk; 2151 uint32_t i; 2152 2153 for (i = 0; i < dep_table->count; i++) { 2154 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable; 2155 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset 2156 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 2163 { 2164 struct vega10_hwmgr *data = hwmgr->backend; 2165 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2166 struct phm_ppt_v2_information *table_info = 2167 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2168 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2169 table_info->vdd_dep_on_sclk; 2170 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 2171 int result = 0; 2172 uint32_t i; 2173 2174 pp_table->MinVoltageVid = (uint8_t)0xff; 2175 pp_table->MaxVoltageVid = (uint8_t)0; 2176 2177 if (data->smu_features[GNLD_AVFS].supported) { 2178 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 2179 if (!result) { 2180 pp_table->MinVoltageVid = (uint8_t) 2181 convert_to_vid((uint16_t)(avfs_params.ulMinVddc)); 2182 pp_table->MaxVoltageVid = (uint8_t) 2183 convert_to_vid((uint16_t)(avfs_params.ulMaxVddc)); 2184 2185 pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0); 2186 pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1); 2187 pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2); 2188 pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2189 pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean); 2190 pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2191 pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor); 2192 2193 pp_table->BtcGbVdroopTableCksOff.a0 = 2194 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0); 2195 pp_table->BtcGbVdroopTableCksOff.a0_shift = 20; 2196 pp_table->BtcGbVdroopTableCksOff.a1 = 2197 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1); 2198 pp_table->BtcGbVdroopTableCksOff.a1_shift = 20; 2199 pp_table->BtcGbVdroopTableCksOff.a2 = 2200 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2); 2201 pp_table->BtcGbVdroopTableCksOff.a2_shift = 20; 2202 2203 pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson; 2204 pp_table->BtcGbVdroopTableCksOn.a0 = 2205 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0); 2206 pp_table->BtcGbVdroopTableCksOn.a0_shift = 20; 2207 pp_table->BtcGbVdroopTableCksOn.a1 = 2208 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1); 2209 pp_table->BtcGbVdroopTableCksOn.a1_shift = 20; 2210 pp_table->BtcGbVdroopTableCksOn.a2 = 2211 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2); 2212 pp_table->BtcGbVdroopTableCksOn.a2_shift = 20; 2213 2214 pp_table->AvfsGbCksOn.m1 = 2215 cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); 2216 pp_table->AvfsGbCksOn.m2 = 2217 cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); 2218 pp_table->AvfsGbCksOn.b = 2219 cpu_to_le32(avfs_params.ulGbFuseTableCksonB); 2220 pp_table->AvfsGbCksOn.m1_shift = 24; 2221 pp_table->AvfsGbCksOn.m2_shift = 12; 2222 pp_table->AvfsGbCksOn.b_shift = 0; 2223 2224 pp_table->OverrideAvfsGbCksOn = 2225 avfs_params.ucEnableGbFuseTableCkson; 2226 pp_table->AvfsGbCksOff.m1 = 2227 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); 2228 pp_table->AvfsGbCksOff.m2 = 2229 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); 2230 pp_table->AvfsGbCksOff.b = 2231 cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); 2232 pp_table->AvfsGbCksOff.m1_shift = 24; 2233 pp_table->AvfsGbCksOff.m2_shift = 12; 2234 pp_table->AvfsGbCksOff.b_shift = 0; 2235 2236 for (i = 0; i < dep_table->count; i++) 2237 pp_table->StaticVoltageOffsetVid[i] = 2238 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset)); 2239 2240 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2241 data->disp_clk_quad_eqn_a) && 2242 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2243 data->disp_clk_quad_eqn_b)) { 2244 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2245 (int32_t)data->disp_clk_quad_eqn_a; 2246 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2247 (int32_t)data->disp_clk_quad_eqn_b; 2248 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2249 (int32_t)data->disp_clk_quad_eqn_c; 2250 } else { 2251 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2252 (int32_t)avfs_params.ulDispclk2GfxclkM1; 2253 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2254 (int32_t)avfs_params.ulDispclk2GfxclkM2; 2255 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2256 (int32_t)avfs_params.ulDispclk2GfxclkB; 2257 } 2258 2259 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; 2260 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; 2261 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12; 2262 2263 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2264 data->dcef_clk_quad_eqn_a) && 2265 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2266 data->dcef_clk_quad_eqn_b)) { 2267 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2268 (int32_t)data->dcef_clk_quad_eqn_a; 2269 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2270 (int32_t)data->dcef_clk_quad_eqn_b; 2271 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2272 (int32_t)data->dcef_clk_quad_eqn_c; 2273 } else { 2274 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2275 (int32_t)avfs_params.ulDcefclk2GfxclkM1; 2276 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2277 (int32_t)avfs_params.ulDcefclk2GfxclkM2; 2278 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2279 (int32_t)avfs_params.ulDcefclk2GfxclkB; 2280 } 2281 2282 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; 2283 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; 2284 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12; 2285 2286 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2287 data->pixel_clk_quad_eqn_a) && 2288 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2289 data->pixel_clk_quad_eqn_b)) { 2290 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2291 (int32_t)data->pixel_clk_quad_eqn_a; 2292 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2293 (int32_t)data->pixel_clk_quad_eqn_b; 2294 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2295 (int32_t)data->pixel_clk_quad_eqn_c; 2296 } else { 2297 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2298 (int32_t)avfs_params.ulPixelclk2GfxclkM1; 2299 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2300 (int32_t)avfs_params.ulPixelclk2GfxclkM2; 2301 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2302 (int32_t)avfs_params.ulPixelclk2GfxclkB; 2303 } 2304 2305 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; 2306 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; 2307 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12; 2308 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2309 data->phy_clk_quad_eqn_a) && 2310 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2311 data->phy_clk_quad_eqn_b)) { 2312 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2313 (int32_t)data->phy_clk_quad_eqn_a; 2314 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2315 (int32_t)data->phy_clk_quad_eqn_b; 2316 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2317 (int32_t)data->phy_clk_quad_eqn_c; 2318 } else { 2319 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2320 (int32_t)avfs_params.ulPhyclk2GfxclkM1; 2321 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2322 (int32_t)avfs_params.ulPhyclk2GfxclkM2; 2323 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2324 (int32_t)avfs_params.ulPhyclk2GfxclkB; 2325 } 2326 2327 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; 2328 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; 2329 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12; 2330 2331 pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0; 2332 pp_table->AcgBtcGbVdroopTable.a0_shift = 20; 2333 pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1; 2334 pp_table->AcgBtcGbVdroopTable.a1_shift = 20; 2335 pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2; 2336 pp_table->AcgBtcGbVdroopTable.a2_shift = 20; 2337 2338 pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1; 2339 pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2; 2340 pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB; 2341 pp_table->AcgAvfsGb.m1_shift = 24; 2342 pp_table->AcgAvfsGb.m2_shift = 12; 2343 pp_table->AcgAvfsGb.b_shift = 0; 2344 2345 } else { 2346 data->smu_features[GNLD_AVFS].supported = false; 2347 } 2348 } 2349 2350 return 0; 2351 } 2352 2353 static int vega10_acg_enable(struct pp_hwmgr *hwmgr) 2354 { 2355 struct vega10_hwmgr *data = hwmgr->backend; 2356 uint32_t agc_btc_response; 2357 2358 if (data->smu_features[GNLD_ACG].supported) { 2359 if (0 == vega10_enable_smc_features(hwmgr, true, 2360 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) 2361 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; 2362 2363 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL); 2364 2365 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response); 2366 2367 if (1 == agc_btc_response) { 2368 if (1 == data->acg_loop_state) 2369 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL); 2370 else if (2 == data->acg_loop_state) 2371 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL); 2372 if (0 == vega10_enable_smc_features(hwmgr, true, 2373 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2374 data->smu_features[GNLD_ACG].enabled = true; 2375 } else { 2376 pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n"); 2377 data->smu_features[GNLD_ACG].enabled = false; 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int vega10_acg_disable(struct pp_hwmgr *hwmgr) 2385 { 2386 struct vega10_hwmgr *data = hwmgr->backend; 2387 2388 if (data->smu_features[GNLD_ACG].supported && 2389 data->smu_features[GNLD_ACG].enabled) 2390 if (!vega10_enable_smc_features(hwmgr, false, 2391 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2392 data->smu_features[GNLD_ACG].enabled = false; 2393 2394 return 0; 2395 } 2396 2397 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) 2398 { 2399 struct vega10_hwmgr *data = hwmgr->backend; 2400 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2401 struct pp_atomfwctrl_gpio_parameters gpio_params = {0}; 2402 int result; 2403 2404 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); 2405 if (!result) { 2406 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && 2407 data->registry_data.regulator_hot_gpio_support) { 2408 pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; 2409 pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; 2410 pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; 2411 pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity; 2412 } else { 2413 pp_table->VR0HotGpio = 0; 2414 pp_table->VR0HotPolarity = 0; 2415 pp_table->VR1HotGpio = 0; 2416 pp_table->VR1HotPolarity = 0; 2417 } 2418 2419 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && 2420 data->registry_data.ac_dc_switch_gpio_support) { 2421 pp_table->AcDcGpio = gpio_params.ucAcDcGpio; 2422 pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; 2423 } else { 2424 pp_table->AcDcGpio = 0; 2425 pp_table->AcDcPolarity = 0; 2426 } 2427 } 2428 2429 return result; 2430 } 2431 2432 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) 2433 { 2434 struct vega10_hwmgr *data = hwmgr->backend; 2435 2436 if (data->smu_features[GNLD_AVFS].supported) { 2437 /* Already enabled or disabled */ 2438 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled)) 2439 return 0; 2440 2441 if (enable) { 2442 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2443 true, 2444 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2445 "[avfs_control] Attempt to Enable AVFS feature Failed!", 2446 return -1); 2447 data->smu_features[GNLD_AVFS].enabled = true; 2448 } else { 2449 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2450 false, 2451 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2452 "[avfs_control] Attempt to Disable AVFS feature Failed!", 2453 return -1); 2454 data->smu_features[GNLD_AVFS].enabled = false; 2455 } 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int vega10_update_avfs(struct pp_hwmgr *hwmgr) 2462 { 2463 struct vega10_hwmgr *data = hwmgr->backend; 2464 2465 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 2466 vega10_avfs_enable(hwmgr, false); 2467 } else if (data->need_update_dpm_table) { 2468 vega10_avfs_enable(hwmgr, false); 2469 vega10_avfs_enable(hwmgr, true); 2470 } else { 2471 vega10_avfs_enable(hwmgr, true); 2472 } 2473 2474 return 0; 2475 } 2476 2477 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) 2478 { 2479 int result = 0; 2480 2481 uint64_t serial_number = 0; 2482 uint32_t top32, bottom32; 2483 struct phm_fuses_default fuse; 2484 2485 struct vega10_hwmgr *data = hwmgr->backend; 2486 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); 2487 2488 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 2489 2490 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 2491 2492 serial_number = ((uint64_t)bottom32 << 32) | top32; 2493 2494 if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { 2495 avfs_fuse_table->VFT0_b = fuse.VFT0_b; 2496 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; 2497 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; 2498 avfs_fuse_table->VFT1_b = fuse.VFT1_b; 2499 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; 2500 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; 2501 avfs_fuse_table->VFT2_b = fuse.VFT2_b; 2502 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; 2503 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; 2504 result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table, 2505 AVFSFUSETABLE, false); 2506 PP_ASSERT_WITH_CODE(!result, 2507 "Failed to upload FuseOVerride!", 2508 ); 2509 } 2510 2511 return result; 2512 } 2513 2514 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 2515 { 2516 struct vega10_hwmgr *data = hwmgr->backend; 2517 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2518 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 2519 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 2520 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 2521 uint32_t i; 2522 2523 dep_table = table_info->vdd_dep_on_mclk; 2524 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk); 2525 2526 for (i = 0; i < dep_table->count; i++) { 2527 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2528 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 2529 return; 2530 } 2531 } 2532 2533 dep_table = table_info->vdd_dep_on_sclk; 2534 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk); 2535 for (i = 0; i < dep_table->count; i++) { 2536 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2537 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 2538 return; 2539 } 2540 } 2541 } 2542 2543 /** 2544 * vega10_init_smc_table - Initializes the SMC table and uploads it 2545 * 2546 * @hwmgr: the address of the powerplay hardware manager. 2547 * return: always 0 2548 */ 2549 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) 2550 { 2551 int result; 2552 struct vega10_hwmgr *data = hwmgr->backend; 2553 struct phm_ppt_v2_information *table_info = 2554 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2555 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2556 struct pp_atomfwctrl_voltage_table voltage_table; 2557 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 2558 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2559 2560 result = vega10_setup_default_dpm_tables(hwmgr); 2561 PP_ASSERT_WITH_CODE(!result, 2562 "Failed to setup default DPM tables!", 2563 return result); 2564 2565 if (!hwmgr->not_vf) 2566 return 0; 2567 2568 /* initialize ODN table */ 2569 if (hwmgr->od_enabled) { 2570 if (odn_table->max_vddc) { 2571 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 2572 vega10_check_dpm_table_updated(hwmgr); 2573 } else { 2574 vega10_odn_initial_default_setting(hwmgr); 2575 } 2576 } 2577 2578 pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, 2579 VOLTAGE_OBJ_SVID2, &voltage_table); 2580 pp_table->MaxVidStep = voltage_table.max_vid_step; 2581 2582 pp_table->GfxDpmVoltageMode = 2583 (uint8_t)(table_info->uc_gfx_dpm_voltage_mode); 2584 pp_table->SocDpmVoltageMode = 2585 (uint8_t)(table_info->uc_soc_dpm_voltage_mode); 2586 pp_table->UclkDpmVoltageMode = 2587 (uint8_t)(table_info->uc_uclk_dpm_voltage_mode); 2588 pp_table->UvdDpmVoltageMode = 2589 (uint8_t)(table_info->uc_uvd_dpm_voltage_mode); 2590 pp_table->VceDpmVoltageMode = 2591 (uint8_t)(table_info->uc_vce_dpm_voltage_mode); 2592 pp_table->Mp0DpmVoltageMode = 2593 (uint8_t)(table_info->uc_mp0_dpm_voltage_mode); 2594 2595 pp_table->DisplayDpmVoltageMode = 2596 (uint8_t)(table_info->uc_dcef_dpm_voltage_mode); 2597 2598 data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable; 2599 data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable; 2600 2601 if (data->registry_data.ulv_support && 2602 table_info->us_ulv_voltage_offset) { 2603 result = vega10_populate_ulv_state(hwmgr); 2604 PP_ASSERT_WITH_CODE(!result, 2605 "Failed to initialize ULV state!", 2606 return result); 2607 } 2608 2609 result = vega10_populate_smc_link_levels(hwmgr); 2610 PP_ASSERT_WITH_CODE(!result, 2611 "Failed to initialize Link Level!", 2612 return result); 2613 2614 result = vega10_override_pcie_parameters(hwmgr); 2615 PP_ASSERT_WITH_CODE(!result, 2616 "Failed to override pcie parameters!", 2617 return result); 2618 2619 result = vega10_populate_all_graphic_levels(hwmgr); 2620 PP_ASSERT_WITH_CODE(!result, 2621 "Failed to initialize Graphics Level!", 2622 return result); 2623 2624 result = vega10_populate_all_memory_levels(hwmgr); 2625 PP_ASSERT_WITH_CODE(!result, 2626 "Failed to initialize Memory Level!", 2627 return result); 2628 2629 vega10_populate_vddc_soc_levels(hwmgr); 2630 2631 result = vega10_populate_all_display_clock_levels(hwmgr); 2632 PP_ASSERT_WITH_CODE(!result, 2633 "Failed to initialize Display Level!", 2634 return result); 2635 2636 result = vega10_populate_smc_vce_levels(hwmgr); 2637 PP_ASSERT_WITH_CODE(!result, 2638 "Failed to initialize VCE Level!", 2639 return result); 2640 2641 result = vega10_populate_smc_uvd_levels(hwmgr); 2642 PP_ASSERT_WITH_CODE(!result, 2643 "Failed to initialize UVD Level!", 2644 return result); 2645 2646 if (data->registry_data.clock_stretcher_support) { 2647 result = vega10_populate_clock_stretcher_table(hwmgr); 2648 PP_ASSERT_WITH_CODE(!result, 2649 "Failed to populate Clock Stretcher Table!", 2650 return result); 2651 } 2652 2653 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 2654 if (!result) { 2655 data->vbios_boot_state.vddc = boot_up_values.usVddc; 2656 data->vbios_boot_state.vddci = boot_up_values.usVddci; 2657 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 2658 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 2659 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 2660 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2661 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); 2662 2663 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2664 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); 2665 2666 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 2667 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 2668 if (0 != boot_up_values.usVddc) { 2669 smum_send_msg_to_smc_with_parameter(hwmgr, 2670 PPSMC_MSG_SetFloorSocVoltage, 2671 (boot_up_values.usVddc * 4), 2672 NULL); 2673 data->vbios_boot_state.bsoc_vddc_lock = true; 2674 } else { 2675 data->vbios_boot_state.bsoc_vddc_lock = false; 2676 } 2677 smum_send_msg_to_smc_with_parameter(hwmgr, 2678 PPSMC_MSG_SetMinDeepSleepDcefclk, 2679 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 2680 NULL); 2681 } 2682 2683 result = vega10_populate_avfs_parameters(hwmgr); 2684 PP_ASSERT_WITH_CODE(!result, 2685 "Failed to initialize AVFS Parameters!", 2686 return result); 2687 2688 result = vega10_populate_gpio_parameters(hwmgr); 2689 PP_ASSERT_WITH_CODE(!result, 2690 "Failed to initialize GPIO Parameters!", 2691 return result); 2692 2693 pp_table->GfxclkAverageAlpha = (uint8_t) 2694 (data->gfxclk_average_alpha); 2695 pp_table->SocclkAverageAlpha = (uint8_t) 2696 (data->socclk_average_alpha); 2697 pp_table->UclkAverageAlpha = (uint8_t) 2698 (data->uclk_average_alpha); 2699 pp_table->GfxActivityAverageAlpha = (uint8_t) 2700 (data->gfx_activity_average_alpha); 2701 2702 vega10_populate_and_upload_avfs_fuse_override(hwmgr); 2703 2704 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 2705 2706 PP_ASSERT_WITH_CODE(!result, 2707 "Failed to upload PPtable!", return result); 2708 2709 result = vega10_avfs_enable(hwmgr, true); 2710 PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", 2711 return result); 2712 vega10_acg_enable(hwmgr); 2713 2714 return 0; 2715 } 2716 2717 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) 2718 { 2719 struct vega10_hwmgr *data = hwmgr->backend; 2720 2721 if (data->smu_features[GNLD_THERMAL].supported) { 2722 if (data->smu_features[GNLD_THERMAL].enabled) 2723 pr_info("THERMAL Feature Already enabled!"); 2724 2725 PP_ASSERT_WITH_CODE( 2726 !vega10_enable_smc_features(hwmgr, 2727 true, 2728 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2729 "Enable THERMAL Feature Failed!", 2730 return -1); 2731 data->smu_features[GNLD_THERMAL].enabled = true; 2732 } 2733 2734 return 0; 2735 } 2736 2737 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) 2738 { 2739 struct vega10_hwmgr *data = hwmgr->backend; 2740 2741 if (data->smu_features[GNLD_THERMAL].supported) { 2742 if (!data->smu_features[GNLD_THERMAL].enabled) 2743 pr_info("THERMAL Feature Already disabled!"); 2744 2745 PP_ASSERT_WITH_CODE( 2746 !vega10_enable_smc_features(hwmgr, 2747 false, 2748 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2749 "disable THERMAL Feature Failed!", 2750 return -1); 2751 data->smu_features[GNLD_THERMAL].enabled = false; 2752 } 2753 2754 return 0; 2755 } 2756 2757 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) 2758 { 2759 struct vega10_hwmgr *data = hwmgr->backend; 2760 2761 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { 2762 if (data->smu_features[GNLD_VR0HOT].supported) { 2763 PP_ASSERT_WITH_CODE( 2764 !vega10_enable_smc_features(hwmgr, 2765 true, 2766 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), 2767 "Attempt to Enable VR0 Hot feature Failed!", 2768 return -1); 2769 data->smu_features[GNLD_VR0HOT].enabled = true; 2770 } else { 2771 if (data->smu_features[GNLD_VR1HOT].supported) { 2772 PP_ASSERT_WITH_CODE( 2773 !vega10_enable_smc_features(hwmgr, 2774 true, 2775 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), 2776 "Attempt to Enable VR0 Hot feature Failed!", 2777 return -1); 2778 data->smu_features[GNLD_VR1HOT].enabled = true; 2779 } 2780 } 2781 } 2782 return 0; 2783 } 2784 2785 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) 2786 { 2787 struct vega10_hwmgr *data = hwmgr->backend; 2788 2789 if (data->registry_data.ulv_support) { 2790 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2791 true, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2792 "Enable ULV Feature Failed!", 2793 return -1); 2794 data->smu_features[GNLD_ULV].enabled = true; 2795 } 2796 2797 return 0; 2798 } 2799 2800 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) 2801 { 2802 struct vega10_hwmgr *data = hwmgr->backend; 2803 2804 if (data->registry_data.ulv_support) { 2805 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2806 false, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2807 "disable ULV Feature Failed!", 2808 return -EINVAL); 2809 data->smu_features[GNLD_ULV].enabled = false; 2810 } 2811 2812 return 0; 2813 } 2814 2815 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2816 { 2817 struct vega10_hwmgr *data = hwmgr->backend; 2818 2819 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2820 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2821 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2822 "Attempt to Enable DS_GFXCLK Feature Failed!", 2823 return -EINVAL); 2824 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 2825 } 2826 2827 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2828 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2829 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2830 "Attempt to Enable DS_SOCCLK Feature Failed!", 2831 return -EINVAL); 2832 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 2833 } 2834 2835 if (data->smu_features[GNLD_DS_LCLK].supported) { 2836 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2837 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2838 "Attempt to Enable DS_LCLK Feature Failed!", 2839 return -EINVAL); 2840 data->smu_features[GNLD_DS_LCLK].enabled = true; 2841 } 2842 2843 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2844 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2845 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2846 "Attempt to Enable DS_DCEFCLK Feature Failed!", 2847 return -EINVAL); 2848 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 2849 } 2850 2851 return 0; 2852 } 2853 2854 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2855 { 2856 struct vega10_hwmgr *data = hwmgr->backend; 2857 2858 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2859 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2860 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2861 "Attempt to disable DS_GFXCLK Feature Failed!", 2862 return -EINVAL); 2863 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 2864 } 2865 2866 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2867 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2868 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2869 "Attempt to disable DS_ Feature Failed!", 2870 return -EINVAL); 2871 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 2872 } 2873 2874 if (data->smu_features[GNLD_DS_LCLK].supported) { 2875 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2876 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2877 "Attempt to disable DS_LCLK Feature Failed!", 2878 return -EINVAL); 2879 data->smu_features[GNLD_DS_LCLK].enabled = false; 2880 } 2881 2882 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2883 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2884 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2885 "Attempt to disable DS_DCEFCLK Feature Failed!", 2886 return -EINVAL); 2887 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 2888 } 2889 2890 return 0; 2891 } 2892 2893 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2894 { 2895 struct vega10_hwmgr *data = hwmgr->backend; 2896 uint32_t i, feature_mask = 0; 2897 2898 if (!hwmgr->not_vf) 2899 return 0; 2900 2901 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2902 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2903 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2904 "Attempt to disable LED DPM feature failed!", return -EINVAL); 2905 data->smu_features[GNLD_LED_DISPLAY].enabled = false; 2906 } 2907 2908 for (i = 0; i < GNLD_DPM_MAX; i++) { 2909 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2910 if (data->smu_features[i].supported) { 2911 if (data->smu_features[i].enabled) { 2912 feature_mask |= data->smu_features[i]. 2913 smu_feature_bitmap; 2914 data->smu_features[i].enabled = false; 2915 } 2916 } 2917 } 2918 } 2919 2920 vega10_enable_smc_features(hwmgr, false, feature_mask); 2921 2922 return 0; 2923 } 2924 2925 /** 2926 * vega10_start_dpm - Tell SMC to enabled the supported DPMs. 2927 * 2928 * @hwmgr: the address of the powerplay hardware manager. 2929 * @bitmap: bitmap for the features to enabled. 2930 * return: 0 on at least one DPM is successfully enabled. 2931 */ 2932 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2933 { 2934 struct vega10_hwmgr *data = hwmgr->backend; 2935 uint32_t i, feature_mask = 0; 2936 2937 for (i = 0; i < GNLD_DPM_MAX; i++) { 2938 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2939 if (data->smu_features[i].supported) { 2940 if (!data->smu_features[i].enabled) { 2941 feature_mask |= data->smu_features[i]. 2942 smu_feature_bitmap; 2943 data->smu_features[i].enabled = true; 2944 } 2945 } 2946 } 2947 } 2948 2949 if (vega10_enable_smc_features(hwmgr, 2950 true, feature_mask)) { 2951 for (i = 0; i < GNLD_DPM_MAX; i++) { 2952 if (data->smu_features[i].smu_feature_bitmap & 2953 feature_mask) 2954 data->smu_features[i].enabled = false; 2955 } 2956 } 2957 2958 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2959 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2960 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2961 "Attempt to Enable LED DPM feature Failed!", return -EINVAL); 2962 data->smu_features[GNLD_LED_DISPLAY].enabled = true; 2963 } 2964 2965 if (data->vbios_boot_state.bsoc_vddc_lock) { 2966 smum_send_msg_to_smc_with_parameter(hwmgr, 2967 PPSMC_MSG_SetFloorSocVoltage, 0, 2968 NULL); 2969 data->vbios_boot_state.bsoc_vddc_lock = false; 2970 } 2971 2972 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { 2973 if (data->smu_features[GNLD_ACDC].supported) { 2974 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2975 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), 2976 "Attempt to Enable DS_GFXCLK Feature Failed!", 2977 return -1); 2978 data->smu_features[GNLD_ACDC].enabled = true; 2979 } 2980 } 2981 2982 if (data->registry_data.pcie_dpm_key_disabled) { 2983 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2984 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap), 2985 "Attempt to Disable Link DPM feature Failed!", return -EINVAL); 2986 data->smu_features[GNLD_DPM_LINK].enabled = false; 2987 data->smu_features[GNLD_DPM_LINK].supported = false; 2988 } 2989 2990 return 0; 2991 } 2992 2993 2994 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) 2995 { 2996 struct vega10_hwmgr *data = hwmgr->backend; 2997 2998 if (data->smu_features[GNLD_PCC_LIMIT].supported) { 2999 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled) 3000 pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled"); 3001 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3002 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap), 3003 "Attempt to Enable PCC Limit feature Failed!", 3004 return -EINVAL); 3005 data->smu_features[GNLD_PCC_LIMIT].enabled = enable; 3006 } 3007 3008 return 0; 3009 } 3010 3011 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 3012 { 3013 struct phm_ppt_v2_information *table_info = 3014 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3015 3016 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 3017 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 3018 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; 3019 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; 3020 } else { 3021 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3022 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; 3023 } 3024 3025 hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk; 3026 hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk; 3027 3028 /* make sure the output is in Mhz */ 3029 hwmgr->pstate_sclk /= 100; 3030 hwmgr->pstate_mclk /= 100; 3031 hwmgr->pstate_sclk_peak /= 100; 3032 hwmgr->pstate_mclk_peak /= 100; 3033 } 3034 3035 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 3036 { 3037 struct vega10_hwmgr *data = hwmgr->backend; 3038 int tmp_result, result = 0; 3039 3040 if (hwmgr->not_vf) { 3041 vega10_enable_disable_PCC_limit_feature(hwmgr, true); 3042 3043 smum_send_msg_to_smc_with_parameter(hwmgr, 3044 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry, 3045 NULL); 3046 3047 tmp_result = vega10_construct_voltage_tables(hwmgr); 3048 PP_ASSERT_WITH_CODE(!tmp_result, 3049 "Failed to construct voltage tables!", 3050 result = tmp_result); 3051 } 3052 3053 if (hwmgr->not_vf || hwmgr->pp_one_vf) { 3054 tmp_result = vega10_init_smc_table(hwmgr); 3055 PP_ASSERT_WITH_CODE(!tmp_result, 3056 "Failed to initialize SMC table!", 3057 result = tmp_result); 3058 } 3059 3060 if (hwmgr->not_vf) { 3061 if (PP_CAP(PHM_PlatformCaps_ThermalController)) { 3062 tmp_result = vega10_enable_thermal_protection(hwmgr); 3063 PP_ASSERT_WITH_CODE(!tmp_result, 3064 "Failed to enable thermal protection!", 3065 result = tmp_result); 3066 } 3067 3068 tmp_result = vega10_enable_vrhot_feature(hwmgr); 3069 PP_ASSERT_WITH_CODE(!tmp_result, 3070 "Failed to enable VR hot feature!", 3071 result = tmp_result); 3072 3073 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); 3074 PP_ASSERT_WITH_CODE(!tmp_result, 3075 "Failed to enable deep sleep master switch!", 3076 result = tmp_result); 3077 } 3078 3079 if (hwmgr->not_vf) { 3080 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES); 3081 PP_ASSERT_WITH_CODE(!tmp_result, 3082 "Failed to start DPM!", result = tmp_result); 3083 } 3084 3085 if (hwmgr->not_vf) { 3086 /* enable didt, do not abort if failed didt */ 3087 tmp_result = vega10_enable_didt_config(hwmgr); 3088 PP_ASSERT(!tmp_result, 3089 "Failed to enable didt config!"); 3090 } 3091 3092 tmp_result = vega10_enable_power_containment(hwmgr); 3093 PP_ASSERT_WITH_CODE(!tmp_result, 3094 "Failed to enable power containment!", 3095 result = tmp_result); 3096 3097 if (hwmgr->not_vf) { 3098 tmp_result = vega10_power_control_set_level(hwmgr); 3099 PP_ASSERT_WITH_CODE(!tmp_result, 3100 "Failed to power control set level!", 3101 result = tmp_result); 3102 3103 tmp_result = vega10_enable_ulv(hwmgr); 3104 PP_ASSERT_WITH_CODE(!tmp_result, 3105 "Failed to enable ULV!", 3106 result = tmp_result); 3107 } 3108 3109 vega10_populate_umdpstate_clocks(hwmgr); 3110 3111 return result; 3112 } 3113 3114 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr) 3115 { 3116 return sizeof(struct vega10_power_state); 3117 } 3118 3119 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, 3120 void *state, struct pp_power_state *power_state, 3121 void *pp_table, uint32_t classification_flag) 3122 { 3123 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; 3124 struct vega10_power_state *vega10_ps = 3125 cast_phw_vega10_power_state(&(power_state->hardware)); 3126 struct vega10_performance_level *performance_level; 3127 ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state; 3128 ATOM_Vega10_POWERPLAYTABLE *powerplay_table = 3129 (ATOM_Vega10_POWERPLAYTABLE *)pp_table; 3130 ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = 3131 (ATOM_Vega10_SOCCLK_Dependency_Table *) 3132 (((unsigned long)powerplay_table) + 3133 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); 3134 ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = 3135 (ATOM_Vega10_GFXCLK_Dependency_Table *) 3136 (((unsigned long)powerplay_table) + 3137 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); 3138 ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = 3139 (ATOM_Vega10_MCLK_Dependency_Table *) 3140 (((unsigned long)powerplay_table) + 3141 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3142 3143 3144 /* The following fields are not initialized here: 3145 * id orderedList allStatesList 3146 */ 3147 power_state->classification.ui_label = 3148 (le16_to_cpu(state_entry->usClassification) & 3149 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3150 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3151 power_state->classification.flags = classification_flag; 3152 /* NOTE: There is a classification2 flag in BIOS 3153 * that is not being used right now 3154 */ 3155 power_state->classification.temporary_state = false; 3156 power_state->classification.to_be_deleted = false; 3157 3158 power_state->validation.disallowOnDC = 3159 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3160 ATOM_Vega10_DISALLOW_ON_DC) != 0); 3161 3162 power_state->display.disableFrameModulation = false; 3163 power_state->display.limitRefreshrate = false; 3164 power_state->display.enableVariBright = 3165 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3166 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0); 3167 3168 power_state->validation.supportedPowerLevels = 0; 3169 power_state->uvd_clocks.VCLK = 0; 3170 power_state->uvd_clocks.DCLK = 0; 3171 power_state->temperatures.min = 0; 3172 power_state->temperatures.max = 0; 3173 3174 performance_level = &(vega10_ps->performance_levels 3175 [vega10_ps->performance_level_count++]); 3176 3177 PP_ASSERT_WITH_CODE( 3178 (vega10_ps->performance_level_count < 3179 NUM_GFXCLK_DPM_LEVELS), 3180 "Performance levels exceeds SMC limit!", 3181 return -1); 3182 3183 PP_ASSERT_WITH_CODE( 3184 (vega10_ps->performance_level_count < 3185 hwmgr->platform_descriptor. 3186 hardwareActivityPerformanceLevels), 3187 "Performance levels exceeds Driver limit!", 3188 return -1); 3189 3190 /* Performance levels are arranged from low to high. */ 3191 performance_level->soc_clock = socclk_dep_table->entries 3192 [state_entry->ucSocClockIndexLow].ulClk; 3193 performance_level->gfx_clock = gfxclk_dep_table->entries 3194 [state_entry->ucGfxClockIndexLow].ulClk; 3195 performance_level->mem_clock = mclk_dep_table->entries 3196 [state_entry->ucMemClockIndexLow].ulMemClk; 3197 3198 performance_level = &(vega10_ps->performance_levels 3199 [vega10_ps->performance_level_count++]); 3200 performance_level->soc_clock = socclk_dep_table->entries 3201 [state_entry->ucSocClockIndexHigh].ulClk; 3202 if (gfxclk_dep_table->ucRevId == 0) { 3203 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 3204 * to level-4 due to the limited 110w-power 3205 */ 3206 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3207 performance_level->gfx_clock = 3208 gfxclk_dep_table->entries[4].ulClk; 3209 else 3210 performance_level->gfx_clock = gfxclk_dep_table->entries 3211 [state_entry->ucGfxClockIndexHigh].ulClk; 3212 } else if (gfxclk_dep_table->ucRevId == 1) { 3213 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; 3214 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3215 performance_level->gfx_clock = patom_record_V2[4].ulClk; 3216 else 3217 performance_level->gfx_clock = 3218 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk; 3219 } 3220 3221 performance_level->mem_clock = mclk_dep_table->entries 3222 [state_entry->ucMemClockIndexHigh].ulMemClk; 3223 return 0; 3224 } 3225 3226 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3227 unsigned long entry_index, struct pp_power_state *state) 3228 { 3229 int result; 3230 struct vega10_power_state *vega10_ps; 3231 3232 state->hardware.magic = PhwVega10_Magic; 3233 3234 vega10_ps = cast_phw_vega10_power_state(&state->hardware); 3235 3236 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state, 3237 vega10_get_pp_table_entry_callback_func); 3238 if (result) 3239 return result; 3240 3241 /* 3242 * This is the earliest time we have all the dependency table 3243 * and the VBIOS boot state 3244 */ 3245 /* set DC compatible flag if this state supports DC */ 3246 if (!state->validation.disallowOnDC) 3247 vega10_ps->dc_compatible = true; 3248 3249 vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3250 vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3251 3252 return 0; 3253 } 3254 3255 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr, 3256 struct pp_hw_power_state *hw_ps) 3257 { 3258 return 0; 3259 } 3260 3261 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3262 struct pp_power_state *request_ps, 3263 const struct pp_power_state *current_ps) 3264 { 3265 struct amdgpu_device *adev = hwmgr->adev; 3266 struct vega10_power_state *vega10_ps = 3267 cast_phw_vega10_power_state(&request_ps->hardware); 3268 uint32_t sclk; 3269 uint32_t mclk; 3270 struct PP_Clocks minimum_clocks = {0}; 3271 bool disable_mclk_switching; 3272 bool disable_mclk_switching_for_frame_lock; 3273 bool disable_mclk_switching_for_vr; 3274 bool force_mclk_high; 3275 const struct phm_clock_and_voltage_limits *max_limits; 3276 uint32_t i; 3277 struct vega10_hwmgr *data = hwmgr->backend; 3278 struct phm_ppt_v2_information *table_info = 3279 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3280 int32_t count; 3281 uint32_t stable_pstate_sclk_dpm_percentage; 3282 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3283 uint32_t latency; 3284 3285 data->battery_state = (PP_StateUILabel_Battery == 3286 request_ps->classification.ui_label); 3287 3288 if (vega10_ps->performance_level_count != 2) 3289 pr_info("VI should always have 2 performance levels"); 3290 3291 max_limits = adev->pm.ac_power ? 3292 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3293 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3294 3295 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3296 if (!adev->pm.ac_power) { 3297 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3298 if (vega10_ps->performance_levels[i].mem_clock > 3299 max_limits->mclk) 3300 vega10_ps->performance_levels[i].mem_clock = 3301 max_limits->mclk; 3302 if (vega10_ps->performance_levels[i].gfx_clock > 3303 max_limits->sclk) 3304 vega10_ps->performance_levels[i].gfx_clock = 3305 max_limits->sclk; 3306 } 3307 } 3308 3309 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ 3310 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3311 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3312 3313 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3314 stable_pstate_sclk_dpm_percentage = 3315 data->registry_data.stable_pstate_sclk_dpm_percentage; 3316 PP_ASSERT_WITH_CODE( 3317 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && 3318 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, 3319 "percent sclk value must range from 1% to 100%, setting default value", 3320 stable_pstate_sclk_dpm_percentage = 75); 3321 3322 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3323 stable_pstate_sclk = (max_limits->sclk * 3324 stable_pstate_sclk_dpm_percentage) / 100; 3325 3326 for (count = table_info->vdd_dep_on_sclk->count - 1; 3327 count >= 0; count--) { 3328 if (stable_pstate_sclk >= 3329 table_info->vdd_dep_on_sclk->entries[count].clk) { 3330 stable_pstate_sclk = 3331 table_info->vdd_dep_on_sclk->entries[count].clk; 3332 break; 3333 } 3334 } 3335 3336 if (count < 0) 3337 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3338 3339 stable_pstate_mclk = max_limits->mclk; 3340 3341 minimum_clocks.engineClock = stable_pstate_sclk; 3342 minimum_clocks.memoryClock = stable_pstate_mclk; 3343 } 3344 3345 disable_mclk_switching_for_frame_lock = 3346 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3347 disable_mclk_switching_for_vr = 3348 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); 3349 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); 3350 3351 if (hwmgr->display_config->num_display == 0) 3352 disable_mclk_switching = false; 3353 else 3354 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 3355 !hwmgr->display_config->multi_monitor_in_sync) || 3356 disable_mclk_switching_for_frame_lock || 3357 disable_mclk_switching_for_vr || 3358 force_mclk_high; 3359 3360 sclk = vega10_ps->performance_levels[0].gfx_clock; 3361 mclk = vega10_ps->performance_levels[0].mem_clock; 3362 3363 if (sclk < minimum_clocks.engineClock) 3364 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3365 max_limits->sclk : minimum_clocks.engineClock; 3366 3367 if (mclk < minimum_clocks.memoryClock) 3368 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3369 max_limits->mclk : minimum_clocks.memoryClock; 3370 3371 vega10_ps->performance_levels[0].gfx_clock = sclk; 3372 vega10_ps->performance_levels[0].mem_clock = mclk; 3373 3374 if (vega10_ps->performance_levels[1].gfx_clock < 3375 vega10_ps->performance_levels[0].gfx_clock) 3376 vega10_ps->performance_levels[0].gfx_clock = 3377 vega10_ps->performance_levels[1].gfx_clock; 3378 3379 if (disable_mclk_switching) { 3380 /* Set Mclk the max of level 0 and level 1 */ 3381 if (mclk < vega10_ps->performance_levels[1].mem_clock) 3382 mclk = vega10_ps->performance_levels[1].mem_clock; 3383 3384 /* Find the lowest MCLK frequency that is within 3385 * the tolerable latency defined in DAL 3386 */ 3387 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3388 for (i = 0; i < data->mclk_latency_table.count; i++) { 3389 if ((data->mclk_latency_table.entries[i].latency <= latency) && 3390 (data->mclk_latency_table.entries[i].frequency >= 3391 vega10_ps->performance_levels[0].mem_clock) && 3392 (data->mclk_latency_table.entries[i].frequency <= 3393 vega10_ps->performance_levels[1].mem_clock)) 3394 mclk = data->mclk_latency_table.entries[i].frequency; 3395 } 3396 vega10_ps->performance_levels[0].mem_clock = mclk; 3397 } else { 3398 if (vega10_ps->performance_levels[1].mem_clock < 3399 vega10_ps->performance_levels[0].mem_clock) 3400 vega10_ps->performance_levels[0].mem_clock = 3401 vega10_ps->performance_levels[1].mem_clock; 3402 } 3403 3404 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3405 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3406 vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; 3407 vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; 3408 } 3409 } 3410 3411 return 0; 3412 } 3413 3414 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 3415 { 3416 struct vega10_hwmgr *data = hwmgr->backend; 3417 const struct phm_set_power_state_input *states = 3418 (const struct phm_set_power_state_input *)input; 3419 const struct vega10_power_state *vega10_ps = 3420 cast_const_phw_vega10_power_state(states->pnew_state); 3421 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 3422 uint32_t sclk = vega10_ps->performance_levels 3423 [vega10_ps->performance_level_count - 1].gfx_clock; 3424 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 3425 uint32_t mclk = vega10_ps->performance_levels 3426 [vega10_ps->performance_level_count - 1].mem_clock; 3427 uint32_t i; 3428 3429 for (i = 0; i < sclk_table->count; i++) { 3430 if (sclk == sclk_table->dpm_levels[i].value) 3431 break; 3432 } 3433 3434 if (i >= sclk_table->count) { 3435 if (sclk > sclk_table->dpm_levels[i-1].value) { 3436 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3437 sclk_table->dpm_levels[i-1].value = sclk; 3438 } 3439 } 3440 3441 for (i = 0; i < mclk_table->count; i++) { 3442 if (mclk == mclk_table->dpm_levels[i].value) 3443 break; 3444 } 3445 3446 if (i >= mclk_table->count) { 3447 if (mclk > mclk_table->dpm_levels[i-1].value) { 3448 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3449 mclk_table->dpm_levels[i-1].value = mclk; 3450 } 3451 } 3452 3453 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3454 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; 3455 3456 return 0; 3457 } 3458 3459 static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 3460 struct pp_hwmgr *hwmgr, const void *input) 3461 { 3462 int result = 0; 3463 struct vega10_hwmgr *data = hwmgr->backend; 3464 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3465 struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table; 3466 struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk; 3467 int count; 3468 3469 if (!data->need_update_dpm_table) 3470 return 0; 3471 3472 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 3473 for (count = 0; count < dpm_table->gfx_table.count; count++) 3474 dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3475 } 3476 3477 odn_clk_table = &odn_table->vdd_dep_on_mclk; 3478 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 3479 for (count = 0; count < dpm_table->mem_table.count; count++) 3480 dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3481 } 3482 3483 if (data->need_update_dpm_table & 3484 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { 3485 result = vega10_populate_all_graphic_levels(hwmgr); 3486 PP_ASSERT_WITH_CODE((0 == result), 3487 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 3488 return result); 3489 } 3490 3491 if (data->need_update_dpm_table & 3492 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3493 result = vega10_populate_all_memory_levels(hwmgr); 3494 PP_ASSERT_WITH_CODE((0 == result), 3495 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 3496 return result); 3497 } 3498 3499 vega10_populate_vddc_soc_levels(hwmgr); 3500 3501 return result; 3502 } 3503 3504 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 3505 struct vega10_single_dpm_table *dpm_table, 3506 uint32_t low_limit, uint32_t high_limit) 3507 { 3508 uint32_t i; 3509 3510 for (i = 0; i < dpm_table->count; i++) { 3511 if ((dpm_table->dpm_levels[i].value < low_limit) || 3512 (dpm_table->dpm_levels[i].value > high_limit)) 3513 dpm_table->dpm_levels[i].enabled = false; 3514 else 3515 dpm_table->dpm_levels[i].enabled = true; 3516 } 3517 return 0; 3518 } 3519 3520 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, 3521 struct vega10_single_dpm_table *dpm_table, 3522 uint32_t low_limit, uint32_t high_limit, 3523 uint32_t disable_dpm_mask) 3524 { 3525 uint32_t i; 3526 3527 for (i = 0; i < dpm_table->count; i++) { 3528 if ((dpm_table->dpm_levels[i].value < low_limit) || 3529 (dpm_table->dpm_levels[i].value > high_limit)) 3530 dpm_table->dpm_levels[i].enabled = false; 3531 else if (!((1 << i) & disable_dpm_mask)) 3532 dpm_table->dpm_levels[i].enabled = false; 3533 else 3534 dpm_table->dpm_levels[i].enabled = true; 3535 } 3536 return 0; 3537 } 3538 3539 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr, 3540 const struct vega10_power_state *vega10_ps) 3541 { 3542 struct vega10_hwmgr *data = hwmgr->backend; 3543 uint32_t high_limit_count; 3544 3545 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), 3546 "power state did not have any performance level", 3547 return -1); 3548 3549 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; 3550 3551 vega10_trim_single_dpm_states(hwmgr, 3552 &(data->dpm_table.soc_table), 3553 vega10_ps->performance_levels[0].soc_clock, 3554 vega10_ps->performance_levels[high_limit_count].soc_clock); 3555 3556 vega10_trim_single_dpm_states_with_mask(hwmgr, 3557 &(data->dpm_table.gfx_table), 3558 vega10_ps->performance_levels[0].gfx_clock, 3559 vega10_ps->performance_levels[high_limit_count].gfx_clock, 3560 data->disable_dpm_mask); 3561 3562 vega10_trim_single_dpm_states(hwmgr, 3563 &(data->dpm_table.mem_table), 3564 vega10_ps->performance_levels[0].mem_clock, 3565 vega10_ps->performance_levels[high_limit_count].mem_clock); 3566 3567 return 0; 3568 } 3569 3570 static uint32_t vega10_find_lowest_dpm_level( 3571 struct vega10_single_dpm_table *table) 3572 { 3573 uint32_t i; 3574 3575 for (i = 0; i < table->count; i++) { 3576 if (table->dpm_levels[i].enabled) 3577 break; 3578 } 3579 3580 return i; 3581 } 3582 3583 static uint32_t vega10_find_highest_dpm_level( 3584 struct vega10_single_dpm_table *table) 3585 { 3586 uint32_t i = 0; 3587 3588 if (table->count <= MAX_REGULAR_DPM_NUMBER) { 3589 for (i = table->count; i > 0; i--) { 3590 if (table->dpm_levels[i - 1].enabled) 3591 return i - 1; 3592 } 3593 } else { 3594 pr_info("DPM Table Has Too Many Entries!"); 3595 return MAX_REGULAR_DPM_NUMBER - 1; 3596 } 3597 3598 return i; 3599 } 3600 3601 static void vega10_apply_dal_minimum_voltage_request( 3602 struct pp_hwmgr *hwmgr) 3603 { 3604 return; 3605 } 3606 3607 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) 3608 { 3609 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk; 3610 struct phm_ppt_v2_information *table_info = 3611 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3612 3613 vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk; 3614 3615 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; 3616 } 3617 3618 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) 3619 { 3620 struct vega10_hwmgr *data = hwmgr->backend; 3621 uint32_t socclk_idx; 3622 3623 vega10_apply_dal_minimum_voltage_request(hwmgr); 3624 3625 if (!data->registry_data.sclk_dpm_key_disabled) { 3626 if (data->smc_state_table.gfx_boot_level != 3627 data->dpm_table.gfx_table.dpm_state.soft_min_level) { 3628 smum_send_msg_to_smc_with_parameter(hwmgr, 3629 PPSMC_MSG_SetSoftMinGfxclkByIndex, 3630 data->smc_state_table.gfx_boot_level, 3631 NULL); 3632 3633 data->dpm_table.gfx_table.dpm_state.soft_min_level = 3634 data->smc_state_table.gfx_boot_level; 3635 } 3636 } 3637 3638 if (!data->registry_data.mclk_dpm_key_disabled) { 3639 if (data->smc_state_table.mem_boot_level != 3640 data->dpm_table.mem_table.dpm_state.soft_min_level) { 3641 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) 3642 && hwmgr->not_vf) { 3643 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); 3644 smum_send_msg_to_smc_with_parameter(hwmgr, 3645 PPSMC_MSG_SetSoftMinSocclkByIndex, 3646 socclk_idx, 3647 NULL); 3648 } else { 3649 smum_send_msg_to_smc_with_parameter(hwmgr, 3650 PPSMC_MSG_SetSoftMinUclkByIndex, 3651 data->smc_state_table.mem_boot_level, 3652 NULL); 3653 } 3654 data->dpm_table.mem_table.dpm_state.soft_min_level = 3655 data->smc_state_table.mem_boot_level; 3656 } 3657 } 3658 3659 if (!hwmgr->not_vf) 3660 return 0; 3661 3662 if (!data->registry_data.socclk_dpm_key_disabled) { 3663 if (data->smc_state_table.soc_boot_level != 3664 data->dpm_table.soc_table.dpm_state.soft_min_level) { 3665 smum_send_msg_to_smc_with_parameter(hwmgr, 3666 PPSMC_MSG_SetSoftMinSocclkByIndex, 3667 data->smc_state_table.soc_boot_level, 3668 NULL); 3669 data->dpm_table.soc_table.dpm_state.soft_min_level = 3670 data->smc_state_table.soc_boot_level; 3671 } 3672 } 3673 3674 return 0; 3675 } 3676 3677 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 3678 { 3679 struct vega10_hwmgr *data = hwmgr->backend; 3680 3681 vega10_apply_dal_minimum_voltage_request(hwmgr); 3682 3683 if (!data->registry_data.sclk_dpm_key_disabled) { 3684 if (data->smc_state_table.gfx_max_level != 3685 data->dpm_table.gfx_table.dpm_state.soft_max_level) { 3686 smum_send_msg_to_smc_with_parameter(hwmgr, 3687 PPSMC_MSG_SetSoftMaxGfxclkByIndex, 3688 data->smc_state_table.gfx_max_level, 3689 NULL); 3690 data->dpm_table.gfx_table.dpm_state.soft_max_level = 3691 data->smc_state_table.gfx_max_level; 3692 } 3693 } 3694 3695 if (!data->registry_data.mclk_dpm_key_disabled) { 3696 if (data->smc_state_table.mem_max_level != 3697 data->dpm_table.mem_table.dpm_state.soft_max_level) { 3698 smum_send_msg_to_smc_with_parameter(hwmgr, 3699 PPSMC_MSG_SetSoftMaxUclkByIndex, 3700 data->smc_state_table.mem_max_level, 3701 NULL); 3702 data->dpm_table.mem_table.dpm_state.soft_max_level = 3703 data->smc_state_table.mem_max_level; 3704 } 3705 } 3706 3707 if (!hwmgr->not_vf) 3708 return 0; 3709 3710 if (!data->registry_data.socclk_dpm_key_disabled) { 3711 if (data->smc_state_table.soc_max_level != 3712 data->dpm_table.soc_table.dpm_state.soft_max_level) { 3713 smum_send_msg_to_smc_with_parameter(hwmgr, 3714 PPSMC_MSG_SetSoftMaxSocclkByIndex, 3715 data->smc_state_table.soc_max_level, 3716 NULL); 3717 data->dpm_table.soc_table.dpm_state.soft_max_level = 3718 data->smc_state_table.soc_max_level; 3719 } 3720 } 3721 3722 return 0; 3723 } 3724 3725 static int vega10_generate_dpm_level_enable_mask( 3726 struct pp_hwmgr *hwmgr, const void *input) 3727 { 3728 struct vega10_hwmgr *data = hwmgr->backend; 3729 const struct phm_set_power_state_input *states = 3730 (const struct phm_set_power_state_input *)input; 3731 const struct vega10_power_state *vega10_ps = 3732 cast_const_phw_vega10_power_state(states->pnew_state); 3733 int i; 3734 3735 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), 3736 "Attempt to Trim DPM States Failed!", 3737 return -1); 3738 3739 data->smc_state_table.gfx_boot_level = 3740 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 3741 data->smc_state_table.gfx_max_level = 3742 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 3743 data->smc_state_table.mem_boot_level = 3744 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 3745 data->smc_state_table.mem_max_level = 3746 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 3747 data->smc_state_table.soc_boot_level = 3748 vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 3749 data->smc_state_table.soc_max_level = 3750 vega10_find_highest_dpm_level(&(data->dpm_table.soc_table)); 3751 3752 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 3753 "Attempt to upload DPM Bootup Levels Failed!", 3754 return -1); 3755 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 3756 "Attempt to upload DPM Max Levels Failed!", 3757 return -1); 3758 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) 3759 data->dpm_table.gfx_table.dpm_levels[i].enabled = true; 3760 3761 3762 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) 3763 data->dpm_table.mem_table.dpm_levels[i].enabled = true; 3764 3765 for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++) 3766 data->dpm_table.soc_table.dpm_levels[i].enabled = true; 3767 3768 return 0; 3769 } 3770 3771 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 3772 { 3773 struct vega10_hwmgr *data = hwmgr->backend; 3774 3775 if (data->smu_features[GNLD_DPM_VCE].supported) { 3776 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3777 enable, 3778 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 3779 "Attempt to Enable/Disable DPM VCE Failed!", 3780 return -1); 3781 data->smu_features[GNLD_DPM_VCE].enabled = enable; 3782 } 3783 3784 return 0; 3785 } 3786 3787 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 3788 { 3789 struct vega10_hwmgr *data = hwmgr->backend; 3790 uint32_t low_sclk_interrupt_threshold = 0; 3791 3792 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && 3793 (data->low_sclk_interrupt_threshold != 0)) { 3794 low_sclk_interrupt_threshold = 3795 data->low_sclk_interrupt_threshold; 3796 3797 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = 3798 cpu_to_le32(low_sclk_interrupt_threshold); 3799 3800 /* This message will also enable SmcToHost Interrupt */ 3801 smum_send_msg_to_smc_with_parameter(hwmgr, 3802 PPSMC_MSG_SetLowGfxclkInterruptThreshold, 3803 (uint32_t)low_sclk_interrupt_threshold, 3804 NULL); 3805 } 3806 3807 return 0; 3808 } 3809 3810 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, 3811 const void *input) 3812 { 3813 int tmp_result, result = 0; 3814 struct vega10_hwmgr *data = hwmgr->backend; 3815 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 3816 3817 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 3818 PP_ASSERT_WITH_CODE(!tmp_result, 3819 "Failed to find DPM states clocks in DPM table!", 3820 result = tmp_result); 3821 3822 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 3823 PP_ASSERT_WITH_CODE(!tmp_result, 3824 "Failed to populate and upload SCLK MCLK DPM levels!", 3825 result = tmp_result); 3826 3827 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input); 3828 PP_ASSERT_WITH_CODE(!tmp_result, 3829 "Failed to generate DPM level enabled mask!", 3830 result = tmp_result); 3831 3832 tmp_result = vega10_update_sclk_threshold(hwmgr); 3833 PP_ASSERT_WITH_CODE(!tmp_result, 3834 "Failed to update SCLK threshold!", 3835 result = tmp_result); 3836 3837 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 3838 PP_ASSERT_WITH_CODE(!result, 3839 "Failed to upload PPtable!", return result); 3840 3841 /* 3842 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 3843 * That effectively disables AVFS feature. 3844 */ 3845 if(hwmgr->hardcode_pp_table != NULL) 3846 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 3847 3848 vega10_update_avfs(hwmgr); 3849 3850 /* 3851 * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC. 3852 * That will help to keep AVFS disabled. 3853 */ 3854 data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 3855 3856 return 0; 3857 } 3858 3859 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3860 { 3861 struct pp_power_state *ps; 3862 struct vega10_power_state *vega10_ps; 3863 3864 if (hwmgr == NULL) 3865 return -EINVAL; 3866 3867 ps = hwmgr->request_ps; 3868 3869 if (ps == NULL) 3870 return -EINVAL; 3871 3872 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3873 3874 if (low) 3875 return vega10_ps->performance_levels[0].gfx_clock; 3876 else 3877 return vega10_ps->performance_levels 3878 [vega10_ps->performance_level_count - 1].gfx_clock; 3879 } 3880 3881 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3882 { 3883 struct pp_power_state *ps; 3884 struct vega10_power_state *vega10_ps; 3885 3886 if (hwmgr == NULL) 3887 return -EINVAL; 3888 3889 ps = hwmgr->request_ps; 3890 3891 if (ps == NULL) 3892 return -EINVAL; 3893 3894 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3895 3896 if (low) 3897 return vega10_ps->performance_levels[0].mem_clock; 3898 else 3899 return vega10_ps->performance_levels 3900 [vega10_ps->performance_level_count-1].mem_clock; 3901 } 3902 3903 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, 3904 uint32_t *query) 3905 { 3906 uint32_t value; 3907 3908 if (!query) 3909 return -EINVAL; 3910 3911 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); 3912 3913 /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */ 3914 *query = value << 8; 3915 3916 return 0; 3917 } 3918 3919 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 3920 void *value, int *size) 3921 { 3922 struct amdgpu_device *adev = hwmgr->adev; 3923 uint32_t sclk_mhz, mclk_idx, activity_percent = 0; 3924 struct vega10_hwmgr *data = hwmgr->backend; 3925 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3926 int ret = 0; 3927 uint32_t val_vid; 3928 3929 switch (idx) { 3930 case AMDGPU_PP_SENSOR_GFX_SCLK: 3931 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz); 3932 *((uint32_t *)value) = sclk_mhz * 100; 3933 break; 3934 case AMDGPU_PP_SENSOR_GFX_MCLK: 3935 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx); 3936 if (mclk_idx < dpm_table->mem_table.count) { 3937 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; 3938 *size = 4; 3939 } else { 3940 ret = -EINVAL; 3941 } 3942 break; 3943 case AMDGPU_PP_SENSOR_GPU_LOAD: 3944 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, 3945 &activity_percent); 3946 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 3947 *size = 4; 3948 break; 3949 case AMDGPU_PP_SENSOR_GPU_TEMP: 3950 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); 3951 *size = 4; 3952 break; 3953 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 3954 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value); 3955 *((uint32_t *)value) = *((uint32_t *)value) * 3956 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3957 *size = 4; 3958 break; 3959 case AMDGPU_PP_SENSOR_MEM_TEMP: 3960 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value); 3961 *((uint32_t *)value) = *((uint32_t *)value) * 3962 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3963 *size = 4; 3964 break; 3965 case AMDGPU_PP_SENSOR_UVD_POWER: 3966 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 3967 *size = 4; 3968 break; 3969 case AMDGPU_PP_SENSOR_VCE_POWER: 3970 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 3971 *size = 4; 3972 break; 3973 case AMDGPU_PP_SENSOR_GPU_POWER: 3974 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); 3975 break; 3976 case AMDGPU_PP_SENSOR_VDDGFX: 3977 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & 3978 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >> 3979 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT; 3980 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid); 3981 return 0; 3982 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 3983 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value); 3984 if (!ret) 3985 *size = 8; 3986 break; 3987 default: 3988 ret = -EOPNOTSUPP; 3989 break; 3990 } 3991 3992 return ret; 3993 } 3994 3995 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, 3996 bool has_disp) 3997 { 3998 smum_send_msg_to_smc_with_parameter(hwmgr, 3999 PPSMC_MSG_SetUclkFastSwitch, 4000 has_disp ? 1 : 0, 4001 NULL); 4002 } 4003 4004 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 4005 struct pp_display_clock_request *clock_req) 4006 { 4007 int result = 0; 4008 enum amd_pp_clock_type clk_type = clock_req->clock_type; 4009 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 4010 DSPCLK_e clk_select = 0; 4011 uint32_t clk_request = 0; 4012 4013 switch (clk_type) { 4014 case amd_pp_dcef_clock: 4015 clk_select = DSPCLK_DCEFCLK; 4016 break; 4017 case amd_pp_disp_clock: 4018 clk_select = DSPCLK_DISPCLK; 4019 break; 4020 case amd_pp_pixel_clock: 4021 clk_select = DSPCLK_PIXCLK; 4022 break; 4023 case amd_pp_phy_clock: 4024 clk_select = DSPCLK_PHYCLK; 4025 break; 4026 default: 4027 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 4028 result = -1; 4029 break; 4030 } 4031 4032 if (!result) { 4033 clk_request = (clk_freq << 16) | clk_select; 4034 smum_send_msg_to_smc_with_parameter(hwmgr, 4035 PPSMC_MSG_RequestDisplayClockByFreq, 4036 clk_request, 4037 NULL); 4038 } 4039 4040 return result; 4041 } 4042 4043 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, 4044 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, 4045 uint32_t frequency) 4046 { 4047 uint8_t count; 4048 uint8_t i; 4049 4050 if (mclk_table == NULL || mclk_table->count == 0) 4051 return 0; 4052 4053 count = (uint8_t)(mclk_table->count); 4054 4055 for(i = 0; i < count; i++) { 4056 if(mclk_table->entries[i].clk >= frequency) 4057 return i; 4058 } 4059 4060 return i-1; 4061 } 4062 4063 static int vega10_notify_smc_display_config_after_ps_adjustment( 4064 struct pp_hwmgr *hwmgr) 4065 { 4066 struct vega10_hwmgr *data = hwmgr->backend; 4067 struct vega10_single_dpm_table *dpm_table = 4068 &data->dpm_table.dcef_table; 4069 struct phm_ppt_v2_information *table_info = 4070 (struct phm_ppt_v2_information *)hwmgr->pptable; 4071 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; 4072 uint32_t idx; 4073 struct PP_Clocks min_clocks = {0}; 4074 uint32_t i; 4075 struct pp_display_clock_request clock_req; 4076 4077 if ((hwmgr->display_config->num_display > 1) && 4078 !hwmgr->display_config->multi_monitor_in_sync && 4079 !hwmgr->display_config->nb_pstate_switch_disable) 4080 vega10_notify_smc_display_change(hwmgr, false); 4081 else 4082 vega10_notify_smc_display_change(hwmgr, true); 4083 4084 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 4085 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 4086 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 4087 4088 for (i = 0; i < dpm_table->count; i++) { 4089 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) 4090 break; 4091 } 4092 4093 if (i < dpm_table->count) { 4094 clock_req.clock_type = amd_pp_dcef_clock; 4095 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; 4096 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { 4097 smum_send_msg_to_smc_with_parameter( 4098 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 4099 min_clocks.dcefClockInSR / 100, 4100 NULL); 4101 } else { 4102 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 4103 } 4104 } else { 4105 pr_debug("Cannot find requested DCEFCLK!"); 4106 } 4107 4108 if (min_clocks.memoryClock != 0) { 4109 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); 4110 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx, 4111 NULL); 4112 data->dpm_table.mem_table.dpm_state.soft_min_level= idx; 4113 } 4114 4115 return 0; 4116 } 4117 4118 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) 4119 { 4120 struct vega10_hwmgr *data = hwmgr->backend; 4121 4122 data->smc_state_table.gfx_boot_level = 4123 data->smc_state_table.gfx_max_level = 4124 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4125 data->smc_state_table.mem_boot_level = 4126 data->smc_state_table.mem_max_level = 4127 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4128 4129 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4130 "Failed to upload boot level to highest!", 4131 return -1); 4132 4133 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4134 "Failed to upload dpm max level to highest!", 4135 return -1); 4136 4137 return 0; 4138 } 4139 4140 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) 4141 { 4142 struct vega10_hwmgr *data = hwmgr->backend; 4143 4144 data->smc_state_table.gfx_boot_level = 4145 data->smc_state_table.gfx_max_level = 4146 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4147 data->smc_state_table.mem_boot_level = 4148 data->smc_state_table.mem_max_level = 4149 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4150 4151 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4152 "Failed to upload boot level to highest!", 4153 return -1); 4154 4155 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4156 "Failed to upload dpm max level to highest!", 4157 return -1); 4158 4159 return 0; 4160 4161 } 4162 4163 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 4164 { 4165 struct vega10_hwmgr *data = hwmgr->backend; 4166 4167 data->smc_state_table.gfx_boot_level = 4168 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4169 data->smc_state_table.gfx_max_level = 4170 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4171 data->smc_state_table.mem_boot_level = 4172 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4173 data->smc_state_table.mem_max_level = 4174 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4175 4176 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4177 "Failed to upload DPM Bootup Levels!", 4178 return -1); 4179 4180 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4181 "Failed to upload DPM Max Levels!", 4182 return -1); 4183 return 0; 4184 } 4185 4186 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 4187 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 4188 { 4189 struct phm_ppt_v2_information *table_info = 4190 (struct phm_ppt_v2_information *)(hwmgr->pptable); 4191 4192 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 4193 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL && 4194 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 4195 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; 4196 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; 4197 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; 4198 } 4199 4200 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 4201 *sclk_mask = 0; 4202 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 4203 *mclk_mask = 0; 4204 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 4205 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 4206 * to level-4 due to the limited power 4207 */ 4208 if (hwmgr->pp_one_vf) 4209 *sclk_mask = 4; 4210 else 4211 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 4212 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; 4213 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; 4214 } 4215 4216 return 0; 4217 } 4218 4219 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 4220 { 4221 if (!hwmgr->not_vf) 4222 return; 4223 4224 switch (mode) { 4225 case AMD_FAN_CTRL_NONE: 4226 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 4227 break; 4228 case AMD_FAN_CTRL_MANUAL: 4229 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4230 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 4231 break; 4232 case AMD_FAN_CTRL_AUTO: 4233 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4234 vega10_fan_ctrl_start_smc_fan_control(hwmgr); 4235 break; 4236 default: 4237 break; 4238 } 4239 } 4240 4241 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, 4242 enum pp_clock_type type, uint32_t mask) 4243 { 4244 struct vega10_hwmgr *data = hwmgr->backend; 4245 4246 switch (type) { 4247 case PP_SCLK: 4248 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; 4249 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; 4250 4251 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4252 "Failed to upload boot level to lowest!", 4253 return -EINVAL); 4254 4255 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4256 "Failed to upload dpm max level to highest!", 4257 return -EINVAL); 4258 break; 4259 4260 case PP_MCLK: 4261 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; 4262 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; 4263 4264 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4265 "Failed to upload boot level to lowest!", 4266 return -EINVAL); 4267 4268 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4269 "Failed to upload dpm max level to highest!", 4270 return -EINVAL); 4271 4272 break; 4273 4274 case PP_SOCCLK: 4275 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; 4276 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; 4277 4278 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4279 "Failed to upload boot level to lowest!", 4280 return -EINVAL); 4281 4282 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4283 "Failed to upload dpm max level to highest!", 4284 return -EINVAL); 4285 4286 break; 4287 4288 case PP_DCEFCLK: 4289 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n"); 4290 break; 4291 4292 case PP_PCIE: 4293 default: 4294 break; 4295 } 4296 4297 return 0; 4298 } 4299 4300 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 4301 enum amd_dpm_forced_level level) 4302 { 4303 int ret = 0; 4304 uint32_t sclk_mask = 0; 4305 uint32_t mclk_mask = 0; 4306 uint32_t soc_mask = 0; 4307 4308 switch (level) { 4309 case AMD_DPM_FORCED_LEVEL_HIGH: 4310 ret = vega10_force_dpm_highest(hwmgr); 4311 break; 4312 case AMD_DPM_FORCED_LEVEL_LOW: 4313 ret = vega10_force_dpm_lowest(hwmgr); 4314 break; 4315 case AMD_DPM_FORCED_LEVEL_AUTO: 4316 ret = vega10_unforce_dpm_levels(hwmgr); 4317 break; 4318 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 4319 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 4320 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 4321 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 4322 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 4323 if (ret) 4324 return ret; 4325 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 4326 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 4327 break; 4328 case AMD_DPM_FORCED_LEVEL_MANUAL: 4329 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 4330 default: 4331 break; 4332 } 4333 4334 if (!hwmgr->not_vf) 4335 return ret; 4336 4337 if (!ret) { 4338 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4339 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); 4340 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4341 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); 4342 } 4343 4344 return ret; 4345 } 4346 4347 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) 4348 { 4349 struct vega10_hwmgr *data = hwmgr->backend; 4350 4351 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 4352 return AMD_FAN_CTRL_MANUAL; 4353 else 4354 return AMD_FAN_CTRL_AUTO; 4355 } 4356 4357 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr, 4358 struct amd_pp_simple_clock_info *info) 4359 { 4360 struct phm_ppt_v2_information *table_info = 4361 (struct phm_ppt_v2_information *)hwmgr->pptable; 4362 struct phm_clock_and_voltage_limits *max_limits = 4363 &table_info->max_clock_voltage_on_ac; 4364 4365 info->engine_max_clock = max_limits->sclk; 4366 info->memory_max_clock = max_limits->mclk; 4367 4368 return 0; 4369 } 4370 4371 static void vega10_get_sclks(struct pp_hwmgr *hwmgr, 4372 struct pp_clock_levels_with_latency *clocks) 4373 { 4374 struct phm_ppt_v2_information *table_info = 4375 (struct phm_ppt_v2_information *)hwmgr->pptable; 4376 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4377 table_info->vdd_dep_on_sclk; 4378 uint32_t i; 4379 4380 clocks->num_levels = 0; 4381 for (i = 0; i < dep_table->count; i++) { 4382 if (dep_table->entries[i].clk) { 4383 clocks->data[clocks->num_levels].clocks_in_khz = 4384 dep_table->entries[i].clk * 10; 4385 clocks->num_levels++; 4386 } 4387 } 4388 4389 } 4390 4391 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, 4392 struct pp_clock_levels_with_latency *clocks) 4393 { 4394 struct phm_ppt_v2_information *table_info = 4395 (struct phm_ppt_v2_information *)hwmgr->pptable; 4396 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4397 table_info->vdd_dep_on_mclk; 4398 struct vega10_hwmgr *data = hwmgr->backend; 4399 uint32_t j = 0; 4400 uint32_t i; 4401 4402 for (i = 0; i < dep_table->count; i++) { 4403 if (dep_table->entries[i].clk) { 4404 4405 clocks->data[j].clocks_in_khz = 4406 dep_table->entries[i].clk * 10; 4407 data->mclk_latency_table.entries[j].frequency = 4408 dep_table->entries[i].clk; 4409 clocks->data[j].latency_in_us = 4410 data->mclk_latency_table.entries[j].latency = 25; 4411 j++; 4412 } 4413 } 4414 clocks->num_levels = data->mclk_latency_table.count = j; 4415 } 4416 4417 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, 4418 struct pp_clock_levels_with_latency *clocks) 4419 { 4420 struct phm_ppt_v2_information *table_info = 4421 (struct phm_ppt_v2_information *)hwmgr->pptable; 4422 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4423 table_info->vdd_dep_on_dcefclk; 4424 uint32_t i; 4425 4426 for (i = 0; i < dep_table->count; i++) { 4427 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4428 clocks->data[i].latency_in_us = 0; 4429 clocks->num_levels++; 4430 } 4431 } 4432 4433 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, 4434 struct pp_clock_levels_with_latency *clocks) 4435 { 4436 struct phm_ppt_v2_information *table_info = 4437 (struct phm_ppt_v2_information *)hwmgr->pptable; 4438 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4439 table_info->vdd_dep_on_socclk; 4440 uint32_t i; 4441 4442 for (i = 0; i < dep_table->count; i++) { 4443 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4444 clocks->data[i].latency_in_us = 0; 4445 clocks->num_levels++; 4446 } 4447 } 4448 4449 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 4450 enum amd_pp_clock_type type, 4451 struct pp_clock_levels_with_latency *clocks) 4452 { 4453 switch (type) { 4454 case amd_pp_sys_clock: 4455 vega10_get_sclks(hwmgr, clocks); 4456 break; 4457 case amd_pp_mem_clock: 4458 vega10_get_memclocks(hwmgr, clocks); 4459 break; 4460 case amd_pp_dcef_clock: 4461 vega10_get_dcefclocks(hwmgr, clocks); 4462 break; 4463 case amd_pp_soc_clock: 4464 vega10_get_socclocks(hwmgr, clocks); 4465 break; 4466 default: 4467 return -1; 4468 } 4469 4470 return 0; 4471 } 4472 4473 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 4474 enum amd_pp_clock_type type, 4475 struct pp_clock_levels_with_voltage *clocks) 4476 { 4477 struct phm_ppt_v2_information *table_info = 4478 (struct phm_ppt_v2_information *)hwmgr->pptable; 4479 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 4480 uint32_t i; 4481 4482 switch (type) { 4483 case amd_pp_mem_clock: 4484 dep_table = table_info->vdd_dep_on_mclk; 4485 break; 4486 case amd_pp_dcef_clock: 4487 dep_table = table_info->vdd_dep_on_dcefclk; 4488 break; 4489 case amd_pp_disp_clock: 4490 dep_table = table_info->vdd_dep_on_dispclk; 4491 break; 4492 case amd_pp_pixel_clock: 4493 dep_table = table_info->vdd_dep_on_pixclk; 4494 break; 4495 case amd_pp_phy_clock: 4496 dep_table = table_info->vdd_dep_on_phyclk; 4497 break; 4498 default: 4499 return -1; 4500 } 4501 4502 for (i = 0; i < dep_table->count; i++) { 4503 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4504 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> 4505 entries[dep_table->entries[i].vddInd].us_vdd); 4506 clocks->num_levels++; 4507 } 4508 4509 if (i < dep_table->count) 4510 return -1; 4511 4512 return 0; 4513 } 4514 4515 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 4516 void *clock_range) 4517 { 4518 struct vega10_hwmgr *data = hwmgr->backend; 4519 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; 4520 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 4521 4522 if (!data->registry_data.disable_water_mark) { 4523 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 4524 data->water_marks_bitmap = WaterMarksExist; 4525 } 4526 4527 return 0; 4528 } 4529 4530 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 4531 { 4532 static const char *ppfeature_name[] = { 4533 "DPM_PREFETCHER", 4534 "GFXCLK_DPM", 4535 "UCLK_DPM", 4536 "SOCCLK_DPM", 4537 "UVD_DPM", 4538 "VCE_DPM", 4539 "ULV", 4540 "MP0CLK_DPM", 4541 "LINK_DPM", 4542 "DCEFCLK_DPM", 4543 "AVFS", 4544 "GFXCLK_DS", 4545 "SOCCLK_DS", 4546 "LCLK_DS", 4547 "PPT", 4548 "TDC", 4549 "THERMAL", 4550 "GFX_PER_CU_CG", 4551 "RM", 4552 "DCEFCLK_DS", 4553 "ACDC", 4554 "VR0HOT", 4555 "VR1HOT", 4556 "FW_CTF", 4557 "LED_DISPLAY", 4558 "FAN_CONTROL", 4559 "FAST_PPT", 4560 "DIDT", 4561 "ACG", 4562 "PCC_LIMIT"}; 4563 static const char *output_title[] = { 4564 "FEATURES", 4565 "BITMASK", 4566 "ENABLEMENT"}; 4567 uint64_t features_enabled; 4568 int i; 4569 int ret = 0; 4570 int size = 0; 4571 4572 phm_get_sysfs_buf(&buf, &size); 4573 4574 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4575 PP_ASSERT_WITH_CODE(!ret, 4576 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 4577 return ret); 4578 4579 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 4580 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 4581 output_title[0], 4582 output_title[1], 4583 output_title[2]); 4584 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 4585 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 4586 ppfeature_name[i], 4587 1ULL << i, 4588 (features_enabled & (1ULL << i)) ? "Y" : "N"); 4589 } 4590 4591 return size; 4592 } 4593 4594 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 4595 { 4596 uint64_t features_enabled; 4597 uint64_t features_to_enable; 4598 uint64_t features_to_disable; 4599 int ret = 0; 4600 4601 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 4602 return -EINVAL; 4603 4604 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4605 if (ret) 4606 return ret; 4607 4608 features_to_disable = 4609 features_enabled & ~new_ppfeature_masks; 4610 features_to_enable = 4611 ~features_enabled & new_ppfeature_masks; 4612 4613 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 4614 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 4615 4616 if (features_to_disable) { 4617 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); 4618 if (ret) 4619 return ret; 4620 } 4621 4622 if (features_to_enable) { 4623 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); 4624 if (ret) 4625 return ret; 4626 } 4627 4628 return 0; 4629 } 4630 4631 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 4632 { 4633 struct amdgpu_device *adev = hwmgr->adev; 4634 4635 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 4636 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 4637 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 4638 } 4639 4640 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 4641 { 4642 struct amdgpu_device *adev = hwmgr->adev; 4643 4644 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 4645 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 4646 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 4647 } 4648 4649 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr, 4650 enum pp_clock_type type, char *buf, int *offset) 4651 { 4652 struct vega10_hwmgr *data = hwmgr->backend; 4653 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4654 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4655 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4656 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4657 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4658 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4659 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4660 4661 uint32_t i, now, count = 0; 4662 int ret = 0; 4663 4664 switch (type) { 4665 case PP_SCLK: 4666 if (data->registry_data.sclk_dpm_key_disabled) 4667 return -EOPNOTSUPP; 4668 4669 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4670 if (unlikely(ret != 0)) 4671 return ret; 4672 4673 if (hwmgr->pp_one_vf && 4674 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4675 count = 5; 4676 else 4677 count = sclk_table->count; 4678 for (i = 0; i < count; i++) 4679 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4680 i, sclk_table->dpm_levels[i].value / 100, 4681 (i == now) ? "*" : ""); 4682 break; 4683 case PP_MCLK: 4684 if (data->registry_data.mclk_dpm_key_disabled) 4685 return -EOPNOTSUPP; 4686 4687 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4688 if (unlikely(ret != 0)) 4689 return ret; 4690 4691 for (i = 0; i < mclk_table->count; i++) 4692 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4693 i, mclk_table->dpm_levels[i].value / 100, 4694 (i == now) ? "*" : ""); 4695 break; 4696 case PP_SOCCLK: 4697 if (data->registry_data.socclk_dpm_key_disabled) 4698 return -EOPNOTSUPP; 4699 4700 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4701 if (unlikely(ret != 0)) 4702 return ret; 4703 4704 for (i = 0; i < soc_table->count; i++) 4705 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4706 i, soc_table->dpm_levels[i].value / 100, 4707 (i == now) ? "*" : ""); 4708 break; 4709 case PP_DCEFCLK: 4710 if (data->registry_data.dcefclk_dpm_key_disabled) 4711 return -EOPNOTSUPP; 4712 4713 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4714 PPSMC_MSG_GetClockFreqMHz, 4715 CLK_DCEFCLK, &now); 4716 if (unlikely(ret != 0)) 4717 return ret; 4718 4719 for (i = 0; i < dcef_table->count; i++) 4720 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4721 i, dcef_table->dpm_levels[i].value / 100, 4722 (dcef_table->dpm_levels[i].value / 100 == now) ? 4723 "*" : ""); 4724 break; 4725 case PP_PCIE: 4726 current_gen_speed = 4727 vega10_get_current_pcie_link_speed_level(hwmgr); 4728 current_lane_width = 4729 vega10_get_current_pcie_link_width_level(hwmgr); 4730 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4731 gen_speed = pptable->PcieGenSpeed[i]; 4732 lane_width = pptable->PcieLaneCount[i]; 4733 4734 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i, 4735 (gen_speed == 0) ? "2.5GT/s," : 4736 (gen_speed == 1) ? "5.0GT/s," : 4737 (gen_speed == 2) ? "8.0GT/s," : 4738 (gen_speed == 3) ? "16.0GT/s," : "", 4739 (lane_width == 1) ? "x1" : 4740 (lane_width == 2) ? "x2" : 4741 (lane_width == 3) ? "x4" : 4742 (lane_width == 4) ? "x8" : 4743 (lane_width == 5) ? "x12" : 4744 (lane_width == 6) ? "x16" : "", 4745 (current_gen_speed == gen_speed) && 4746 (current_lane_width == lane_width) ? 4747 "*" : ""); 4748 } 4749 break; 4750 4751 case OD_SCLK: 4752 if (!hwmgr->od_enabled) 4753 return -EOPNOTSUPP; 4754 4755 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); 4756 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4757 for (i = 0; i < podn_vdd_dep->count; i++) 4758 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4759 i, podn_vdd_dep->entries[i].clk / 100, 4760 podn_vdd_dep->entries[i].vddc); 4761 break; 4762 case OD_MCLK: 4763 if (!hwmgr->od_enabled) 4764 return -EOPNOTSUPP; 4765 4766 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); 4767 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4768 for (i = 0; i < podn_vdd_dep->count; i++) 4769 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4770 i, podn_vdd_dep->entries[i].clk/100, 4771 podn_vdd_dep->entries[i].vddc); 4772 break; 4773 case OD_RANGE: 4774 if (!hwmgr->od_enabled) 4775 return -EOPNOTSUPP; 4776 4777 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 4778 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n", 4779 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4780 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4781 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n", 4782 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4783 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4784 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n", 4785 data->odn_dpm_table.min_vddc, 4786 data->odn_dpm_table.max_vddc); 4787 break; 4788 default: 4789 ret = -ENOENT; 4790 break; 4791 } 4792 return ret; 4793 } 4794 4795 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, 4796 enum pp_clock_type type, char *buf) 4797 { 4798 struct vega10_hwmgr *data = hwmgr->backend; 4799 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4800 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4801 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4802 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4803 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4804 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4805 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4806 4807 int i, now, size = 0, count = 0; 4808 4809 switch (type) { 4810 case PP_SCLK: 4811 if (data->registry_data.sclk_dpm_key_disabled) 4812 break; 4813 4814 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4815 4816 if (hwmgr->pp_one_vf && 4817 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4818 count = 5; 4819 else 4820 count = sclk_table->count; 4821 for (i = 0; i < count; i++) 4822 size += sprintf(buf + size, "%d: %uMhz %s\n", 4823 i, sclk_table->dpm_levels[i].value / 100, 4824 (i == now) ? "*" : ""); 4825 break; 4826 case PP_MCLK: 4827 if (data->registry_data.mclk_dpm_key_disabled) 4828 break; 4829 4830 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4831 4832 for (i = 0; i < mclk_table->count; i++) 4833 size += sprintf(buf + size, "%d: %uMhz %s\n", 4834 i, mclk_table->dpm_levels[i].value / 100, 4835 (i == now) ? "*" : ""); 4836 break; 4837 case PP_SOCCLK: 4838 if (data->registry_data.socclk_dpm_key_disabled) 4839 break; 4840 4841 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4842 4843 for (i = 0; i < soc_table->count; i++) 4844 size += sprintf(buf + size, "%d: %uMhz %s\n", 4845 i, soc_table->dpm_levels[i].value / 100, 4846 (i == now) ? "*" : ""); 4847 break; 4848 case PP_DCEFCLK: 4849 if (data->registry_data.dcefclk_dpm_key_disabled) 4850 break; 4851 4852 smum_send_msg_to_smc_with_parameter(hwmgr, 4853 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now); 4854 4855 for (i = 0; i < dcef_table->count; i++) 4856 size += sprintf(buf + size, "%d: %uMhz %s\n", 4857 i, dcef_table->dpm_levels[i].value / 100, 4858 (dcef_table->dpm_levels[i].value / 100 == now) ? 4859 "*" : ""); 4860 break; 4861 case PP_PCIE: 4862 current_gen_speed = 4863 vega10_get_current_pcie_link_speed_level(hwmgr); 4864 current_lane_width = 4865 vega10_get_current_pcie_link_width_level(hwmgr); 4866 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4867 gen_speed = pptable->PcieGenSpeed[i]; 4868 lane_width = pptable->PcieLaneCount[i]; 4869 4870 size += sprintf(buf + size, "%d: %s %s %s\n", i, 4871 (gen_speed == 0) ? "2.5GT/s," : 4872 (gen_speed == 1) ? "5.0GT/s," : 4873 (gen_speed == 2) ? "8.0GT/s," : 4874 (gen_speed == 3) ? "16.0GT/s," : "", 4875 (lane_width == 1) ? "x1" : 4876 (lane_width == 2) ? "x2" : 4877 (lane_width == 3) ? "x4" : 4878 (lane_width == 4) ? "x8" : 4879 (lane_width == 5) ? "x12" : 4880 (lane_width == 6) ? "x16" : "", 4881 (current_gen_speed == gen_speed) && 4882 (current_lane_width == lane_width) ? 4883 "*" : ""); 4884 } 4885 break; 4886 4887 case OD_SCLK: 4888 if (hwmgr->od_enabled) { 4889 size += sprintf(buf + size, "%s:\n", "OD_SCLK"); 4890 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4891 for (i = 0; i < podn_vdd_dep->count; i++) 4892 size += sprintf(buf + size, "%d: %10uMhz %10umV\n", 4893 i, podn_vdd_dep->entries[i].clk / 100, 4894 podn_vdd_dep->entries[i].vddc); 4895 } 4896 break; 4897 case OD_MCLK: 4898 if (hwmgr->od_enabled) { 4899 size += sprintf(buf + size, "%s:\n", "OD_MCLK"); 4900 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4901 for (i = 0; i < podn_vdd_dep->count; i++) 4902 size += sprintf(buf + size, "%d: %10uMhz %10umV\n", 4903 i, podn_vdd_dep->entries[i].clk/100, 4904 podn_vdd_dep->entries[i].vddc); 4905 } 4906 break; 4907 case OD_RANGE: 4908 if (hwmgr->od_enabled) { 4909 size += sprintf(buf + size, "%s:\n", "OD_RANGE"); 4910 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 4911 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4912 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4913 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", 4914 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4915 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4916 size += sprintf(buf + size, "VDDC: %7umV %11umV\n", 4917 data->odn_dpm_table.min_vddc, 4918 data->odn_dpm_table.max_vddc); 4919 } 4920 break; 4921 default: 4922 break; 4923 } 4924 return size; 4925 } 4926 4927 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4928 { 4929 struct vega10_hwmgr *data = hwmgr->backend; 4930 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 4931 int result = 0; 4932 4933 if ((data->water_marks_bitmap & WaterMarksExist) && 4934 !(data->water_marks_bitmap & WaterMarksLoaded)) { 4935 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); 4936 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 4937 data->water_marks_bitmap |= WaterMarksLoaded; 4938 } 4939 4940 if (data->water_marks_bitmap & WaterMarksLoaded) { 4941 smum_send_msg_to_smc_with_parameter(hwmgr, 4942 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 4943 NULL); 4944 } 4945 4946 return result; 4947 } 4948 4949 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 4950 { 4951 struct vega10_hwmgr *data = hwmgr->backend; 4952 4953 if (data->smu_features[GNLD_DPM_UVD].supported) { 4954 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 4955 enable, 4956 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 4957 "Attempt to Enable/Disable DPM UVD Failed!", 4958 return -1); 4959 data->smu_features[GNLD_DPM_UVD].enabled = enable; 4960 } 4961 return 0; 4962 } 4963 4964 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 4965 { 4966 struct vega10_hwmgr *data = hwmgr->backend; 4967 4968 data->vce_power_gated = bgate; 4969 vega10_enable_disable_vce_dpm(hwmgr, !bgate); 4970 } 4971 4972 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 4973 { 4974 struct vega10_hwmgr *data = hwmgr->backend; 4975 4976 data->uvd_power_gated = bgate; 4977 vega10_enable_disable_uvd_dpm(hwmgr, !bgate); 4978 } 4979 4980 static inline bool vega10_are_power_levels_equal( 4981 const struct vega10_performance_level *pl1, 4982 const struct vega10_performance_level *pl2) 4983 { 4984 return ((pl1->soc_clock == pl2->soc_clock) && 4985 (pl1->gfx_clock == pl2->gfx_clock) && 4986 (pl1->mem_clock == pl2->mem_clock)); 4987 } 4988 4989 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, 4990 const struct pp_hw_power_state *pstate1, 4991 const struct pp_hw_power_state *pstate2, bool *equal) 4992 { 4993 const struct vega10_power_state *vega10_psa; 4994 const struct vega10_power_state *vega10_psb; 4995 int i; 4996 4997 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 4998 return -EINVAL; 4999 5000 vega10_psa = cast_const_phw_vega10_power_state(pstate1); 5001 vega10_psb = cast_const_phw_vega10_power_state(pstate2); 5002 5003 /* If the two states don't even have the same number of performance levels 5004 * they cannot be the same state. 5005 */ 5006 if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) { 5007 *equal = false; 5008 return 0; 5009 } 5010 5011 for (i = 0; i < vega10_psa->performance_level_count; i++) { 5012 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]), 5013 &(vega10_psb->performance_levels[i]))) { 5014 /* If we have found even one performance level pair 5015 * that is different the states are different. 5016 */ 5017 *equal = false; 5018 return 0; 5019 } 5020 } 5021 5022 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 5023 *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) && 5024 (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk)); 5025 *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) && 5026 (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk)); 5027 *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold); 5028 5029 return 0; 5030 } 5031 5032 static bool 5033 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 5034 { 5035 struct vega10_hwmgr *data = hwmgr->backend; 5036 bool is_update_required = false; 5037 5038 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 5039 is_update_required = true; 5040 5041 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { 5042 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 5043 is_update_required = true; 5044 } 5045 5046 return is_update_required; 5047 } 5048 5049 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 5050 { 5051 int tmp_result, result = 0; 5052 5053 if (!hwmgr->not_vf) 5054 return 0; 5055 5056 if (PP_CAP(PHM_PlatformCaps_ThermalController)) 5057 vega10_disable_thermal_protection(hwmgr); 5058 5059 tmp_result = vega10_disable_power_containment(hwmgr); 5060 PP_ASSERT_WITH_CODE((tmp_result == 0), 5061 "Failed to disable power containment!", result = tmp_result); 5062 5063 tmp_result = vega10_disable_didt_config(hwmgr); 5064 PP_ASSERT_WITH_CODE((tmp_result == 0), 5065 "Failed to disable didt config!", result = tmp_result); 5066 5067 tmp_result = vega10_avfs_enable(hwmgr, false); 5068 PP_ASSERT_WITH_CODE((tmp_result == 0), 5069 "Failed to disable AVFS!", result = tmp_result); 5070 5071 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); 5072 PP_ASSERT_WITH_CODE((tmp_result == 0), 5073 "Failed to stop DPM!", result = tmp_result); 5074 5075 tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); 5076 PP_ASSERT_WITH_CODE((tmp_result == 0), 5077 "Failed to disable deep sleep!", result = tmp_result); 5078 5079 tmp_result = vega10_disable_ulv(hwmgr); 5080 PP_ASSERT_WITH_CODE((tmp_result == 0), 5081 "Failed to disable ulv!", result = tmp_result); 5082 5083 tmp_result = vega10_acg_disable(hwmgr); 5084 PP_ASSERT_WITH_CODE((tmp_result == 0), 5085 "Failed to disable acg!", result = tmp_result); 5086 5087 vega10_enable_disable_PCC_limit_feature(hwmgr, false); 5088 return result; 5089 } 5090 5091 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) 5092 { 5093 struct vega10_hwmgr *data = hwmgr->backend; 5094 int result; 5095 5096 result = vega10_disable_dpm_tasks(hwmgr); 5097 PP_ASSERT_WITH_CODE((0 == result), 5098 "[disable_dpm_tasks] Failed to disable DPM!", 5099 ); 5100 data->water_marks_bitmap &= ~(WaterMarksLoaded); 5101 5102 return result; 5103 } 5104 5105 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) 5106 { 5107 struct vega10_hwmgr *data = hwmgr->backend; 5108 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 5109 struct vega10_single_dpm_table *golden_sclk_table = 5110 &(data->golden_dpm_table.gfx_table); 5111 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 5112 int golden_value = golden_sclk_table->dpm_levels 5113 [golden_sclk_table->count - 1].value; 5114 5115 value -= golden_value; 5116 value = DIV_ROUND_UP(value * 100, golden_value); 5117 5118 return value; 5119 } 5120 5121 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5122 { 5123 struct vega10_hwmgr *data = hwmgr->backend; 5124 struct vega10_single_dpm_table *golden_sclk_table = 5125 &(data->golden_dpm_table.gfx_table); 5126 struct pp_power_state *ps; 5127 struct vega10_power_state *vega10_ps; 5128 5129 ps = hwmgr->request_ps; 5130 5131 if (ps == NULL) 5132 return -EINVAL; 5133 5134 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5135 5136 vega10_ps->performance_levels 5137 [vega10_ps->performance_level_count - 1].gfx_clock = 5138 golden_sclk_table->dpm_levels 5139 [golden_sclk_table->count - 1].value * 5140 value / 100 + 5141 golden_sclk_table->dpm_levels 5142 [golden_sclk_table->count - 1].value; 5143 5144 if (vega10_ps->performance_levels 5145 [vega10_ps->performance_level_count - 1].gfx_clock > 5146 hwmgr->platform_descriptor.overdriveLimit.engineClock) { 5147 vega10_ps->performance_levels 5148 [vega10_ps->performance_level_count - 1].gfx_clock = 5149 hwmgr->platform_descriptor.overdriveLimit.engineClock; 5150 pr_warn("max sclk supported by vbios is %d\n", 5151 hwmgr->platform_descriptor.overdriveLimit.engineClock); 5152 } 5153 return 0; 5154 } 5155 5156 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) 5157 { 5158 struct vega10_hwmgr *data = hwmgr->backend; 5159 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 5160 struct vega10_single_dpm_table *golden_mclk_table = 5161 &(data->golden_dpm_table.mem_table); 5162 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5163 int golden_value = golden_mclk_table->dpm_levels 5164 [golden_mclk_table->count - 1].value; 5165 5166 value -= golden_value; 5167 value = DIV_ROUND_UP(value * 100, golden_value); 5168 5169 return value; 5170 } 5171 5172 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5173 { 5174 struct vega10_hwmgr *data = hwmgr->backend; 5175 struct vega10_single_dpm_table *golden_mclk_table = 5176 &(data->golden_dpm_table.mem_table); 5177 struct pp_power_state *ps; 5178 struct vega10_power_state *vega10_ps; 5179 5180 ps = hwmgr->request_ps; 5181 5182 if (ps == NULL) 5183 return -EINVAL; 5184 5185 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5186 5187 vega10_ps->performance_levels 5188 [vega10_ps->performance_level_count - 1].mem_clock = 5189 golden_mclk_table->dpm_levels 5190 [golden_mclk_table->count - 1].value * 5191 value / 100 + 5192 golden_mclk_table->dpm_levels 5193 [golden_mclk_table->count - 1].value; 5194 5195 if (vega10_ps->performance_levels 5196 [vega10_ps->performance_level_count - 1].mem_clock > 5197 hwmgr->platform_descriptor.overdriveLimit.memoryClock) { 5198 vega10_ps->performance_levels 5199 [vega10_ps->performance_level_count - 1].mem_clock = 5200 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 5201 pr_warn("max mclk supported by vbios is %d\n", 5202 hwmgr->platform_descriptor.overdriveLimit.memoryClock); 5203 } 5204 5205 return 0; 5206 } 5207 5208 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5209 uint32_t virtual_addr_low, 5210 uint32_t virtual_addr_hi, 5211 uint32_t mc_addr_low, 5212 uint32_t mc_addr_hi, 5213 uint32_t size) 5214 { 5215 smum_send_msg_to_smc_with_parameter(hwmgr, 5216 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 5217 virtual_addr_hi, 5218 NULL); 5219 smum_send_msg_to_smc_with_parameter(hwmgr, 5220 PPSMC_MSG_SetSystemVirtualDramAddrLow, 5221 virtual_addr_low, 5222 NULL); 5223 smum_send_msg_to_smc_with_parameter(hwmgr, 5224 PPSMC_MSG_DramLogSetDramAddrHigh, 5225 mc_addr_hi, 5226 NULL); 5227 5228 smum_send_msg_to_smc_with_parameter(hwmgr, 5229 PPSMC_MSG_DramLogSetDramAddrLow, 5230 mc_addr_low, 5231 NULL); 5232 5233 smum_send_msg_to_smc_with_parameter(hwmgr, 5234 PPSMC_MSG_DramLogSetDramSize, 5235 size, 5236 NULL); 5237 return 0; 5238 } 5239 5240 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5241 struct PP_TemperatureRange *thermal_data) 5242 { 5243 struct vega10_hwmgr *data = hwmgr->backend; 5244 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 5245 5246 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 5247 5248 thermal_data->max = pp_table->TedgeLimit * 5249 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5250 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 5251 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5252 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 5253 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5254 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 5255 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5256 thermal_data->mem_crit_max = pp_table->ThbmLimit * 5257 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5258 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 5259 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5260 5261 return 0; 5262 } 5263 5264 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5265 { 5266 struct vega10_hwmgr *data = hwmgr->backend; 5267 uint32_t i, size = 0; 5268 static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,}, 5269 {70, 60, 1, 3,}, 5270 {90, 60, 0, 0,}, 5271 {70, 60, 0, 0,}, 5272 {70, 90, 0, 0,}, 5273 {30, 60, 0, 6,}, 5274 }; 5275 static const char *title[6] = {"NUM", 5276 "MODE_NAME", 5277 "BUSY_SET_POINT", 5278 "FPS", 5279 "USE_RLC_BUSY", 5280 "MIN_ACTIVE_LEVEL"}; 5281 5282 if (!buf) 5283 return -EINVAL; 5284 5285 phm_get_sysfs_buf(&buf, &size); 5286 5287 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0], 5288 title[1], title[2], title[3], title[4], title[5]); 5289 5290 for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) 5291 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", 5292 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5293 profile_mode_setting[i][0], profile_mode_setting[i][1], 5294 profile_mode_setting[i][2], profile_mode_setting[i][3]); 5295 5296 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i, 5297 amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5298 data->custom_profile_mode[0], data->custom_profile_mode[1], 5299 data->custom_profile_mode[2], data->custom_profile_mode[3]); 5300 return size; 5301 } 5302 5303 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr) 5304 { 5305 struct amdgpu_device *adev = hwmgr->adev; 5306 5307 return (adev->pdev->device == 0x6860); 5308 } 5309 5310 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5311 { 5312 struct vega10_hwmgr *data = hwmgr->backend; 5313 uint8_t busy_set_point; 5314 uint8_t FPS; 5315 uint8_t use_rlc_busy; 5316 uint8_t min_active_level; 5317 uint32_t power_profile_mode = input[size]; 5318 5319 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 5320 if (size != 0 && size != 4) 5321 return -EINVAL; 5322 5323 /* If size = 0 and the CUSTOM profile has been set already 5324 * then just apply the profile. The copy stored in the hwmgr 5325 * is zeroed out on init 5326 */ 5327 if (size == 0) { 5328 if (data->custom_profile_mode[0] != 0) 5329 goto out; 5330 else 5331 return -EINVAL; 5332 } 5333 5334 data->custom_profile_mode[0] = busy_set_point = input[0]; 5335 data->custom_profile_mode[1] = FPS = input[1]; 5336 data->custom_profile_mode[2] = use_rlc_busy = input[2]; 5337 data->custom_profile_mode[3] = min_active_level = input[3]; 5338 smum_send_msg_to_smc_with_parameter(hwmgr, 5339 PPSMC_MSG_SetCustomGfxDpmParameters, 5340 busy_set_point | FPS<<8 | 5341 use_rlc_busy << 16 | min_active_level<<24, 5342 NULL); 5343 } 5344 5345 out: 5346 if (vega10_get_power_profile_mode_quirks(hwmgr)) 5347 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5348 1 << power_profile_mode, 5349 NULL); 5350 else 5351 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5352 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), 5353 NULL); 5354 5355 hwmgr->power_profile_mode = power_profile_mode; 5356 5357 return 0; 5358 } 5359 5360 5361 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5362 enum PP_OD_DPM_TABLE_COMMAND type, 5363 uint32_t clk, 5364 uint32_t voltage) 5365 { 5366 struct vega10_hwmgr *data = hwmgr->backend; 5367 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 5368 struct vega10_single_dpm_table *golden_table; 5369 5370 if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) { 5371 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc); 5372 return false; 5373 } 5374 5375 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5376 golden_table = &(data->golden_dpm_table.gfx_table); 5377 if (golden_table->dpm_levels[0].value > clk || 5378 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5379 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5380 golden_table->dpm_levels[0].value/100, 5381 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5382 return false; 5383 } 5384 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5385 golden_table = &(data->golden_dpm_table.mem_table); 5386 if (golden_table->dpm_levels[0].value > clk || 5387 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5388 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5389 golden_table->dpm_levels[0].value/100, 5390 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5391 return false; 5392 } 5393 } else { 5394 return false; 5395 } 5396 5397 return true; 5398 } 5399 5400 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr) 5401 { 5402 struct vega10_hwmgr *data = hwmgr->backend; 5403 struct pp_power_state *ps = hwmgr->request_ps; 5404 struct vega10_power_state *vega10_ps; 5405 struct vega10_single_dpm_table *gfx_dpm_table = 5406 &data->dpm_table.gfx_table; 5407 struct vega10_single_dpm_table *soc_dpm_table = 5408 &data->dpm_table.soc_table; 5409 struct vega10_single_dpm_table *mem_dpm_table = 5410 &data->dpm_table.mem_table; 5411 int max_level; 5412 5413 if (!ps) 5414 return; 5415 5416 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5417 max_level = vega10_ps->performance_level_count - 1; 5418 5419 if (vega10_ps->performance_levels[max_level].gfx_clock != 5420 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5421 vega10_ps->performance_levels[max_level].gfx_clock = 5422 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5423 5424 if (vega10_ps->performance_levels[max_level].soc_clock != 5425 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5426 vega10_ps->performance_levels[max_level].soc_clock = 5427 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5428 5429 if (vega10_ps->performance_levels[max_level].mem_clock != 5430 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5431 vega10_ps->performance_levels[max_level].mem_clock = 5432 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5433 5434 if (!hwmgr->ps) 5435 return; 5436 5437 ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1)); 5438 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5439 max_level = vega10_ps->performance_level_count - 1; 5440 5441 if (vega10_ps->performance_levels[max_level].gfx_clock != 5442 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5443 vega10_ps->performance_levels[max_level].gfx_clock = 5444 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5445 5446 if (vega10_ps->performance_levels[max_level].soc_clock != 5447 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5448 vega10_ps->performance_levels[max_level].soc_clock = 5449 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5450 5451 if (vega10_ps->performance_levels[max_level].mem_clock != 5452 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5453 vega10_ps->performance_levels[max_level].mem_clock = 5454 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5455 } 5456 5457 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr, 5458 enum PP_OD_DPM_TABLE_COMMAND type) 5459 { 5460 struct vega10_hwmgr *data = hwmgr->backend; 5461 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 5462 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk; 5463 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; 5464 5465 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk = 5466 &data->odn_dpm_table.vdd_dep_on_socclk; 5467 struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table; 5468 5469 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep; 5470 uint8_t i, j; 5471 5472 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5473 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 5474 for (i = 0; i < podn_vdd_dep->count; i++) 5475 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; 5476 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5477 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 5478 for (i = 0; i < dpm_table->count; i++) { 5479 for (j = 0; j < od_vddc_lookup_table->count; j++) { 5480 if (od_vddc_lookup_table->entries[j].us_vdd > 5481 podn_vdd_dep->entries[i].vddc) 5482 break; 5483 } 5484 if (j == od_vddc_lookup_table->count) { 5485 j = od_vddc_lookup_table->count - 1; 5486 od_vddc_lookup_table->entries[j].us_vdd = 5487 podn_vdd_dep->entries[i].vddc; 5488 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 5489 } 5490 podn_vdd_dep->entries[i].vddInd = j; 5491 } 5492 dpm_table = &data->dpm_table.soc_table; 5493 for (i = 0; i < dep_table->count; i++) { 5494 if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd && 5495 dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) { 5496 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5497 for (; (i < dep_table->count) && 5498 (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) { 5499 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk; 5500 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk; 5501 } 5502 break; 5503 } else { 5504 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk; 5505 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc; 5506 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd; 5507 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk; 5508 } 5509 } 5510 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk < 5511 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) { 5512 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5513 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = 5514 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5515 dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = 5516 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5517 } 5518 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd < 5519 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) { 5520 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5521 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = 5522 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd; 5523 } 5524 } 5525 vega10_odn_update_power_state(hwmgr); 5526 } 5527 5528 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5529 enum PP_OD_DPM_TABLE_COMMAND type, 5530 long *input, uint32_t size) 5531 { 5532 struct vega10_hwmgr *data = hwmgr->backend; 5533 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table; 5534 struct vega10_single_dpm_table *dpm_table; 5535 5536 uint32_t input_clk; 5537 uint32_t input_vol; 5538 uint32_t input_level; 5539 uint32_t i; 5540 5541 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5542 return -EINVAL); 5543 5544 if (!hwmgr->od_enabled) { 5545 pr_info("OverDrive feature not enabled\n"); 5546 return -EINVAL; 5547 } 5548 5549 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5550 dpm_table = &data->dpm_table.gfx_table; 5551 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk; 5552 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 5553 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5554 dpm_table = &data->dpm_table.mem_table; 5555 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk; 5556 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 5557 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5558 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table)); 5559 vega10_odn_initial_default_setting(hwmgr); 5560 vega10_odn_update_power_state(hwmgr); 5561 /* force to update all clock tables */ 5562 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | 5563 DPMTABLE_UPDATE_MCLK | 5564 DPMTABLE_UPDATE_SOCCLK; 5565 return 0; 5566 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5567 vega10_check_dpm_table_updated(hwmgr); 5568 return 0; 5569 } else { 5570 return -EINVAL; 5571 } 5572 5573 for (i = 0; i < size; i += 3) { 5574 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) { 5575 pr_info("invalid clock voltage input\n"); 5576 return 0; 5577 } 5578 input_level = input[i]; 5579 input_clk = input[i+1] * 100; 5580 input_vol = input[i+2]; 5581 5582 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5583 dpm_table->dpm_levels[input_level].value = input_clk; 5584 podn_vdd_dep_table->entries[input_level].clk = input_clk; 5585 podn_vdd_dep_table->entries[input_level].vddc = input_vol; 5586 } else { 5587 return -EINVAL; 5588 } 5589 } 5590 vega10_odn_update_soc_table(hwmgr, type); 5591 return 0; 5592 } 5593 5594 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr, 5595 enum pp_mp1_state mp1_state) 5596 { 5597 uint16_t msg; 5598 int ret; 5599 5600 switch (mp1_state) { 5601 case PP_MP1_STATE_UNLOAD: 5602 msg = PPSMC_MSG_PrepareMp1ForUnload; 5603 break; 5604 case PP_MP1_STATE_SHUTDOWN: 5605 case PP_MP1_STATE_RESET: 5606 case PP_MP1_STATE_NONE: 5607 default: 5608 return 0; 5609 } 5610 5611 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 5612 "[PrepareMp1] Failed!", 5613 return ret); 5614 5615 return 0; 5616 } 5617 5618 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5619 PHM_PerformanceLevelDesignation designation, uint32_t index, 5620 PHM_PerformanceLevel *level) 5621 { 5622 const struct vega10_power_state *vega10_ps; 5623 uint32_t i; 5624 5625 if (level == NULL || hwmgr == NULL || state == NULL) 5626 return -EINVAL; 5627 5628 vega10_ps = cast_const_phw_vega10_power_state(state); 5629 5630 i = index > vega10_ps->performance_level_count - 1 ? 5631 vega10_ps->performance_level_count - 1 : index; 5632 5633 level->coreClock = vega10_ps->performance_levels[i].gfx_clock; 5634 level->memory_clock = vega10_ps->performance_levels[i].mem_clock; 5635 5636 return 0; 5637 } 5638 5639 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable) 5640 { 5641 struct vega10_hwmgr *data = hwmgr->backend; 5642 uint32_t feature_mask = 0; 5643 5644 if (disable) { 5645 feature_mask |= data->smu_features[GNLD_ULV].enabled ? 5646 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5647 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ? 5648 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5649 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ? 5650 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5651 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ? 5652 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5653 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ? 5654 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5655 } else { 5656 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ? 5657 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5658 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ? 5659 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5660 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ? 5661 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5662 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ? 5663 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5664 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ? 5665 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5666 } 5667 5668 if (feature_mask) 5669 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 5670 !disable, feature_mask), 5671 "enable/disable power features for compute performance Failed!", 5672 return -EINVAL); 5673 5674 if (disable) { 5675 data->smu_features[GNLD_ULV].enabled = false; 5676 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 5677 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 5678 data->smu_features[GNLD_DS_LCLK].enabled = false; 5679 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 5680 } else { 5681 data->smu_features[GNLD_ULV].enabled = true; 5682 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 5683 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 5684 data->smu_features[GNLD_DS_LCLK].enabled = true; 5685 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 5686 } 5687 5688 return 0; 5689 5690 } 5691 5692 static const struct pp_hwmgr_func vega10_hwmgr_funcs = { 5693 .backend_init = vega10_hwmgr_backend_init, 5694 .backend_fini = vega10_hwmgr_backend_fini, 5695 .asic_setup = vega10_setup_asic_task, 5696 .dynamic_state_management_enable = vega10_enable_dpm_tasks, 5697 .dynamic_state_management_disable = vega10_disable_dpm_tasks, 5698 .get_num_of_pp_table_entries = 5699 vega10_get_number_of_powerplay_table_entries, 5700 .get_power_state_size = vega10_get_power_state_size, 5701 .get_pp_table_entry = vega10_get_pp_table_entry, 5702 .patch_boot_state = vega10_patch_boot_state, 5703 .apply_state_adjust_rules = vega10_apply_state_adjust_rules, 5704 .power_state_set = vega10_set_power_state_tasks, 5705 .get_sclk = vega10_dpm_get_sclk, 5706 .get_mclk = vega10_dpm_get_mclk, 5707 .notify_smc_display_config_after_ps_adjustment = 5708 vega10_notify_smc_display_config_after_ps_adjustment, 5709 .force_dpm_level = vega10_dpm_force_dpm_level, 5710 .stop_thermal_controller = vega10_thermal_stop_thermal_controller, 5711 .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info, 5712 .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm, 5713 .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm, 5714 .reset_fan_speed_to_default = 5715 vega10_fan_ctrl_reset_fan_speed_to_default, 5716 .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm, 5717 .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm, 5718 .uninitialize_thermal_controller = 5719 vega10_thermal_ctrl_uninitialize_thermal_controller, 5720 .set_fan_control_mode = vega10_set_fan_control_mode, 5721 .get_fan_control_mode = vega10_get_fan_control_mode, 5722 .read_sensor = vega10_read_sensor, 5723 .get_dal_power_level = vega10_get_dal_power_level, 5724 .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency, 5725 .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage, 5726 .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges, 5727 .display_clock_voltage_request = vega10_display_clock_voltage_request, 5728 .force_clock_level = vega10_force_clock_level, 5729 .emit_clock_levels = vega10_emit_clock_levels, 5730 .print_clock_levels = vega10_print_clock_levels, 5731 .display_config_changed = vega10_display_configuration_changed_task, 5732 .powergate_uvd = vega10_power_gate_uvd, 5733 .powergate_vce = vega10_power_gate_vce, 5734 .check_states_equal = vega10_check_states_equal, 5735 .check_smc_update_required_for_display_configuration = 5736 vega10_check_smc_update_required_for_display_configuration, 5737 .power_off_asic = vega10_power_off_asic, 5738 .disable_smc_firmware_ctf = vega10_thermal_disable_alert, 5739 .get_sclk_od = vega10_get_sclk_od, 5740 .set_sclk_od = vega10_set_sclk_od, 5741 .get_mclk_od = vega10_get_mclk_od, 5742 .set_mclk_od = vega10_set_mclk_od, 5743 .avfs_control = vega10_avfs_enable, 5744 .notify_cac_buffer_info = vega10_notify_cac_buffer_info, 5745 .get_thermal_temperature_range = vega10_get_thermal_temperature_range, 5746 .register_irq_handlers = smu9_register_irq_handlers, 5747 .start_thermal_controller = vega10_start_thermal_controller, 5748 .get_power_profile_mode = vega10_get_power_profile_mode, 5749 .set_power_profile_mode = vega10_set_power_profile_mode, 5750 .set_power_limit = vega10_set_power_limit, 5751 .odn_edit_dpm_table = vega10_odn_edit_dpm_table, 5752 .get_performance_level = vega10_get_performance_level, 5753 .get_asic_baco_capability = smu9_baco_get_capability, 5754 .get_asic_baco_state = smu9_baco_get_state, 5755 .set_asic_baco_state = vega10_baco_set_state, 5756 .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost, 5757 .get_ppfeature_status = vega10_get_ppfeature_status, 5758 .set_ppfeature_status = vega10_set_ppfeature_status, 5759 .set_mp1_state = vega10_set_mp1_state, 5760 .disable_power_features_for_compute_performance = 5761 vega10_disable_power_features_for_compute_performance, 5762 }; 5763 5764 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) 5765 { 5766 struct amdgpu_device *adev = hwmgr->adev; 5767 5768 hwmgr->hwmgr_func = &vega10_hwmgr_funcs; 5769 hwmgr->pptable_func = &vega10_pptable_funcs; 5770 if (amdgpu_passthrough(adev)) 5771 return vega10_baco_set_cap(hwmgr); 5772 5773 return 0; 5774 } 5775