1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 29 #include "hwmgr.h" 30 #include "amd_powerplay.h" 31 #include "hardwaremanager.h" 32 #include "ppatomfwctrl.h" 33 #include "atomfirmware.h" 34 #include "cgs_common.h" 35 #include "vega10_powertune.h" 36 #include "smu9.h" 37 #include "smu9_driver_if.h" 38 #include "vega10_inc.h" 39 #include "soc15_common.h" 40 #include "pppcielanes.h" 41 #include "vega10_hwmgr.h" 42 #include "vega10_smumgr.h" 43 #include "vega10_processpptables.h" 44 #include "vega10_pptable.h" 45 #include "vega10_thermal.h" 46 #include "pp_debug.h" 47 #include "amd_pcie_helpers.h" 48 #include "ppinterrupt.h" 49 #include "pp_overdriver.h" 50 #include "pp_thermal.h" 51 #include "vega10_baco.h" 52 53 #include "smuio/smuio_9_0_offset.h" 54 #include "smuio/smuio_9_0_sh_mask.h" 55 56 #define smnPCIE_LC_SPEED_CNTL 0x11140290 57 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288 58 59 #define HBM_MEMORY_CHANNEL_WIDTH 128 60 61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2}; 62 63 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0 65 66 //DF_CS_AON0_DramBaseAddress0 67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc 72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L 73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L 74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L 75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L 76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L 77 78 typedef enum { 79 CLK_SMNCLK = 0, 80 CLK_SOCCLK, 81 CLK_MP0CLK, 82 CLK_MP1CLK, 83 CLK_LCLK, 84 CLK_DCEFCLK, 85 CLK_VCLK, 86 CLK_DCLK, 87 CLK_ECLK, 88 CLK_UCLK, 89 CLK_GFXCLK, 90 CLK_COUNT, 91 } CLOCK_ID_e; 92 93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic); 94 95 static struct vega10_power_state *cast_phw_vega10_power_state( 96 struct pp_hw_power_state *hw_ps) 97 { 98 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 99 "Invalid Powerstate Type!", 100 return NULL;); 101 102 return (struct vega10_power_state *)hw_ps; 103 } 104 105 static const struct vega10_power_state *cast_const_phw_vega10_power_state( 106 const struct pp_hw_power_state *hw_ps) 107 { 108 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic), 109 "Invalid Powerstate Type!", 110 return NULL;); 111 112 return (const struct vega10_power_state *)hw_ps; 113 } 114 115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr) 116 { 117 struct vega10_hwmgr *data = hwmgr->backend; 118 119 data->registry_data.sclk_dpm_key_disabled = 120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 121 data->registry_data.socclk_dpm_key_disabled = 122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; 123 data->registry_data.mclk_dpm_key_disabled = 124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 125 data->registry_data.pcie_dpm_key_disabled = 126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; 127 128 data->registry_data.dcefclk_dpm_key_disabled = 129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; 130 131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { 132 data->registry_data.power_containment_support = 1; 133 data->registry_data.enable_pkg_pwr_tracking_feature = 1; 134 data->registry_data.enable_tdc_limit_feature = 1; 135 } 136 137 data->registry_data.clock_stretcher_support = 138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; 139 140 data->registry_data.ulv_support = 141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; 142 143 data->registry_data.sclk_deep_sleep_support = 144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; 145 146 data->registry_data.disable_water_mark = 0; 147 148 data->registry_data.fan_control_support = 1; 149 data->registry_data.thermal_support = 1; 150 data->registry_data.fw_ctf_enabled = 1; 151 152 data->registry_data.avfs_support = 153 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; 154 data->registry_data.led_dpm_enabled = 1; 155 156 data->registry_data.vr0hot_enabled = 1; 157 data->registry_data.vr1hot_enabled = 1; 158 data->registry_data.regulator_hot_gpio_support = 1; 159 160 data->registry_data.didt_support = 1; 161 if (data->registry_data.didt_support) { 162 data->registry_data.didt_mode = 6; 163 data->registry_data.sq_ramping_support = 1; 164 data->registry_data.db_ramping_support = 0; 165 data->registry_data.td_ramping_support = 0; 166 data->registry_data.tcp_ramping_support = 0; 167 data->registry_data.dbr_ramping_support = 0; 168 data->registry_data.edc_didt_support = 1; 169 data->registry_data.gc_didt_support = 0; 170 data->registry_data.psm_didt_support = 0; 171 } 172 173 data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT; 174 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 175 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 176 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 177 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 178 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 179 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 180 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 181 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 182 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 183 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 184 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 185 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT; 186 187 data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT; 188 data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT; 189 data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT; 190 data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT; 191 } 192 193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) 194 { 195 struct vega10_hwmgr *data = hwmgr->backend; 196 struct phm_ppt_v2_information *table_info = 197 (struct phm_ppt_v2_information *)hwmgr->pptable; 198 struct amdgpu_device *adev = hwmgr->adev; 199 200 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 201 PHM_PlatformCaps_SclkDeepSleep); 202 203 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 204 PHM_PlatformCaps_DynamicPatchPowerState); 205 206 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) 207 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 208 PHM_PlatformCaps_ControlVDDCI); 209 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_EnableSMU7ThermalManagement); 212 213 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 214 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 215 PHM_PlatformCaps_UVDPowerGating); 216 217 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 218 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 219 PHM_PlatformCaps_VCEPowerGating); 220 221 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 222 PHM_PlatformCaps_UnTabledHardwareInterface); 223 224 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 225 PHM_PlatformCaps_FanSpeedInTableIsRPM); 226 227 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 228 PHM_PlatformCaps_ODFuzzyFanControlSupport); 229 230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 231 PHM_PlatformCaps_DynamicPowerManagement); 232 233 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_SMC); 235 236 /* power tune caps */ 237 /* assume disabled */ 238 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 239 PHM_PlatformCaps_PowerContainment); 240 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 241 PHM_PlatformCaps_DiDtSupport); 242 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 243 PHM_PlatformCaps_SQRamping); 244 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 245 PHM_PlatformCaps_DBRamping); 246 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 247 PHM_PlatformCaps_TDRamping); 248 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 249 PHM_PlatformCaps_TCPRamping); 250 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 251 PHM_PlatformCaps_DBRRamping); 252 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 253 PHM_PlatformCaps_DiDtEDCEnable); 254 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 255 PHM_PlatformCaps_GCEDC); 256 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 257 PHM_PlatformCaps_PSM); 258 259 if (data->registry_data.didt_support) { 260 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport); 261 if (data->registry_data.sq_ramping_support) 262 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping); 263 if (data->registry_data.db_ramping_support) 264 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping); 265 if (data->registry_data.td_ramping_support) 266 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping); 267 if (data->registry_data.tcp_ramping_support) 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping); 269 if (data->registry_data.dbr_ramping_support) 270 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping); 271 if (data->registry_data.edc_didt_support) 272 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable); 273 if (data->registry_data.gc_didt_support) 274 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC); 275 if (data->registry_data.psm_didt_support) 276 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM); 277 } 278 279 if (data->registry_data.power_containment_support) 280 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 281 PHM_PlatformCaps_PowerContainment); 282 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 283 PHM_PlatformCaps_CAC); 284 285 if (table_info->tdp_table->usClockStretchAmount && 286 data->registry_data.clock_stretcher_support) 287 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 288 PHM_PlatformCaps_ClockStretcher); 289 290 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 291 PHM_PlatformCaps_RegulatorHot); 292 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 293 PHM_PlatformCaps_AutomaticDCTransition); 294 295 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 296 PHM_PlatformCaps_UVDDPM); 297 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 298 PHM_PlatformCaps_VCEDPM); 299 300 return 0; 301 } 302 303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 304 { 305 struct vega10_hwmgr *data = hwmgr->backend; 306 struct phm_ppt_v2_information *table_info = 307 (struct phm_ppt_v2_information *)(hwmgr->pptable); 308 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 309 struct vega10_odn_vddc_lookup_table *od_lookup_table; 310 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 311 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3]; 312 struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3]; 313 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 314 uint32_t i; 315 int result; 316 317 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 318 if (!result) { 319 data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc; 320 data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc; 321 } 322 323 od_lookup_table = &odn_table->vddc_lookup_table; 324 vddc_lookup_table = table_info->vddc_lookup_table; 325 326 for (i = 0; i < vddc_lookup_table->count; i++) 327 od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd; 328 329 od_lookup_table->count = vddc_lookup_table->count; 330 331 dep_table[0] = table_info->vdd_dep_on_sclk; 332 dep_table[1] = table_info->vdd_dep_on_mclk; 333 dep_table[2] = table_info->vdd_dep_on_socclk; 334 od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk; 335 od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk; 336 od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk; 337 338 for (i = 0; i < 3; i++) 339 smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]); 340 341 if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000) 342 odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc; 343 if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000) 344 odn_table->min_vddc = dep_table[0]->entries[0].vddc; 345 346 i = od_table[2]->count - 1; 347 od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ? 348 hwmgr->platform_descriptor.overdriveLimit.memoryClock : 349 od_table[2]->entries[i].clk; 350 od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ? 351 odn_table->max_vddc : 352 od_table[2]->entries[i].vddc; 353 354 return 0; 355 } 356 357 static int vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr) 358 { 359 struct vega10_hwmgr *data = hwmgr->backend; 360 uint32_t sub_vendor_id, hw_revision; 361 uint32_t top32, bottom32; 362 struct amdgpu_device *adev = hwmgr->adev; 363 int ret, i; 364 365 vega10_initialize_power_tune_defaults(hwmgr); 366 367 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 368 data->smu_features[i].smu_feature_id = 0xffff; 369 data->smu_features[i].smu_feature_bitmap = 1 << i; 370 data->smu_features[i].enabled = false; 371 data->smu_features[i].supported = false; 372 } 373 374 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id = 375 FEATURE_DPM_PREFETCHER_BIT; 376 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id = 377 FEATURE_DPM_GFXCLK_BIT; 378 data->smu_features[GNLD_DPM_UCLK].smu_feature_id = 379 FEATURE_DPM_UCLK_BIT; 380 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id = 381 FEATURE_DPM_SOCCLK_BIT; 382 data->smu_features[GNLD_DPM_UVD].smu_feature_id = 383 FEATURE_DPM_UVD_BIT; 384 data->smu_features[GNLD_DPM_VCE].smu_feature_id = 385 FEATURE_DPM_VCE_BIT; 386 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id = 387 FEATURE_DPM_MP0CLK_BIT; 388 data->smu_features[GNLD_DPM_LINK].smu_feature_id = 389 FEATURE_DPM_LINK_BIT; 390 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id = 391 FEATURE_DPM_DCEFCLK_BIT; 392 data->smu_features[GNLD_ULV].smu_feature_id = 393 FEATURE_ULV_BIT; 394 data->smu_features[GNLD_AVFS].smu_feature_id = 395 FEATURE_AVFS_BIT; 396 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id = 397 FEATURE_DS_GFXCLK_BIT; 398 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id = 399 FEATURE_DS_SOCCLK_BIT; 400 data->smu_features[GNLD_DS_LCLK].smu_feature_id = 401 FEATURE_DS_LCLK_BIT; 402 data->smu_features[GNLD_PPT].smu_feature_id = 403 FEATURE_PPT_BIT; 404 data->smu_features[GNLD_TDC].smu_feature_id = 405 FEATURE_TDC_BIT; 406 data->smu_features[GNLD_THERMAL].smu_feature_id = 407 FEATURE_THERMAL_BIT; 408 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id = 409 FEATURE_GFX_PER_CU_CG_BIT; 410 data->smu_features[GNLD_RM].smu_feature_id = 411 FEATURE_RM_BIT; 412 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id = 413 FEATURE_DS_DCEFCLK_BIT; 414 data->smu_features[GNLD_ACDC].smu_feature_id = 415 FEATURE_ACDC_BIT; 416 data->smu_features[GNLD_VR0HOT].smu_feature_id = 417 FEATURE_VR0HOT_BIT; 418 data->smu_features[GNLD_VR1HOT].smu_feature_id = 419 FEATURE_VR1HOT_BIT; 420 data->smu_features[GNLD_FW_CTF].smu_feature_id = 421 FEATURE_FW_CTF_BIT; 422 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id = 423 FEATURE_LED_DISPLAY_BIT; 424 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id = 425 FEATURE_FAN_CONTROL_BIT; 426 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT; 427 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT; 428 data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT; 429 430 if (!data->registry_data.prefetcher_dpm_key_disabled) 431 data->smu_features[GNLD_DPM_PREFETCHER].supported = true; 432 433 if (!data->registry_data.sclk_dpm_key_disabled) 434 data->smu_features[GNLD_DPM_GFXCLK].supported = true; 435 436 if (!data->registry_data.mclk_dpm_key_disabled) 437 data->smu_features[GNLD_DPM_UCLK].supported = true; 438 439 if (!data->registry_data.socclk_dpm_key_disabled) 440 data->smu_features[GNLD_DPM_SOCCLK].supported = true; 441 442 if (PP_CAP(PHM_PlatformCaps_UVDDPM)) 443 data->smu_features[GNLD_DPM_UVD].supported = true; 444 445 if (PP_CAP(PHM_PlatformCaps_VCEDPM)) 446 data->smu_features[GNLD_DPM_VCE].supported = true; 447 448 data->smu_features[GNLD_DPM_LINK].supported = true; 449 450 if (!data->registry_data.dcefclk_dpm_key_disabled) 451 data->smu_features[GNLD_DPM_DCEFCLK].supported = true; 452 453 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) && 454 data->registry_data.sclk_deep_sleep_support) { 455 data->smu_features[GNLD_DS_GFXCLK].supported = true; 456 data->smu_features[GNLD_DS_SOCCLK].supported = true; 457 data->smu_features[GNLD_DS_LCLK].supported = true; 458 data->smu_features[GNLD_DS_DCEFCLK].supported = true; 459 } 460 461 if (data->registry_data.enable_pkg_pwr_tracking_feature) 462 data->smu_features[GNLD_PPT].supported = true; 463 464 if (data->registry_data.enable_tdc_limit_feature) 465 data->smu_features[GNLD_TDC].supported = true; 466 467 if (data->registry_data.thermal_support) 468 data->smu_features[GNLD_THERMAL].supported = true; 469 470 if (data->registry_data.fan_control_support) 471 data->smu_features[GNLD_FAN_CONTROL].supported = true; 472 473 if (data->registry_data.fw_ctf_enabled) 474 data->smu_features[GNLD_FW_CTF].supported = true; 475 476 if (data->registry_data.avfs_support) 477 data->smu_features[GNLD_AVFS].supported = true; 478 479 if (data->registry_data.led_dpm_enabled) 480 data->smu_features[GNLD_LED_DISPLAY].supported = true; 481 482 if (data->registry_data.vr1hot_enabled) 483 data->smu_features[GNLD_VR1HOT].supported = true; 484 485 if (data->registry_data.vr0hot_enabled) 486 data->smu_features[GNLD_VR0HOT].supported = true; 487 488 ret = smum_send_msg_to_smc(hwmgr, 489 PPSMC_MSG_GetSmuVersion, 490 &hwmgr->smu_version); 491 if (ret) 492 return ret; 493 494 /* ACG firmware has major version 5 */ 495 if ((hwmgr->smu_version & 0xff000000) == 0x5000000) 496 data->smu_features[GNLD_ACG].supported = true; 497 if (data->registry_data.didt_support) 498 data->smu_features[GNLD_DIDT].supported = true; 499 500 hw_revision = adev->pdev->revision; 501 sub_vendor_id = adev->pdev->subsystem_vendor; 502 503 if ((hwmgr->chip_id == 0x6862 || 504 hwmgr->chip_id == 0x6861 || 505 hwmgr->chip_id == 0x6868) && 506 (hw_revision == 0) && 507 (sub_vendor_id != 0x1002)) 508 data->smu_features[GNLD_PCC_LIMIT].supported = true; 509 510 /* Get the SN to turn into a Unique ID */ 511 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 512 if (ret) 513 return ret; 514 515 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 516 if (ret) 517 return ret; 518 519 adev->unique_id = ((uint64_t)bottom32 << 32) | top32; 520 return 0; 521 } 522 523 #ifdef PPLIB_VEGA10_EVV_SUPPORT 524 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr, 525 phm_ppt_v1_voltage_lookup_table *lookup_table, 526 uint16_t virtual_voltage_id, int32_t *socclk) 527 { 528 uint8_t entry_id; 529 uint8_t voltage_id; 530 struct phm_ppt_v2_information *table_info = 531 (struct phm_ppt_v2_information *)(hwmgr->pptable); 532 533 PP_ASSERT_WITH_CODE(lookup_table->count != 0, 534 "Lookup table is empty", 535 return -EINVAL); 536 537 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */ 538 for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) { 539 voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd; 540 if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id) 541 break; 542 } 543 544 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count, 545 "Can't find requested voltage id in vdd_dep_on_socclk table!", 546 return -EINVAL); 547 548 *socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk; 549 550 return 0; 551 } 552 553 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 554 /** 555 * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID. 556 * 557 * @hwmgr: the address of the powerplay hardware manager. 558 * return: always 0. 559 */ 560 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr) 561 { 562 struct vega10_hwmgr *data = hwmgr->backend; 563 uint16_t vv_id; 564 uint32_t vddc = 0; 565 uint16_t i, j; 566 uint32_t sclk = 0; 567 struct phm_ppt_v2_information *table_info = 568 (struct phm_ppt_v2_information *)hwmgr->pptable; 569 struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table = 570 table_info->vdd_dep_on_socclk; 571 int result; 572 573 for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) { 574 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 575 576 if (!vega10_get_socclk_for_voltage_evv(hwmgr, 577 table_info->vddc_lookup_table, vv_id, &sclk)) { 578 if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) { 579 for (j = 1; j < socclk_table->count; j++) { 580 if (socclk_table->entries[j].clk == sclk && 581 socclk_table->entries[j].cks_enable == 0) { 582 sclk += 5000; 583 break; 584 } 585 } 586 } 587 588 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, 589 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), 590 "Error retrieving EVV voltage value!", 591 continue); 592 593 594 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */ 595 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0), 596 "Invalid VDDC value", result = -EINVAL;); 597 598 /* the voltage should not be zero nor equal to leakage ID */ 599 if (vddc != 0 && vddc != vv_id) { 600 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100); 601 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 602 data->vddc_leakage.count++; 603 } 604 } 605 } 606 607 return 0; 608 } 609 610 /** 611 * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value. 612 * 613 * @hwmgr: the address of the powerplay hardware manager. 614 * @voltage: pointer to changing voltage 615 * @leakage_table: pointer to leakage table 616 */ 617 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, 618 uint16_t *voltage, struct vega10_leakage_voltage *leakage_table) 619 { 620 uint32_t index; 621 622 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 623 for (index = 0; index < leakage_table->count; index++) { 624 /* if this voltage matches a leakage voltage ID */ 625 /* patch with actual leakage voltage */ 626 if (leakage_table->leakage_id[index] == *voltage) { 627 *voltage = leakage_table->actual_voltage[index]; 628 break; 629 } 630 } 631 632 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 633 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 634 } 635 636 /** 637 * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 638 * 639 * @hwmgr: the address of the powerplay hardware manager. 640 * @lookup_table: pointer to voltage lookup table 641 * @leakage_table: pointer to leakage table 642 * return: always 0 643 */ 644 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 645 phm_ppt_v1_voltage_lookup_table *lookup_table, 646 struct vega10_leakage_voltage *leakage_table) 647 { 648 uint32_t i; 649 650 for (i = 0; i < lookup_table->count; i++) 651 vega10_patch_with_vdd_leakage(hwmgr, 652 &lookup_table->entries[i].us_vdd, leakage_table); 653 654 return 0; 655 } 656 657 static int vega10_patch_clock_voltage_limits_with_vddc_leakage( 658 struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table, 659 uint16_t *vddc) 660 { 661 vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 662 663 return 0; 664 } 665 #endif 666 667 static int vega10_patch_voltage_dependency_tables_with_lookup_table( 668 struct pp_hwmgr *hwmgr) 669 { 670 uint8_t entry_id, voltage_id; 671 unsigned i; 672 struct phm_ppt_v2_information *table_info = 673 (struct phm_ppt_v2_information *)(hwmgr->pptable); 674 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 675 table_info->mm_dep_table; 676 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 677 table_info->vdd_dep_on_mclk; 678 679 for (i = 0; i < 6; i++) { 680 struct phm_ppt_v1_clock_voltage_dependency_table *vdt; 681 switch (i) { 682 case 0: vdt = table_info->vdd_dep_on_socclk; break; 683 case 1: vdt = table_info->vdd_dep_on_sclk; break; 684 case 2: vdt = table_info->vdd_dep_on_dcefclk; break; 685 case 3: vdt = table_info->vdd_dep_on_pixclk; break; 686 case 4: vdt = table_info->vdd_dep_on_dispclk; break; 687 case 5: vdt = table_info->vdd_dep_on_phyclk; break; 688 } 689 690 for (entry_id = 0; entry_id < vdt->count; entry_id++) { 691 voltage_id = vdt->entries[entry_id].vddInd; 692 vdt->entries[entry_id].vddc = 693 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 694 } 695 } 696 697 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 698 voltage_id = mm_table->entries[entry_id].vddcInd; 699 mm_table->entries[entry_id].vddc = 700 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 701 } 702 703 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 704 voltage_id = mclk_table->entries[entry_id].vddInd; 705 mclk_table->entries[entry_id].vddc = 706 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 707 voltage_id = mclk_table->entries[entry_id].vddciInd; 708 mclk_table->entries[entry_id].vddci = 709 table_info->vddci_lookup_table->entries[voltage_id].us_vdd; 710 voltage_id = mclk_table->entries[entry_id].mvddInd; 711 mclk_table->entries[entry_id].mvdd = 712 table_info->vddmem_lookup_table->entries[voltage_id].us_vdd; 713 } 714 715 716 return 0; 717 718 } 719 720 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr, 721 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 722 { 723 uint32_t table_size, i, j; 724 725 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count, 726 "Lookup table is empty", return -EINVAL); 727 728 table_size = lookup_table->count; 729 730 /* Sorting voltages */ 731 for (i = 0; i < table_size - 1; i++) { 732 for (j = i + 1; j > 0; j--) { 733 if (lookup_table->entries[j].us_vdd < 734 lookup_table->entries[j - 1].us_vdd) { 735 swap(lookup_table->entries[j - 1], 736 lookup_table->entries[j]); 737 } 738 } 739 } 740 741 return 0; 742 } 743 744 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr) 745 { 746 int result = 0; 747 int tmp_result; 748 struct phm_ppt_v2_information *table_info = 749 (struct phm_ppt_v2_information *)(hwmgr->pptable); 750 #ifdef PPLIB_VEGA10_EVV_SUPPORT 751 struct vega10_hwmgr *data = hwmgr->backend; 752 753 tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr, 754 table_info->vddc_lookup_table, &(data->vddc_leakage)); 755 if (tmp_result) 756 result = tmp_result; 757 758 tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 759 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 760 if (tmp_result) 761 result = tmp_result; 762 #endif 763 764 tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 765 if (tmp_result) 766 result = tmp_result; 767 768 tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 769 if (tmp_result) 770 result = tmp_result; 771 772 return result; 773 } 774 775 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) 776 { 777 struct phm_ppt_v2_information *table_info = 778 (struct phm_ppt_v2_information *)(hwmgr->pptable); 779 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 780 table_info->vdd_dep_on_socclk; 781 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 782 table_info->vdd_dep_on_mclk; 783 784 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table, 785 "VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL); 786 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 787 "VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL); 788 789 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table, 790 "VDD dependency on MCLK table is missing. This table is mandatory", return -EINVAL); 791 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 792 "VDD dependency on MCLK table is empty. This table is mandatory", return -EINVAL); 793 794 table_info->max_clock_voltage_on_ac.sclk = 795 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 796 table_info->max_clock_voltage_on_ac.mclk = 797 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 798 table_info->max_clock_voltage_on_ac.vddc = 799 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 800 table_info->max_clock_voltage_on_ac.vddci = 801 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 802 803 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 804 table_info->max_clock_voltage_on_ac.sclk; 805 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 806 table_info->max_clock_voltage_on_ac.mclk; 807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 808 table_info->max_clock_voltage_on_ac.vddc; 809 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = 810 table_info->max_clock_voltage_on_ac.vddci; 811 812 return 0; 813 } 814 815 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 816 { 817 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 818 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 819 820 kfree(hwmgr->backend); 821 hwmgr->backend = NULL; 822 823 return 0; 824 } 825 826 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 827 { 828 int result = 0; 829 struct vega10_hwmgr *data; 830 uint32_t config_telemetry = 0; 831 struct pp_atomfwctrl_voltage_table vol_table; 832 struct amdgpu_device *adev = hwmgr->adev; 833 834 data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); 835 if (data == NULL) 836 return -ENOMEM; 837 838 hwmgr->backend = data; 839 840 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; 841 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 842 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; 843 844 vega10_set_default_registry_data(hwmgr); 845 data->disable_dpm_mask = 0xff; 846 847 /* need to set voltage control types before EVV patching */ 848 data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE; 849 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE; 850 data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE; 851 852 /* VDDCR_SOC */ 853 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 854 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) { 855 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 856 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2, 857 &vol_table)) { 858 config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) | 859 (vol_table.telemetry_offset & 0xff); 860 data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 861 } 862 } else { 863 kfree(hwmgr->backend); 864 hwmgr->backend = NULL; 865 PP_ASSERT_WITH_CODE(false, 866 "VDDCR_SOC is not SVID2!", 867 return -1); 868 } 869 870 /* MVDDC */ 871 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 872 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) { 873 if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr, 874 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2, 875 &vol_table)) { 876 config_telemetry |= 877 ((vol_table.telemetry_slope << 24) & 0xff000000) | 878 ((vol_table.telemetry_offset << 16) & 0xff0000); 879 data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2; 880 } 881 } 882 883 /* VDDCI_MEM */ 884 if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) { 885 if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr, 886 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 887 data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO; 888 } 889 890 data->config_telemetry = config_telemetry; 891 892 vega10_set_features_platform_caps(hwmgr); 893 894 result = vega10_init_dpm_defaults(hwmgr); 895 if (result) 896 return result; 897 898 #ifdef PPLIB_VEGA10_EVV_SUPPORT 899 /* Get leakage voltage based on leakage ID. */ 900 PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr), 901 "Get EVV Voltage Failed. Abort Driver loading!", 902 return -1); 903 #endif 904 905 /* Patch our voltage dependency table with actual leakage voltage 906 * We need to perform leakage translation before it's used by other functions 907 */ 908 vega10_complete_dependency_tables(hwmgr); 909 910 /* Parse pptable data read from VBIOS */ 911 vega10_set_private_data_based_on_pptable(hwmgr); 912 913 data->is_tlu_enabled = false; 914 915 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 916 VEGA10_MAX_HARDWARE_POWERLEVELS; 917 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 918 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 919 920 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 921 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 922 hwmgr->platform_descriptor.clockStep.engineClock = 500; 923 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 924 925 data->total_active_cus = adev->gfx.cu_info.number; 926 if (!hwmgr->not_vf) 927 return result; 928 929 /* Setup default Overdrive Fan control settings */ 930 data->odn_fan_table.target_fan_speed = 931 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM; 932 data->odn_fan_table.target_temperature = 933 hwmgr->thermal_controller. 934 advanceFanControlParameters.ucTargetTemperature; 935 data->odn_fan_table.min_performance_clock = 936 hwmgr->thermal_controller.advanceFanControlParameters. 937 ulMinFanSCLKAcousticLimit; 938 data->odn_fan_table.min_fan_limit = 939 hwmgr->thermal_controller. 940 advanceFanControlParameters.usFanPWMMinLimit * 941 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; 942 943 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & 944 DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> 945 DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 946 PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), 947 "Mem Channel Index Exceeded maximum!", 948 return -EINVAL); 949 950 return result; 951 } 952 953 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr) 954 { 955 struct vega10_hwmgr *data = hwmgr->backend; 956 957 data->low_sclk_interrupt_threshold = 0; 958 959 return 0; 960 } 961 962 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr) 963 { 964 struct vega10_hwmgr *data = hwmgr->backend; 965 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 966 967 struct pp_atomfwctrl_voltage_table table; 968 uint8_t i, j; 969 uint32_t mask = 0; 970 uint32_t tmp; 971 int32_t ret = 0; 972 973 ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM, 974 VOLTAGE_OBJ_GPIO_LUT, &table); 975 976 if (!ret) { 977 tmp = table.mask_low; 978 for (i = 0, j = 0; i < 32; i++) { 979 if (tmp & 1) { 980 mask |= (uint32_t)(i << (8 * j)); 981 if (++j >= 3) 982 break; 983 } 984 tmp >>= 1; 985 } 986 } 987 988 pp_table->LedPin0 = (uint8_t)(mask & 0xff); 989 pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff); 990 pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff); 991 return 0; 992 } 993 994 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr) 995 { 996 if (!hwmgr->not_vf) 997 return 0; 998 999 PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr), 1000 "Failed to init sclk threshold!", 1001 return -EINVAL); 1002 1003 PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr), 1004 "Failed to set up led dpm config!", 1005 return -EINVAL); 1006 1007 smum_send_msg_to_smc_with_parameter(hwmgr, 1008 PPSMC_MSG_NumOfDisplays, 1009 0, 1010 NULL); 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values. 1017 * 1018 * @hwmgr: the address of the powerplay hardware manager. 1019 * @vol_table: the pointer to changing voltage table 1020 * return: 0 in success 1021 */ 1022 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr, 1023 struct pp_atomfwctrl_voltage_table *vol_table) 1024 { 1025 uint32_t i, j; 1026 uint16_t vvalue; 1027 bool found = false; 1028 struct pp_atomfwctrl_voltage_table *table; 1029 1030 PP_ASSERT_WITH_CODE(vol_table, 1031 "Voltage Table empty.", return -EINVAL); 1032 table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table), 1033 GFP_KERNEL); 1034 1035 if (!table) 1036 return -ENOMEM; 1037 1038 table->mask_low = vol_table->mask_low; 1039 table->phase_delay = vol_table->phase_delay; 1040 1041 for (i = 0; i < vol_table->count; i++) { 1042 vvalue = vol_table->entries[i].value; 1043 found = false; 1044 1045 for (j = 0; j < table->count; j++) { 1046 if (vvalue == table->entries[j].value) { 1047 found = true; 1048 break; 1049 } 1050 } 1051 1052 if (!found) { 1053 table->entries[table->count].value = vvalue; 1054 table->entries[table->count].smio_low = 1055 vol_table->entries[i].smio_low; 1056 table->count++; 1057 } 1058 } 1059 1060 memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table)); 1061 kfree(table); 1062 1063 return 0; 1064 } 1065 1066 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr, 1067 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1068 struct pp_atomfwctrl_voltage_table *vol_table) 1069 { 1070 int i; 1071 1072 PP_ASSERT_WITH_CODE(dep_table->count, 1073 "Voltage Dependency Table empty.", 1074 return -EINVAL); 1075 1076 vol_table->mask_low = 0; 1077 vol_table->phase_delay = 0; 1078 vol_table->count = dep_table->count; 1079 1080 for (i = 0; i < vol_table->count; i++) { 1081 vol_table->entries[i].value = dep_table->entries[i].mvdd; 1082 vol_table->entries[i].smio_low = 0; 1083 } 1084 1085 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, 1086 vol_table), 1087 "Failed to trim MVDD Table!", 1088 return -1); 1089 1090 return 0; 1091 } 1092 1093 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr, 1094 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1095 struct pp_atomfwctrl_voltage_table *vol_table) 1096 { 1097 uint32_t i; 1098 1099 PP_ASSERT_WITH_CODE(dep_table->count, 1100 "Voltage Dependency Table empty.", 1101 return -EINVAL); 1102 1103 vol_table->mask_low = 0; 1104 vol_table->phase_delay = 0; 1105 vol_table->count = dep_table->count; 1106 1107 for (i = 0; i < dep_table->count; i++) { 1108 vol_table->entries[i].value = dep_table->entries[i].vddci; 1109 vol_table->entries[i].smio_low = 0; 1110 } 1111 1112 PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table), 1113 "Failed to trim VDDCI table.", 1114 return -1); 1115 1116 return 0; 1117 } 1118 1119 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr, 1120 phm_ppt_v1_clock_voltage_dependency_table *dep_table, 1121 struct pp_atomfwctrl_voltage_table *vol_table) 1122 { 1123 int i; 1124 1125 PP_ASSERT_WITH_CODE(dep_table->count, 1126 "Voltage Dependency Table empty.", 1127 return -EINVAL); 1128 1129 vol_table->mask_low = 0; 1130 vol_table->phase_delay = 0; 1131 vol_table->count = dep_table->count; 1132 1133 for (i = 0; i < vol_table->count; i++) { 1134 vol_table->entries[i].value = dep_table->entries[i].vddc; 1135 vol_table->entries[i].smio_low = 0; 1136 } 1137 1138 return 0; 1139 } 1140 1141 /* ---- Voltage Tables ---- 1142 * If the voltage table would be bigger than 1143 * what will fit into the state table on 1144 * the SMC keep only the higher entries. 1145 */ 1146 static void vega10_trim_voltage_table_to_fit_state_table( 1147 struct pp_hwmgr *hwmgr, 1148 uint32_t max_vol_steps, 1149 struct pp_atomfwctrl_voltage_table *vol_table) 1150 { 1151 unsigned int i, diff; 1152 1153 if (vol_table->count <= max_vol_steps) 1154 return; 1155 1156 diff = vol_table->count - max_vol_steps; 1157 1158 for (i = 0; i < max_vol_steps; i++) 1159 vol_table->entries[i] = vol_table->entries[i + diff]; 1160 1161 vol_table->count = max_vol_steps; 1162 } 1163 1164 /** 1165 * vega10_construct_voltage_tables - Create Voltage Tables. 1166 * 1167 * @hwmgr: the address of the powerplay hardware manager. 1168 * return: always 0 1169 */ 1170 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr) 1171 { 1172 struct vega10_hwmgr *data = hwmgr->backend; 1173 struct phm_ppt_v2_information *table_info = 1174 (struct phm_ppt_v2_information *)hwmgr->pptable; 1175 int result; 1176 1177 if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1178 data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1179 result = vega10_get_mvdd_voltage_table(hwmgr, 1180 table_info->vdd_dep_on_mclk, 1181 &(data->mvdd_voltage_table)); 1182 PP_ASSERT_WITH_CODE(!result, 1183 "Failed to retrieve MVDDC table!", 1184 return result); 1185 } 1186 1187 if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1188 result = vega10_get_vddci_voltage_table(hwmgr, 1189 table_info->vdd_dep_on_mclk, 1190 &(data->vddci_voltage_table)); 1191 PP_ASSERT_WITH_CODE(!result, 1192 "Failed to retrieve VDDCI_MEM table!", 1193 return result); 1194 } 1195 1196 if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 || 1197 data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) { 1198 result = vega10_get_vdd_voltage_table(hwmgr, 1199 table_info->vdd_dep_on_sclk, 1200 &(data->vddc_voltage_table)); 1201 PP_ASSERT_WITH_CODE(!result, 1202 "Failed to retrieve VDDCR_SOC table!", 1203 return result); 1204 } 1205 1206 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16, 1207 "Too many voltage values for VDDC. Trimming to fit state table.", 1208 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1209 16, &(data->vddc_voltage_table))); 1210 1211 PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16, 1212 "Too many voltage values for VDDCI. Trimming to fit state table.", 1213 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1214 16, &(data->vddci_voltage_table))); 1215 1216 PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16, 1217 "Too many voltage values for MVDD. Trimming to fit state table.", 1218 vega10_trim_voltage_table_to_fit_state_table(hwmgr, 1219 16, &(data->mvdd_voltage_table))); 1220 1221 1222 return 0; 1223 } 1224 1225 /* 1226 * vega10_init_dpm_state 1227 * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. 1228 * 1229 * @dpm_state: - the address of the DPM Table to initiailize. 1230 * return: None. 1231 */ 1232 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state) 1233 { 1234 dpm_state->soft_min_level = 0xff; 1235 dpm_state->soft_max_level = 0xff; 1236 dpm_state->hard_min_level = 0xff; 1237 dpm_state->hard_max_level = 0xff; 1238 } 1239 1240 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr, 1241 struct vega10_single_dpm_table *dpm_table, 1242 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table) 1243 { 1244 int i; 1245 1246 dpm_table->count = 0; 1247 1248 for (i = 0; i < dep_table->count; i++) { 1249 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= 1250 dep_table->entries[i].clk) { 1251 dpm_table->dpm_levels[dpm_table->count].value = 1252 dep_table->entries[i].clk; 1253 dpm_table->dpm_levels[dpm_table->count].enabled = true; 1254 dpm_table->count++; 1255 } 1256 } 1257 } 1258 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 1259 { 1260 struct vega10_hwmgr *data = hwmgr->backend; 1261 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); 1262 struct phm_ppt_v2_information *table_info = 1263 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1264 struct phm_ppt_v1_pcie_table *bios_pcie_table = 1265 table_info->pcie_table; 1266 uint32_t i; 1267 1268 PP_ASSERT_WITH_CODE(bios_pcie_table->count, 1269 "Incorrect number of PCIE States from VBIOS!", 1270 return -1); 1271 1272 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1273 if (data->registry_data.pcieSpeedOverride) 1274 pcie_table->pcie_gen[i] = 1275 data->registry_data.pcieSpeedOverride; 1276 else 1277 pcie_table->pcie_gen[i] = 1278 bios_pcie_table->entries[i].gen_speed; 1279 1280 if (data->registry_data.pcieLaneOverride) 1281 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1282 data->registry_data.pcieLaneOverride); 1283 else 1284 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( 1285 bios_pcie_table->entries[i].lane_width); 1286 if (data->registry_data.pcieClockOverride) 1287 pcie_table->lclk[i] = 1288 data->registry_data.pcieClockOverride; 1289 else 1290 pcie_table->lclk[i] = 1291 bios_pcie_table->entries[i].pcie_sclk; 1292 } 1293 1294 pcie_table->count = NUM_LINK_LEVELS; 1295 1296 return 0; 1297 } 1298 1299 /* 1300 * This function is to initialize all DPM state tables 1301 * for SMU based on the dependency table. 1302 * Dynamic state patching function will then trim these 1303 * state tables to the allowed range based 1304 * on the power policy or external client requests, 1305 * such as UVD request, etc. 1306 */ 1307 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1308 { 1309 struct vega10_hwmgr *data = hwmgr->backend; 1310 struct phm_ppt_v2_information *table_info = 1311 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1312 struct vega10_single_dpm_table *dpm_table; 1313 uint32_t i; 1314 1315 struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table = 1316 table_info->vdd_dep_on_socclk; 1317 struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table = 1318 table_info->vdd_dep_on_sclk; 1319 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 1320 table_info->vdd_dep_on_mclk; 1321 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table = 1322 table_info->mm_dep_table; 1323 struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table = 1324 table_info->vdd_dep_on_dcefclk; 1325 struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table = 1326 table_info->vdd_dep_on_pixclk; 1327 struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table = 1328 table_info->vdd_dep_on_dispclk; 1329 struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table = 1330 table_info->vdd_dep_on_phyclk; 1331 1332 PP_ASSERT_WITH_CODE(dep_soc_table, 1333 "SOCCLK dependency table is missing. This table is mandatory", 1334 return -EINVAL); 1335 PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1, 1336 "SOCCLK dependency table is empty. This table is mandatory", 1337 return -EINVAL); 1338 1339 PP_ASSERT_WITH_CODE(dep_gfx_table, 1340 "GFXCLK dependency table is missing. This table is mandatory", 1341 return -EINVAL); 1342 PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1, 1343 "GFXCLK dependency table is empty. This table is mandatory", 1344 return -EINVAL); 1345 1346 PP_ASSERT_WITH_CODE(dep_mclk_table, 1347 "MCLK dependency table is missing. This table is mandatory", 1348 return -EINVAL); 1349 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 1350 "MCLK dependency table has to have is missing. This table is mandatory", 1351 return -EINVAL); 1352 1353 /* Initialize Sclk DPM table based on allow Sclk values */ 1354 dpm_table = &(data->dpm_table.soc_table); 1355 vega10_setup_default_single_dpm_table(hwmgr, 1356 dpm_table, 1357 dep_soc_table); 1358 1359 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1360 1361 dpm_table = &(data->dpm_table.gfx_table); 1362 vega10_setup_default_single_dpm_table(hwmgr, 1363 dpm_table, 1364 dep_gfx_table); 1365 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 1366 hwmgr->platform_descriptor.overdriveLimit.engineClock = 1367 dpm_table->dpm_levels[dpm_table->count-1].value; 1368 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1369 1370 /* Initialize Mclk DPM table based on allow Mclk values */ 1371 data->dpm_table.mem_table.count = 0; 1372 dpm_table = &(data->dpm_table.mem_table); 1373 vega10_setup_default_single_dpm_table(hwmgr, 1374 dpm_table, 1375 dep_mclk_table); 1376 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 1377 hwmgr->platform_descriptor.overdriveLimit.memoryClock = 1378 dpm_table->dpm_levels[dpm_table->count-1].value; 1379 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1380 1381 data->dpm_table.eclk_table.count = 0; 1382 dpm_table = &(data->dpm_table.eclk_table); 1383 for (i = 0; i < dep_mm_table->count; i++) { 1384 if (i == 0 || dpm_table->dpm_levels 1385 [dpm_table->count - 1].value <= 1386 dep_mm_table->entries[i].eclk) { 1387 dpm_table->dpm_levels[dpm_table->count].value = 1388 dep_mm_table->entries[i].eclk; 1389 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1390 dpm_table->count++; 1391 } 1392 } 1393 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1394 1395 data->dpm_table.vclk_table.count = 0; 1396 data->dpm_table.dclk_table.count = 0; 1397 dpm_table = &(data->dpm_table.vclk_table); 1398 for (i = 0; i < dep_mm_table->count; i++) { 1399 if (i == 0 || dpm_table->dpm_levels 1400 [dpm_table->count - 1].value <= 1401 dep_mm_table->entries[i].vclk) { 1402 dpm_table->dpm_levels[dpm_table->count].value = 1403 dep_mm_table->entries[i].vclk; 1404 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1405 dpm_table->count++; 1406 } 1407 } 1408 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1409 1410 dpm_table = &(data->dpm_table.dclk_table); 1411 for (i = 0; i < dep_mm_table->count; i++) { 1412 if (i == 0 || dpm_table->dpm_levels 1413 [dpm_table->count - 1].value <= 1414 dep_mm_table->entries[i].dclk) { 1415 dpm_table->dpm_levels[dpm_table->count].value = 1416 dep_mm_table->entries[i].dclk; 1417 dpm_table->dpm_levels[dpm_table->count].enabled = i == 0; 1418 dpm_table->count++; 1419 } 1420 } 1421 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1422 1423 /* Assume there is no headless Vega10 for now */ 1424 dpm_table = &(data->dpm_table.dcef_table); 1425 vega10_setup_default_single_dpm_table(hwmgr, 1426 dpm_table, 1427 dep_dcef_table); 1428 1429 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1430 1431 dpm_table = &(data->dpm_table.pixel_table); 1432 vega10_setup_default_single_dpm_table(hwmgr, 1433 dpm_table, 1434 dep_pix_table); 1435 1436 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1437 1438 dpm_table = &(data->dpm_table.display_table); 1439 vega10_setup_default_single_dpm_table(hwmgr, 1440 dpm_table, 1441 dep_disp_table); 1442 1443 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1444 1445 dpm_table = &(data->dpm_table.phy_table); 1446 vega10_setup_default_single_dpm_table(hwmgr, 1447 dpm_table, 1448 dep_phy_table); 1449 1450 vega10_init_dpm_state(&(dpm_table->dpm_state)); 1451 1452 vega10_setup_default_pcie_table(hwmgr); 1453 1454 /* Zero out the saved copy of the CUSTOM profile 1455 * This will be checked when trying to set the profile 1456 * and will require that new values be passed in 1457 */ 1458 data->custom_profile_mode[0] = 0; 1459 data->custom_profile_mode[1] = 0; 1460 data->custom_profile_mode[2] = 0; 1461 data->custom_profile_mode[3] = 0; 1462 1463 /* save a copy of the default DPM table */ 1464 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1465 sizeof(struct vega10_dpm_table)); 1466 1467 return 0; 1468 } 1469 1470 /* 1471 * vega10_populate_ulv_state 1472 * Function to provide parameters for Utral Low Voltage state to SMC. 1473 * 1474 * @hwmgr: - the address of the hardware manager. 1475 * return: Always 0. 1476 */ 1477 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr) 1478 { 1479 struct vega10_hwmgr *data = hwmgr->backend; 1480 struct phm_ppt_v2_information *table_info = 1481 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1482 1483 data->smc_state_table.pp_table.UlvOffsetVid = 1484 (uint8_t)table_info->us_ulv_voltage_offset; 1485 1486 data->smc_state_table.pp_table.UlvSmnclkDid = 1487 (uint8_t)(table_info->us_ulv_smnclk_did); 1488 data->smc_state_table.pp_table.UlvMp1clkDid = 1489 (uint8_t)(table_info->us_ulv_mp1clk_did); 1490 data->smc_state_table.pp_table.UlvGfxclkBypass = 1491 (uint8_t)(table_info->us_ulv_gfxclk_bypass); 1492 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = 1493 (uint8_t)(data->vddc_voltage_table.psi0_enable); 1494 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = 1495 (uint8_t)(data->vddc_voltage_table.psi1_enable); 1496 1497 return 0; 1498 } 1499 1500 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr, 1501 uint32_t lclock, uint8_t *curr_lclk_did) 1502 { 1503 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1504 1505 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1506 hwmgr, 1507 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1508 lclock, ÷rs), 1509 "Failed to get LCLK clock settings from VBIOS!", 1510 return -1); 1511 1512 *curr_lclk_did = dividers.ulDid; 1513 1514 return 0; 1515 } 1516 1517 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr) 1518 { 1519 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 1520 struct vega10_hwmgr *data = 1521 (struct vega10_hwmgr *)(hwmgr->backend); 1522 uint32_t pcie_gen = 0, pcie_width = 0; 1523 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1524 int i; 1525 1526 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4) 1527 pcie_gen = 3; 1528 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1529 pcie_gen = 2; 1530 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1531 pcie_gen = 1; 1532 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1) 1533 pcie_gen = 0; 1534 1535 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 1536 pcie_width = 6; 1537 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 1538 pcie_width = 5; 1539 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 1540 pcie_width = 4; 1541 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 1542 pcie_width = 3; 1543 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 1544 pcie_width = 2; 1545 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 1546 pcie_width = 1; 1547 1548 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1549 if (pp_table->PcieGenSpeed[i] > pcie_gen) 1550 pp_table->PcieGenSpeed[i] = pcie_gen; 1551 1552 if (pp_table->PcieLaneCount[i] > pcie_width) 1553 pp_table->PcieLaneCount[i] = pcie_width; 1554 } 1555 1556 if (data->registry_data.pcie_dpm_key_disabled) { 1557 for (i = 0; i < NUM_LINK_LEVELS; i++) { 1558 pp_table->PcieGenSpeed[i] = pcie_gen; 1559 pp_table->PcieLaneCount[i] = pcie_width; 1560 } 1561 } 1562 1563 return 0; 1564 } 1565 1566 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) 1567 { 1568 int result = -1; 1569 struct vega10_hwmgr *data = hwmgr->backend; 1570 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1571 struct vega10_pcie_table *pcie_table = 1572 &(data->dpm_table.pcie_table); 1573 uint32_t i, j; 1574 1575 for (i = 0; i < pcie_table->count; i++) { 1576 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i]; 1577 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; 1578 1579 result = vega10_populate_single_lclk_level(hwmgr, 1580 pcie_table->lclk[i], &(pp_table->LclkDid[i])); 1581 if (result) { 1582 pr_info("Populate LClock Level %d Failed!\n", i); 1583 return result; 1584 } 1585 } 1586 1587 j = i - 1; 1588 while (i < NUM_LINK_LEVELS) { 1589 pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j]; 1590 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; 1591 1592 result = vega10_populate_single_lclk_level(hwmgr, 1593 pcie_table->lclk[j], &(pp_table->LclkDid[i])); 1594 if (result) { 1595 pr_info("Populate LClock Level %d Failed!\n", i); 1596 return result; 1597 } 1598 i++; 1599 } 1600 1601 return result; 1602 } 1603 1604 /** 1605 * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure 1606 * using the provided engine clock 1607 * 1608 * @hwmgr: the address of the hardware manager 1609 * @gfx_clock: the GFX clock to use to populate the structure. 1610 * @current_gfxclk_level: location in PPTable for the SMC GFXCLK structure. 1611 * @acg_freq: ACG frequenty to return (MHz) 1612 */ 1613 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, 1614 uint32_t gfx_clock, PllSetting_t *current_gfxclk_level, 1615 uint32_t *acg_freq) 1616 { 1617 struct phm_ppt_v2_information *table_info = 1618 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1619 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk; 1620 struct vega10_hwmgr *data = hwmgr->backend; 1621 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1622 uint32_t gfx_max_clock = 1623 hwmgr->platform_descriptor.overdriveLimit.engineClock; 1624 uint32_t i = 0; 1625 1626 if (hwmgr->od_enabled) 1627 dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1628 &(data->odn_dpm_table.vdd_dep_on_sclk); 1629 else 1630 dep_on_sclk = table_info->vdd_dep_on_sclk; 1631 1632 PP_ASSERT_WITH_CODE(dep_on_sclk, 1633 "Invalid SOC_VDD-GFX_CLK Dependency Table!", 1634 return -EINVAL); 1635 1636 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) 1637 gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock; 1638 else { 1639 for (i = 0; i < dep_on_sclk->count; i++) { 1640 if (dep_on_sclk->entries[i].clk == gfx_clock) 1641 break; 1642 } 1643 PP_ASSERT_WITH_CODE(dep_on_sclk->count > i, 1644 "Cannot find gfx_clk in SOC_VDD-GFX_CLK!", 1645 return -EINVAL); 1646 } 1647 1648 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1649 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK, 1650 gfx_clock, ÷rs), 1651 "Failed to get GFX Clock settings from VBIOS!", 1652 return -EINVAL); 1653 1654 /* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */ 1655 current_gfxclk_level->FbMult = 1656 cpu_to_le32(dividers.ulPll_fb_mult); 1657 /* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */ 1658 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; 1659 current_gfxclk_level->SsFbMult = 1660 cpu_to_le32(dividers.ulPll_ss_fbsmult); 1661 current_gfxclk_level->SsSlewFrac = 1662 cpu_to_le16(dividers.usPll_ss_slew_frac); 1663 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); 1664 1665 *acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */ 1666 1667 return 0; 1668 } 1669 1670 /** 1671 * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure 1672 * using the provided clock. 1673 * 1674 * @hwmgr: the address of the hardware manager. 1675 * @soc_clock: the SOC clock to use to populate the structure. 1676 * @current_soc_did: DFS divider to pass back to caller 1677 * @current_vol_index: index of current VDD to pass back to caller 1678 * return: 0 on success 1679 */ 1680 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr, 1681 uint32_t soc_clock, uint8_t *current_soc_did, 1682 uint8_t *current_vol_index) 1683 { 1684 struct vega10_hwmgr *data = hwmgr->backend; 1685 struct phm_ppt_v2_information *table_info = 1686 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1687 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc; 1688 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1689 uint32_t i; 1690 1691 if (hwmgr->od_enabled) { 1692 dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1693 &data->odn_dpm_table.vdd_dep_on_socclk; 1694 for (i = 0; i < dep_on_soc->count; i++) { 1695 if (dep_on_soc->entries[i].clk >= soc_clock) 1696 break; 1697 } 1698 } else { 1699 dep_on_soc = table_info->vdd_dep_on_socclk; 1700 for (i = 0; i < dep_on_soc->count; i++) { 1701 if (dep_on_soc->entries[i].clk == soc_clock) 1702 break; 1703 } 1704 } 1705 1706 PP_ASSERT_WITH_CODE(dep_on_soc->count > i, 1707 "Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table", 1708 return -EINVAL); 1709 1710 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 1711 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1712 soc_clock, ÷rs), 1713 "Failed to get SOC Clock settings from VBIOS!", 1714 return -EINVAL); 1715 1716 *current_soc_did = (uint8_t)dividers.ulDid; 1717 *current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd); 1718 return 0; 1719 } 1720 1721 /** 1722 * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure 1723 * based on the trimmed allowed dpm engine clock states 1724 * 1725 * @hwmgr: the address of the hardware manager 1726 */ 1727 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 1728 { 1729 struct vega10_hwmgr *data = hwmgr->backend; 1730 struct phm_ppt_v2_information *table_info = 1731 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1732 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1733 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); 1734 int result = 0; 1735 uint32_t i, j; 1736 1737 for (i = 0; i < dpm_table->count; i++) { 1738 result = vega10_populate_single_gfx_level(hwmgr, 1739 dpm_table->dpm_levels[i].value, 1740 &(pp_table->GfxclkLevel[i]), 1741 &(pp_table->AcgFreqTable[i])); 1742 if (result) 1743 return result; 1744 } 1745 1746 j = i - 1; 1747 while (i < NUM_GFXCLK_DPM_LEVELS) { 1748 result = vega10_populate_single_gfx_level(hwmgr, 1749 dpm_table->dpm_levels[j].value, 1750 &(pp_table->GfxclkLevel[i]), 1751 &(pp_table->AcgFreqTable[i])); 1752 if (result) 1753 return result; 1754 i++; 1755 } 1756 1757 pp_table->GfxclkSlewRate = 1758 cpu_to_le16(table_info->us_gfxclk_slew_rate); 1759 1760 dpm_table = &(data->dpm_table.soc_table); 1761 for (i = 0; i < dpm_table->count; i++) { 1762 result = vega10_populate_single_soc_level(hwmgr, 1763 dpm_table->dpm_levels[i].value, 1764 &(pp_table->SocclkDid[i]), 1765 &(pp_table->SocDpmVoltageIndex[i])); 1766 if (result) 1767 return result; 1768 } 1769 1770 j = i - 1; 1771 while (i < NUM_SOCCLK_DPM_LEVELS) { 1772 result = vega10_populate_single_soc_level(hwmgr, 1773 dpm_table->dpm_levels[j].value, 1774 &(pp_table->SocclkDid[i]), 1775 &(pp_table->SocDpmVoltageIndex[i])); 1776 if (result) 1777 return result; 1778 i++; 1779 } 1780 1781 return result; 1782 } 1783 1784 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr) 1785 { 1786 struct vega10_hwmgr *data = hwmgr->backend; 1787 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1788 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 1789 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 1790 1791 uint8_t soc_vid = 0; 1792 uint32_t i, max_vddc_level; 1793 1794 if (hwmgr->od_enabled) 1795 vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table; 1796 else 1797 vddc_lookup_table = table_info->vddc_lookup_table; 1798 1799 max_vddc_level = vddc_lookup_table->count; 1800 for (i = 0; i < max_vddc_level; i++) { 1801 soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd); 1802 pp_table->SocVid[i] = soc_vid; 1803 } 1804 while (i < MAX_REGULAR_DPM_NUMBER) { 1805 pp_table->SocVid[i] = soc_vid; 1806 i++; 1807 } 1808 } 1809 1810 /* 1811 * Populates single SMC GFXCLK structure using the provided clock. 1812 * 1813 * @hwmgr: the address of the hardware manager. 1814 * @mem_clock: the memory clock to use to populate the structure. 1815 * return: 0 on success.. 1816 */ 1817 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr, 1818 uint32_t mem_clock, uint8_t *current_mem_vid, 1819 PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind) 1820 { 1821 struct vega10_hwmgr *data = hwmgr->backend; 1822 struct phm_ppt_v2_information *table_info = 1823 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1824 struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk; 1825 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1826 uint32_t mem_max_clock = 1827 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 1828 uint32_t i = 0; 1829 1830 if (hwmgr->od_enabled) 1831 dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *) 1832 &data->odn_dpm_table.vdd_dep_on_mclk; 1833 else 1834 dep_on_mclk = table_info->vdd_dep_on_mclk; 1835 1836 PP_ASSERT_WITH_CODE(dep_on_mclk, 1837 "Invalid SOC_VDD-UCLK Dependency Table!", 1838 return -EINVAL); 1839 1840 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 1841 mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock; 1842 } else { 1843 for (i = 0; i < dep_on_mclk->count; i++) { 1844 if (dep_on_mclk->entries[i].clk == mem_clock) 1845 break; 1846 } 1847 PP_ASSERT_WITH_CODE(dep_on_mclk->count > i, 1848 "Cannot find UCLK in SOC_VDD-UCLK Dependency Table!", 1849 return -EINVAL); 1850 } 1851 1852 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10( 1853 hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, ÷rs), 1854 "Failed to get UCLK settings from VBIOS!", 1855 return -1); 1856 1857 *current_mem_vid = 1858 (uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd)); 1859 *current_mem_soc_vind = 1860 (uint8_t)(dep_on_mclk->entries[i].vddInd); 1861 current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult); 1862 current_memclk_level->Did = (uint8_t)(dividers.ulDid); 1863 1864 PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1, 1865 "Invalid Divider ID!", 1866 return -EINVAL); 1867 1868 return 0; 1869 } 1870 1871 /** 1872 * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure 1873 * based on the trimmed allowed dpm memory clock states. 1874 * 1875 * @hwmgr: the address of the hardware manager. 1876 * return: PP_Result_OK on success. 1877 */ 1878 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1879 { 1880 struct vega10_hwmgr *data = hwmgr->backend; 1881 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1882 struct vega10_single_dpm_table *dpm_table = 1883 &(data->dpm_table.mem_table); 1884 int result = 0; 1885 uint32_t i, j; 1886 1887 for (i = 0; i < dpm_table->count; i++) { 1888 result = vega10_populate_single_memory_level(hwmgr, 1889 dpm_table->dpm_levels[i].value, 1890 &(pp_table->MemVid[i]), 1891 &(pp_table->UclkLevel[i]), 1892 &(pp_table->MemSocVoltageIndex[i])); 1893 if (result) 1894 return result; 1895 } 1896 1897 j = i - 1; 1898 while (i < NUM_UCLK_DPM_LEVELS) { 1899 result = vega10_populate_single_memory_level(hwmgr, 1900 dpm_table->dpm_levels[j].value, 1901 &(pp_table->MemVid[i]), 1902 &(pp_table->UclkLevel[i]), 1903 &(pp_table->MemSocVoltageIndex[i])); 1904 if (result) 1905 return result; 1906 i++; 1907 } 1908 1909 pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); 1910 pp_table->MemoryChannelWidth = 1911 (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * 1912 channel_number[data->mem_channels]); 1913 1914 pp_table->LowestUclkReservedForUlv = 1915 (uint8_t)(data->lowest_uclk_reserved_for_ulv); 1916 1917 return result; 1918 } 1919 1920 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr, 1921 DSPCLK_e disp_clock) 1922 { 1923 struct vega10_hwmgr *data = hwmgr->backend; 1924 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 1925 struct phm_ppt_v2_information *table_info = 1926 (struct phm_ppt_v2_information *) 1927 (hwmgr->pptable); 1928 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1929 uint32_t i; 1930 uint16_t clk = 0, vddc = 0; 1931 uint8_t vid = 0; 1932 1933 switch (disp_clock) { 1934 case DSPCLK_DCEFCLK: 1935 dep_table = table_info->vdd_dep_on_dcefclk; 1936 break; 1937 case DSPCLK_DISPCLK: 1938 dep_table = table_info->vdd_dep_on_dispclk; 1939 break; 1940 case DSPCLK_PIXCLK: 1941 dep_table = table_info->vdd_dep_on_pixclk; 1942 break; 1943 case DSPCLK_PHYCLK: 1944 dep_table = table_info->vdd_dep_on_phyclk; 1945 break; 1946 default: 1947 return -1; 1948 } 1949 1950 PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS, 1951 "Number Of Entries Exceeded maximum!", 1952 return -1); 1953 1954 for (i = 0; i < dep_table->count; i++) { 1955 clk = (uint16_t)(dep_table->entries[i].clk / 100); 1956 vddc = table_info->vddc_lookup_table-> 1957 entries[dep_table->entries[i].vddInd].us_vdd; 1958 vid = (uint8_t)convert_to_vid(vddc); 1959 pp_table->DisplayClockTable[disp_clock][i].Freq = 1960 cpu_to_le16(clk); 1961 pp_table->DisplayClockTable[disp_clock][i].Vid = 1962 cpu_to_le16(vid); 1963 } 1964 1965 while (i < NUM_DSPCLK_LEVELS) { 1966 pp_table->DisplayClockTable[disp_clock][i].Freq = 1967 cpu_to_le16(clk); 1968 pp_table->DisplayClockTable[disp_clock][i].Vid = 1969 cpu_to_le16(vid); 1970 i++; 1971 } 1972 1973 return 0; 1974 } 1975 1976 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr) 1977 { 1978 uint32_t i; 1979 1980 for (i = 0; i < DSPCLK_COUNT; i++) { 1981 PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i), 1982 "Failed to populate Clock in DisplayClockTable!", 1983 return -1); 1984 } 1985 1986 return 0; 1987 } 1988 1989 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr, 1990 uint32_t eclock, uint8_t *current_eclk_did, 1991 uint8_t *current_soc_vol) 1992 { 1993 struct phm_ppt_v2_information *table_info = 1994 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1995 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 1996 table_info->mm_dep_table; 1997 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 1998 uint32_t i; 1999 2000 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2001 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2002 eclock, ÷rs), 2003 "Failed to get ECLK clock settings from VBIOS!", 2004 return -1); 2005 2006 *current_eclk_did = (uint8_t)dividers.ulDid; 2007 2008 for (i = 0; i < dep_table->count; i++) { 2009 if (dep_table->entries[i].eclk == eclock) 2010 *current_soc_vol = dep_table->entries[i].vddcInd; 2011 } 2012 2013 return 0; 2014 } 2015 2016 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr) 2017 { 2018 struct vega10_hwmgr *data = hwmgr->backend; 2019 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2020 struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table); 2021 int result = -EINVAL; 2022 uint32_t i, j; 2023 2024 for (i = 0; i < dpm_table->count; i++) { 2025 result = vega10_populate_single_eclock_level(hwmgr, 2026 dpm_table->dpm_levels[i].value, 2027 &(pp_table->EclkDid[i]), 2028 &(pp_table->VceDpmVoltageIndex[i])); 2029 if (result) 2030 return result; 2031 } 2032 2033 j = i - 1; 2034 while (i < NUM_VCE_DPM_LEVELS) { 2035 result = vega10_populate_single_eclock_level(hwmgr, 2036 dpm_table->dpm_levels[j].value, 2037 &(pp_table->EclkDid[i]), 2038 &(pp_table->VceDpmVoltageIndex[i])); 2039 if (result) 2040 return result; 2041 i++; 2042 } 2043 2044 return result; 2045 } 2046 2047 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr, 2048 uint32_t vclock, uint8_t *current_vclk_did) 2049 { 2050 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2051 2052 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2053 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2054 vclock, ÷rs), 2055 "Failed to get VCLK clock settings from VBIOS!", 2056 return -EINVAL); 2057 2058 *current_vclk_did = (uint8_t)dividers.ulDid; 2059 2060 return 0; 2061 } 2062 2063 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr, 2064 uint32_t dclock, uint8_t *current_dclk_did) 2065 { 2066 struct pp_atomfwctrl_clock_dividers_soc15 dividers; 2067 2068 PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr, 2069 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 2070 dclock, ÷rs), 2071 "Failed to get DCLK clock settings from VBIOS!", 2072 return -EINVAL); 2073 2074 *current_dclk_did = (uint8_t)dividers.ulDid; 2075 2076 return 0; 2077 } 2078 2079 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr) 2080 { 2081 struct vega10_hwmgr *data = hwmgr->backend; 2082 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2083 struct vega10_single_dpm_table *vclk_dpm_table = 2084 &(data->dpm_table.vclk_table); 2085 struct vega10_single_dpm_table *dclk_dpm_table = 2086 &(data->dpm_table.dclk_table); 2087 struct phm_ppt_v2_information *table_info = 2088 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2089 struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table = 2090 table_info->mm_dep_table; 2091 int result = -EINVAL; 2092 uint32_t i, j; 2093 2094 for (i = 0; i < vclk_dpm_table->count; i++) { 2095 result = vega10_populate_single_vclock_level(hwmgr, 2096 vclk_dpm_table->dpm_levels[i].value, 2097 &(pp_table->VclkDid[i])); 2098 if (result) 2099 return result; 2100 } 2101 2102 j = i - 1; 2103 while (i < NUM_UVD_DPM_LEVELS) { 2104 result = vega10_populate_single_vclock_level(hwmgr, 2105 vclk_dpm_table->dpm_levels[j].value, 2106 &(pp_table->VclkDid[i])); 2107 if (result) 2108 return result; 2109 i++; 2110 } 2111 2112 for (i = 0; i < dclk_dpm_table->count; i++) { 2113 result = vega10_populate_single_dclock_level(hwmgr, 2114 dclk_dpm_table->dpm_levels[i].value, 2115 &(pp_table->DclkDid[i])); 2116 if (result) 2117 return result; 2118 } 2119 2120 j = i - 1; 2121 while (i < NUM_UVD_DPM_LEVELS) { 2122 result = vega10_populate_single_dclock_level(hwmgr, 2123 dclk_dpm_table->dpm_levels[j].value, 2124 &(pp_table->DclkDid[i])); 2125 if (result) 2126 return result; 2127 i++; 2128 } 2129 2130 for (i = 0; i < dep_table->count; i++) { 2131 if (dep_table->entries[i].vclk == 2132 vclk_dpm_table->dpm_levels[i].value && 2133 dep_table->entries[i].dclk == 2134 dclk_dpm_table->dpm_levels[i].value) 2135 pp_table->UvdDpmVoltageIndex[i] = 2136 dep_table->entries[i].vddcInd; 2137 else 2138 return -1; 2139 } 2140 2141 j = i - 1; 2142 while (i < NUM_UVD_DPM_LEVELS) { 2143 pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd; 2144 i++; 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr) 2151 { 2152 struct vega10_hwmgr *data = hwmgr->backend; 2153 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2154 struct phm_ppt_v2_information *table_info = 2155 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2156 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2157 table_info->vdd_dep_on_sclk; 2158 uint32_t i; 2159 2160 for (i = 0; i < dep_table->count; i++) { 2161 pp_table->CksEnable[i] = dep_table->entries[i].cks_enable; 2162 pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset 2163 * VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr) 2170 { 2171 struct vega10_hwmgr *data = hwmgr->backend; 2172 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2173 struct phm_ppt_v2_information *table_info = 2174 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2175 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 2176 table_info->vdd_dep_on_sclk; 2177 struct pp_atomfwctrl_avfs_parameters avfs_params = {0}; 2178 int result = 0; 2179 uint32_t i; 2180 2181 pp_table->MinVoltageVid = (uint8_t)0xff; 2182 pp_table->MaxVoltageVid = (uint8_t)0; 2183 2184 if (data->smu_features[GNLD_AVFS].supported) { 2185 result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params); 2186 if (!result) { 2187 pp_table->MinVoltageVid = (uint8_t) 2188 convert_to_vid((uint16_t)(avfs_params.ulMinVddc)); 2189 pp_table->MaxVoltageVid = (uint8_t) 2190 convert_to_vid((uint16_t)(avfs_params.ulMaxVddc)); 2191 2192 pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0); 2193 pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1); 2194 pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2); 2195 pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2196 pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean); 2197 pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma); 2198 pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor); 2199 2200 pp_table->BtcGbVdroopTableCksOff.a0 = 2201 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0); 2202 pp_table->BtcGbVdroopTableCksOff.a0_shift = 20; 2203 pp_table->BtcGbVdroopTableCksOff.a1 = 2204 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1); 2205 pp_table->BtcGbVdroopTableCksOff.a1_shift = 20; 2206 pp_table->BtcGbVdroopTableCksOff.a2 = 2207 cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2); 2208 pp_table->BtcGbVdroopTableCksOff.a2_shift = 20; 2209 2210 pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson; 2211 pp_table->BtcGbVdroopTableCksOn.a0 = 2212 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0); 2213 pp_table->BtcGbVdroopTableCksOn.a0_shift = 20; 2214 pp_table->BtcGbVdroopTableCksOn.a1 = 2215 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1); 2216 pp_table->BtcGbVdroopTableCksOn.a1_shift = 20; 2217 pp_table->BtcGbVdroopTableCksOn.a2 = 2218 cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2); 2219 pp_table->BtcGbVdroopTableCksOn.a2_shift = 20; 2220 2221 pp_table->AvfsGbCksOn.m1 = 2222 cpu_to_le32(avfs_params.ulGbFuseTableCksonM1); 2223 pp_table->AvfsGbCksOn.m2 = 2224 cpu_to_le32(avfs_params.ulGbFuseTableCksonM2); 2225 pp_table->AvfsGbCksOn.b = 2226 cpu_to_le32(avfs_params.ulGbFuseTableCksonB); 2227 pp_table->AvfsGbCksOn.m1_shift = 24; 2228 pp_table->AvfsGbCksOn.m2_shift = 12; 2229 pp_table->AvfsGbCksOn.b_shift = 0; 2230 2231 pp_table->OverrideAvfsGbCksOn = 2232 avfs_params.ucEnableGbFuseTableCkson; 2233 pp_table->AvfsGbCksOff.m1 = 2234 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1); 2235 pp_table->AvfsGbCksOff.m2 = 2236 cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2); 2237 pp_table->AvfsGbCksOff.b = 2238 cpu_to_le32(avfs_params.ulGbFuseTableCksoffB); 2239 pp_table->AvfsGbCksOff.m1_shift = 24; 2240 pp_table->AvfsGbCksOff.m2_shift = 12; 2241 pp_table->AvfsGbCksOff.b_shift = 0; 2242 2243 for (i = 0; i < dep_table->count; i++) 2244 pp_table->StaticVoltageOffsetVid[i] = 2245 convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset)); 2246 2247 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2248 data->disp_clk_quad_eqn_a) && 2249 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2250 data->disp_clk_quad_eqn_b)) { 2251 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2252 (int32_t)data->disp_clk_quad_eqn_a; 2253 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2254 (int32_t)data->disp_clk_quad_eqn_b; 2255 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2256 (int32_t)data->disp_clk_quad_eqn_c; 2257 } else { 2258 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 = 2259 (int32_t)avfs_params.ulDispclk2GfxclkM1; 2260 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 = 2261 (int32_t)avfs_params.ulDispclk2GfxclkM2; 2262 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b = 2263 (int32_t)avfs_params.ulDispclk2GfxclkB; 2264 } 2265 2266 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24; 2267 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12; 2268 pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12; 2269 2270 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2271 data->dcef_clk_quad_eqn_a) && 2272 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2273 data->dcef_clk_quad_eqn_b)) { 2274 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2275 (int32_t)data->dcef_clk_quad_eqn_a; 2276 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2277 (int32_t)data->dcef_clk_quad_eqn_b; 2278 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2279 (int32_t)data->dcef_clk_quad_eqn_c; 2280 } else { 2281 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 = 2282 (int32_t)avfs_params.ulDcefclk2GfxclkM1; 2283 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 = 2284 (int32_t)avfs_params.ulDcefclk2GfxclkM2; 2285 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b = 2286 (int32_t)avfs_params.ulDcefclk2GfxclkB; 2287 } 2288 2289 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24; 2290 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12; 2291 pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12; 2292 2293 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2294 data->pixel_clk_quad_eqn_a) && 2295 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2296 data->pixel_clk_quad_eqn_b)) { 2297 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2298 (int32_t)data->pixel_clk_quad_eqn_a; 2299 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2300 (int32_t)data->pixel_clk_quad_eqn_b; 2301 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2302 (int32_t)data->pixel_clk_quad_eqn_c; 2303 } else { 2304 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 = 2305 (int32_t)avfs_params.ulPixelclk2GfxclkM1; 2306 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 = 2307 (int32_t)avfs_params.ulPixelclk2GfxclkM2; 2308 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b = 2309 (int32_t)avfs_params.ulPixelclk2GfxclkB; 2310 } 2311 2312 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24; 2313 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12; 2314 pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12; 2315 if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2316 data->phy_clk_quad_eqn_a) && 2317 (PPREGKEY_VEGA10QUADRATICEQUATION_DFLT != 2318 data->phy_clk_quad_eqn_b)) { 2319 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2320 (int32_t)data->phy_clk_quad_eqn_a; 2321 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2322 (int32_t)data->phy_clk_quad_eqn_b; 2323 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2324 (int32_t)data->phy_clk_quad_eqn_c; 2325 } else { 2326 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 = 2327 (int32_t)avfs_params.ulPhyclk2GfxclkM1; 2328 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 = 2329 (int32_t)avfs_params.ulPhyclk2GfxclkM2; 2330 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b = 2331 (int32_t)avfs_params.ulPhyclk2GfxclkB; 2332 } 2333 2334 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24; 2335 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12; 2336 pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12; 2337 2338 pp_table->AcgBtcGbVdroopTable.a0 = avfs_params.ulAcgGbVdroopTableA0; 2339 pp_table->AcgBtcGbVdroopTable.a0_shift = 20; 2340 pp_table->AcgBtcGbVdroopTable.a1 = avfs_params.ulAcgGbVdroopTableA1; 2341 pp_table->AcgBtcGbVdroopTable.a1_shift = 20; 2342 pp_table->AcgBtcGbVdroopTable.a2 = avfs_params.ulAcgGbVdroopTableA2; 2343 pp_table->AcgBtcGbVdroopTable.a2_shift = 20; 2344 2345 pp_table->AcgAvfsGb.m1 = avfs_params.ulAcgGbFuseTableM1; 2346 pp_table->AcgAvfsGb.m2 = avfs_params.ulAcgGbFuseTableM2; 2347 pp_table->AcgAvfsGb.b = avfs_params.ulAcgGbFuseTableB; 2348 pp_table->AcgAvfsGb.m1_shift = 24; 2349 pp_table->AcgAvfsGb.m2_shift = 12; 2350 pp_table->AcgAvfsGb.b_shift = 0; 2351 2352 } else { 2353 data->smu_features[GNLD_AVFS].supported = false; 2354 } 2355 } 2356 2357 return 0; 2358 } 2359 2360 static int vega10_acg_enable(struct pp_hwmgr *hwmgr) 2361 { 2362 struct vega10_hwmgr *data = hwmgr->backend; 2363 uint32_t agc_btc_response; 2364 2365 if (data->smu_features[GNLD_ACG].supported) { 2366 if (0 == vega10_enable_smc_features(hwmgr, true, 2367 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap)) 2368 data->smu_features[GNLD_DPM_PREFETCHER].enabled = true; 2369 2370 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL); 2371 2372 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response); 2373 2374 if (1 == agc_btc_response) { 2375 if (1 == data->acg_loop_state) 2376 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL); 2377 else if (2 == data->acg_loop_state) 2378 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL); 2379 if (0 == vega10_enable_smc_features(hwmgr, true, 2380 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2381 data->smu_features[GNLD_ACG].enabled = true; 2382 } else { 2383 pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n"); 2384 data->smu_features[GNLD_ACG].enabled = false; 2385 } 2386 } 2387 2388 return 0; 2389 } 2390 2391 static int vega10_acg_disable(struct pp_hwmgr *hwmgr) 2392 { 2393 struct vega10_hwmgr *data = hwmgr->backend; 2394 2395 if (data->smu_features[GNLD_ACG].supported && 2396 data->smu_features[GNLD_ACG].enabled) 2397 if (!vega10_enable_smc_features(hwmgr, false, 2398 data->smu_features[GNLD_ACG].smu_feature_bitmap)) 2399 data->smu_features[GNLD_ACG].enabled = false; 2400 2401 return 0; 2402 } 2403 2404 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr) 2405 { 2406 struct vega10_hwmgr *data = hwmgr->backend; 2407 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2408 struct pp_atomfwctrl_gpio_parameters gpio_params = {0}; 2409 int result; 2410 2411 result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params); 2412 if (!result) { 2413 if (PP_CAP(PHM_PlatformCaps_RegulatorHot) && 2414 data->registry_data.regulator_hot_gpio_support) { 2415 pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio; 2416 pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity; 2417 pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio; 2418 pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity; 2419 } else { 2420 pp_table->VR0HotGpio = 0; 2421 pp_table->VR0HotPolarity = 0; 2422 pp_table->VR1HotGpio = 0; 2423 pp_table->VR1HotPolarity = 0; 2424 } 2425 2426 if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) && 2427 data->registry_data.ac_dc_switch_gpio_support) { 2428 pp_table->AcDcGpio = gpio_params.ucAcDcGpio; 2429 pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity; 2430 } else { 2431 pp_table->AcDcGpio = 0; 2432 pp_table->AcDcPolarity = 0; 2433 } 2434 } 2435 2436 return result; 2437 } 2438 2439 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable) 2440 { 2441 struct vega10_hwmgr *data = hwmgr->backend; 2442 2443 if (data->smu_features[GNLD_AVFS].supported) { 2444 /* Already enabled or disabled */ 2445 if (!(enable ^ data->smu_features[GNLD_AVFS].enabled)) 2446 return 0; 2447 2448 if (enable) { 2449 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2450 true, 2451 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2452 "[avfs_control] Attempt to Enable AVFS feature Failed!", 2453 return -1); 2454 data->smu_features[GNLD_AVFS].enabled = true; 2455 } else { 2456 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2457 false, 2458 data->smu_features[GNLD_AVFS].smu_feature_bitmap), 2459 "[avfs_control] Attempt to Disable AVFS feature Failed!", 2460 return -1); 2461 data->smu_features[GNLD_AVFS].enabled = false; 2462 } 2463 } 2464 2465 return 0; 2466 } 2467 2468 static int vega10_update_avfs(struct pp_hwmgr *hwmgr) 2469 { 2470 struct vega10_hwmgr *data = hwmgr->backend; 2471 2472 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 2473 vega10_avfs_enable(hwmgr, false); 2474 } else if (data->need_update_dpm_table) { 2475 vega10_avfs_enable(hwmgr, false); 2476 vega10_avfs_enable(hwmgr, true); 2477 } else { 2478 vega10_avfs_enable(hwmgr, true); 2479 } 2480 2481 return 0; 2482 } 2483 2484 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr) 2485 { 2486 int result = 0; 2487 2488 uint64_t serial_number = 0; 2489 uint32_t top32, bottom32; 2490 struct phm_fuses_default fuse; 2491 2492 struct vega10_hwmgr *data = hwmgr->backend; 2493 AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table); 2494 2495 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32); 2496 2497 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32); 2498 2499 serial_number = ((uint64_t)bottom32 << 32) | top32; 2500 2501 if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) { 2502 avfs_fuse_table->VFT0_b = fuse.VFT0_b; 2503 avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1; 2504 avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2; 2505 avfs_fuse_table->VFT1_b = fuse.VFT1_b; 2506 avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1; 2507 avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2; 2508 avfs_fuse_table->VFT2_b = fuse.VFT2_b; 2509 avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1; 2510 avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2; 2511 result = smum_smc_table_manager(hwmgr, (uint8_t *)avfs_fuse_table, 2512 AVFSFUSETABLE, false); 2513 PP_ASSERT_WITH_CODE(!result, 2514 "Failed to upload FuseOVerride!", 2515 ); 2516 } 2517 2518 return result; 2519 } 2520 2521 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 2522 { 2523 struct vega10_hwmgr *data = hwmgr->backend; 2524 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2525 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 2526 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 2527 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 2528 uint32_t i; 2529 2530 dep_table = table_info->vdd_dep_on_mclk; 2531 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk); 2532 2533 for (i = 0; i < dep_table->count; i++) { 2534 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2535 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 2536 return; 2537 } 2538 } 2539 2540 dep_table = table_info->vdd_dep_on_sclk; 2541 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk); 2542 for (i = 0; i < dep_table->count; i++) { 2543 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 2544 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 2545 return; 2546 } 2547 } 2548 } 2549 2550 /** 2551 * vega10_init_smc_table - Initializes the SMC table and uploads it 2552 * 2553 * @hwmgr: the address of the powerplay hardware manager. 2554 * return: always 0 2555 */ 2556 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr) 2557 { 2558 int result; 2559 struct vega10_hwmgr *data = hwmgr->backend; 2560 struct phm_ppt_v2_information *table_info = 2561 (struct phm_ppt_v2_information *)(hwmgr->pptable); 2562 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 2563 struct pp_atomfwctrl_voltage_table voltage_table; 2564 struct pp_atomfwctrl_bios_boot_up_values boot_up_values; 2565 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 2566 2567 result = vega10_setup_default_dpm_tables(hwmgr); 2568 PP_ASSERT_WITH_CODE(!result, 2569 "Failed to setup default DPM tables!", 2570 return result); 2571 2572 if (!hwmgr->not_vf) 2573 return 0; 2574 2575 /* initialize ODN table */ 2576 if (hwmgr->od_enabled) { 2577 if (odn_table->max_vddc) { 2578 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 2579 vega10_check_dpm_table_updated(hwmgr); 2580 } else { 2581 vega10_odn_initial_default_setting(hwmgr); 2582 } 2583 } 2584 2585 result = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC, 2586 VOLTAGE_OBJ_SVID2, &voltage_table); 2587 PP_ASSERT_WITH_CODE(!result, 2588 "Failed to get voltage table!", 2589 return result); 2590 pp_table->MaxVidStep = voltage_table.max_vid_step; 2591 2592 pp_table->GfxDpmVoltageMode = 2593 (uint8_t)(table_info->uc_gfx_dpm_voltage_mode); 2594 pp_table->SocDpmVoltageMode = 2595 (uint8_t)(table_info->uc_soc_dpm_voltage_mode); 2596 pp_table->UclkDpmVoltageMode = 2597 (uint8_t)(table_info->uc_uclk_dpm_voltage_mode); 2598 pp_table->UvdDpmVoltageMode = 2599 (uint8_t)(table_info->uc_uvd_dpm_voltage_mode); 2600 pp_table->VceDpmVoltageMode = 2601 (uint8_t)(table_info->uc_vce_dpm_voltage_mode); 2602 pp_table->Mp0DpmVoltageMode = 2603 (uint8_t)(table_info->uc_mp0_dpm_voltage_mode); 2604 2605 pp_table->DisplayDpmVoltageMode = 2606 (uint8_t)(table_info->uc_dcef_dpm_voltage_mode); 2607 2608 data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable; 2609 data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable; 2610 2611 if (data->registry_data.ulv_support && 2612 table_info->us_ulv_voltage_offset) { 2613 result = vega10_populate_ulv_state(hwmgr); 2614 PP_ASSERT_WITH_CODE(!result, 2615 "Failed to initialize ULV state!", 2616 return result); 2617 } 2618 2619 result = vega10_populate_smc_link_levels(hwmgr); 2620 PP_ASSERT_WITH_CODE(!result, 2621 "Failed to initialize Link Level!", 2622 return result); 2623 2624 result = vega10_override_pcie_parameters(hwmgr); 2625 PP_ASSERT_WITH_CODE(!result, 2626 "Failed to override pcie parameters!", 2627 return result); 2628 2629 result = vega10_populate_all_graphic_levels(hwmgr); 2630 PP_ASSERT_WITH_CODE(!result, 2631 "Failed to initialize Graphics Level!", 2632 return result); 2633 2634 result = vega10_populate_all_memory_levels(hwmgr); 2635 PP_ASSERT_WITH_CODE(!result, 2636 "Failed to initialize Memory Level!", 2637 return result); 2638 2639 vega10_populate_vddc_soc_levels(hwmgr); 2640 2641 result = vega10_populate_all_display_clock_levels(hwmgr); 2642 PP_ASSERT_WITH_CODE(!result, 2643 "Failed to initialize Display Level!", 2644 return result); 2645 2646 result = vega10_populate_smc_vce_levels(hwmgr); 2647 PP_ASSERT_WITH_CODE(!result, 2648 "Failed to initialize VCE Level!", 2649 return result); 2650 2651 result = vega10_populate_smc_uvd_levels(hwmgr); 2652 PP_ASSERT_WITH_CODE(!result, 2653 "Failed to initialize UVD Level!", 2654 return result); 2655 2656 if (data->registry_data.clock_stretcher_support) { 2657 result = vega10_populate_clock_stretcher_table(hwmgr); 2658 PP_ASSERT_WITH_CODE(!result, 2659 "Failed to populate Clock Stretcher Table!", 2660 return result); 2661 } 2662 2663 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values); 2664 if (!result) { 2665 data->vbios_boot_state.vddc = boot_up_values.usVddc; 2666 data->vbios_boot_state.vddci = boot_up_values.usVddci; 2667 data->vbios_boot_state.mvddc = boot_up_values.usMvddc; 2668 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk; 2669 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk; 2670 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2671 SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk); 2672 2673 pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, 2674 SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk); 2675 2676 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk; 2677 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk; 2678 if (0 != boot_up_values.usVddc) { 2679 smum_send_msg_to_smc_with_parameter(hwmgr, 2680 PPSMC_MSG_SetFloorSocVoltage, 2681 (boot_up_values.usVddc * 4), 2682 NULL); 2683 data->vbios_boot_state.bsoc_vddc_lock = true; 2684 } else { 2685 data->vbios_boot_state.bsoc_vddc_lock = false; 2686 } 2687 smum_send_msg_to_smc_with_parameter(hwmgr, 2688 PPSMC_MSG_SetMinDeepSleepDcefclk, 2689 (uint32_t)(data->vbios_boot_state.dcef_clock / 100), 2690 NULL); 2691 } 2692 2693 result = vega10_populate_avfs_parameters(hwmgr); 2694 PP_ASSERT_WITH_CODE(!result, 2695 "Failed to initialize AVFS Parameters!", 2696 return result); 2697 2698 result = vega10_populate_gpio_parameters(hwmgr); 2699 PP_ASSERT_WITH_CODE(!result, 2700 "Failed to initialize GPIO Parameters!", 2701 return result); 2702 2703 pp_table->GfxclkAverageAlpha = (uint8_t) 2704 (data->gfxclk_average_alpha); 2705 pp_table->SocclkAverageAlpha = (uint8_t) 2706 (data->socclk_average_alpha); 2707 pp_table->UclkAverageAlpha = (uint8_t) 2708 (data->uclk_average_alpha); 2709 pp_table->GfxActivityAverageAlpha = (uint8_t) 2710 (data->gfx_activity_average_alpha); 2711 2712 vega10_populate_and_upload_avfs_fuse_override(hwmgr); 2713 2714 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 2715 2716 PP_ASSERT_WITH_CODE(!result, 2717 "Failed to upload PPtable!", return result); 2718 2719 result = vega10_avfs_enable(hwmgr, true); 2720 PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!", 2721 return result); 2722 vega10_acg_enable(hwmgr); 2723 2724 return 0; 2725 } 2726 2727 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr) 2728 { 2729 struct vega10_hwmgr *data = hwmgr->backend; 2730 2731 if (data->smu_features[GNLD_THERMAL].supported) { 2732 if (data->smu_features[GNLD_THERMAL].enabled) 2733 pr_info("THERMAL Feature Already enabled!"); 2734 2735 PP_ASSERT_WITH_CODE( 2736 !vega10_enable_smc_features(hwmgr, 2737 true, 2738 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2739 "Enable THERMAL Feature Failed!", 2740 return -1); 2741 data->smu_features[GNLD_THERMAL].enabled = true; 2742 } 2743 2744 return 0; 2745 } 2746 2747 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr) 2748 { 2749 struct vega10_hwmgr *data = hwmgr->backend; 2750 2751 if (data->smu_features[GNLD_THERMAL].supported) { 2752 if (!data->smu_features[GNLD_THERMAL].enabled) 2753 pr_info("THERMAL Feature Already disabled!"); 2754 2755 PP_ASSERT_WITH_CODE( 2756 !vega10_enable_smc_features(hwmgr, 2757 false, 2758 data->smu_features[GNLD_THERMAL].smu_feature_bitmap), 2759 "disable THERMAL Feature Failed!", 2760 return -1); 2761 data->smu_features[GNLD_THERMAL].enabled = false; 2762 } 2763 2764 return 0; 2765 } 2766 2767 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr) 2768 { 2769 struct vega10_hwmgr *data = hwmgr->backend; 2770 2771 if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) { 2772 if (data->smu_features[GNLD_VR0HOT].supported) { 2773 PP_ASSERT_WITH_CODE( 2774 !vega10_enable_smc_features(hwmgr, 2775 true, 2776 data->smu_features[GNLD_VR0HOT].smu_feature_bitmap), 2777 "Attempt to Enable VR0 Hot feature Failed!", 2778 return -1); 2779 data->smu_features[GNLD_VR0HOT].enabled = true; 2780 } else { 2781 if (data->smu_features[GNLD_VR1HOT].supported) { 2782 PP_ASSERT_WITH_CODE( 2783 !vega10_enable_smc_features(hwmgr, 2784 true, 2785 data->smu_features[GNLD_VR1HOT].smu_feature_bitmap), 2786 "Attempt to Enable VR0 Hot feature Failed!", 2787 return -1); 2788 data->smu_features[GNLD_VR1HOT].enabled = true; 2789 } 2790 } 2791 } 2792 return 0; 2793 } 2794 2795 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr) 2796 { 2797 struct vega10_hwmgr *data = hwmgr->backend; 2798 2799 if (data->registry_data.ulv_support) { 2800 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2801 true, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2802 "Enable ULV Feature Failed!", 2803 return -1); 2804 data->smu_features[GNLD_ULV].enabled = true; 2805 } 2806 2807 return 0; 2808 } 2809 2810 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr) 2811 { 2812 struct vega10_hwmgr *data = hwmgr->backend; 2813 2814 if (data->registry_data.ulv_support) { 2815 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2816 false, data->smu_features[GNLD_ULV].smu_feature_bitmap), 2817 "disable ULV Feature Failed!", 2818 return -EINVAL); 2819 data->smu_features[GNLD_ULV].enabled = false; 2820 } 2821 2822 return 0; 2823 } 2824 2825 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2826 { 2827 struct vega10_hwmgr *data = hwmgr->backend; 2828 2829 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2830 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2831 true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2832 "Attempt to Enable DS_GFXCLK Feature Failed!", 2833 return -EINVAL); 2834 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 2835 } 2836 2837 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2838 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2839 true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2840 "Attempt to Enable DS_SOCCLK Feature Failed!", 2841 return -EINVAL); 2842 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 2843 } 2844 2845 if (data->smu_features[GNLD_DS_LCLK].supported) { 2846 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2847 true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2848 "Attempt to Enable DS_LCLK Feature Failed!", 2849 return -EINVAL); 2850 data->smu_features[GNLD_DS_LCLK].enabled = true; 2851 } 2852 2853 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2854 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2855 true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2856 "Attempt to Enable DS_DCEFCLK Feature Failed!", 2857 return -EINVAL); 2858 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 2859 } 2860 2861 return 0; 2862 } 2863 2864 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 2865 { 2866 struct vega10_hwmgr *data = hwmgr->backend; 2867 2868 if (data->smu_features[GNLD_DS_GFXCLK].supported) { 2869 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2870 false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap), 2871 "Attempt to disable DS_GFXCLK Feature Failed!", 2872 return -EINVAL); 2873 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 2874 } 2875 2876 if (data->smu_features[GNLD_DS_SOCCLK].supported) { 2877 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2878 false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap), 2879 "Attempt to disable DS_ Feature Failed!", 2880 return -EINVAL); 2881 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 2882 } 2883 2884 if (data->smu_features[GNLD_DS_LCLK].supported) { 2885 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2886 false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap), 2887 "Attempt to disable DS_LCLK Feature Failed!", 2888 return -EINVAL); 2889 data->smu_features[GNLD_DS_LCLK].enabled = false; 2890 } 2891 2892 if (data->smu_features[GNLD_DS_DCEFCLK].supported) { 2893 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2894 false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap), 2895 "Attempt to disable DS_DCEFCLK Feature Failed!", 2896 return -EINVAL); 2897 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 2898 } 2899 2900 return 0; 2901 } 2902 2903 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2904 { 2905 struct vega10_hwmgr *data = hwmgr->backend; 2906 uint32_t i, feature_mask = 0; 2907 2908 if (!hwmgr->not_vf) 2909 return 0; 2910 2911 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2912 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2913 false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2914 "Attempt to disable LED DPM feature failed!", return -EINVAL); 2915 data->smu_features[GNLD_LED_DISPLAY].enabled = false; 2916 } 2917 2918 for (i = 0; i < GNLD_DPM_MAX; i++) { 2919 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2920 if (data->smu_features[i].supported) { 2921 if (data->smu_features[i].enabled) { 2922 feature_mask |= data->smu_features[i]. 2923 smu_feature_bitmap; 2924 data->smu_features[i].enabled = false; 2925 } 2926 } 2927 } 2928 } 2929 2930 vega10_enable_smc_features(hwmgr, false, feature_mask); 2931 2932 return 0; 2933 } 2934 2935 /** 2936 * vega10_start_dpm - Tell SMC to enabled the supported DPMs. 2937 * 2938 * @hwmgr: the address of the powerplay hardware manager. 2939 * @bitmap: bitmap for the features to enabled. 2940 * return: 0 on at least one DPM is successfully enabled. 2941 */ 2942 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) 2943 { 2944 struct vega10_hwmgr *data = hwmgr->backend; 2945 uint32_t i, feature_mask = 0; 2946 2947 for (i = 0; i < GNLD_DPM_MAX; i++) { 2948 if (data->smu_features[i].smu_feature_bitmap & bitmap) { 2949 if (data->smu_features[i].supported) { 2950 if (!data->smu_features[i].enabled) { 2951 feature_mask |= data->smu_features[i]. 2952 smu_feature_bitmap; 2953 data->smu_features[i].enabled = true; 2954 } 2955 } 2956 } 2957 } 2958 2959 if (vega10_enable_smc_features(hwmgr, 2960 true, feature_mask)) { 2961 for (i = 0; i < GNLD_DPM_MAX; i++) { 2962 if (data->smu_features[i].smu_feature_bitmap & 2963 feature_mask) 2964 data->smu_features[i].enabled = false; 2965 } 2966 } 2967 2968 if(data->smu_features[GNLD_LED_DISPLAY].supported == true){ 2969 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2970 true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), 2971 "Attempt to Enable LED DPM feature Failed!", return -EINVAL); 2972 data->smu_features[GNLD_LED_DISPLAY].enabled = true; 2973 } 2974 2975 if (data->vbios_boot_state.bsoc_vddc_lock) { 2976 smum_send_msg_to_smc_with_parameter(hwmgr, 2977 PPSMC_MSG_SetFloorSocVoltage, 0, 2978 NULL); 2979 data->vbios_boot_state.bsoc_vddc_lock = false; 2980 } 2981 2982 if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) { 2983 if (data->smu_features[GNLD_ACDC].supported) { 2984 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2985 true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), 2986 "Attempt to Enable DS_GFXCLK Feature Failed!", 2987 return -1); 2988 data->smu_features[GNLD_ACDC].enabled = true; 2989 } 2990 } 2991 2992 if (data->registry_data.pcie_dpm_key_disabled) { 2993 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 2994 false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap), 2995 "Attempt to Disable Link DPM feature Failed!", return -EINVAL); 2996 data->smu_features[GNLD_DPM_LINK].enabled = false; 2997 data->smu_features[GNLD_DPM_LINK].supported = false; 2998 } 2999 3000 return 0; 3001 } 3002 3003 3004 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable) 3005 { 3006 struct vega10_hwmgr *data = hwmgr->backend; 3007 3008 if (data->smu_features[GNLD_PCC_LIMIT].supported) { 3009 if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled) 3010 pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled"); 3011 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3012 enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap), 3013 "Attempt to Enable PCC Limit feature Failed!", 3014 return -EINVAL); 3015 data->smu_features[GNLD_PCC_LIMIT].enabled = enable; 3016 } 3017 3018 return 0; 3019 } 3020 3021 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 3022 { 3023 struct phm_ppt_v2_information *table_info = 3024 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3025 3026 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 3027 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 3028 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; 3029 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; 3030 } else { 3031 hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3032 hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk; 3033 } 3034 3035 hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk; 3036 hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk; 3037 3038 /* make sure the output is in Mhz */ 3039 hwmgr->pstate_sclk /= 100; 3040 hwmgr->pstate_mclk /= 100; 3041 hwmgr->pstate_sclk_peak /= 100; 3042 hwmgr->pstate_mclk_peak /= 100; 3043 } 3044 3045 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 3046 { 3047 struct vega10_hwmgr *data = hwmgr->backend; 3048 int tmp_result, result = 0; 3049 3050 if (hwmgr->not_vf) { 3051 vega10_enable_disable_PCC_limit_feature(hwmgr, true); 3052 3053 smum_send_msg_to_smc_with_parameter(hwmgr, 3054 PPSMC_MSG_ConfigureTelemetry, data->config_telemetry, 3055 NULL); 3056 3057 tmp_result = vega10_construct_voltage_tables(hwmgr); 3058 PP_ASSERT_WITH_CODE(!tmp_result, 3059 "Failed to construct voltage tables!", 3060 result = tmp_result); 3061 } 3062 3063 if (hwmgr->not_vf || hwmgr->pp_one_vf) { 3064 tmp_result = vega10_init_smc_table(hwmgr); 3065 PP_ASSERT_WITH_CODE(!tmp_result, 3066 "Failed to initialize SMC table!", 3067 result = tmp_result); 3068 } 3069 3070 if (hwmgr->not_vf) { 3071 if (PP_CAP(PHM_PlatformCaps_ThermalController)) { 3072 tmp_result = vega10_enable_thermal_protection(hwmgr); 3073 PP_ASSERT_WITH_CODE(!tmp_result, 3074 "Failed to enable thermal protection!", 3075 result = tmp_result); 3076 } 3077 3078 tmp_result = vega10_enable_vrhot_feature(hwmgr); 3079 PP_ASSERT_WITH_CODE(!tmp_result, 3080 "Failed to enable VR hot feature!", 3081 result = tmp_result); 3082 3083 tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr); 3084 PP_ASSERT_WITH_CODE(!tmp_result, 3085 "Failed to enable deep sleep master switch!", 3086 result = tmp_result); 3087 } 3088 3089 if (hwmgr->not_vf) { 3090 tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES); 3091 PP_ASSERT_WITH_CODE(!tmp_result, 3092 "Failed to start DPM!", result = tmp_result); 3093 } 3094 3095 if (hwmgr->not_vf) { 3096 /* enable didt, do not abort if failed didt */ 3097 tmp_result = vega10_enable_didt_config(hwmgr); 3098 PP_ASSERT(!tmp_result, 3099 "Failed to enable didt config!"); 3100 } 3101 3102 tmp_result = vega10_enable_power_containment(hwmgr); 3103 PP_ASSERT_WITH_CODE(!tmp_result, 3104 "Failed to enable power containment!", 3105 result = tmp_result); 3106 3107 if (hwmgr->not_vf) { 3108 tmp_result = vega10_power_control_set_level(hwmgr); 3109 PP_ASSERT_WITH_CODE(!tmp_result, 3110 "Failed to power control set level!", 3111 result = tmp_result); 3112 3113 tmp_result = vega10_enable_ulv(hwmgr); 3114 PP_ASSERT_WITH_CODE(!tmp_result, 3115 "Failed to enable ULV!", 3116 result = tmp_result); 3117 } 3118 3119 vega10_populate_umdpstate_clocks(hwmgr); 3120 3121 return result; 3122 } 3123 3124 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr) 3125 { 3126 return sizeof(struct vega10_power_state); 3127 } 3128 3129 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, 3130 void *state, struct pp_power_state *power_state, 3131 void *pp_table, uint32_t classification_flag) 3132 { 3133 ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2; 3134 struct vega10_power_state *vega10_ps = 3135 cast_phw_vega10_power_state(&(power_state->hardware)); 3136 struct vega10_performance_level *performance_level; 3137 ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state; 3138 ATOM_Vega10_POWERPLAYTABLE *powerplay_table = 3139 (ATOM_Vega10_POWERPLAYTABLE *)pp_table; 3140 ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table = 3141 (ATOM_Vega10_SOCCLK_Dependency_Table *) 3142 (((unsigned long)powerplay_table) + 3143 le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset)); 3144 ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table = 3145 (ATOM_Vega10_GFXCLK_Dependency_Table *) 3146 (((unsigned long)powerplay_table) + 3147 le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset)); 3148 ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table = 3149 (ATOM_Vega10_MCLK_Dependency_Table *) 3150 (((unsigned long)powerplay_table) + 3151 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3152 3153 3154 /* The following fields are not initialized here: 3155 * id orderedList allStatesList 3156 */ 3157 power_state->classification.ui_label = 3158 (le16_to_cpu(state_entry->usClassification) & 3159 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3160 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3161 power_state->classification.flags = classification_flag; 3162 /* NOTE: There is a classification2 flag in BIOS 3163 * that is not being used right now 3164 */ 3165 power_state->classification.temporary_state = false; 3166 power_state->classification.to_be_deleted = false; 3167 3168 power_state->validation.disallowOnDC = 3169 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3170 ATOM_Vega10_DISALLOW_ON_DC) != 0); 3171 3172 power_state->display.disableFrameModulation = false; 3173 power_state->display.limitRefreshrate = false; 3174 power_state->display.enableVariBright = 3175 ((le32_to_cpu(state_entry->ulCapsAndSettings) & 3176 ATOM_Vega10_ENABLE_VARIBRIGHT) != 0); 3177 3178 power_state->validation.supportedPowerLevels = 0; 3179 power_state->uvd_clocks.VCLK = 0; 3180 power_state->uvd_clocks.DCLK = 0; 3181 power_state->temperatures.min = 0; 3182 power_state->temperatures.max = 0; 3183 3184 performance_level = &(vega10_ps->performance_levels 3185 [vega10_ps->performance_level_count++]); 3186 3187 PP_ASSERT_WITH_CODE( 3188 (vega10_ps->performance_level_count < 3189 NUM_GFXCLK_DPM_LEVELS), 3190 "Performance levels exceeds SMC limit!", 3191 return -1); 3192 3193 PP_ASSERT_WITH_CODE( 3194 (vega10_ps->performance_level_count < 3195 hwmgr->platform_descriptor. 3196 hardwareActivityPerformanceLevels), 3197 "Performance levels exceeds Driver limit!", 3198 return -1); 3199 3200 /* Performance levels are arranged from low to high. */ 3201 performance_level->soc_clock = socclk_dep_table->entries 3202 [state_entry->ucSocClockIndexLow].ulClk; 3203 performance_level->gfx_clock = gfxclk_dep_table->entries 3204 [state_entry->ucGfxClockIndexLow].ulClk; 3205 performance_level->mem_clock = mclk_dep_table->entries 3206 [state_entry->ucMemClockIndexLow].ulMemClk; 3207 3208 performance_level = &(vega10_ps->performance_levels 3209 [vega10_ps->performance_level_count++]); 3210 performance_level->soc_clock = socclk_dep_table->entries 3211 [state_entry->ucSocClockIndexHigh].ulClk; 3212 if (gfxclk_dep_table->ucRevId == 0) { 3213 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 3214 * to level-4 due to the limited 110w-power 3215 */ 3216 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3217 performance_level->gfx_clock = 3218 gfxclk_dep_table->entries[4].ulClk; 3219 else 3220 performance_level->gfx_clock = gfxclk_dep_table->entries 3221 [state_entry->ucGfxClockIndexHigh].ulClk; 3222 } else if (gfxclk_dep_table->ucRevId == 1) { 3223 patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries; 3224 if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0)) 3225 performance_level->gfx_clock = patom_record_V2[4].ulClk; 3226 else 3227 performance_level->gfx_clock = 3228 patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk; 3229 } 3230 3231 performance_level->mem_clock = mclk_dep_table->entries 3232 [state_entry->ucMemClockIndexHigh].ulMemClk; 3233 return 0; 3234 } 3235 3236 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3237 unsigned long entry_index, struct pp_power_state *state) 3238 { 3239 int result; 3240 struct vega10_power_state *vega10_ps; 3241 3242 state->hardware.magic = PhwVega10_Magic; 3243 3244 vega10_ps = cast_phw_vega10_power_state(&state->hardware); 3245 3246 result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state, 3247 vega10_get_pp_table_entry_callback_func); 3248 if (result) 3249 return result; 3250 3251 /* 3252 * This is the earliest time we have all the dependency table 3253 * and the VBIOS boot state 3254 */ 3255 /* set DC compatible flag if this state supports DC */ 3256 if (!state->validation.disallowOnDC) 3257 vega10_ps->dc_compatible = true; 3258 3259 vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3260 vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3261 3262 return 0; 3263 } 3264 3265 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr, 3266 struct pp_hw_power_state *hw_ps) 3267 { 3268 return 0; 3269 } 3270 3271 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3272 struct pp_power_state *request_ps, 3273 const struct pp_power_state *current_ps) 3274 { 3275 struct amdgpu_device *adev = hwmgr->adev; 3276 struct vega10_power_state *vega10_ps; 3277 uint32_t sclk; 3278 uint32_t mclk; 3279 struct PP_Clocks minimum_clocks = {0}; 3280 bool disable_mclk_switching; 3281 bool disable_mclk_switching_for_frame_lock; 3282 bool disable_mclk_switching_for_vr; 3283 bool force_mclk_high; 3284 const struct phm_clock_and_voltage_limits *max_limits; 3285 uint32_t i; 3286 struct vega10_hwmgr *data = hwmgr->backend; 3287 struct phm_ppt_v2_information *table_info = 3288 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3289 int32_t count; 3290 uint32_t stable_pstate_sclk_dpm_percentage; 3291 uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3292 uint32_t latency; 3293 3294 vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware); 3295 if (!vega10_ps) 3296 return -EINVAL; 3297 3298 data->battery_state = (PP_StateUILabel_Battery == 3299 request_ps->classification.ui_label); 3300 3301 if (vega10_ps->performance_level_count != 2) 3302 pr_info("VI should always have 2 performance levels"); 3303 3304 max_limits = adev->pm.ac_power ? 3305 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3306 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3307 3308 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3309 if (!adev->pm.ac_power) { 3310 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3311 if (vega10_ps->performance_levels[i].mem_clock > 3312 max_limits->mclk) 3313 vega10_ps->performance_levels[i].mem_clock = 3314 max_limits->mclk; 3315 if (vega10_ps->performance_levels[i].gfx_clock > 3316 max_limits->sclk) 3317 vega10_ps->performance_levels[i].gfx_clock = 3318 max_limits->sclk; 3319 } 3320 } 3321 3322 /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ 3323 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3324 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3325 3326 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3327 stable_pstate_sclk_dpm_percentage = 3328 data->registry_data.stable_pstate_sclk_dpm_percentage; 3329 PP_ASSERT_WITH_CODE( 3330 data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && 3331 data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, 3332 "percent sclk value must range from 1% to 100%, setting default value", 3333 stable_pstate_sclk_dpm_percentage = 75); 3334 3335 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3336 stable_pstate_sclk = (max_limits->sclk * 3337 stable_pstate_sclk_dpm_percentage) / 100; 3338 3339 for (count = table_info->vdd_dep_on_sclk->count - 1; 3340 count >= 0; count--) { 3341 if (stable_pstate_sclk >= 3342 table_info->vdd_dep_on_sclk->entries[count].clk) { 3343 stable_pstate_sclk = 3344 table_info->vdd_dep_on_sclk->entries[count].clk; 3345 break; 3346 } 3347 } 3348 3349 if (count < 0) 3350 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3351 3352 stable_pstate_mclk = max_limits->mclk; 3353 3354 minimum_clocks.engineClock = stable_pstate_sclk; 3355 minimum_clocks.memoryClock = stable_pstate_mclk; 3356 } 3357 3358 disable_mclk_switching_for_frame_lock = 3359 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3360 disable_mclk_switching_for_vr = 3361 PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR); 3362 force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh); 3363 3364 if (hwmgr->display_config->num_display == 0) 3365 disable_mclk_switching = false; 3366 else 3367 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && 3368 !hwmgr->display_config->multi_monitor_in_sync) || 3369 disable_mclk_switching_for_frame_lock || 3370 disable_mclk_switching_for_vr || 3371 force_mclk_high; 3372 3373 sclk = vega10_ps->performance_levels[0].gfx_clock; 3374 mclk = vega10_ps->performance_levels[0].mem_clock; 3375 3376 if (sclk < minimum_clocks.engineClock) 3377 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3378 max_limits->sclk : minimum_clocks.engineClock; 3379 3380 if (mclk < minimum_clocks.memoryClock) 3381 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3382 max_limits->mclk : minimum_clocks.memoryClock; 3383 3384 vega10_ps->performance_levels[0].gfx_clock = sclk; 3385 vega10_ps->performance_levels[0].mem_clock = mclk; 3386 3387 if (vega10_ps->performance_levels[1].gfx_clock < 3388 vega10_ps->performance_levels[0].gfx_clock) 3389 vega10_ps->performance_levels[0].gfx_clock = 3390 vega10_ps->performance_levels[1].gfx_clock; 3391 3392 if (disable_mclk_switching) { 3393 /* Set Mclk the max of level 0 and level 1 */ 3394 if (mclk < vega10_ps->performance_levels[1].mem_clock) 3395 mclk = vega10_ps->performance_levels[1].mem_clock; 3396 3397 /* Find the lowest MCLK frequency that is within 3398 * the tolerable latency defined in DAL 3399 */ 3400 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3401 for (i = 0; i < data->mclk_latency_table.count; i++) { 3402 if ((data->mclk_latency_table.entries[i].latency <= latency) && 3403 (data->mclk_latency_table.entries[i].frequency >= 3404 vega10_ps->performance_levels[0].mem_clock) && 3405 (data->mclk_latency_table.entries[i].frequency <= 3406 vega10_ps->performance_levels[1].mem_clock)) 3407 mclk = data->mclk_latency_table.entries[i].frequency; 3408 } 3409 vega10_ps->performance_levels[0].mem_clock = mclk; 3410 } else { 3411 if (vega10_ps->performance_levels[1].mem_clock < 3412 vega10_ps->performance_levels[0].mem_clock) 3413 vega10_ps->performance_levels[0].mem_clock = 3414 vega10_ps->performance_levels[1].mem_clock; 3415 } 3416 3417 if (PP_CAP(PHM_PlatformCaps_StablePState)) { 3418 for (i = 0; i < vega10_ps->performance_level_count; i++) { 3419 vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk; 3420 vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk; 3421 } 3422 } 3423 3424 return 0; 3425 } 3426 3427 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 3428 { 3429 struct vega10_hwmgr *data = hwmgr->backend; 3430 const struct phm_set_power_state_input *states = 3431 (const struct phm_set_power_state_input *)input; 3432 const struct vega10_power_state *vega10_ps = 3433 cast_const_phw_vega10_power_state(states->pnew_state); 3434 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 3435 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 3436 uint32_t sclk, mclk; 3437 uint32_t i; 3438 3439 if (vega10_ps == NULL) 3440 return -EINVAL; 3441 sclk = vega10_ps->performance_levels 3442 [vega10_ps->performance_level_count - 1].gfx_clock; 3443 mclk = vega10_ps->performance_levels 3444 [vega10_ps->performance_level_count - 1].mem_clock; 3445 3446 for (i = 0; i < sclk_table->count; i++) { 3447 if (sclk == sclk_table->dpm_levels[i].value) 3448 break; 3449 } 3450 3451 if (i >= sclk_table->count) { 3452 if (sclk > sclk_table->dpm_levels[i-1].value) { 3453 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3454 sclk_table->dpm_levels[i-1].value = sclk; 3455 } 3456 } 3457 3458 for (i = 0; i < mclk_table->count; i++) { 3459 if (mclk == mclk_table->dpm_levels[i].value) 3460 break; 3461 } 3462 3463 if (i >= mclk_table->count) { 3464 if (mclk > mclk_table->dpm_levels[i-1].value) { 3465 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3466 mclk_table->dpm_levels[i-1].value = mclk; 3467 } 3468 } 3469 3470 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3471 data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK; 3472 3473 return 0; 3474 } 3475 3476 static int vega10_populate_and_upload_sclk_mclk_dpm_levels( 3477 struct pp_hwmgr *hwmgr, const void *input) 3478 { 3479 int result = 0; 3480 struct vega10_hwmgr *data = hwmgr->backend; 3481 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3482 struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table; 3483 struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk; 3484 int count; 3485 3486 if (!data->need_update_dpm_table) 3487 return 0; 3488 3489 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 3490 for (count = 0; count < dpm_table->gfx_table.count; count++) 3491 dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3492 } 3493 3494 odn_clk_table = &odn_table->vdd_dep_on_mclk; 3495 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 3496 for (count = 0; count < dpm_table->mem_table.count; count++) 3497 dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk; 3498 } 3499 3500 if (data->need_update_dpm_table & 3501 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { 3502 result = vega10_populate_all_graphic_levels(hwmgr); 3503 PP_ASSERT_WITH_CODE((0 == result), 3504 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 3505 return result); 3506 } 3507 3508 if (data->need_update_dpm_table & 3509 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 3510 result = vega10_populate_all_memory_levels(hwmgr); 3511 PP_ASSERT_WITH_CODE((0 == result), 3512 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 3513 return result); 3514 } 3515 3516 vega10_populate_vddc_soc_levels(hwmgr); 3517 3518 return result; 3519 } 3520 3521 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 3522 struct vega10_single_dpm_table *dpm_table, 3523 uint32_t low_limit, uint32_t high_limit) 3524 { 3525 uint32_t i; 3526 3527 for (i = 0; i < dpm_table->count; i++) { 3528 if ((dpm_table->dpm_levels[i].value < low_limit) || 3529 (dpm_table->dpm_levels[i].value > high_limit)) 3530 dpm_table->dpm_levels[i].enabled = false; 3531 else 3532 dpm_table->dpm_levels[i].enabled = true; 3533 } 3534 return 0; 3535 } 3536 3537 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr, 3538 struct vega10_single_dpm_table *dpm_table, 3539 uint32_t low_limit, uint32_t high_limit, 3540 uint32_t disable_dpm_mask) 3541 { 3542 uint32_t i; 3543 3544 for (i = 0; i < dpm_table->count; i++) { 3545 if ((dpm_table->dpm_levels[i].value < low_limit) || 3546 (dpm_table->dpm_levels[i].value > high_limit)) 3547 dpm_table->dpm_levels[i].enabled = false; 3548 else if (!((1 << i) & disable_dpm_mask)) 3549 dpm_table->dpm_levels[i].enabled = false; 3550 else 3551 dpm_table->dpm_levels[i].enabled = true; 3552 } 3553 return 0; 3554 } 3555 3556 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr, 3557 const struct vega10_power_state *vega10_ps) 3558 { 3559 struct vega10_hwmgr *data = hwmgr->backend; 3560 uint32_t high_limit_count; 3561 3562 PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1), 3563 "power state did not have any performance level", 3564 return -1); 3565 3566 high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1; 3567 3568 vega10_trim_single_dpm_states(hwmgr, 3569 &(data->dpm_table.soc_table), 3570 vega10_ps->performance_levels[0].soc_clock, 3571 vega10_ps->performance_levels[high_limit_count].soc_clock); 3572 3573 vega10_trim_single_dpm_states_with_mask(hwmgr, 3574 &(data->dpm_table.gfx_table), 3575 vega10_ps->performance_levels[0].gfx_clock, 3576 vega10_ps->performance_levels[high_limit_count].gfx_clock, 3577 data->disable_dpm_mask); 3578 3579 vega10_trim_single_dpm_states(hwmgr, 3580 &(data->dpm_table.mem_table), 3581 vega10_ps->performance_levels[0].mem_clock, 3582 vega10_ps->performance_levels[high_limit_count].mem_clock); 3583 3584 return 0; 3585 } 3586 3587 static uint32_t vega10_find_lowest_dpm_level( 3588 struct vega10_single_dpm_table *table) 3589 { 3590 uint32_t i; 3591 3592 for (i = 0; i < table->count; i++) { 3593 if (table->dpm_levels[i].enabled) 3594 break; 3595 } 3596 3597 return i; 3598 } 3599 3600 static uint32_t vega10_find_highest_dpm_level( 3601 struct vega10_single_dpm_table *table) 3602 { 3603 uint32_t i = 0; 3604 3605 if (table->count <= MAX_REGULAR_DPM_NUMBER) { 3606 for (i = table->count; i > 0; i--) { 3607 if (table->dpm_levels[i - 1].enabled) 3608 return i - 1; 3609 } 3610 } else { 3611 pr_info("DPM Table Has Too Many Entries!"); 3612 return MAX_REGULAR_DPM_NUMBER - 1; 3613 } 3614 3615 return i; 3616 } 3617 3618 static void vega10_apply_dal_minimum_voltage_request( 3619 struct pp_hwmgr *hwmgr) 3620 { 3621 return; 3622 } 3623 3624 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr) 3625 { 3626 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk; 3627 struct phm_ppt_v2_information *table_info = 3628 (struct phm_ppt_v2_information *)(hwmgr->pptable); 3629 3630 vdd_dep_table_on_mclk = table_info->vdd_dep_on_mclk; 3631 3632 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; 3633 } 3634 3635 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr) 3636 { 3637 struct vega10_hwmgr *data = hwmgr->backend; 3638 uint32_t socclk_idx; 3639 3640 vega10_apply_dal_minimum_voltage_request(hwmgr); 3641 3642 if (!data->registry_data.sclk_dpm_key_disabled) { 3643 if (data->smc_state_table.gfx_boot_level != 3644 data->dpm_table.gfx_table.dpm_state.soft_min_level) { 3645 smum_send_msg_to_smc_with_parameter(hwmgr, 3646 PPSMC_MSG_SetSoftMinGfxclkByIndex, 3647 data->smc_state_table.gfx_boot_level, 3648 NULL); 3649 3650 data->dpm_table.gfx_table.dpm_state.soft_min_level = 3651 data->smc_state_table.gfx_boot_level; 3652 } 3653 } 3654 3655 if (!data->registry_data.mclk_dpm_key_disabled) { 3656 if (data->smc_state_table.mem_boot_level != 3657 data->dpm_table.mem_table.dpm_state.soft_min_level) { 3658 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) 3659 && hwmgr->not_vf) { 3660 socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr); 3661 smum_send_msg_to_smc_with_parameter(hwmgr, 3662 PPSMC_MSG_SetSoftMinSocclkByIndex, 3663 socclk_idx, 3664 NULL); 3665 } else { 3666 smum_send_msg_to_smc_with_parameter(hwmgr, 3667 PPSMC_MSG_SetSoftMinUclkByIndex, 3668 data->smc_state_table.mem_boot_level, 3669 NULL); 3670 } 3671 data->dpm_table.mem_table.dpm_state.soft_min_level = 3672 data->smc_state_table.mem_boot_level; 3673 } 3674 } 3675 3676 if (!hwmgr->not_vf) 3677 return 0; 3678 3679 if (!data->registry_data.socclk_dpm_key_disabled) { 3680 if (data->smc_state_table.soc_boot_level != 3681 data->dpm_table.soc_table.dpm_state.soft_min_level) { 3682 smum_send_msg_to_smc_with_parameter(hwmgr, 3683 PPSMC_MSG_SetSoftMinSocclkByIndex, 3684 data->smc_state_table.soc_boot_level, 3685 NULL); 3686 data->dpm_table.soc_table.dpm_state.soft_min_level = 3687 data->smc_state_table.soc_boot_level; 3688 } 3689 } 3690 3691 return 0; 3692 } 3693 3694 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr) 3695 { 3696 struct vega10_hwmgr *data = hwmgr->backend; 3697 3698 vega10_apply_dal_minimum_voltage_request(hwmgr); 3699 3700 if (!data->registry_data.sclk_dpm_key_disabled) { 3701 if (data->smc_state_table.gfx_max_level != 3702 data->dpm_table.gfx_table.dpm_state.soft_max_level) { 3703 smum_send_msg_to_smc_with_parameter(hwmgr, 3704 PPSMC_MSG_SetSoftMaxGfxclkByIndex, 3705 data->smc_state_table.gfx_max_level, 3706 NULL); 3707 data->dpm_table.gfx_table.dpm_state.soft_max_level = 3708 data->smc_state_table.gfx_max_level; 3709 } 3710 } 3711 3712 if (!data->registry_data.mclk_dpm_key_disabled) { 3713 if (data->smc_state_table.mem_max_level != 3714 data->dpm_table.mem_table.dpm_state.soft_max_level) { 3715 smum_send_msg_to_smc_with_parameter(hwmgr, 3716 PPSMC_MSG_SetSoftMaxUclkByIndex, 3717 data->smc_state_table.mem_max_level, 3718 NULL); 3719 data->dpm_table.mem_table.dpm_state.soft_max_level = 3720 data->smc_state_table.mem_max_level; 3721 } 3722 } 3723 3724 if (!hwmgr->not_vf) 3725 return 0; 3726 3727 if (!data->registry_data.socclk_dpm_key_disabled) { 3728 if (data->smc_state_table.soc_max_level != 3729 data->dpm_table.soc_table.dpm_state.soft_max_level) { 3730 smum_send_msg_to_smc_with_parameter(hwmgr, 3731 PPSMC_MSG_SetSoftMaxSocclkByIndex, 3732 data->smc_state_table.soc_max_level, 3733 NULL); 3734 data->dpm_table.soc_table.dpm_state.soft_max_level = 3735 data->smc_state_table.soc_max_level; 3736 } 3737 } 3738 3739 return 0; 3740 } 3741 3742 static int vega10_generate_dpm_level_enable_mask( 3743 struct pp_hwmgr *hwmgr, const void *input) 3744 { 3745 struct vega10_hwmgr *data = hwmgr->backend; 3746 const struct phm_set_power_state_input *states = 3747 (const struct phm_set_power_state_input *)input; 3748 const struct vega10_power_state *vega10_ps = 3749 cast_const_phw_vega10_power_state(states->pnew_state); 3750 int i; 3751 3752 if (vega10_ps == NULL) 3753 return -EINVAL; 3754 3755 PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps), 3756 "Attempt to Trim DPM States Failed!", 3757 return -1); 3758 3759 data->smc_state_table.gfx_boot_level = 3760 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 3761 data->smc_state_table.gfx_max_level = 3762 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 3763 data->smc_state_table.mem_boot_level = 3764 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 3765 data->smc_state_table.mem_max_level = 3766 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 3767 data->smc_state_table.soc_boot_level = 3768 vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table)); 3769 data->smc_state_table.soc_max_level = 3770 vega10_find_highest_dpm_level(&(data->dpm_table.soc_table)); 3771 3772 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 3773 "Attempt to upload DPM Bootup Levels Failed!", 3774 return -1); 3775 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 3776 "Attempt to upload DPM Max Levels Failed!", 3777 return -1); 3778 for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++) 3779 data->dpm_table.gfx_table.dpm_levels[i].enabled = true; 3780 3781 3782 for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++) 3783 data->dpm_table.mem_table.dpm_levels[i].enabled = true; 3784 3785 for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++) 3786 data->dpm_table.soc_table.dpm_levels[i].enabled = true; 3787 3788 return 0; 3789 } 3790 3791 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 3792 { 3793 struct vega10_hwmgr *data = hwmgr->backend; 3794 3795 if (data->smu_features[GNLD_DPM_VCE].supported) { 3796 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 3797 enable, 3798 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap), 3799 "Attempt to Enable/Disable DPM VCE Failed!", 3800 return -1); 3801 data->smu_features[GNLD_DPM_VCE].enabled = enable; 3802 } 3803 3804 return 0; 3805 } 3806 3807 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) 3808 { 3809 struct vega10_hwmgr *data = hwmgr->backend; 3810 uint32_t low_sclk_interrupt_threshold = 0; 3811 3812 if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && 3813 (data->low_sclk_interrupt_threshold != 0)) { 3814 low_sclk_interrupt_threshold = 3815 data->low_sclk_interrupt_threshold; 3816 3817 data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = 3818 cpu_to_le32(low_sclk_interrupt_threshold); 3819 3820 /* This message will also enable SmcToHost Interrupt */ 3821 smum_send_msg_to_smc_with_parameter(hwmgr, 3822 PPSMC_MSG_SetLowGfxclkInterruptThreshold, 3823 (uint32_t)low_sclk_interrupt_threshold, 3824 NULL); 3825 } 3826 3827 return 0; 3828 } 3829 3830 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr, 3831 const void *input) 3832 { 3833 int tmp_result, result = 0; 3834 struct vega10_hwmgr *data = hwmgr->backend; 3835 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 3836 3837 tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 3838 PP_ASSERT_WITH_CODE(!tmp_result, 3839 "Failed to find DPM states clocks in DPM table!", 3840 result = tmp_result); 3841 3842 tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 3843 PP_ASSERT_WITH_CODE(!tmp_result, 3844 "Failed to populate and upload SCLK MCLK DPM levels!", 3845 result = tmp_result); 3846 3847 tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input); 3848 PP_ASSERT_WITH_CODE(!tmp_result, 3849 "Failed to generate DPM level enabled mask!", 3850 result = tmp_result); 3851 3852 tmp_result = vega10_update_sclk_threshold(hwmgr); 3853 PP_ASSERT_WITH_CODE(!tmp_result, 3854 "Failed to update SCLK threshold!", 3855 result = tmp_result); 3856 3857 result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false); 3858 PP_ASSERT_WITH_CODE(!result, 3859 "Failed to upload PPtable!", return result); 3860 3861 /* 3862 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 3863 * That effectively disables AVFS feature. 3864 */ 3865 if(hwmgr->hardcode_pp_table != NULL) 3866 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 3867 3868 vega10_update_avfs(hwmgr); 3869 3870 /* 3871 * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC. 3872 * That will help to keep AVFS disabled. 3873 */ 3874 data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 3875 3876 return 0; 3877 } 3878 3879 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3880 { 3881 struct pp_power_state *ps; 3882 struct vega10_power_state *vega10_ps; 3883 3884 if (hwmgr == NULL) 3885 return -EINVAL; 3886 3887 ps = hwmgr->request_ps; 3888 3889 if (ps == NULL) 3890 return -EINVAL; 3891 3892 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3893 3894 if (low) 3895 return vega10_ps->performance_levels[0].gfx_clock; 3896 else 3897 return vega10_ps->performance_levels 3898 [vega10_ps->performance_level_count - 1].gfx_clock; 3899 } 3900 3901 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3902 { 3903 struct pp_power_state *ps; 3904 struct vega10_power_state *vega10_ps; 3905 3906 if (hwmgr == NULL) 3907 return -EINVAL; 3908 3909 ps = hwmgr->request_ps; 3910 3911 if (ps == NULL) 3912 return -EINVAL; 3913 3914 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 3915 3916 if (low) 3917 return vega10_ps->performance_levels[0].mem_clock; 3918 else 3919 return vega10_ps->performance_levels 3920 [vega10_ps->performance_level_count-1].mem_clock; 3921 } 3922 3923 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr, 3924 uint32_t *query) 3925 { 3926 uint32_t value; 3927 int ret; 3928 3929 if (!query) 3930 return -EINVAL; 3931 3932 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value); 3933 if (ret) 3934 return ret; 3935 3936 /* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */ 3937 *query = value << 8; 3938 3939 return 0; 3940 } 3941 3942 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 3943 void *value, int *size) 3944 { 3945 struct amdgpu_device *adev = hwmgr->adev; 3946 uint32_t sclk_mhz, mclk_idx, activity_percent = 0; 3947 struct vega10_hwmgr *data = hwmgr->backend; 3948 struct vega10_dpm_table *dpm_table = &data->dpm_table; 3949 int ret = 0; 3950 uint32_t val_vid; 3951 3952 switch (idx) { 3953 case AMDGPU_PP_SENSOR_GFX_SCLK: 3954 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz); 3955 *((uint32_t *)value) = sclk_mhz * 100; 3956 break; 3957 case AMDGPU_PP_SENSOR_GFX_MCLK: 3958 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx); 3959 if (mclk_idx < dpm_table->mem_table.count) { 3960 *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value; 3961 *size = 4; 3962 } else { 3963 ret = -EINVAL; 3964 } 3965 break; 3966 case AMDGPU_PP_SENSOR_GPU_LOAD: 3967 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0, 3968 &activity_percent); 3969 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 3970 *size = 4; 3971 break; 3972 case AMDGPU_PP_SENSOR_GPU_TEMP: 3973 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr); 3974 *size = 4; 3975 break; 3976 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: 3977 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value); 3978 *((uint32_t *)value) = *((uint32_t *)value) * 3979 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3980 *size = 4; 3981 break; 3982 case AMDGPU_PP_SENSOR_MEM_TEMP: 3983 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value); 3984 *((uint32_t *)value) = *((uint32_t *)value) * 3985 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 3986 *size = 4; 3987 break; 3988 case AMDGPU_PP_SENSOR_UVD_POWER: 3989 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 3990 *size = 4; 3991 break; 3992 case AMDGPU_PP_SENSOR_VCE_POWER: 3993 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 3994 *size = 4; 3995 break; 3996 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: 3997 ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value); 3998 break; 3999 case AMDGPU_PP_SENSOR_VDDGFX: 4000 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) & 4001 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >> 4002 SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT; 4003 *((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid); 4004 return 0; 4005 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: 4006 ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value); 4007 if (!ret) 4008 *size = 8; 4009 break; 4010 default: 4011 ret = -EOPNOTSUPP; 4012 break; 4013 } 4014 4015 return ret; 4016 } 4017 4018 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr, 4019 bool has_disp) 4020 { 4021 smum_send_msg_to_smc_with_parameter(hwmgr, 4022 PPSMC_MSG_SetUclkFastSwitch, 4023 has_disp ? 1 : 0, 4024 NULL); 4025 } 4026 4027 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 4028 struct pp_display_clock_request *clock_req) 4029 { 4030 int result = 0; 4031 enum amd_pp_clock_type clk_type = clock_req->clock_type; 4032 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 4033 DSPCLK_e clk_select = 0; 4034 uint32_t clk_request = 0; 4035 4036 switch (clk_type) { 4037 case amd_pp_dcef_clock: 4038 clk_select = DSPCLK_DCEFCLK; 4039 break; 4040 case amd_pp_disp_clock: 4041 clk_select = DSPCLK_DISPCLK; 4042 break; 4043 case amd_pp_pixel_clock: 4044 clk_select = DSPCLK_PIXCLK; 4045 break; 4046 case amd_pp_phy_clock: 4047 clk_select = DSPCLK_PHYCLK; 4048 break; 4049 default: 4050 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 4051 result = -1; 4052 break; 4053 } 4054 4055 if (!result) { 4056 clk_request = (clk_freq << 16) | clk_select; 4057 smum_send_msg_to_smc_with_parameter(hwmgr, 4058 PPSMC_MSG_RequestDisplayClockByFreq, 4059 clk_request, 4060 NULL); 4061 } 4062 4063 return result; 4064 } 4065 4066 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr, 4067 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table, 4068 uint32_t frequency) 4069 { 4070 uint8_t count; 4071 uint8_t i; 4072 4073 if (mclk_table == NULL || mclk_table->count == 0) 4074 return 0; 4075 4076 count = (uint8_t)(mclk_table->count); 4077 4078 for(i = 0; i < count; i++) { 4079 if(mclk_table->entries[i].clk >= frequency) 4080 return i; 4081 } 4082 4083 return i-1; 4084 } 4085 4086 static int vega10_notify_smc_display_config_after_ps_adjustment( 4087 struct pp_hwmgr *hwmgr) 4088 { 4089 struct vega10_hwmgr *data = hwmgr->backend; 4090 struct vega10_single_dpm_table *dpm_table = 4091 &data->dpm_table.dcef_table; 4092 struct phm_ppt_v2_information *table_info = 4093 (struct phm_ppt_v2_information *)hwmgr->pptable; 4094 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk; 4095 uint32_t idx; 4096 struct PP_Clocks min_clocks = {0}; 4097 uint32_t i; 4098 struct pp_display_clock_request clock_req; 4099 4100 if ((hwmgr->display_config->num_display > 1) && 4101 !hwmgr->display_config->multi_monitor_in_sync && 4102 !hwmgr->display_config->nb_pstate_switch_disable) 4103 vega10_notify_smc_display_change(hwmgr, false); 4104 else 4105 vega10_notify_smc_display_change(hwmgr, true); 4106 4107 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 4108 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; 4109 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 4110 4111 for (i = 0; i < dpm_table->count; i++) { 4112 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) 4113 break; 4114 } 4115 4116 if (i < dpm_table->count) { 4117 clock_req.clock_type = amd_pp_dcef_clock; 4118 clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10; 4119 if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) { 4120 smum_send_msg_to_smc_with_parameter( 4121 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk, 4122 min_clocks.dcefClockInSR / 100, 4123 NULL); 4124 } else { 4125 pr_info("Attempt to set Hard Min for DCEFCLK Failed!"); 4126 } 4127 } else { 4128 pr_debug("Cannot find requested DCEFCLK!"); 4129 } 4130 4131 if (min_clocks.memoryClock != 0) { 4132 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); 4133 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx, 4134 NULL); 4135 data->dpm_table.mem_table.dpm_state.soft_min_level= idx; 4136 } 4137 4138 return 0; 4139 } 4140 4141 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr) 4142 { 4143 struct vega10_hwmgr *data = hwmgr->backend; 4144 4145 data->smc_state_table.gfx_boot_level = 4146 data->smc_state_table.gfx_max_level = 4147 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4148 data->smc_state_table.mem_boot_level = 4149 data->smc_state_table.mem_max_level = 4150 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4151 4152 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4153 "Failed to upload boot level to highest!", 4154 return -1); 4155 4156 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4157 "Failed to upload dpm max level to highest!", 4158 return -1); 4159 4160 return 0; 4161 } 4162 4163 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr) 4164 { 4165 struct vega10_hwmgr *data = hwmgr->backend; 4166 4167 data->smc_state_table.gfx_boot_level = 4168 data->smc_state_table.gfx_max_level = 4169 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4170 data->smc_state_table.mem_boot_level = 4171 data->smc_state_table.mem_max_level = 4172 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4173 4174 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4175 "Failed to upload boot level to highest!", 4176 return -1); 4177 4178 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4179 "Failed to upload dpm max level to highest!", 4180 return -1); 4181 4182 return 0; 4183 4184 } 4185 4186 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 4187 { 4188 struct vega10_hwmgr *data = hwmgr->backend; 4189 4190 data->smc_state_table.gfx_boot_level = 4191 vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table)); 4192 data->smc_state_table.gfx_max_level = 4193 vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table)); 4194 data->smc_state_table.mem_boot_level = 4195 vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table)); 4196 data->smc_state_table.mem_max_level = 4197 vega10_find_highest_dpm_level(&(data->dpm_table.mem_table)); 4198 4199 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4200 "Failed to upload DPM Bootup Levels!", 4201 return -1); 4202 4203 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4204 "Failed to upload DPM Max Levels!", 4205 return -1); 4206 return 0; 4207 } 4208 4209 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 4210 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 4211 { 4212 struct phm_ppt_v2_information *table_info = 4213 (struct phm_ppt_v2_information *)(hwmgr->pptable); 4214 4215 if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL && 4216 table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL && 4217 table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) { 4218 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; 4219 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; 4220 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; 4221 } 4222 4223 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 4224 *sclk_mask = 0; 4225 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) { 4226 *mclk_mask = 0; 4227 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) { 4228 /* under vega10 pp one vf mode, the gfx clk dpm need be lower 4229 * to level-4 due to the limited power 4230 */ 4231 if (hwmgr->pp_one_vf) 4232 *sclk_mask = 4; 4233 else 4234 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 4235 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; 4236 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; 4237 } 4238 4239 return 0; 4240 } 4241 4242 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 4243 { 4244 if (!hwmgr->not_vf) 4245 return; 4246 4247 switch (mode) { 4248 case AMD_FAN_CTRL_NONE: 4249 vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 4250 break; 4251 case AMD_FAN_CTRL_MANUAL: 4252 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4253 vega10_fan_ctrl_stop_smc_fan_control(hwmgr); 4254 break; 4255 case AMD_FAN_CTRL_AUTO: 4256 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) 4257 vega10_fan_ctrl_start_smc_fan_control(hwmgr); 4258 break; 4259 default: 4260 break; 4261 } 4262 } 4263 4264 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr, 4265 enum pp_clock_type type, uint32_t mask) 4266 { 4267 struct vega10_hwmgr *data = hwmgr->backend; 4268 4269 switch (type) { 4270 case PP_SCLK: 4271 data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0; 4272 data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0; 4273 4274 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4275 "Failed to upload boot level to lowest!", 4276 return -EINVAL); 4277 4278 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4279 "Failed to upload dpm max level to highest!", 4280 return -EINVAL); 4281 break; 4282 4283 case PP_MCLK: 4284 data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0; 4285 data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0; 4286 4287 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4288 "Failed to upload boot level to lowest!", 4289 return -EINVAL); 4290 4291 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4292 "Failed to upload dpm max level to highest!", 4293 return -EINVAL); 4294 4295 break; 4296 4297 case PP_SOCCLK: 4298 data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0; 4299 data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0; 4300 4301 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr), 4302 "Failed to upload boot level to lowest!", 4303 return -EINVAL); 4304 4305 PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr), 4306 "Failed to upload dpm max level to highest!", 4307 return -EINVAL); 4308 4309 break; 4310 4311 case PP_DCEFCLK: 4312 pr_info("Setting DCEFCLK min/max dpm level is not supported!\n"); 4313 break; 4314 4315 case PP_PCIE: 4316 default: 4317 break; 4318 } 4319 4320 return 0; 4321 } 4322 4323 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 4324 enum amd_dpm_forced_level level) 4325 { 4326 int ret = 0; 4327 uint32_t sclk_mask = 0; 4328 uint32_t mclk_mask = 0; 4329 uint32_t soc_mask = 0; 4330 4331 switch (level) { 4332 case AMD_DPM_FORCED_LEVEL_HIGH: 4333 ret = vega10_force_dpm_highest(hwmgr); 4334 break; 4335 case AMD_DPM_FORCED_LEVEL_LOW: 4336 ret = vega10_force_dpm_lowest(hwmgr); 4337 break; 4338 case AMD_DPM_FORCED_LEVEL_AUTO: 4339 ret = vega10_unforce_dpm_levels(hwmgr); 4340 break; 4341 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 4342 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 4343 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 4344 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 4345 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 4346 if (ret) 4347 return ret; 4348 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 4349 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 4350 break; 4351 case AMD_DPM_FORCED_LEVEL_MANUAL: 4352 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 4353 default: 4354 break; 4355 } 4356 4357 if (!hwmgr->not_vf) 4358 return ret; 4359 4360 if (!ret) { 4361 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4362 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE); 4363 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 4364 vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO); 4365 } 4366 4367 return ret; 4368 } 4369 4370 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr) 4371 { 4372 struct vega10_hwmgr *data = hwmgr->backend; 4373 4374 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false) 4375 return AMD_FAN_CTRL_MANUAL; 4376 else 4377 return AMD_FAN_CTRL_AUTO; 4378 } 4379 4380 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr, 4381 struct amd_pp_simple_clock_info *info) 4382 { 4383 struct phm_ppt_v2_information *table_info = 4384 (struct phm_ppt_v2_information *)hwmgr->pptable; 4385 struct phm_clock_and_voltage_limits *max_limits = 4386 &table_info->max_clock_voltage_on_ac; 4387 4388 info->engine_max_clock = max_limits->sclk; 4389 info->memory_max_clock = max_limits->mclk; 4390 4391 return 0; 4392 } 4393 4394 static void vega10_get_sclks(struct pp_hwmgr *hwmgr, 4395 struct pp_clock_levels_with_latency *clocks) 4396 { 4397 struct phm_ppt_v2_information *table_info = 4398 (struct phm_ppt_v2_information *)hwmgr->pptable; 4399 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4400 table_info->vdd_dep_on_sclk; 4401 uint32_t i; 4402 4403 clocks->num_levels = 0; 4404 for (i = 0; i < dep_table->count; i++) { 4405 if (dep_table->entries[i].clk) { 4406 clocks->data[clocks->num_levels].clocks_in_khz = 4407 dep_table->entries[i].clk * 10; 4408 clocks->num_levels++; 4409 } 4410 } 4411 4412 } 4413 4414 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr, 4415 struct pp_clock_levels_with_latency *clocks) 4416 { 4417 struct phm_ppt_v2_information *table_info = 4418 (struct phm_ppt_v2_information *)hwmgr->pptable; 4419 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4420 table_info->vdd_dep_on_mclk; 4421 struct vega10_hwmgr *data = hwmgr->backend; 4422 uint32_t j = 0; 4423 uint32_t i; 4424 4425 for (i = 0; i < dep_table->count; i++) { 4426 if (dep_table->entries[i].clk) { 4427 4428 clocks->data[j].clocks_in_khz = 4429 dep_table->entries[i].clk * 10; 4430 data->mclk_latency_table.entries[j].frequency = 4431 dep_table->entries[i].clk; 4432 clocks->data[j].latency_in_us = 4433 data->mclk_latency_table.entries[j].latency = 25; 4434 j++; 4435 } 4436 } 4437 clocks->num_levels = data->mclk_latency_table.count = j; 4438 } 4439 4440 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr, 4441 struct pp_clock_levels_with_latency *clocks) 4442 { 4443 struct phm_ppt_v2_information *table_info = 4444 (struct phm_ppt_v2_information *)hwmgr->pptable; 4445 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4446 table_info->vdd_dep_on_dcefclk; 4447 uint32_t i; 4448 4449 for (i = 0; i < dep_table->count; i++) { 4450 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4451 clocks->data[i].latency_in_us = 0; 4452 clocks->num_levels++; 4453 } 4454 } 4455 4456 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr, 4457 struct pp_clock_levels_with_latency *clocks) 4458 { 4459 struct phm_ppt_v2_information *table_info = 4460 (struct phm_ppt_v2_information *)hwmgr->pptable; 4461 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = 4462 table_info->vdd_dep_on_socclk; 4463 uint32_t i; 4464 4465 for (i = 0; i < dep_table->count; i++) { 4466 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4467 clocks->data[i].latency_in_us = 0; 4468 clocks->num_levels++; 4469 } 4470 } 4471 4472 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 4473 enum amd_pp_clock_type type, 4474 struct pp_clock_levels_with_latency *clocks) 4475 { 4476 switch (type) { 4477 case amd_pp_sys_clock: 4478 vega10_get_sclks(hwmgr, clocks); 4479 break; 4480 case amd_pp_mem_clock: 4481 vega10_get_memclocks(hwmgr, clocks); 4482 break; 4483 case amd_pp_dcef_clock: 4484 vega10_get_dcefclocks(hwmgr, clocks); 4485 break; 4486 case amd_pp_soc_clock: 4487 vega10_get_socclocks(hwmgr, clocks); 4488 break; 4489 default: 4490 return -1; 4491 } 4492 4493 return 0; 4494 } 4495 4496 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 4497 enum amd_pp_clock_type type, 4498 struct pp_clock_levels_with_voltage *clocks) 4499 { 4500 struct phm_ppt_v2_information *table_info = 4501 (struct phm_ppt_v2_information *)hwmgr->pptable; 4502 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 4503 uint32_t i; 4504 4505 switch (type) { 4506 case amd_pp_mem_clock: 4507 dep_table = table_info->vdd_dep_on_mclk; 4508 break; 4509 case amd_pp_dcef_clock: 4510 dep_table = table_info->vdd_dep_on_dcefclk; 4511 break; 4512 case amd_pp_disp_clock: 4513 dep_table = table_info->vdd_dep_on_dispclk; 4514 break; 4515 case amd_pp_pixel_clock: 4516 dep_table = table_info->vdd_dep_on_pixclk; 4517 break; 4518 case amd_pp_phy_clock: 4519 dep_table = table_info->vdd_dep_on_phyclk; 4520 break; 4521 default: 4522 return -1; 4523 } 4524 4525 for (i = 0; i < dep_table->count; i++) { 4526 clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10; 4527 clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table-> 4528 entries[dep_table->entries[i].vddInd].us_vdd); 4529 clocks->num_levels++; 4530 } 4531 4532 if (i < dep_table->count) 4533 return -1; 4534 4535 return 0; 4536 } 4537 4538 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 4539 void *clock_range) 4540 { 4541 struct vega10_hwmgr *data = hwmgr->backend; 4542 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; 4543 Watermarks_t *table = &(data->smc_state_table.water_marks_table); 4544 4545 if (!data->registry_data.disable_water_mark) { 4546 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 4547 data->water_marks_bitmap = WaterMarksExist; 4548 } 4549 4550 return 0; 4551 } 4552 4553 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 4554 { 4555 static const char *ppfeature_name[] = { 4556 "DPM_PREFETCHER", 4557 "GFXCLK_DPM", 4558 "UCLK_DPM", 4559 "SOCCLK_DPM", 4560 "UVD_DPM", 4561 "VCE_DPM", 4562 "ULV", 4563 "MP0CLK_DPM", 4564 "LINK_DPM", 4565 "DCEFCLK_DPM", 4566 "AVFS", 4567 "GFXCLK_DS", 4568 "SOCCLK_DS", 4569 "LCLK_DS", 4570 "PPT", 4571 "TDC", 4572 "THERMAL", 4573 "GFX_PER_CU_CG", 4574 "RM", 4575 "DCEFCLK_DS", 4576 "ACDC", 4577 "VR0HOT", 4578 "VR1HOT", 4579 "FW_CTF", 4580 "LED_DISPLAY", 4581 "FAN_CONTROL", 4582 "FAST_PPT", 4583 "DIDT", 4584 "ACG", 4585 "PCC_LIMIT"}; 4586 static const char *output_title[] = { 4587 "FEATURES", 4588 "BITMASK", 4589 "ENABLEMENT"}; 4590 uint64_t features_enabled; 4591 int i; 4592 int ret = 0; 4593 int size = 0; 4594 4595 phm_get_sysfs_buf(&buf, &size); 4596 4597 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4598 PP_ASSERT_WITH_CODE(!ret, 4599 "[EnableAllSmuFeatures] Failed to get enabled smc features!", 4600 return ret); 4601 4602 size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled); 4603 size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n", 4604 output_title[0], 4605 output_title[1], 4606 output_title[2]); 4607 for (i = 0; i < GNLD_FEATURES_MAX; i++) { 4608 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n", 4609 ppfeature_name[i], 4610 1ULL << i, 4611 (features_enabled & (1ULL << i)) ? "Y" : "N"); 4612 } 4613 4614 return size; 4615 } 4616 4617 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) 4618 { 4619 uint64_t features_enabled; 4620 uint64_t features_to_enable; 4621 uint64_t features_to_disable; 4622 int ret = 0; 4623 4624 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX)) 4625 return -EINVAL; 4626 4627 ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled); 4628 if (ret) 4629 return ret; 4630 4631 features_to_disable = 4632 features_enabled & ~new_ppfeature_masks; 4633 features_to_enable = 4634 ~features_enabled & new_ppfeature_masks; 4635 4636 pr_debug("features_to_disable 0x%llx\n", features_to_disable); 4637 pr_debug("features_to_enable 0x%llx\n", features_to_enable); 4638 4639 if (features_to_disable) { 4640 ret = vega10_enable_smc_features(hwmgr, false, features_to_disable); 4641 if (ret) 4642 return ret; 4643 } 4644 4645 if (features_to_enable) { 4646 ret = vega10_enable_smc_features(hwmgr, true, features_to_enable); 4647 if (ret) 4648 return ret; 4649 } 4650 4651 return 0; 4652 } 4653 4654 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) 4655 { 4656 struct amdgpu_device *adev = hwmgr->adev; 4657 4658 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & 4659 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) 4660 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; 4661 } 4662 4663 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) 4664 { 4665 struct amdgpu_device *adev = hwmgr->adev; 4666 4667 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & 4668 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) 4669 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 4670 } 4671 4672 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr, 4673 enum pp_clock_type type, char *buf, int *offset) 4674 { 4675 struct vega10_hwmgr *data = hwmgr->backend; 4676 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4677 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4678 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4679 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4680 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4681 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4682 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4683 4684 uint32_t i, now, count = 0; 4685 int ret = 0; 4686 4687 switch (type) { 4688 case PP_SCLK: 4689 if (data->registry_data.sclk_dpm_key_disabled) 4690 return -EOPNOTSUPP; 4691 4692 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4693 if (unlikely(ret != 0)) 4694 return ret; 4695 4696 if (hwmgr->pp_one_vf && 4697 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4698 count = 5; 4699 else 4700 count = sclk_table->count; 4701 for (i = 0; i < count; i++) 4702 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4703 i, sclk_table->dpm_levels[i].value / 100, 4704 (i == now) ? "*" : ""); 4705 break; 4706 case PP_MCLK: 4707 if (data->registry_data.mclk_dpm_key_disabled) 4708 return -EOPNOTSUPP; 4709 4710 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4711 if (unlikely(ret != 0)) 4712 return ret; 4713 4714 for (i = 0; i < mclk_table->count; i++) 4715 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4716 i, mclk_table->dpm_levels[i].value / 100, 4717 (i == now) ? "*" : ""); 4718 break; 4719 case PP_SOCCLK: 4720 if (data->registry_data.socclk_dpm_key_disabled) 4721 return -EOPNOTSUPP; 4722 4723 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4724 if (unlikely(ret != 0)) 4725 return ret; 4726 4727 for (i = 0; i < soc_table->count; i++) 4728 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4729 i, soc_table->dpm_levels[i].value / 100, 4730 (i == now) ? "*" : ""); 4731 break; 4732 case PP_DCEFCLK: 4733 if (data->registry_data.dcefclk_dpm_key_disabled) 4734 return -EOPNOTSUPP; 4735 4736 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4737 PPSMC_MSG_GetClockFreqMHz, 4738 CLK_DCEFCLK, &now); 4739 if (unlikely(ret != 0)) 4740 return ret; 4741 4742 for (i = 0; i < dcef_table->count; i++) 4743 *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", 4744 i, dcef_table->dpm_levels[i].value / 100, 4745 (dcef_table->dpm_levels[i].value / 100 == now) ? 4746 "*" : ""); 4747 break; 4748 case PP_PCIE: 4749 current_gen_speed = 4750 vega10_get_current_pcie_link_speed_level(hwmgr); 4751 current_lane_width = 4752 vega10_get_current_pcie_link_width_level(hwmgr); 4753 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4754 gen_speed = pptable->PcieGenSpeed[i]; 4755 lane_width = pptable->PcieLaneCount[i]; 4756 4757 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i, 4758 (gen_speed == 0) ? "2.5GT/s," : 4759 (gen_speed == 1) ? "5.0GT/s," : 4760 (gen_speed == 2) ? "8.0GT/s," : 4761 (gen_speed == 3) ? "16.0GT/s," : "", 4762 (lane_width == 1) ? "x1" : 4763 (lane_width == 2) ? "x2" : 4764 (lane_width == 3) ? "x4" : 4765 (lane_width == 4) ? "x8" : 4766 (lane_width == 5) ? "x12" : 4767 (lane_width == 6) ? "x16" : "", 4768 (current_gen_speed == gen_speed) && 4769 (current_lane_width == lane_width) ? 4770 "*" : ""); 4771 } 4772 break; 4773 4774 case OD_SCLK: 4775 if (!hwmgr->od_enabled) 4776 return -EOPNOTSUPP; 4777 4778 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); 4779 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4780 for (i = 0; i < podn_vdd_dep->count; i++) 4781 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4782 i, podn_vdd_dep->entries[i].clk / 100, 4783 podn_vdd_dep->entries[i].vddc); 4784 break; 4785 case OD_MCLK: 4786 if (!hwmgr->od_enabled) 4787 return -EOPNOTSUPP; 4788 4789 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); 4790 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4791 for (i = 0; i < podn_vdd_dep->count; i++) 4792 *offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n", 4793 i, podn_vdd_dep->entries[i].clk/100, 4794 podn_vdd_dep->entries[i].vddc); 4795 break; 4796 case OD_RANGE: 4797 if (!hwmgr->od_enabled) 4798 return -EOPNOTSUPP; 4799 4800 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE"); 4801 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n", 4802 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4803 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4804 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n", 4805 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4806 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4807 *offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n", 4808 data->odn_dpm_table.min_vddc, 4809 data->odn_dpm_table.max_vddc); 4810 break; 4811 default: 4812 ret = -ENOENT; 4813 break; 4814 } 4815 return ret; 4816 } 4817 4818 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, 4819 enum pp_clock_type type, char *buf) 4820 { 4821 struct vega10_hwmgr *data = hwmgr->backend; 4822 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 4823 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 4824 struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); 4825 struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); 4826 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; 4827 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; 4828 PPTable_t *pptable = &(data->smc_state_table.pp_table); 4829 4830 int i, ret, now, size = 0, count = 0; 4831 4832 switch (type) { 4833 case PP_SCLK: 4834 if (data->registry_data.sclk_dpm_key_disabled) 4835 break; 4836 4837 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); 4838 if (ret) 4839 break; 4840 4841 if (hwmgr->pp_one_vf && 4842 (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) 4843 count = 5; 4844 else 4845 count = sclk_table->count; 4846 for (i = 0; i < count; i++) 4847 size += sprintf(buf + size, "%d: %uMhz %s\n", 4848 i, sclk_table->dpm_levels[i].value / 100, 4849 (i == now) ? "*" : ""); 4850 break; 4851 case PP_MCLK: 4852 if (data->registry_data.mclk_dpm_key_disabled) 4853 break; 4854 4855 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); 4856 if (ret) 4857 break; 4858 4859 for (i = 0; i < mclk_table->count; i++) 4860 size += sprintf(buf + size, "%d: %uMhz %s\n", 4861 i, mclk_table->dpm_levels[i].value / 100, 4862 (i == now) ? "*" : ""); 4863 break; 4864 case PP_SOCCLK: 4865 if (data->registry_data.socclk_dpm_key_disabled) 4866 break; 4867 4868 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); 4869 if (ret) 4870 break; 4871 4872 for (i = 0; i < soc_table->count; i++) 4873 size += sprintf(buf + size, "%d: %uMhz %s\n", 4874 i, soc_table->dpm_levels[i].value / 100, 4875 (i == now) ? "*" : ""); 4876 break; 4877 case PP_DCEFCLK: 4878 if (data->registry_data.dcefclk_dpm_key_disabled) 4879 break; 4880 4881 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 4882 PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now); 4883 if (ret) 4884 break; 4885 4886 for (i = 0; i < dcef_table->count; i++) 4887 size += sprintf(buf + size, "%d: %uMhz %s\n", 4888 i, dcef_table->dpm_levels[i].value / 100, 4889 (dcef_table->dpm_levels[i].value / 100 == now) ? 4890 "*" : ""); 4891 break; 4892 case PP_PCIE: 4893 current_gen_speed = 4894 vega10_get_current_pcie_link_speed_level(hwmgr); 4895 current_lane_width = 4896 vega10_get_current_pcie_link_width_level(hwmgr); 4897 for (i = 0; i < NUM_LINK_LEVELS; i++) { 4898 gen_speed = pptable->PcieGenSpeed[i]; 4899 lane_width = pptable->PcieLaneCount[i]; 4900 4901 size += sprintf(buf + size, "%d: %s %s %s\n", i, 4902 (gen_speed == 0) ? "2.5GT/s," : 4903 (gen_speed == 1) ? "5.0GT/s," : 4904 (gen_speed == 2) ? "8.0GT/s," : 4905 (gen_speed == 3) ? "16.0GT/s," : "", 4906 (lane_width == 1) ? "x1" : 4907 (lane_width == 2) ? "x2" : 4908 (lane_width == 3) ? "x4" : 4909 (lane_width == 4) ? "x8" : 4910 (lane_width == 5) ? "x12" : 4911 (lane_width == 6) ? "x16" : "", 4912 (current_gen_speed == gen_speed) && 4913 (current_lane_width == lane_width) ? 4914 "*" : ""); 4915 } 4916 break; 4917 4918 case OD_SCLK: 4919 if (hwmgr->od_enabled) { 4920 size += sprintf(buf + size, "%s:\n", "OD_SCLK"); 4921 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 4922 for (i = 0; i < podn_vdd_dep->count; i++) 4923 size += sprintf(buf + size, "%d: %10uMhz %10umV\n", 4924 i, podn_vdd_dep->entries[i].clk / 100, 4925 podn_vdd_dep->entries[i].vddc); 4926 } 4927 break; 4928 case OD_MCLK: 4929 if (hwmgr->od_enabled) { 4930 size += sprintf(buf + size, "%s:\n", "OD_MCLK"); 4931 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 4932 for (i = 0; i < podn_vdd_dep->count; i++) 4933 size += sprintf(buf + size, "%d: %10uMhz %10umV\n", 4934 i, podn_vdd_dep->entries[i].clk/100, 4935 podn_vdd_dep->entries[i].vddc); 4936 } 4937 break; 4938 case OD_RANGE: 4939 if (hwmgr->od_enabled) { 4940 size += sprintf(buf + size, "%s:\n", "OD_RANGE"); 4941 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 4942 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, 4943 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4944 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", 4945 data->golden_dpm_table.mem_table.dpm_levels[0].value/100, 4946 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4947 size += sprintf(buf + size, "VDDC: %7umV %11umV\n", 4948 data->odn_dpm_table.min_vddc, 4949 data->odn_dpm_table.max_vddc); 4950 } 4951 break; 4952 default: 4953 break; 4954 } 4955 return size; 4956 } 4957 4958 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4959 { 4960 struct vega10_hwmgr *data = hwmgr->backend; 4961 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); 4962 int result = 0; 4963 4964 if ((data->water_marks_bitmap & WaterMarksExist) && 4965 !(data->water_marks_bitmap & WaterMarksLoaded)) { 4966 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); 4967 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL); 4968 data->water_marks_bitmap |= WaterMarksLoaded; 4969 } 4970 4971 if (data->water_marks_bitmap & WaterMarksLoaded) { 4972 smum_send_msg_to_smc_with_parameter(hwmgr, 4973 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display, 4974 NULL); 4975 } 4976 4977 return result; 4978 } 4979 4980 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 4981 { 4982 struct vega10_hwmgr *data = hwmgr->backend; 4983 4984 if (data->smu_features[GNLD_DPM_UVD].supported) { 4985 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 4986 enable, 4987 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap), 4988 "Attempt to Enable/Disable DPM UVD Failed!", 4989 return -1); 4990 data->smu_features[GNLD_DPM_UVD].enabled = enable; 4991 } 4992 return 0; 4993 } 4994 4995 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) 4996 { 4997 struct vega10_hwmgr *data = hwmgr->backend; 4998 4999 data->vce_power_gated = bgate; 5000 vega10_enable_disable_vce_dpm(hwmgr, !bgate); 5001 } 5002 5003 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 5004 { 5005 struct vega10_hwmgr *data = hwmgr->backend; 5006 5007 data->uvd_power_gated = bgate; 5008 vega10_enable_disable_uvd_dpm(hwmgr, !bgate); 5009 } 5010 5011 static inline bool vega10_are_power_levels_equal( 5012 const struct vega10_performance_level *pl1, 5013 const struct vega10_performance_level *pl2) 5014 { 5015 return ((pl1->soc_clock == pl2->soc_clock) && 5016 (pl1->gfx_clock == pl2->gfx_clock) && 5017 (pl1->mem_clock == pl2->mem_clock)); 5018 } 5019 5020 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr, 5021 const struct pp_hw_power_state *pstate1, 5022 const struct pp_hw_power_state *pstate2, bool *equal) 5023 { 5024 const struct vega10_power_state *vega10_psa; 5025 const struct vega10_power_state *vega10_psb; 5026 int i; 5027 5028 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 5029 return -EINVAL; 5030 5031 vega10_psa = cast_const_phw_vega10_power_state(pstate1); 5032 vega10_psb = cast_const_phw_vega10_power_state(pstate2); 5033 if (vega10_psa == NULL || vega10_psb == NULL) 5034 return -EINVAL; 5035 5036 /* If the two states don't even have the same number of performance levels 5037 * they cannot be the same state. 5038 */ 5039 if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) { 5040 *equal = false; 5041 return 0; 5042 } 5043 5044 for (i = 0; i < vega10_psa->performance_level_count; i++) { 5045 if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]), 5046 &(vega10_psb->performance_levels[i]))) { 5047 /* If we have found even one performance level pair 5048 * that is different the states are different. 5049 */ 5050 *equal = false; 5051 return 0; 5052 } 5053 } 5054 5055 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 5056 *equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) && 5057 (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk)); 5058 *equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) && 5059 (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk)); 5060 *equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold); 5061 5062 return 0; 5063 } 5064 5065 static bool 5066 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 5067 { 5068 struct vega10_hwmgr *data = hwmgr->backend; 5069 bool is_update_required = false; 5070 5071 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 5072 is_update_required = true; 5073 5074 if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) { 5075 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr) 5076 is_update_required = true; 5077 } 5078 5079 return is_update_required; 5080 } 5081 5082 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 5083 { 5084 int tmp_result, result = 0; 5085 5086 if (!hwmgr->not_vf) 5087 return 0; 5088 5089 if (PP_CAP(PHM_PlatformCaps_ThermalController)) 5090 vega10_disable_thermal_protection(hwmgr); 5091 5092 tmp_result = vega10_disable_power_containment(hwmgr); 5093 PP_ASSERT_WITH_CODE((tmp_result == 0), 5094 "Failed to disable power containment!", result = tmp_result); 5095 5096 tmp_result = vega10_disable_didt_config(hwmgr); 5097 PP_ASSERT_WITH_CODE((tmp_result == 0), 5098 "Failed to disable didt config!", result = tmp_result); 5099 5100 tmp_result = vega10_avfs_enable(hwmgr, false); 5101 PP_ASSERT_WITH_CODE((tmp_result == 0), 5102 "Failed to disable AVFS!", result = tmp_result); 5103 5104 tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES); 5105 PP_ASSERT_WITH_CODE((tmp_result == 0), 5106 "Failed to stop DPM!", result = tmp_result); 5107 5108 tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr); 5109 PP_ASSERT_WITH_CODE((tmp_result == 0), 5110 "Failed to disable deep sleep!", result = tmp_result); 5111 5112 tmp_result = vega10_disable_ulv(hwmgr); 5113 PP_ASSERT_WITH_CODE((tmp_result == 0), 5114 "Failed to disable ulv!", result = tmp_result); 5115 5116 tmp_result = vega10_acg_disable(hwmgr); 5117 PP_ASSERT_WITH_CODE((tmp_result == 0), 5118 "Failed to disable acg!", result = tmp_result); 5119 5120 vega10_enable_disable_PCC_limit_feature(hwmgr, false); 5121 return result; 5122 } 5123 5124 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr) 5125 { 5126 struct vega10_hwmgr *data = hwmgr->backend; 5127 int result; 5128 5129 result = vega10_disable_dpm_tasks(hwmgr); 5130 PP_ASSERT_WITH_CODE((0 == result), 5131 "[disable_dpm_tasks] Failed to disable DPM!", 5132 ); 5133 data->water_marks_bitmap &= ~(WaterMarksLoaded); 5134 5135 return result; 5136 } 5137 5138 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr) 5139 { 5140 struct vega10_hwmgr *data = hwmgr->backend; 5141 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); 5142 struct vega10_single_dpm_table *golden_sclk_table = 5143 &(data->golden_dpm_table.gfx_table); 5144 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 5145 int golden_value = golden_sclk_table->dpm_levels 5146 [golden_sclk_table->count - 1].value; 5147 5148 value -= golden_value; 5149 value = DIV_ROUND_UP(value * 100, golden_value); 5150 5151 return value; 5152 } 5153 5154 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5155 { 5156 struct vega10_hwmgr *data = hwmgr->backend; 5157 struct vega10_single_dpm_table *golden_sclk_table = 5158 &(data->golden_dpm_table.gfx_table); 5159 struct pp_power_state *ps; 5160 struct vega10_power_state *vega10_ps; 5161 5162 ps = hwmgr->request_ps; 5163 5164 if (ps == NULL) 5165 return -EINVAL; 5166 5167 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5168 if (vega10_ps == NULL) 5169 return -EINVAL; 5170 5171 vega10_ps->performance_levels 5172 [vega10_ps->performance_level_count - 1].gfx_clock = 5173 golden_sclk_table->dpm_levels 5174 [golden_sclk_table->count - 1].value * 5175 value / 100 + 5176 golden_sclk_table->dpm_levels 5177 [golden_sclk_table->count - 1].value; 5178 5179 if (vega10_ps->performance_levels 5180 [vega10_ps->performance_level_count - 1].gfx_clock > 5181 hwmgr->platform_descriptor.overdriveLimit.engineClock) { 5182 vega10_ps->performance_levels 5183 [vega10_ps->performance_level_count - 1].gfx_clock = 5184 hwmgr->platform_descriptor.overdriveLimit.engineClock; 5185 pr_warn("max sclk supported by vbios is %d\n", 5186 hwmgr->platform_descriptor.overdriveLimit.engineClock); 5187 } 5188 return 0; 5189 } 5190 5191 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr) 5192 { 5193 struct vega10_hwmgr *data = hwmgr->backend; 5194 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); 5195 struct vega10_single_dpm_table *golden_mclk_table = 5196 &(data->golden_dpm_table.mem_table); 5197 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5198 int golden_value = golden_mclk_table->dpm_levels 5199 [golden_mclk_table->count - 1].value; 5200 5201 value -= golden_value; 5202 value = DIV_ROUND_UP(value * 100, golden_value); 5203 5204 return value; 5205 } 5206 5207 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5208 { 5209 struct vega10_hwmgr *data = hwmgr->backend; 5210 struct vega10_single_dpm_table *golden_mclk_table = 5211 &(data->golden_dpm_table.mem_table); 5212 struct pp_power_state *ps; 5213 struct vega10_power_state *vega10_ps; 5214 5215 ps = hwmgr->request_ps; 5216 5217 if (ps == NULL) 5218 return -EINVAL; 5219 5220 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5221 if (vega10_ps == NULL) 5222 return -EINVAL; 5223 5224 vega10_ps->performance_levels 5225 [vega10_ps->performance_level_count - 1].mem_clock = 5226 golden_mclk_table->dpm_levels 5227 [golden_mclk_table->count - 1].value * 5228 value / 100 + 5229 golden_mclk_table->dpm_levels 5230 [golden_mclk_table->count - 1].value; 5231 5232 if (vega10_ps->performance_levels 5233 [vega10_ps->performance_level_count - 1].mem_clock > 5234 hwmgr->platform_descriptor.overdriveLimit.memoryClock) { 5235 vega10_ps->performance_levels 5236 [vega10_ps->performance_level_count - 1].mem_clock = 5237 hwmgr->platform_descriptor.overdriveLimit.memoryClock; 5238 pr_warn("max mclk supported by vbios is %d\n", 5239 hwmgr->platform_descriptor.overdriveLimit.memoryClock); 5240 } 5241 5242 return 0; 5243 } 5244 5245 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5246 uint32_t virtual_addr_low, 5247 uint32_t virtual_addr_hi, 5248 uint32_t mc_addr_low, 5249 uint32_t mc_addr_hi, 5250 uint32_t size) 5251 { 5252 smum_send_msg_to_smc_with_parameter(hwmgr, 5253 PPSMC_MSG_SetSystemVirtualDramAddrHigh, 5254 virtual_addr_hi, 5255 NULL); 5256 smum_send_msg_to_smc_with_parameter(hwmgr, 5257 PPSMC_MSG_SetSystemVirtualDramAddrLow, 5258 virtual_addr_low, 5259 NULL); 5260 smum_send_msg_to_smc_with_parameter(hwmgr, 5261 PPSMC_MSG_DramLogSetDramAddrHigh, 5262 mc_addr_hi, 5263 NULL); 5264 5265 smum_send_msg_to_smc_with_parameter(hwmgr, 5266 PPSMC_MSG_DramLogSetDramAddrLow, 5267 mc_addr_low, 5268 NULL); 5269 5270 smum_send_msg_to_smc_with_parameter(hwmgr, 5271 PPSMC_MSG_DramLogSetDramSize, 5272 size, 5273 NULL); 5274 return 0; 5275 } 5276 5277 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5278 struct PP_TemperatureRange *thermal_data) 5279 { 5280 struct vega10_hwmgr *data = hwmgr->backend; 5281 PPTable_t *pp_table = &(data->smc_state_table.pp_table); 5282 struct phm_ppt_v2_information *pp_table_info = 5283 (struct phm_ppt_v2_information *)(hwmgr->pptable); 5284 struct phm_tdp_table *tdp_table = pp_table_info->tdp_table; 5285 5286 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange)); 5287 5288 thermal_data->max = pp_table->TedgeLimit * 5289 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5290 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) * 5291 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5292 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit * 5293 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5294 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) * 5295 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5296 thermal_data->mem_crit_max = pp_table->ThbmLimit * 5297 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5298 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)* 5299 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5300 5301 if (tdp_table->usSoftwareShutdownTemp > pp_table->ThotspotLimit && 5302 tdp_table->usSoftwareShutdownTemp < VEGA10_THERMAL_MAXIMUM_ALERT_TEMP) 5303 thermal_data->sw_ctf_threshold = tdp_table->usSoftwareShutdownTemp; 5304 else 5305 thermal_data->sw_ctf_threshold = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP; 5306 thermal_data->sw_ctf_threshold *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5307 5308 return 0; 5309 } 5310 5311 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5312 { 5313 struct vega10_hwmgr *data = hwmgr->backend; 5314 uint32_t i, size = 0; 5315 static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,}, 5316 {70, 60, 1, 3,}, 5317 {90, 60, 0, 0,}, 5318 {70, 60, 0, 0,}, 5319 {70, 90, 0, 0,}, 5320 {30, 60, 0, 6,}, 5321 }; 5322 static const char *title[6] = {"NUM", 5323 "MODE_NAME", 5324 "BUSY_SET_POINT", 5325 "FPS", 5326 "USE_RLC_BUSY", 5327 "MIN_ACTIVE_LEVEL"}; 5328 5329 if (!buf) 5330 return -EINVAL; 5331 5332 phm_get_sysfs_buf(&buf, &size); 5333 5334 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0], 5335 title[1], title[2], title[3], title[4], title[5]); 5336 5337 for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++) 5338 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", 5339 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5340 profile_mode_setting[i][0], profile_mode_setting[i][1], 5341 profile_mode_setting[i][2], profile_mode_setting[i][3]); 5342 5343 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i, 5344 amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 5345 data->custom_profile_mode[0], data->custom_profile_mode[1], 5346 data->custom_profile_mode[2], data->custom_profile_mode[3]); 5347 return size; 5348 } 5349 5350 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr) 5351 { 5352 struct amdgpu_device *adev = hwmgr->adev; 5353 5354 return (adev->pdev->device == 0x6860); 5355 } 5356 5357 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5358 { 5359 struct vega10_hwmgr *data = hwmgr->backend; 5360 uint8_t busy_set_point; 5361 uint8_t FPS; 5362 uint8_t use_rlc_busy; 5363 uint8_t min_active_level; 5364 uint32_t power_profile_mode = input[size]; 5365 5366 if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 5367 if (size != 0 && size != 4) 5368 return -EINVAL; 5369 5370 /* If size = 0 and the CUSTOM profile has been set already 5371 * then just apply the profile. The copy stored in the hwmgr 5372 * is zeroed out on init 5373 */ 5374 if (size == 0) { 5375 if (data->custom_profile_mode[0] != 0) 5376 goto out; 5377 else 5378 return -EINVAL; 5379 } 5380 5381 data->custom_profile_mode[0] = busy_set_point = input[0]; 5382 data->custom_profile_mode[1] = FPS = input[1]; 5383 data->custom_profile_mode[2] = use_rlc_busy = input[2]; 5384 data->custom_profile_mode[3] = min_active_level = input[3]; 5385 smum_send_msg_to_smc_with_parameter(hwmgr, 5386 PPSMC_MSG_SetCustomGfxDpmParameters, 5387 busy_set_point | FPS<<8 | 5388 use_rlc_busy << 16 | min_active_level<<24, 5389 NULL); 5390 } 5391 5392 out: 5393 if (vega10_get_power_profile_mode_quirks(hwmgr)) 5394 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5395 1 << power_profile_mode, 5396 NULL); 5397 else 5398 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask, 5399 (!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1), 5400 NULL); 5401 5402 hwmgr->power_profile_mode = power_profile_mode; 5403 5404 return 0; 5405 } 5406 5407 5408 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5409 enum PP_OD_DPM_TABLE_COMMAND type, 5410 uint32_t clk, 5411 uint32_t voltage) 5412 { 5413 struct vega10_hwmgr *data = hwmgr->backend; 5414 struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table); 5415 struct vega10_single_dpm_table *golden_table; 5416 5417 if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) { 5418 pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc); 5419 return false; 5420 } 5421 5422 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5423 golden_table = &(data->golden_dpm_table.gfx_table); 5424 if (golden_table->dpm_levels[0].value > clk || 5425 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5426 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5427 golden_table->dpm_levels[0].value/100, 5428 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5429 return false; 5430 } 5431 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5432 golden_table = &(data->golden_dpm_table.mem_table); 5433 if (golden_table->dpm_levels[0].value > clk || 5434 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5435 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5436 golden_table->dpm_levels[0].value/100, 5437 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5438 return false; 5439 } 5440 } else { 5441 return false; 5442 } 5443 5444 return true; 5445 } 5446 5447 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr) 5448 { 5449 struct vega10_hwmgr *data = hwmgr->backend; 5450 struct pp_power_state *ps = hwmgr->request_ps; 5451 struct vega10_power_state *vega10_ps; 5452 struct vega10_single_dpm_table *gfx_dpm_table = 5453 &data->dpm_table.gfx_table; 5454 struct vega10_single_dpm_table *soc_dpm_table = 5455 &data->dpm_table.soc_table; 5456 struct vega10_single_dpm_table *mem_dpm_table = 5457 &data->dpm_table.mem_table; 5458 int max_level; 5459 5460 if (!ps) 5461 return; 5462 5463 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5464 if (vega10_ps == NULL) 5465 return; 5466 5467 max_level = vega10_ps->performance_level_count - 1; 5468 5469 if (vega10_ps->performance_levels[max_level].gfx_clock != 5470 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5471 vega10_ps->performance_levels[max_level].gfx_clock = 5472 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5473 5474 if (vega10_ps->performance_levels[max_level].soc_clock != 5475 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5476 vega10_ps->performance_levels[max_level].soc_clock = 5477 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5478 5479 if (vega10_ps->performance_levels[max_level].mem_clock != 5480 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5481 vega10_ps->performance_levels[max_level].mem_clock = 5482 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5483 5484 if (!hwmgr->ps) 5485 return; 5486 5487 ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1)); 5488 vega10_ps = cast_phw_vega10_power_state(&ps->hardware); 5489 if (vega10_ps == NULL) 5490 return; 5491 5492 max_level = vega10_ps->performance_level_count - 1; 5493 5494 if (vega10_ps->performance_levels[max_level].gfx_clock != 5495 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value) 5496 vega10_ps->performance_levels[max_level].gfx_clock = 5497 gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value; 5498 5499 if (vega10_ps->performance_levels[max_level].soc_clock != 5500 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value) 5501 vega10_ps->performance_levels[max_level].soc_clock = 5502 soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value; 5503 5504 if (vega10_ps->performance_levels[max_level].mem_clock != 5505 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value) 5506 vega10_ps->performance_levels[max_level].mem_clock = 5507 mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value; 5508 } 5509 5510 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr, 5511 enum PP_OD_DPM_TABLE_COMMAND type) 5512 { 5513 struct vega10_hwmgr *data = hwmgr->backend; 5514 struct phm_ppt_v2_information *table_info = hwmgr->pptable; 5515 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk; 5516 struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table; 5517 5518 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk = 5519 &data->odn_dpm_table.vdd_dep_on_socclk; 5520 struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table; 5521 5522 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep; 5523 uint8_t i, j; 5524 5525 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5526 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; 5527 for (i = 0; i < podn_vdd_dep->count; i++) 5528 od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc; 5529 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5530 podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; 5531 for (i = 0; i < dpm_table->count; i++) { 5532 for (j = 0; j < od_vddc_lookup_table->count; j++) { 5533 if (od_vddc_lookup_table->entries[j].us_vdd > 5534 podn_vdd_dep->entries[i].vddc) 5535 break; 5536 } 5537 if (j == od_vddc_lookup_table->count) { 5538 j = od_vddc_lookup_table->count - 1; 5539 od_vddc_lookup_table->entries[j].us_vdd = 5540 podn_vdd_dep->entries[i].vddc; 5541 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 5542 } 5543 podn_vdd_dep->entries[i].vddInd = j; 5544 } 5545 dpm_table = &data->dpm_table.soc_table; 5546 for (i = 0; i < dep_table->count; i++) { 5547 if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd && 5548 dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) { 5549 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5550 for (; (i < dep_table->count) && 5551 (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) { 5552 podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk; 5553 dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk; 5554 } 5555 break; 5556 } else { 5557 dpm_table->dpm_levels[i].value = dep_table->entries[i].clk; 5558 podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc; 5559 podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd; 5560 podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk; 5561 } 5562 } 5563 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk < 5564 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) { 5565 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5566 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk = 5567 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5568 dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value = 5569 podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk; 5570 } 5571 if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd < 5572 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) { 5573 data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK; 5574 podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd = 5575 podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd; 5576 } 5577 } 5578 vega10_odn_update_power_state(hwmgr); 5579 } 5580 5581 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5582 enum PP_OD_DPM_TABLE_COMMAND type, 5583 long *input, uint32_t size) 5584 { 5585 struct vega10_hwmgr *data = hwmgr->backend; 5586 struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table; 5587 struct vega10_single_dpm_table *dpm_table; 5588 5589 uint32_t input_clk; 5590 uint32_t input_vol; 5591 uint32_t input_level; 5592 uint32_t i; 5593 5594 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5595 return -EINVAL); 5596 5597 if (!hwmgr->od_enabled) { 5598 pr_info("OverDrive feature not enabled\n"); 5599 return -EINVAL; 5600 } 5601 5602 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5603 dpm_table = &data->dpm_table.gfx_table; 5604 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk; 5605 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 5606 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5607 dpm_table = &data->dpm_table.mem_table; 5608 podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk; 5609 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 5610 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5611 memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table)); 5612 vega10_odn_initial_default_setting(hwmgr); 5613 vega10_odn_update_power_state(hwmgr); 5614 /* force to update all clock tables */ 5615 data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK | 5616 DPMTABLE_UPDATE_MCLK | 5617 DPMTABLE_UPDATE_SOCCLK; 5618 return 0; 5619 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5620 vega10_check_dpm_table_updated(hwmgr); 5621 return 0; 5622 } else { 5623 return -EINVAL; 5624 } 5625 5626 for (i = 0; i < size; i += 3) { 5627 if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) { 5628 pr_info("invalid clock voltage input\n"); 5629 return 0; 5630 } 5631 input_level = input[i]; 5632 input_clk = input[i+1] * 100; 5633 input_vol = input[i+2]; 5634 5635 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5636 dpm_table->dpm_levels[input_level].value = input_clk; 5637 podn_vdd_dep_table->entries[input_level].clk = input_clk; 5638 podn_vdd_dep_table->entries[input_level].vddc = input_vol; 5639 } else { 5640 return -EINVAL; 5641 } 5642 } 5643 vega10_odn_update_soc_table(hwmgr, type); 5644 return 0; 5645 } 5646 5647 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr, 5648 enum pp_mp1_state mp1_state) 5649 { 5650 uint16_t msg; 5651 int ret; 5652 5653 switch (mp1_state) { 5654 case PP_MP1_STATE_UNLOAD: 5655 msg = PPSMC_MSG_PrepareMp1ForUnload; 5656 break; 5657 case PP_MP1_STATE_SHUTDOWN: 5658 case PP_MP1_STATE_RESET: 5659 case PP_MP1_STATE_NONE: 5660 default: 5661 return 0; 5662 } 5663 5664 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0, 5665 "[PrepareMp1] Failed!", 5666 return ret); 5667 5668 return 0; 5669 } 5670 5671 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5672 PHM_PerformanceLevelDesignation designation, uint32_t index, 5673 PHM_PerformanceLevel *level) 5674 { 5675 const struct vega10_power_state *vega10_ps; 5676 uint32_t i; 5677 5678 if (level == NULL || hwmgr == NULL || state == NULL) 5679 return -EINVAL; 5680 5681 vega10_ps = cast_const_phw_vega10_power_state(state); 5682 if (vega10_ps == NULL) 5683 return -EINVAL; 5684 5685 i = index > vega10_ps->performance_level_count - 1 ? 5686 vega10_ps->performance_level_count - 1 : index; 5687 5688 level->coreClock = vega10_ps->performance_levels[i].gfx_clock; 5689 level->memory_clock = vega10_ps->performance_levels[i].mem_clock; 5690 5691 return 0; 5692 } 5693 5694 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable) 5695 { 5696 struct vega10_hwmgr *data = hwmgr->backend; 5697 uint32_t feature_mask = 0; 5698 5699 if (disable) { 5700 feature_mask |= data->smu_features[GNLD_ULV].enabled ? 5701 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5702 feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ? 5703 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5704 feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ? 5705 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5706 feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ? 5707 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5708 feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ? 5709 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5710 } else { 5711 feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ? 5712 data->smu_features[GNLD_ULV].smu_feature_bitmap : 0; 5713 feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ? 5714 data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0; 5715 feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ? 5716 data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0; 5717 feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ? 5718 data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0; 5719 feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ? 5720 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0; 5721 } 5722 5723 if (feature_mask) 5724 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 5725 !disable, feature_mask), 5726 "enable/disable power features for compute performance Failed!", 5727 return -EINVAL); 5728 5729 if (disable) { 5730 data->smu_features[GNLD_ULV].enabled = false; 5731 data->smu_features[GNLD_DS_GFXCLK].enabled = false; 5732 data->smu_features[GNLD_DS_SOCCLK].enabled = false; 5733 data->smu_features[GNLD_DS_LCLK].enabled = false; 5734 data->smu_features[GNLD_DS_DCEFCLK].enabled = false; 5735 } else { 5736 data->smu_features[GNLD_ULV].enabled = true; 5737 data->smu_features[GNLD_DS_GFXCLK].enabled = true; 5738 data->smu_features[GNLD_DS_SOCCLK].enabled = true; 5739 data->smu_features[GNLD_DS_LCLK].enabled = true; 5740 data->smu_features[GNLD_DS_DCEFCLK].enabled = true; 5741 } 5742 5743 return 0; 5744 5745 } 5746 5747 static const struct pp_hwmgr_func vega10_hwmgr_funcs = { 5748 .backend_init = vega10_hwmgr_backend_init, 5749 .backend_fini = vega10_hwmgr_backend_fini, 5750 .asic_setup = vega10_setup_asic_task, 5751 .dynamic_state_management_enable = vega10_enable_dpm_tasks, 5752 .dynamic_state_management_disable = vega10_disable_dpm_tasks, 5753 .get_num_of_pp_table_entries = 5754 vega10_get_number_of_powerplay_table_entries, 5755 .get_power_state_size = vega10_get_power_state_size, 5756 .get_pp_table_entry = vega10_get_pp_table_entry, 5757 .patch_boot_state = vega10_patch_boot_state, 5758 .apply_state_adjust_rules = vega10_apply_state_adjust_rules, 5759 .power_state_set = vega10_set_power_state_tasks, 5760 .get_sclk = vega10_dpm_get_sclk, 5761 .get_mclk = vega10_dpm_get_mclk, 5762 .notify_smc_display_config_after_ps_adjustment = 5763 vega10_notify_smc_display_config_after_ps_adjustment, 5764 .force_dpm_level = vega10_dpm_force_dpm_level, 5765 .stop_thermal_controller = vega10_thermal_stop_thermal_controller, 5766 .get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info, 5767 .get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm, 5768 .set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm, 5769 .reset_fan_speed_to_default = 5770 vega10_fan_ctrl_reset_fan_speed_to_default, 5771 .get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm, 5772 .set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm, 5773 .uninitialize_thermal_controller = 5774 vega10_thermal_ctrl_uninitialize_thermal_controller, 5775 .set_fan_control_mode = vega10_set_fan_control_mode, 5776 .get_fan_control_mode = vega10_get_fan_control_mode, 5777 .read_sensor = vega10_read_sensor, 5778 .get_dal_power_level = vega10_get_dal_power_level, 5779 .get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency, 5780 .get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage, 5781 .set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges, 5782 .display_clock_voltage_request = vega10_display_clock_voltage_request, 5783 .force_clock_level = vega10_force_clock_level, 5784 .emit_clock_levels = vega10_emit_clock_levels, 5785 .print_clock_levels = vega10_print_clock_levels, 5786 .display_config_changed = vega10_display_configuration_changed_task, 5787 .powergate_uvd = vega10_power_gate_uvd, 5788 .powergate_vce = vega10_power_gate_vce, 5789 .check_states_equal = vega10_check_states_equal, 5790 .check_smc_update_required_for_display_configuration = 5791 vega10_check_smc_update_required_for_display_configuration, 5792 .power_off_asic = vega10_power_off_asic, 5793 .disable_smc_firmware_ctf = vega10_thermal_disable_alert, 5794 .get_sclk_od = vega10_get_sclk_od, 5795 .set_sclk_od = vega10_set_sclk_od, 5796 .get_mclk_od = vega10_get_mclk_od, 5797 .set_mclk_od = vega10_set_mclk_od, 5798 .avfs_control = vega10_avfs_enable, 5799 .notify_cac_buffer_info = vega10_notify_cac_buffer_info, 5800 .get_thermal_temperature_range = vega10_get_thermal_temperature_range, 5801 .register_irq_handlers = smu9_register_irq_handlers, 5802 .start_thermal_controller = vega10_start_thermal_controller, 5803 .get_power_profile_mode = vega10_get_power_profile_mode, 5804 .set_power_profile_mode = vega10_set_power_profile_mode, 5805 .set_power_limit = vega10_set_power_limit, 5806 .odn_edit_dpm_table = vega10_odn_edit_dpm_table, 5807 .get_performance_level = vega10_get_performance_level, 5808 .get_asic_baco_capability = smu9_baco_get_capability, 5809 .get_asic_baco_state = smu9_baco_get_state, 5810 .set_asic_baco_state = vega10_baco_set_state, 5811 .enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost, 5812 .get_ppfeature_status = vega10_get_ppfeature_status, 5813 .set_ppfeature_status = vega10_set_ppfeature_status, 5814 .set_mp1_state = vega10_set_mp1_state, 5815 .disable_power_features_for_compute_performance = 5816 vega10_disable_power_features_for_compute_performance, 5817 }; 5818 5819 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr) 5820 { 5821 struct amdgpu_device *adev = hwmgr->adev; 5822 5823 hwmgr->hwmgr_func = &vega10_hwmgr_funcs; 5824 hwmgr->pptable_func = &vega10_pptable_funcs; 5825 if (amdgpu_passthrough(adev)) 5826 return vega10_baco_set_cap(hwmgr); 5827 5828 return 0; 5829 } 5830