1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/slab.h>
28 
29 #include "hwmgr.h"
30 #include "amd_powerplay.h"
31 #include "hardwaremanager.h"
32 #include "ppatomfwctrl.h"
33 #include "atomfirmware.h"
34 #include "cgs_common.h"
35 #include "vega10_powertune.h"
36 #include "smu9.h"
37 #include "smu9_driver_if.h"
38 #include "vega10_inc.h"
39 #include "soc15_common.h"
40 #include "pppcielanes.h"
41 #include "vega10_hwmgr.h"
42 #include "vega10_smumgr.h"
43 #include "vega10_processpptables.h"
44 #include "vega10_pptable.h"
45 #include "vega10_thermal.h"
46 #include "pp_debug.h"
47 #include "amd_pcie_helpers.h"
48 #include "ppinterrupt.h"
49 #include "pp_overdriver.h"
50 #include "pp_thermal.h"
51 #include "vega10_baco.h"
52 
53 #include "smuio/smuio_9_0_offset.h"
54 #include "smuio/smuio_9_0_sh_mask.h"
55 
56 #define smnPCIE_LC_SPEED_CNTL			0x11140290
57 #define smnPCIE_LC_LINK_WIDTH_CNTL		0x11140288
58 
59 #define HBM_MEMORY_CHANNEL_WIDTH    128
60 
61 static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
62 
63 #define mmDF_CS_AON0_DramBaseAddress0                                                                  0x0044
64 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX                                                         0
65 
66 //DF_CS_AON0_DramBaseAddress0
67 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT                                                        0x0
68 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT                                                    0x1
69 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT                                                      0x4
70 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT                                                      0x8
71 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT                                                      0xc
72 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK                                                          0x00000001L
73 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK                                                      0x00000002L
74 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK                                                        0x000000F0L
75 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK                                                        0x00000700L
76 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK                                                        0xFFFFF000L
77 
78 typedef enum {
79 	CLK_SMNCLK = 0,
80 	CLK_SOCCLK,
81 	CLK_MP0CLK,
82 	CLK_MP1CLK,
83 	CLK_LCLK,
84 	CLK_DCEFCLK,
85 	CLK_VCLK,
86 	CLK_DCLK,
87 	CLK_ECLK,
88 	CLK_UCLK,
89 	CLK_GFXCLK,
90 	CLK_COUNT,
91 } CLOCK_ID_e;
92 
93 static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
94 
95 static struct vega10_power_state *cast_phw_vega10_power_state(
96 				  struct pp_hw_power_state *hw_ps)
97 {
98 	PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
99 				"Invalid Powerstate Type!",
100 				 return NULL;);
101 
102 	return (struct vega10_power_state *)hw_ps;
103 }
104 
105 static const struct vega10_power_state *cast_const_phw_vega10_power_state(
106 				 const struct pp_hw_power_state *hw_ps)
107 {
108 	PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
109 				"Invalid Powerstate Type!",
110 				 return NULL;);
111 
112 	return (const struct vega10_power_state *)hw_ps;
113 }
114 
115 static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
116 {
117 	struct vega10_hwmgr *data = hwmgr->backend;
118 
119 	data->registry_data.sclk_dpm_key_disabled =
120 			hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
121 	data->registry_data.socclk_dpm_key_disabled =
122 			hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
123 	data->registry_data.mclk_dpm_key_disabled =
124 			hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
125 	data->registry_data.pcie_dpm_key_disabled =
126 			hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
127 
128 	data->registry_data.dcefclk_dpm_key_disabled =
129 			hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
130 
131 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
132 		data->registry_data.power_containment_support = 1;
133 		data->registry_data.enable_pkg_pwr_tracking_feature = 1;
134 		data->registry_data.enable_tdc_limit_feature = 1;
135 	}
136 
137 	data->registry_data.clock_stretcher_support =
138 			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
139 
140 	data->registry_data.ulv_support =
141 			hwmgr->feature_mask & PP_ULV_MASK ? true : false;
142 
143 	data->registry_data.sclk_deep_sleep_support =
144 			hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
145 
146 	data->registry_data.disable_water_mark = 0;
147 
148 	data->registry_data.fan_control_support = 1;
149 	data->registry_data.thermal_support = 1;
150 	data->registry_data.fw_ctf_enabled = 1;
151 
152 	data->registry_data.avfs_support =
153 		hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
154 	data->registry_data.led_dpm_enabled = 1;
155 
156 	data->registry_data.vr0hot_enabled = 1;
157 	data->registry_data.vr1hot_enabled = 1;
158 	data->registry_data.regulator_hot_gpio_support = 1;
159 
160 	data->registry_data.didt_support = 1;
161 	if (data->registry_data.didt_support) {
162 		data->registry_data.didt_mode = 6;
163 		data->registry_data.sq_ramping_support = 1;
164 		data->registry_data.db_ramping_support = 0;
165 		data->registry_data.td_ramping_support = 0;
166 		data->registry_data.tcp_ramping_support = 0;
167 		data->registry_data.dbr_ramping_support = 0;
168 		data->registry_data.edc_didt_support = 1;
169 		data->registry_data.gc_didt_support = 0;
170 		data->registry_data.psm_didt_support = 0;
171 	}
172 
173 	data->display_voltage_mode = PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
174 	data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
175 	data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
176 	data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
177 	data->disp_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
178 	data->disp_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
179 	data->disp_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
180 	data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
181 	data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
182 	data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
183 	data->phy_clk_quad_eqn_a = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
184 	data->phy_clk_quad_eqn_b = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
185 	data->phy_clk_quad_eqn_c = PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
186 
187 	data->gfxclk_average_alpha = PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT;
188 	data->socclk_average_alpha = PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT;
189 	data->uclk_average_alpha = PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT;
190 	data->gfx_activity_average_alpha = PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT;
191 }
192 
193 static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
194 {
195 	struct vega10_hwmgr *data = hwmgr->backend;
196 	struct phm_ppt_v2_information *table_info =
197 			(struct phm_ppt_v2_information *)hwmgr->pptable;
198 	struct amdgpu_device *adev = hwmgr->adev;
199 
200 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
201 			PHM_PlatformCaps_SclkDeepSleep);
202 
203 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 			PHM_PlatformCaps_DynamicPatchPowerState);
205 
206 	if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE)
207 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
208 				PHM_PlatformCaps_ControlVDDCI);
209 
210 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
211 			PHM_PlatformCaps_EnableSMU7ThermalManagement);
212 
213 	if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
214 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
215 				PHM_PlatformCaps_UVDPowerGating);
216 
217 	if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
218 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
219 				PHM_PlatformCaps_VCEPowerGating);
220 
221 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
222 			PHM_PlatformCaps_UnTabledHardwareInterface);
223 
224 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
225 			PHM_PlatformCaps_FanSpeedInTableIsRPM);
226 
227 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
228 			PHM_PlatformCaps_ODFuzzyFanControlSupport);
229 
230 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
231 				PHM_PlatformCaps_DynamicPowerManagement);
232 
233 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
234 			PHM_PlatformCaps_SMC);
235 
236 	/* power tune caps */
237 	/* assume disabled */
238 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
239 			PHM_PlatformCaps_PowerContainment);
240 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
241 			PHM_PlatformCaps_DiDtSupport);
242 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
243 			PHM_PlatformCaps_SQRamping);
244 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
245 			PHM_PlatformCaps_DBRamping);
246 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
247 			PHM_PlatformCaps_TDRamping);
248 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
249 			PHM_PlatformCaps_TCPRamping);
250 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
251 			PHM_PlatformCaps_DBRRamping);
252 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
253 			PHM_PlatformCaps_DiDtEDCEnable);
254 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
255 			PHM_PlatformCaps_GCEDC);
256 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
257 			PHM_PlatformCaps_PSM);
258 
259 	if (data->registry_data.didt_support) {
260 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
261 		if (data->registry_data.sq_ramping_support)
262 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
263 		if (data->registry_data.db_ramping_support)
264 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
265 		if (data->registry_data.td_ramping_support)
266 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
267 		if (data->registry_data.tcp_ramping_support)
268 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
269 		if (data->registry_data.dbr_ramping_support)
270 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
271 		if (data->registry_data.edc_didt_support)
272 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
273 		if (data->registry_data.gc_didt_support)
274 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
275 		if (data->registry_data.psm_didt_support)
276 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
277 	}
278 
279 	if (data->registry_data.power_containment_support)
280 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
281 				PHM_PlatformCaps_PowerContainment);
282 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
283 			PHM_PlatformCaps_CAC);
284 
285 	if (table_info->tdp_table->usClockStretchAmount &&
286 			data->registry_data.clock_stretcher_support)
287 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
288 				PHM_PlatformCaps_ClockStretcher);
289 
290 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 			PHM_PlatformCaps_RegulatorHot);
292 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
293 			PHM_PlatformCaps_AutomaticDCTransition);
294 
295 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
296 			PHM_PlatformCaps_UVDDPM);
297 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
298 			PHM_PlatformCaps_VCEDPM);
299 
300 	return 0;
301 }
302 
303 static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
304 {
305 	struct vega10_hwmgr *data = hwmgr->backend;
306 	struct phm_ppt_v2_information *table_info =
307 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
308 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
309 	struct vega10_odn_vddc_lookup_table *od_lookup_table;
310 	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
311 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table[3];
312 	struct phm_ppt_v1_clock_voltage_dependency_table *od_table[3];
313 	struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
314 	uint32_t i;
315 	int result;
316 
317 	result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
318 	if (!result) {
319 		data->odn_dpm_table.max_vddc = avfs_params.ulMaxVddc;
320 		data->odn_dpm_table.min_vddc = avfs_params.ulMinVddc;
321 	}
322 
323 	od_lookup_table = &odn_table->vddc_lookup_table;
324 	vddc_lookup_table = table_info->vddc_lookup_table;
325 
326 	for (i = 0; i < vddc_lookup_table->count; i++)
327 		od_lookup_table->entries[i].us_vdd = vddc_lookup_table->entries[i].us_vdd;
328 
329 	od_lookup_table->count = vddc_lookup_table->count;
330 
331 	dep_table[0] = table_info->vdd_dep_on_sclk;
332 	dep_table[1] = table_info->vdd_dep_on_mclk;
333 	dep_table[2] = table_info->vdd_dep_on_socclk;
334 	od_table[0] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_sclk;
335 	od_table[1] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_mclk;
336 	od_table[2] = (struct phm_ppt_v1_clock_voltage_dependency_table *)&odn_table->vdd_dep_on_socclk;
337 
338 	for (i = 0; i < 3; i++)
339 		smu_get_voltage_dependency_table_ppt_v1(dep_table[i], od_table[i]);
340 
341 	if (odn_table->max_vddc == 0 || odn_table->max_vddc > 2000)
342 		odn_table->max_vddc = dep_table[0]->entries[dep_table[0]->count - 1].vddc;
343 	if (odn_table->min_vddc == 0 || odn_table->min_vddc > 2000)
344 		odn_table->min_vddc = dep_table[0]->entries[0].vddc;
345 
346 	i = od_table[2]->count - 1;
347 	od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
348 					hwmgr->platform_descriptor.overdriveLimit.memoryClock :
349 					od_table[2]->entries[i].clk;
350 	od_table[2]->entries[i].vddc = odn_table->max_vddc > od_table[2]->entries[i].vddc ?
351 					odn_table->max_vddc :
352 					od_table[2]->entries[i].vddc;
353 
354 	return 0;
355 }
356 
357 static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
358 {
359 	struct vega10_hwmgr *data = hwmgr->backend;
360 	int i;
361 	uint32_t sub_vendor_id, hw_revision;
362 	uint32_t top32, bottom32;
363 	struct amdgpu_device *adev = hwmgr->adev;
364 
365 	vega10_initialize_power_tune_defaults(hwmgr);
366 
367 	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
368 		data->smu_features[i].smu_feature_id = 0xffff;
369 		data->smu_features[i].smu_feature_bitmap = 1 << i;
370 		data->smu_features[i].enabled = false;
371 		data->smu_features[i].supported = false;
372 	}
373 
374 	data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
375 			FEATURE_DPM_PREFETCHER_BIT;
376 	data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
377 			FEATURE_DPM_GFXCLK_BIT;
378 	data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
379 			FEATURE_DPM_UCLK_BIT;
380 	data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
381 			FEATURE_DPM_SOCCLK_BIT;
382 	data->smu_features[GNLD_DPM_UVD].smu_feature_id =
383 			FEATURE_DPM_UVD_BIT;
384 	data->smu_features[GNLD_DPM_VCE].smu_feature_id =
385 			FEATURE_DPM_VCE_BIT;
386 	data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
387 			FEATURE_DPM_MP0CLK_BIT;
388 	data->smu_features[GNLD_DPM_LINK].smu_feature_id =
389 			FEATURE_DPM_LINK_BIT;
390 	data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
391 			FEATURE_DPM_DCEFCLK_BIT;
392 	data->smu_features[GNLD_ULV].smu_feature_id =
393 			FEATURE_ULV_BIT;
394 	data->smu_features[GNLD_AVFS].smu_feature_id =
395 			FEATURE_AVFS_BIT;
396 	data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
397 			FEATURE_DS_GFXCLK_BIT;
398 	data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
399 			FEATURE_DS_SOCCLK_BIT;
400 	data->smu_features[GNLD_DS_LCLK].smu_feature_id =
401 			FEATURE_DS_LCLK_BIT;
402 	data->smu_features[GNLD_PPT].smu_feature_id =
403 			FEATURE_PPT_BIT;
404 	data->smu_features[GNLD_TDC].smu_feature_id =
405 			FEATURE_TDC_BIT;
406 	data->smu_features[GNLD_THERMAL].smu_feature_id =
407 			FEATURE_THERMAL_BIT;
408 	data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
409 			FEATURE_GFX_PER_CU_CG_BIT;
410 	data->smu_features[GNLD_RM].smu_feature_id =
411 			FEATURE_RM_BIT;
412 	data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
413 			FEATURE_DS_DCEFCLK_BIT;
414 	data->smu_features[GNLD_ACDC].smu_feature_id =
415 			FEATURE_ACDC_BIT;
416 	data->smu_features[GNLD_VR0HOT].smu_feature_id =
417 			FEATURE_VR0HOT_BIT;
418 	data->smu_features[GNLD_VR1HOT].smu_feature_id =
419 			FEATURE_VR1HOT_BIT;
420 	data->smu_features[GNLD_FW_CTF].smu_feature_id =
421 			FEATURE_FW_CTF_BIT;
422 	data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
423 			FEATURE_LED_DISPLAY_BIT;
424 	data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
425 			FEATURE_FAN_CONTROL_BIT;
426 	data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
427 	data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
428 	data->smu_features[GNLD_PCC_LIMIT].smu_feature_id = FEATURE_PCC_LIMIT_CONTROL_BIT;
429 
430 	if (!data->registry_data.prefetcher_dpm_key_disabled)
431 		data->smu_features[GNLD_DPM_PREFETCHER].supported = true;
432 
433 	if (!data->registry_data.sclk_dpm_key_disabled)
434 		data->smu_features[GNLD_DPM_GFXCLK].supported = true;
435 
436 	if (!data->registry_data.mclk_dpm_key_disabled)
437 		data->smu_features[GNLD_DPM_UCLK].supported = true;
438 
439 	if (!data->registry_data.socclk_dpm_key_disabled)
440 		data->smu_features[GNLD_DPM_SOCCLK].supported = true;
441 
442 	if (PP_CAP(PHM_PlatformCaps_UVDDPM))
443 		data->smu_features[GNLD_DPM_UVD].supported = true;
444 
445 	if (PP_CAP(PHM_PlatformCaps_VCEDPM))
446 		data->smu_features[GNLD_DPM_VCE].supported = true;
447 
448 	data->smu_features[GNLD_DPM_LINK].supported = true;
449 
450 	if (!data->registry_data.dcefclk_dpm_key_disabled)
451 		data->smu_features[GNLD_DPM_DCEFCLK].supported = true;
452 
453 	if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep) &&
454 	    data->registry_data.sclk_deep_sleep_support) {
455 		data->smu_features[GNLD_DS_GFXCLK].supported = true;
456 		data->smu_features[GNLD_DS_SOCCLK].supported = true;
457 		data->smu_features[GNLD_DS_LCLK].supported = true;
458 		data->smu_features[GNLD_DS_DCEFCLK].supported = true;
459 	}
460 
461 	if (data->registry_data.enable_pkg_pwr_tracking_feature)
462 		data->smu_features[GNLD_PPT].supported = true;
463 
464 	if (data->registry_data.enable_tdc_limit_feature)
465 		data->smu_features[GNLD_TDC].supported = true;
466 
467 	if (data->registry_data.thermal_support)
468 		data->smu_features[GNLD_THERMAL].supported = true;
469 
470 	if (data->registry_data.fan_control_support)
471 		data->smu_features[GNLD_FAN_CONTROL].supported = true;
472 
473 	if (data->registry_data.fw_ctf_enabled)
474 		data->smu_features[GNLD_FW_CTF].supported = true;
475 
476 	if (data->registry_data.avfs_support)
477 		data->smu_features[GNLD_AVFS].supported = true;
478 
479 	if (data->registry_data.led_dpm_enabled)
480 		data->smu_features[GNLD_LED_DISPLAY].supported = true;
481 
482 	if (data->registry_data.vr1hot_enabled)
483 		data->smu_features[GNLD_VR1HOT].supported = true;
484 
485 	if (data->registry_data.vr0hot_enabled)
486 		data->smu_features[GNLD_VR0HOT].supported = true;
487 
488 	smum_send_msg_to_smc(hwmgr,
489 			PPSMC_MSG_GetSmuVersion,
490 			&hwmgr->smu_version);
491 		/* ACG firmware has major version 5 */
492 	if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
493 		data->smu_features[GNLD_ACG].supported = true;
494 	if (data->registry_data.didt_support)
495 		data->smu_features[GNLD_DIDT].supported = true;
496 
497 	hw_revision = adev->pdev->revision;
498 	sub_vendor_id = adev->pdev->subsystem_vendor;
499 
500 	if ((hwmgr->chip_id == 0x6862 ||
501 		hwmgr->chip_id == 0x6861 ||
502 		hwmgr->chip_id == 0x6868) &&
503 		(hw_revision == 0) &&
504 		(sub_vendor_id != 0x1002))
505 		data->smu_features[GNLD_PCC_LIMIT].supported = true;
506 
507 	/* Get the SN to turn into a Unique ID */
508 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
509 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
510 
511 	adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
512 }
513 
514 #ifdef PPLIB_VEGA10_EVV_SUPPORT
515 static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
516 	phm_ppt_v1_voltage_lookup_table *lookup_table,
517 	uint16_t virtual_voltage_id, int32_t *socclk)
518 {
519 	uint8_t entry_id;
520 	uint8_t voltage_id;
521 	struct phm_ppt_v2_information *table_info =
522 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
523 
524 	PP_ASSERT_WITH_CODE(lookup_table->count != 0,
525 			"Lookup table is empty",
526 			return -EINVAL);
527 
528 	/* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
529 	for (entry_id = 0; entry_id < table_info->vdd_dep_on_sclk->count; entry_id++) {
530 		voltage_id = table_info->vdd_dep_on_socclk->entries[entry_id].vddInd;
531 		if (lookup_table->entries[voltage_id].us_vdd == virtual_voltage_id)
532 			break;
533 	}
534 
535 	PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
536 			"Can't find requested voltage id in vdd_dep_on_socclk table!",
537 			return -EINVAL);
538 
539 	*socclk = table_info->vdd_dep_on_socclk->entries[entry_id].clk;
540 
541 	return 0;
542 }
543 
544 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
545 /**
546  * vega10_get_evv_voltages - Get Leakage VDDC based on leakage ID.
547  *
548  * @hwmgr:  the address of the powerplay hardware manager.
549  * return:  always 0.
550  */
551 static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
552 {
553 	struct vega10_hwmgr *data = hwmgr->backend;
554 	uint16_t vv_id;
555 	uint32_t vddc = 0;
556 	uint16_t i, j;
557 	uint32_t sclk = 0;
558 	struct phm_ppt_v2_information *table_info =
559 			(struct phm_ppt_v2_information *)hwmgr->pptable;
560 	struct phm_ppt_v1_clock_voltage_dependency_table *socclk_table =
561 			table_info->vdd_dep_on_socclk;
562 	int result;
563 
564 	for (i = 0; i < VEGA10_MAX_LEAKAGE_COUNT; i++) {
565 		vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
566 
567 		if (!vega10_get_socclk_for_voltage_evv(hwmgr,
568 				table_info->vddc_lookup_table, vv_id, &sclk)) {
569 			if (PP_CAP(PHM_PlatformCaps_ClockStretcher)) {
570 				for (j = 1; j < socclk_table->count; j++) {
571 					if (socclk_table->entries[j].clk == sclk &&
572 							socclk_table->entries[j].cks_enable == 0) {
573 						sclk += 5000;
574 						break;
575 					}
576 				}
577 			}
578 
579 			PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
580 					VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
581 					"Error retrieving EVV voltage value!",
582 					continue);
583 
584 
585 			/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
586 			PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
587 					"Invalid VDDC value", result = -EINVAL;);
588 
589 			/* the voltage should not be zero nor equal to leakage ID */
590 			if (vddc != 0 && vddc != vv_id) {
591 				data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc/100);
592 				data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id;
593 				data->vddc_leakage.count++;
594 			}
595 		}
596 	}
597 
598 	return 0;
599 }
600 
601 /**
602  * vega10_patch_with_vdd_leakage - Change virtual leakage voltage to actual value.
603  *
604  * @hwmgr:         the address of the powerplay hardware manager.
605  * @voltage:       pointer to changing voltage
606  * @leakage_table: pointer to leakage table
607  */
608 static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
609 		uint16_t *voltage, struct vega10_leakage_voltage *leakage_table)
610 {
611 	uint32_t index;
612 
613 	/* search for leakage voltage ID 0xff01 ~ 0xff08 */
614 	for (index = 0; index < leakage_table->count; index++) {
615 		/* if this voltage matches a leakage voltage ID */
616 		/* patch with actual leakage voltage */
617 		if (leakage_table->leakage_id[index] == *voltage) {
618 			*voltage = leakage_table->actual_voltage[index];
619 			break;
620 		}
621 	}
622 
623 	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
624 		pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
625 }
626 
627 /**
628  * vega10_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages.
629  *
630  * @hwmgr:         the address of the powerplay hardware manager.
631  * @lookup_table:  pointer to voltage lookup table
632  * @leakage_table: pointer to leakage table
633  * return:         always 0
634  */
635 static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
636 		phm_ppt_v1_voltage_lookup_table *lookup_table,
637 		struct vega10_leakage_voltage *leakage_table)
638 {
639 	uint32_t i;
640 
641 	for (i = 0; i < lookup_table->count; i++)
642 		vega10_patch_with_vdd_leakage(hwmgr,
643 				&lookup_table->entries[i].us_vdd, leakage_table);
644 
645 	return 0;
646 }
647 
648 static int vega10_patch_clock_voltage_limits_with_vddc_leakage(
649 		struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
650 		uint16_t *vddc)
651 {
652 	vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
653 
654 	return 0;
655 }
656 #endif
657 
658 static int vega10_patch_voltage_dependency_tables_with_lookup_table(
659 		struct pp_hwmgr *hwmgr)
660 {
661 	uint8_t entry_id, voltage_id;
662 	unsigned i;
663 	struct phm_ppt_v2_information *table_info =
664 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
665 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
666 			table_info->mm_dep_table;
667 	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
668 			table_info->vdd_dep_on_mclk;
669 
670 	for (i = 0; i < 6; i++) {
671 		struct phm_ppt_v1_clock_voltage_dependency_table *vdt;
672 		switch (i) {
673 			case 0: vdt = table_info->vdd_dep_on_socclk; break;
674 			case 1: vdt = table_info->vdd_dep_on_sclk; break;
675 			case 2: vdt = table_info->vdd_dep_on_dcefclk; break;
676 			case 3: vdt = table_info->vdd_dep_on_pixclk; break;
677 			case 4: vdt = table_info->vdd_dep_on_dispclk; break;
678 			case 5: vdt = table_info->vdd_dep_on_phyclk; break;
679 		}
680 
681 		for (entry_id = 0; entry_id < vdt->count; entry_id++) {
682 			voltage_id = vdt->entries[entry_id].vddInd;
683 			vdt->entries[entry_id].vddc =
684 					table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
685 		}
686 	}
687 
688 	for (entry_id = 0; entry_id < mm_table->count; ++entry_id) {
689 		voltage_id = mm_table->entries[entry_id].vddcInd;
690 		mm_table->entries[entry_id].vddc =
691 			table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
692 	}
693 
694 	for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) {
695 		voltage_id = mclk_table->entries[entry_id].vddInd;
696 		mclk_table->entries[entry_id].vddc =
697 				table_info->vddc_lookup_table->entries[voltage_id].us_vdd;
698 		voltage_id = mclk_table->entries[entry_id].vddciInd;
699 		mclk_table->entries[entry_id].vddci =
700 				table_info->vddci_lookup_table->entries[voltage_id].us_vdd;
701 		voltage_id = mclk_table->entries[entry_id].mvddInd;
702 		mclk_table->entries[entry_id].mvdd =
703 				table_info->vddmem_lookup_table->entries[voltage_id].us_vdd;
704 	}
705 
706 
707 	return 0;
708 
709 }
710 
711 static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
712 		struct phm_ppt_v1_voltage_lookup_table *lookup_table)
713 {
714 	uint32_t table_size, i, j;
715 
716 	PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
717 		"Lookup table is empty", return -EINVAL);
718 
719 	table_size = lookup_table->count;
720 
721 	/* Sorting voltages */
722 	for (i = 0; i < table_size - 1; i++) {
723 		for (j = i + 1; j > 0; j--) {
724 			if (lookup_table->entries[j].us_vdd <
725 					lookup_table->entries[j - 1].us_vdd) {
726 				swap(lookup_table->entries[j - 1],
727 				     lookup_table->entries[j]);
728 			}
729 		}
730 	}
731 
732 	return 0;
733 }
734 
735 static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
736 {
737 	int result = 0;
738 	int tmp_result;
739 	struct phm_ppt_v2_information *table_info =
740 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
741 #ifdef PPLIB_VEGA10_EVV_SUPPORT
742 	struct vega10_hwmgr *data = hwmgr->backend;
743 
744 	tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
745 			table_info->vddc_lookup_table, &(data->vddc_leakage));
746 	if (tmp_result)
747 		result = tmp_result;
748 
749 	tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
750 			&(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
751 	if (tmp_result)
752 		result = tmp_result;
753 #endif
754 
755 	tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
756 	if (tmp_result)
757 		result = tmp_result;
758 
759 	tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
760 	if (tmp_result)
761 		result = tmp_result;
762 
763 	return result;
764 }
765 
766 static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
767 {
768 	struct phm_ppt_v2_information *table_info =
769 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
770 	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
771 			table_info->vdd_dep_on_socclk;
772 	struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
773 			table_info->vdd_dep_on_mclk;
774 
775 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
776 		"VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
777 	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
778 		"VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
779 
780 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
781 		"VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
782 	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
783 		"VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
784 
785 	table_info->max_clock_voltage_on_ac.sclk =
786 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
787 	table_info->max_clock_voltage_on_ac.mclk =
788 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
789 	table_info->max_clock_voltage_on_ac.vddc =
790 		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
791 	table_info->max_clock_voltage_on_ac.vddci =
792 		allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
793 
794 	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
795 		table_info->max_clock_voltage_on_ac.sclk;
796 	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
797 		table_info->max_clock_voltage_on_ac.mclk;
798 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
799 		table_info->max_clock_voltage_on_ac.vddc;
800 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
801 		table_info->max_clock_voltage_on_ac.vddci;
802 
803 	return 0;
804 }
805 
806 static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
807 {
808 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
809 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
810 
811 	kfree(hwmgr->backend);
812 	hwmgr->backend = NULL;
813 
814 	return 0;
815 }
816 
817 static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
818 {
819 	int result = 0;
820 	struct vega10_hwmgr *data;
821 	uint32_t config_telemetry = 0;
822 	struct pp_atomfwctrl_voltage_table vol_table;
823 	struct amdgpu_device *adev = hwmgr->adev;
824 
825 	data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
826 	if (data == NULL)
827 		return -ENOMEM;
828 
829 	hwmgr->backend = data;
830 
831 	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
832 	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
833 	hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
834 
835 	vega10_set_default_registry_data(hwmgr);
836 	data->disable_dpm_mask = 0xff;
837 
838 	/* need to set voltage control types before EVV patching */
839 	data->vddc_control = VEGA10_VOLTAGE_CONTROL_NONE;
840 	data->mvdd_control = VEGA10_VOLTAGE_CONTROL_NONE;
841 	data->vddci_control = VEGA10_VOLTAGE_CONTROL_NONE;
842 
843 	/* VDDCR_SOC */
844 	if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
845 			VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) {
846 		if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
847 				VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2,
848 				&vol_table)) {
849 			config_telemetry = ((vol_table.telemetry_slope << 8) & 0xff00) |
850 					(vol_table.telemetry_offset & 0xff);
851 			data->vddc_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
852 		}
853 	} else {
854 		kfree(hwmgr->backend);
855 		hwmgr->backend = NULL;
856 		PP_ASSERT_WITH_CODE(false,
857 				"VDDCR_SOC is not SVID2!",
858 				return -1);
859 	}
860 
861 	/* MVDDC */
862 	if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
863 			VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) {
864 		if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
865 				VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2,
866 				&vol_table)) {
867 			config_telemetry |=
868 					((vol_table.telemetry_slope << 24) & 0xff000000) |
869 					((vol_table.telemetry_offset << 16) & 0xff0000);
870 			data->mvdd_control = VEGA10_VOLTAGE_CONTROL_BY_SVID2;
871 		}
872 	}
873 
874 	 /* VDDCI_MEM */
875 	if (PP_CAP(PHM_PlatformCaps_ControlVDDCI)) {
876 		if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
877 				VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
878 			data->vddci_control = VEGA10_VOLTAGE_CONTROL_BY_GPIO;
879 	}
880 
881 	data->config_telemetry = config_telemetry;
882 
883 	vega10_set_features_platform_caps(hwmgr);
884 
885 	vega10_init_dpm_defaults(hwmgr);
886 
887 #ifdef PPLIB_VEGA10_EVV_SUPPORT
888 	/* Get leakage voltage based on leakage ID. */
889 	PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
890 			"Get EVV Voltage Failed.  Abort Driver loading!",
891 			return -1);
892 #endif
893 
894 	/* Patch our voltage dependency table with actual leakage voltage
895 	 * We need to perform leakage translation before it's used by other functions
896 	 */
897 	vega10_complete_dependency_tables(hwmgr);
898 
899 	/* Parse pptable data read from VBIOS */
900 	vega10_set_private_data_based_on_pptable(hwmgr);
901 
902 	data->is_tlu_enabled = false;
903 
904 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
905 			VEGA10_MAX_HARDWARE_POWERLEVELS;
906 	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
907 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
908 
909 	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
910 	/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
911 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
912 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
913 
914 	data->total_active_cus = adev->gfx.cu_info.number;
915 	if (!hwmgr->not_vf)
916 		return result;
917 
918 	/* Setup default Overdrive Fan control settings */
919 	data->odn_fan_table.target_fan_speed =
920 			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
921 	data->odn_fan_table.target_temperature =
922 			hwmgr->thermal_controller.
923 			advanceFanControlParameters.ucTargetTemperature;
924 	data->odn_fan_table.min_performance_clock =
925 			hwmgr->thermal_controller.advanceFanControlParameters.
926 			ulMinFanSCLKAcousticLimit;
927 	data->odn_fan_table.min_fan_limit =
928 			hwmgr->thermal_controller.
929 			advanceFanControlParameters.usFanPWMMinLimit *
930 			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
931 
932 	data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) &
933 			DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
934 			DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
935 	PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
936 			"Mem Channel Index Exceeded maximum!",
937 			return -EINVAL);
938 
939 	return result;
940 }
941 
942 static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
943 {
944 	struct vega10_hwmgr *data = hwmgr->backend;
945 
946 	data->low_sclk_interrupt_threshold = 0;
947 
948 	return 0;
949 }
950 
951 static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
952 {
953 	struct vega10_hwmgr *data = hwmgr->backend;
954 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
955 
956 	struct pp_atomfwctrl_voltage_table table;
957 	uint8_t i, j;
958 	uint32_t mask = 0;
959 	uint32_t tmp;
960 	int32_t ret = 0;
961 
962 	ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
963 						VOLTAGE_OBJ_GPIO_LUT, &table);
964 
965 	if (!ret) {
966 		tmp = table.mask_low;
967 		for (i = 0, j = 0; i < 32; i++) {
968 			if (tmp & 1) {
969 				mask |= (uint32_t)(i << (8 * j));
970 				if (++j >= 3)
971 					break;
972 			}
973 			tmp >>= 1;
974 		}
975 	}
976 
977 	pp_table->LedPin0 = (uint8_t)(mask & 0xff);
978 	pp_table->LedPin1 = (uint8_t)((mask >> 8) & 0xff);
979 	pp_table->LedPin2 = (uint8_t)((mask >> 16) & 0xff);
980 	return 0;
981 }
982 
983 static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
984 {
985 	if (!hwmgr->not_vf)
986 		return 0;
987 
988 	PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
989 			"Failed to init sclk threshold!",
990 			return -EINVAL);
991 
992 	PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
993 			"Failed to set up led dpm config!",
994 			return -EINVAL);
995 
996 	smum_send_msg_to_smc_with_parameter(hwmgr,
997 				PPSMC_MSG_NumOfDisplays,
998 				0,
999 				NULL);
1000 
1001 	return 0;
1002 }
1003 
1004 /**
1005  * vega10_trim_voltage_table - Remove repeated voltage values and create table with unique values.
1006  *
1007  * @hwmgr:      the address of the powerplay hardware manager.
1008  * @vol_table:  the pointer to changing voltage table
1009  * return:      0 in success
1010  */
1011 static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
1012 		struct pp_atomfwctrl_voltage_table *vol_table)
1013 {
1014 	uint32_t i, j;
1015 	uint16_t vvalue;
1016 	bool found = false;
1017 	struct pp_atomfwctrl_voltage_table *table;
1018 
1019 	PP_ASSERT_WITH_CODE(vol_table,
1020 			"Voltage Table empty.", return -EINVAL);
1021 	table = kzalloc(sizeof(struct pp_atomfwctrl_voltage_table),
1022 			GFP_KERNEL);
1023 
1024 	if (!table)
1025 		return -ENOMEM;
1026 
1027 	table->mask_low = vol_table->mask_low;
1028 	table->phase_delay = vol_table->phase_delay;
1029 
1030 	for (i = 0; i < vol_table->count; i++) {
1031 		vvalue = vol_table->entries[i].value;
1032 		found = false;
1033 
1034 		for (j = 0; j < table->count; j++) {
1035 			if (vvalue == table->entries[j].value) {
1036 				found = true;
1037 				break;
1038 			}
1039 		}
1040 
1041 		if (!found) {
1042 			table->entries[table->count].value = vvalue;
1043 			table->entries[table->count].smio_low =
1044 					vol_table->entries[i].smio_low;
1045 			table->count++;
1046 		}
1047 	}
1048 
1049 	memcpy(vol_table, table, sizeof(struct pp_atomfwctrl_voltage_table));
1050 	kfree(table);
1051 
1052 	return 0;
1053 }
1054 
1055 static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
1056 		phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1057 		struct pp_atomfwctrl_voltage_table *vol_table)
1058 {
1059 	int i;
1060 
1061 	PP_ASSERT_WITH_CODE(dep_table->count,
1062 			"Voltage Dependency Table empty.",
1063 			return -EINVAL);
1064 
1065 	vol_table->mask_low = 0;
1066 	vol_table->phase_delay = 0;
1067 	vol_table->count = dep_table->count;
1068 
1069 	for (i = 0; i < vol_table->count; i++) {
1070 		vol_table->entries[i].value = dep_table->entries[i].mvdd;
1071 		vol_table->entries[i].smio_low = 0;
1072 	}
1073 
1074 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
1075 			vol_table),
1076 			"Failed to trim MVDD Table!",
1077 			return -1);
1078 
1079 	return 0;
1080 }
1081 
1082 static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
1083 		phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1084 		struct pp_atomfwctrl_voltage_table *vol_table)
1085 {
1086 	uint32_t i;
1087 
1088 	PP_ASSERT_WITH_CODE(dep_table->count,
1089 			"Voltage Dependency Table empty.",
1090 			return -EINVAL);
1091 
1092 	vol_table->mask_low = 0;
1093 	vol_table->phase_delay = 0;
1094 	vol_table->count = dep_table->count;
1095 
1096 	for (i = 0; i < dep_table->count; i++) {
1097 		vol_table->entries[i].value = dep_table->entries[i].vddci;
1098 		vol_table->entries[i].smio_low = 0;
1099 	}
1100 
1101 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
1102 			"Failed to trim VDDCI table.",
1103 			return -1);
1104 
1105 	return 0;
1106 }
1107 
1108 static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1109 		phm_ppt_v1_clock_voltage_dependency_table *dep_table,
1110 		struct pp_atomfwctrl_voltage_table *vol_table)
1111 {
1112 	int i;
1113 
1114 	PP_ASSERT_WITH_CODE(dep_table->count,
1115 			"Voltage Dependency Table empty.",
1116 			return -EINVAL);
1117 
1118 	vol_table->mask_low = 0;
1119 	vol_table->phase_delay = 0;
1120 	vol_table->count = dep_table->count;
1121 
1122 	for (i = 0; i < vol_table->count; i++) {
1123 		vol_table->entries[i].value = dep_table->entries[i].vddc;
1124 		vol_table->entries[i].smio_low = 0;
1125 	}
1126 
1127 	return 0;
1128 }
1129 
1130 /* ---- Voltage Tables ----
1131  * If the voltage table would be bigger than
1132  * what will fit into the state table on
1133  * the SMC keep only the higher entries.
1134  */
1135 static void vega10_trim_voltage_table_to_fit_state_table(
1136 		struct pp_hwmgr *hwmgr,
1137 		uint32_t max_vol_steps,
1138 		struct pp_atomfwctrl_voltage_table *vol_table)
1139 {
1140 	unsigned int i, diff;
1141 
1142 	if (vol_table->count <= max_vol_steps)
1143 		return;
1144 
1145 	diff = vol_table->count - max_vol_steps;
1146 
1147 	for (i = 0; i < max_vol_steps; i++)
1148 		vol_table->entries[i] = vol_table->entries[i + diff];
1149 
1150 	vol_table->count = max_vol_steps;
1151 }
1152 
1153 /**
1154  * vega10_construct_voltage_tables - Create Voltage Tables.
1155  *
1156  * @hwmgr:  the address of the powerplay hardware manager.
1157  * return:  always 0
1158  */
1159 static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1160 {
1161 	struct vega10_hwmgr *data = hwmgr->backend;
1162 	struct phm_ppt_v2_information *table_info =
1163 			(struct phm_ppt_v2_information *)hwmgr->pptable;
1164 	int result;
1165 
1166 	if (data->mvdd_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1167 			data->mvdd_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1168 		result = vega10_get_mvdd_voltage_table(hwmgr,
1169 				table_info->vdd_dep_on_mclk,
1170 				&(data->mvdd_voltage_table));
1171 		PP_ASSERT_WITH_CODE(!result,
1172 				"Failed to retrieve MVDDC table!",
1173 				return result);
1174 	}
1175 
1176 	if (data->vddci_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1177 		result = vega10_get_vddci_voltage_table(hwmgr,
1178 				table_info->vdd_dep_on_mclk,
1179 				&(data->vddci_voltage_table));
1180 		PP_ASSERT_WITH_CODE(!result,
1181 				"Failed to retrieve VDDCI_MEM table!",
1182 				return result);
1183 	}
1184 
1185 	if (data->vddc_control == VEGA10_VOLTAGE_CONTROL_BY_SVID2 ||
1186 			data->vddc_control == VEGA10_VOLTAGE_CONTROL_NONE) {
1187 		result = vega10_get_vdd_voltage_table(hwmgr,
1188 				table_info->vdd_dep_on_sclk,
1189 				&(data->vddc_voltage_table));
1190 		PP_ASSERT_WITH_CODE(!result,
1191 				"Failed to retrieve VDDCR_SOC table!",
1192 				return result);
1193 	}
1194 
1195 	PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 16,
1196 			"Too many voltage values for VDDC. Trimming to fit state table.",
1197 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1198 					16, &(data->vddc_voltage_table)));
1199 
1200 	PP_ASSERT_WITH_CODE(data->vddci_voltage_table.count <= 16,
1201 			"Too many voltage values for VDDCI. Trimming to fit state table.",
1202 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1203 					16, &(data->vddci_voltage_table)));
1204 
1205 	PP_ASSERT_WITH_CODE(data->mvdd_voltage_table.count <= 16,
1206 			"Too many voltage values for MVDD. Trimming to fit state table.",
1207 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,
1208 					16, &(data->mvdd_voltage_table)));
1209 
1210 
1211 	return 0;
1212 }
1213 
1214 /*
1215  * vega10_init_dpm_state
1216  * Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
1217  *
1218  * @dpm_state: - the address of the DPM Table to initiailize.
1219  * return:   None.
1220  */
1221 static void vega10_init_dpm_state(struct vega10_dpm_state *dpm_state)
1222 {
1223 	dpm_state->soft_min_level = 0xff;
1224 	dpm_state->soft_max_level = 0xff;
1225 	dpm_state->hard_min_level = 0xff;
1226 	dpm_state->hard_max_level = 0xff;
1227 }
1228 
1229 static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
1230 		struct vega10_single_dpm_table *dpm_table,
1231 		struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
1232 {
1233 	int i;
1234 
1235 	dpm_table->count = 0;
1236 
1237 	for (i = 0; i < dep_table->count; i++) {
1238 		if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <=
1239 				dep_table->entries[i].clk) {
1240 			dpm_table->dpm_levels[dpm_table->count].value =
1241 					dep_table->entries[i].clk;
1242 			dpm_table->dpm_levels[dpm_table->count].enabled = true;
1243 			dpm_table->count++;
1244 		}
1245 	}
1246 }
1247 static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1248 {
1249 	struct vega10_hwmgr *data = hwmgr->backend;
1250 	struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
1251 	struct phm_ppt_v2_information *table_info =
1252 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1253 	struct phm_ppt_v1_pcie_table *bios_pcie_table =
1254 			table_info->pcie_table;
1255 	uint32_t i;
1256 
1257 	PP_ASSERT_WITH_CODE(bios_pcie_table->count,
1258 			"Incorrect number of PCIE States from VBIOS!",
1259 			return -1);
1260 
1261 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
1262 		if (data->registry_data.pcieSpeedOverride)
1263 			pcie_table->pcie_gen[i] =
1264 					data->registry_data.pcieSpeedOverride;
1265 		else
1266 			pcie_table->pcie_gen[i] =
1267 					bios_pcie_table->entries[i].gen_speed;
1268 
1269 		if (data->registry_data.pcieLaneOverride)
1270 			pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1271 					data->registry_data.pcieLaneOverride);
1272 		else
1273 			pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(
1274 							bios_pcie_table->entries[i].lane_width);
1275 		if (data->registry_data.pcieClockOverride)
1276 			pcie_table->lclk[i] =
1277 					data->registry_data.pcieClockOverride;
1278 		else
1279 			pcie_table->lclk[i] =
1280 					bios_pcie_table->entries[i].pcie_sclk;
1281 	}
1282 
1283 	pcie_table->count = NUM_LINK_LEVELS;
1284 
1285 	return 0;
1286 }
1287 
1288 /*
1289  * This function is to initialize all DPM state tables
1290  * for SMU based on the dependency table.
1291  * Dynamic state patching function will then trim these
1292  * state tables to the allowed range based
1293  * on the power policy or external client requests,
1294  * such as UVD request, etc.
1295  */
1296 static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1297 {
1298 	struct vega10_hwmgr *data = hwmgr->backend;
1299 	struct phm_ppt_v2_information *table_info =
1300 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1301 	struct vega10_single_dpm_table *dpm_table;
1302 	uint32_t i;
1303 
1304 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_soc_table =
1305 			table_info->vdd_dep_on_socclk;
1306 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_gfx_table =
1307 			table_info->vdd_dep_on_sclk;
1308 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1309 			table_info->vdd_dep_on_mclk;
1310 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_mm_table =
1311 			table_info->mm_dep_table;
1312 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_dcef_table =
1313 			table_info->vdd_dep_on_dcefclk;
1314 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_pix_table =
1315 			table_info->vdd_dep_on_pixclk;
1316 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_disp_table =
1317 			table_info->vdd_dep_on_dispclk;
1318 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_phy_table =
1319 			table_info->vdd_dep_on_phyclk;
1320 
1321 	PP_ASSERT_WITH_CODE(dep_soc_table,
1322 			"SOCCLK dependency table is missing. This table is mandatory",
1323 			return -EINVAL);
1324 	PP_ASSERT_WITH_CODE(dep_soc_table->count >= 1,
1325 			"SOCCLK dependency table is empty. This table is mandatory",
1326 			return -EINVAL);
1327 
1328 	PP_ASSERT_WITH_CODE(dep_gfx_table,
1329 			"GFXCLK dependency table is missing. This table is mandatory",
1330 			return -EINVAL);
1331 	PP_ASSERT_WITH_CODE(dep_gfx_table->count >= 1,
1332 			"GFXCLK dependency table is empty. This table is mandatory",
1333 			return -EINVAL);
1334 
1335 	PP_ASSERT_WITH_CODE(dep_mclk_table,
1336 			"MCLK dependency table is missing. This table is mandatory",
1337 			return -EINVAL);
1338 	PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1339 			"MCLK dependency table has to have is missing. This table is mandatory",
1340 			return -EINVAL);
1341 
1342 	/* Initialize Sclk DPM table based on allow Sclk values */
1343 	dpm_table = &(data->dpm_table.soc_table);
1344 	vega10_setup_default_single_dpm_table(hwmgr,
1345 			dpm_table,
1346 			dep_soc_table);
1347 
1348 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1349 
1350 	dpm_table = &(data->dpm_table.gfx_table);
1351 	vega10_setup_default_single_dpm_table(hwmgr,
1352 			dpm_table,
1353 			dep_gfx_table);
1354 	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
1355 		hwmgr->platform_descriptor.overdriveLimit.engineClock =
1356 					dpm_table->dpm_levels[dpm_table->count-1].value;
1357 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1358 
1359 	/* Initialize Mclk DPM table based on allow Mclk values */
1360 	data->dpm_table.mem_table.count = 0;
1361 	dpm_table = &(data->dpm_table.mem_table);
1362 	vega10_setup_default_single_dpm_table(hwmgr,
1363 			dpm_table,
1364 			dep_mclk_table);
1365 	if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
1366 		hwmgr->platform_descriptor.overdriveLimit.memoryClock =
1367 					dpm_table->dpm_levels[dpm_table->count-1].value;
1368 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1369 
1370 	data->dpm_table.eclk_table.count = 0;
1371 	dpm_table = &(data->dpm_table.eclk_table);
1372 	for (i = 0; i < dep_mm_table->count; i++) {
1373 		if (i == 0 || dpm_table->dpm_levels
1374 				[dpm_table->count - 1].value <=
1375 						dep_mm_table->entries[i].eclk) {
1376 			dpm_table->dpm_levels[dpm_table->count].value =
1377 					dep_mm_table->entries[i].eclk;
1378 			dpm_table->dpm_levels[dpm_table->count].enabled = i == 0;
1379 			dpm_table->count++;
1380 		}
1381 	}
1382 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1383 
1384 	data->dpm_table.vclk_table.count = 0;
1385 	data->dpm_table.dclk_table.count = 0;
1386 	dpm_table = &(data->dpm_table.vclk_table);
1387 	for (i = 0; i < dep_mm_table->count; i++) {
1388 		if (i == 0 || dpm_table->dpm_levels
1389 				[dpm_table->count - 1].value <=
1390 						dep_mm_table->entries[i].vclk) {
1391 			dpm_table->dpm_levels[dpm_table->count].value =
1392 					dep_mm_table->entries[i].vclk;
1393 			dpm_table->dpm_levels[dpm_table->count].enabled = i == 0;
1394 			dpm_table->count++;
1395 		}
1396 	}
1397 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1398 
1399 	dpm_table = &(data->dpm_table.dclk_table);
1400 	for (i = 0; i < dep_mm_table->count; i++) {
1401 		if (i == 0 || dpm_table->dpm_levels
1402 				[dpm_table->count - 1].value <=
1403 						dep_mm_table->entries[i].dclk) {
1404 			dpm_table->dpm_levels[dpm_table->count].value =
1405 					dep_mm_table->entries[i].dclk;
1406 			dpm_table->dpm_levels[dpm_table->count].enabled = i == 0;
1407 			dpm_table->count++;
1408 		}
1409 	}
1410 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1411 
1412 	/* Assume there is no headless Vega10 for now */
1413 	dpm_table = &(data->dpm_table.dcef_table);
1414 	vega10_setup_default_single_dpm_table(hwmgr,
1415 			dpm_table,
1416 			dep_dcef_table);
1417 
1418 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1419 
1420 	dpm_table = &(data->dpm_table.pixel_table);
1421 	vega10_setup_default_single_dpm_table(hwmgr,
1422 			dpm_table,
1423 			dep_pix_table);
1424 
1425 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1426 
1427 	dpm_table = &(data->dpm_table.display_table);
1428 	vega10_setup_default_single_dpm_table(hwmgr,
1429 			dpm_table,
1430 			dep_disp_table);
1431 
1432 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1433 
1434 	dpm_table = &(data->dpm_table.phy_table);
1435 	vega10_setup_default_single_dpm_table(hwmgr,
1436 			dpm_table,
1437 			dep_phy_table);
1438 
1439 	vega10_init_dpm_state(&(dpm_table->dpm_state));
1440 
1441 	vega10_setup_default_pcie_table(hwmgr);
1442 
1443 	/* Zero out the saved copy of the CUSTOM profile
1444 	 * This will be checked when trying to set the profile
1445 	 * and will require that new values be passed in
1446 	 */
1447 	data->custom_profile_mode[0] = 0;
1448 	data->custom_profile_mode[1] = 0;
1449 	data->custom_profile_mode[2] = 0;
1450 	data->custom_profile_mode[3] = 0;
1451 
1452 	/* save a copy of the default DPM table */
1453 	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1454 			sizeof(struct vega10_dpm_table));
1455 
1456 	return 0;
1457 }
1458 
1459 /*
1460  * vega10_populate_ulv_state
1461  * Function to provide parameters for Utral Low Voltage state to SMC.
1462  *
1463  * @hwmgr: - the address of the hardware manager.
1464  * return:   Always 0.
1465  */
1466 static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
1467 {
1468 	struct vega10_hwmgr *data = hwmgr->backend;
1469 	struct phm_ppt_v2_information *table_info =
1470 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1471 
1472 	data->smc_state_table.pp_table.UlvOffsetVid =
1473 			(uint8_t)table_info->us_ulv_voltage_offset;
1474 
1475 	data->smc_state_table.pp_table.UlvSmnclkDid =
1476 			(uint8_t)(table_info->us_ulv_smnclk_did);
1477 	data->smc_state_table.pp_table.UlvMp1clkDid =
1478 			(uint8_t)(table_info->us_ulv_mp1clk_did);
1479 	data->smc_state_table.pp_table.UlvGfxclkBypass =
1480 			(uint8_t)(table_info->us_ulv_gfxclk_bypass);
1481 	data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 =
1482 			(uint8_t)(data->vddc_voltage_table.psi0_enable);
1483 	data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 =
1484 			(uint8_t)(data->vddc_voltage_table.psi1_enable);
1485 
1486 	return 0;
1487 }
1488 
1489 static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
1490 		uint32_t lclock, uint8_t *curr_lclk_did)
1491 {
1492 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1493 
1494 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1495 			hwmgr,
1496 			COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1497 			lclock, &dividers),
1498 			"Failed to get LCLK clock settings from VBIOS!",
1499 			return -1);
1500 
1501 	*curr_lclk_did = dividers.ulDid;
1502 
1503 	return 0;
1504 }
1505 
1506 static int vega10_override_pcie_parameters(struct pp_hwmgr *hwmgr)
1507 {
1508 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
1509 	struct vega10_hwmgr *data =
1510 			(struct vega10_hwmgr *)(hwmgr->backend);
1511 	uint32_t pcie_gen = 0, pcie_width = 0;
1512 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1513 	int i;
1514 
1515 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1516 		pcie_gen = 3;
1517 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1518 		pcie_gen = 2;
1519 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1520 		pcie_gen = 1;
1521 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1522 		pcie_gen = 0;
1523 
1524 	if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1525 		pcie_width = 6;
1526 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1527 		pcie_width = 5;
1528 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1529 		pcie_width = 4;
1530 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1531 		pcie_width = 3;
1532 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1533 		pcie_width = 2;
1534 	else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1535 		pcie_width = 1;
1536 
1537 	for (i = 0; i < NUM_LINK_LEVELS; i++) {
1538 		if (pp_table->PcieGenSpeed[i] > pcie_gen)
1539 			pp_table->PcieGenSpeed[i] = pcie_gen;
1540 
1541 		if (pp_table->PcieLaneCount[i] > pcie_width)
1542 			pp_table->PcieLaneCount[i] = pcie_width;
1543 	}
1544 
1545 	if (data->registry_data.pcie_dpm_key_disabled) {
1546 		for (i = 0; i < NUM_LINK_LEVELS; i++) {
1547 			pp_table->PcieGenSpeed[i] = pcie_gen;
1548 			pp_table->PcieLaneCount[i] = pcie_width;
1549 		}
1550 	}
1551 
1552 	return 0;
1553 }
1554 
1555 static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
1556 {
1557 	int result = -1;
1558 	struct vega10_hwmgr *data = hwmgr->backend;
1559 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1560 	struct vega10_pcie_table *pcie_table =
1561 			&(data->dpm_table.pcie_table);
1562 	uint32_t i, j;
1563 
1564 	for (i = 0; i < pcie_table->count; i++) {
1565 		pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[i];
1566 		pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i];
1567 
1568 		result = vega10_populate_single_lclk_level(hwmgr,
1569 				pcie_table->lclk[i], &(pp_table->LclkDid[i]));
1570 		if (result) {
1571 			pr_info("Populate LClock Level %d Failed!\n", i);
1572 			return result;
1573 		}
1574 	}
1575 
1576 	j = i - 1;
1577 	while (i < NUM_LINK_LEVELS) {
1578 		pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j];
1579 		pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j];
1580 
1581 		result = vega10_populate_single_lclk_level(hwmgr,
1582 				pcie_table->lclk[j], &(pp_table->LclkDid[i]));
1583 		if (result) {
1584 			pr_info("Populate LClock Level %d Failed!\n", i);
1585 			return result;
1586 		}
1587 		i++;
1588 	}
1589 
1590 	return result;
1591 }
1592 
1593 /**
1594  * vega10_populate_single_gfx_level - Populates single SMC GFXSCLK structure
1595  *                                    using the provided engine clock
1596  *
1597  * @hwmgr:      the address of the hardware manager
1598  * @gfx_clock:  the GFX clock to use to populate the structure.
1599  * @current_gfxclk_level:  location in PPTable for the SMC GFXCLK structure.
1600  * @acg_freq:   ACG frequenty to return (MHz)
1601  */
1602 static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
1603 		uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,
1604 		uint32_t *acg_freq)
1605 {
1606 	struct phm_ppt_v2_information *table_info =
1607 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1608 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_sclk;
1609 	struct vega10_hwmgr *data = hwmgr->backend;
1610 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1611 	uint32_t gfx_max_clock =
1612 			hwmgr->platform_descriptor.overdriveLimit.engineClock;
1613 	uint32_t i = 0;
1614 
1615 	if (hwmgr->od_enabled)
1616 		dep_on_sclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1617 						&(data->odn_dpm_table.vdd_dep_on_sclk);
1618 	else
1619 		dep_on_sclk = table_info->vdd_dep_on_sclk;
1620 
1621 	PP_ASSERT_WITH_CODE(dep_on_sclk,
1622 			"Invalid SOC_VDD-GFX_CLK Dependency Table!",
1623 			return -EINVAL);
1624 
1625 	if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
1626 		gfx_clock = gfx_clock > gfx_max_clock ? gfx_max_clock : gfx_clock;
1627 	else {
1628 		for (i = 0; i < dep_on_sclk->count; i++) {
1629 			if (dep_on_sclk->entries[i].clk == gfx_clock)
1630 				break;
1631 		}
1632 		PP_ASSERT_WITH_CODE(dep_on_sclk->count > i,
1633 				"Cannot find gfx_clk in SOC_VDD-GFX_CLK!",
1634 				return -EINVAL);
1635 	}
1636 
1637 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1638 			COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK,
1639 			gfx_clock, &dividers),
1640 			"Failed to get GFX Clock settings from VBIOS!",
1641 			return -EINVAL);
1642 
1643 	/* Feedback Multiplier: bit 0:8 int, bit 15:12 post_div, bit 31:16 frac */
1644 	current_gfxclk_level->FbMult =
1645 			cpu_to_le32(dividers.ulPll_fb_mult);
1646 	/* Spread FB Multiplier bit: bit 0:8 int, bit 31:16 frac */
1647 	current_gfxclk_level->SsOn = dividers.ucPll_ss_enable;
1648 	current_gfxclk_level->SsFbMult =
1649 			cpu_to_le32(dividers.ulPll_ss_fbsmult);
1650 	current_gfxclk_level->SsSlewFrac =
1651 			cpu_to_le16(dividers.usPll_ss_slew_frac);
1652 	current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);
1653 
1654 	*acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */
1655 
1656 	return 0;
1657 }
1658 
1659 /**
1660  * vega10_populate_single_soc_level - Populates single SMC SOCCLK structure
1661  *                                    using the provided clock.
1662  *
1663  * @hwmgr:     the address of the hardware manager.
1664  * @soc_clock: the SOC clock to use to populate the structure.
1665  * @current_soc_did:   DFS divider to pass back to caller
1666  * @current_vol_index: index of current VDD to pass back to caller
1667  * return:      0 on success
1668  */
1669 static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
1670 		uint32_t soc_clock, uint8_t *current_soc_did,
1671 		uint8_t *current_vol_index)
1672 {
1673 	struct vega10_hwmgr *data = hwmgr->backend;
1674 	struct phm_ppt_v2_information *table_info =
1675 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1676 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_soc;
1677 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1678 	uint32_t i;
1679 
1680 	if (hwmgr->od_enabled) {
1681 		dep_on_soc = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1682 						&data->odn_dpm_table.vdd_dep_on_socclk;
1683 		for (i = 0; i < dep_on_soc->count; i++) {
1684 			if (dep_on_soc->entries[i].clk >= soc_clock)
1685 				break;
1686 		}
1687 	} else {
1688 		dep_on_soc = table_info->vdd_dep_on_socclk;
1689 		for (i = 0; i < dep_on_soc->count; i++) {
1690 			if (dep_on_soc->entries[i].clk == soc_clock)
1691 				break;
1692 		}
1693 	}
1694 
1695 	PP_ASSERT_WITH_CODE(dep_on_soc->count > i,
1696 			"Cannot find SOC_CLK in SOC_VDD-SOC_CLK Dependency Table",
1697 			return -EINVAL);
1698 
1699 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1700 			COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1701 			soc_clock, &dividers),
1702 			"Failed to get SOC Clock settings from VBIOS!",
1703 			return -EINVAL);
1704 
1705 	*current_soc_did = (uint8_t)dividers.ulDid;
1706 	*current_vol_index = (uint8_t)(dep_on_soc->entries[i].vddInd);
1707 	return 0;
1708 }
1709 
1710 /**
1711  * vega10_populate_all_graphic_levels - Populates all SMC SCLK levels' structure
1712  *                                      based on the trimmed allowed dpm engine clock states
1713  *
1714  * @hwmgr:      the address of the hardware manager
1715  */
1716 static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1717 {
1718 	struct vega10_hwmgr *data = hwmgr->backend;
1719 	struct phm_ppt_v2_information *table_info =
1720 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1721 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1722 	struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
1723 	int result = 0;
1724 	uint32_t i, j;
1725 
1726 	for (i = 0; i < dpm_table->count; i++) {
1727 		result = vega10_populate_single_gfx_level(hwmgr,
1728 				dpm_table->dpm_levels[i].value,
1729 				&(pp_table->GfxclkLevel[i]),
1730 				&(pp_table->AcgFreqTable[i]));
1731 		if (result)
1732 			return result;
1733 	}
1734 
1735 	j = i - 1;
1736 	while (i < NUM_GFXCLK_DPM_LEVELS) {
1737 		result = vega10_populate_single_gfx_level(hwmgr,
1738 				dpm_table->dpm_levels[j].value,
1739 				&(pp_table->GfxclkLevel[i]),
1740 				&(pp_table->AcgFreqTable[i]));
1741 		if (result)
1742 			return result;
1743 		i++;
1744 	}
1745 
1746 	pp_table->GfxclkSlewRate =
1747 			cpu_to_le16(table_info->us_gfxclk_slew_rate);
1748 
1749 	dpm_table = &(data->dpm_table.soc_table);
1750 	for (i = 0; i < dpm_table->count; i++) {
1751 		result = vega10_populate_single_soc_level(hwmgr,
1752 				dpm_table->dpm_levels[i].value,
1753 				&(pp_table->SocclkDid[i]),
1754 				&(pp_table->SocDpmVoltageIndex[i]));
1755 		if (result)
1756 			return result;
1757 	}
1758 
1759 	j = i - 1;
1760 	while (i < NUM_SOCCLK_DPM_LEVELS) {
1761 		result = vega10_populate_single_soc_level(hwmgr,
1762 				dpm_table->dpm_levels[j].value,
1763 				&(pp_table->SocclkDid[i]),
1764 				&(pp_table->SocDpmVoltageIndex[i]));
1765 		if (result)
1766 			return result;
1767 		i++;
1768 	}
1769 
1770 	return result;
1771 }
1772 
1773 static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
1774 {
1775 	struct vega10_hwmgr *data = hwmgr->backend;
1776 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1777 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
1778 	struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
1779 
1780 	uint8_t soc_vid = 0;
1781 	uint32_t i, max_vddc_level;
1782 
1783 	if (hwmgr->od_enabled)
1784 		vddc_lookup_table = (struct phm_ppt_v1_voltage_lookup_table *)&data->odn_dpm_table.vddc_lookup_table;
1785 	else
1786 		vddc_lookup_table = table_info->vddc_lookup_table;
1787 
1788 	max_vddc_level = vddc_lookup_table->count;
1789 	for (i = 0; i < max_vddc_level; i++) {
1790 		soc_vid = (uint8_t)convert_to_vid(vddc_lookup_table->entries[i].us_vdd);
1791 		pp_table->SocVid[i] = soc_vid;
1792 	}
1793 	while (i < MAX_REGULAR_DPM_NUMBER) {
1794 		pp_table->SocVid[i] = soc_vid;
1795 		i++;
1796 	}
1797 }
1798 
1799 /*
1800  * Populates single SMC GFXCLK structure using the provided clock.
1801  *
1802  * @hwmgr:     the address of the hardware manager.
1803  * @mem_clock: the memory clock to use to populate the structure.
1804  * return:     0 on success..
1805  */
1806 static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1807 		uint32_t mem_clock, uint8_t *current_mem_vid,
1808 		PllSetting_t *current_memclk_level, uint8_t *current_mem_soc_vind)
1809 {
1810 	struct vega10_hwmgr *data = hwmgr->backend;
1811 	struct phm_ppt_v2_information *table_info =
1812 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1813 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_on_mclk;
1814 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1815 	uint32_t mem_max_clock =
1816 			hwmgr->platform_descriptor.overdriveLimit.memoryClock;
1817 	uint32_t i = 0;
1818 
1819 	if (hwmgr->od_enabled)
1820 		dep_on_mclk = (struct phm_ppt_v1_clock_voltage_dependency_table *)
1821 					&data->odn_dpm_table.vdd_dep_on_mclk;
1822 	else
1823 		dep_on_mclk = table_info->vdd_dep_on_mclk;
1824 
1825 	PP_ASSERT_WITH_CODE(dep_on_mclk,
1826 			"Invalid SOC_VDD-UCLK Dependency Table!",
1827 			return -EINVAL);
1828 
1829 	if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
1830 		mem_clock = mem_clock > mem_max_clock ? mem_max_clock : mem_clock;
1831 	} else {
1832 		for (i = 0; i < dep_on_mclk->count; i++) {
1833 			if (dep_on_mclk->entries[i].clk == mem_clock)
1834 				break;
1835 		}
1836 		PP_ASSERT_WITH_CODE(dep_on_mclk->count > i,
1837 				"Cannot find UCLK in SOC_VDD-UCLK Dependency Table!",
1838 				return -EINVAL);
1839 	}
1840 
1841 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(
1842 			hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
1843 			"Failed to get UCLK settings from VBIOS!",
1844 			return -1);
1845 
1846 	*current_mem_vid =
1847 			(uint8_t)(convert_to_vid(dep_on_mclk->entries[i].mvdd));
1848 	*current_mem_soc_vind =
1849 			(uint8_t)(dep_on_mclk->entries[i].vddInd);
1850 	current_memclk_level->FbMult = cpu_to_le32(dividers.ulPll_fb_mult);
1851 	current_memclk_level->Did = (uint8_t)(dividers.ulDid);
1852 
1853 	PP_ASSERT_WITH_CODE(current_memclk_level->Did >= 1,
1854 			"Invalid Divider ID!",
1855 			return -EINVAL);
1856 
1857 	return 0;
1858 }
1859 
1860 /**
1861  * vega10_populate_all_memory_levels - Populates all SMC MCLK levels' structure
1862  *                                     based on the trimmed allowed dpm memory clock states.
1863  *
1864  * @hwmgr:  the address of the hardware manager.
1865  * return:   PP_Result_OK on success.
1866  */
1867 static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1868 {
1869 	struct vega10_hwmgr *data = hwmgr->backend;
1870 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1871 	struct vega10_single_dpm_table *dpm_table =
1872 			&(data->dpm_table.mem_table);
1873 	int result = 0;
1874 	uint32_t i, j;
1875 
1876 	for (i = 0; i < dpm_table->count; i++) {
1877 		result = vega10_populate_single_memory_level(hwmgr,
1878 				dpm_table->dpm_levels[i].value,
1879 				&(pp_table->MemVid[i]),
1880 				&(pp_table->UclkLevel[i]),
1881 				&(pp_table->MemSocVoltageIndex[i]));
1882 		if (result)
1883 			return result;
1884 	}
1885 
1886 	j = i - 1;
1887 	while (i < NUM_UCLK_DPM_LEVELS) {
1888 		result = vega10_populate_single_memory_level(hwmgr,
1889 				dpm_table->dpm_levels[j].value,
1890 				&(pp_table->MemVid[i]),
1891 				&(pp_table->UclkLevel[i]),
1892 				&(pp_table->MemSocVoltageIndex[i]));
1893 		if (result)
1894 			return result;
1895 		i++;
1896 	}
1897 
1898 	pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
1899 	pp_table->MemoryChannelWidth =
1900 			(uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
1901 					channel_number[data->mem_channels]);
1902 
1903 	pp_table->LowestUclkReservedForUlv =
1904 			(uint8_t)(data->lowest_uclk_reserved_for_ulv);
1905 
1906 	return result;
1907 }
1908 
1909 static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
1910 		DSPCLK_e disp_clock)
1911 {
1912 	struct vega10_hwmgr *data = hwmgr->backend;
1913 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
1914 	struct phm_ppt_v2_information *table_info =
1915 			(struct phm_ppt_v2_information *)
1916 			(hwmgr->pptable);
1917 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
1918 	uint32_t i;
1919 	uint16_t clk = 0, vddc = 0;
1920 	uint8_t vid = 0;
1921 
1922 	switch (disp_clock) {
1923 	case DSPCLK_DCEFCLK:
1924 		dep_table = table_info->vdd_dep_on_dcefclk;
1925 		break;
1926 	case DSPCLK_DISPCLK:
1927 		dep_table = table_info->vdd_dep_on_dispclk;
1928 		break;
1929 	case DSPCLK_PIXCLK:
1930 		dep_table = table_info->vdd_dep_on_pixclk;
1931 		break;
1932 	case DSPCLK_PHYCLK:
1933 		dep_table = table_info->vdd_dep_on_phyclk;
1934 		break;
1935 	default:
1936 		return -1;
1937 	}
1938 
1939 	PP_ASSERT_WITH_CODE(dep_table->count <= NUM_DSPCLK_LEVELS,
1940 			"Number Of Entries Exceeded maximum!",
1941 			return -1);
1942 
1943 	for (i = 0; i < dep_table->count; i++) {
1944 		clk = (uint16_t)(dep_table->entries[i].clk / 100);
1945 		vddc = table_info->vddc_lookup_table->
1946 				entries[dep_table->entries[i].vddInd].us_vdd;
1947 		vid = (uint8_t)convert_to_vid(vddc);
1948 		pp_table->DisplayClockTable[disp_clock][i].Freq =
1949 				cpu_to_le16(clk);
1950 		pp_table->DisplayClockTable[disp_clock][i].Vid =
1951 				cpu_to_le16(vid);
1952 	}
1953 
1954 	while (i < NUM_DSPCLK_LEVELS) {
1955 		pp_table->DisplayClockTable[disp_clock][i].Freq =
1956 				cpu_to_le16(clk);
1957 		pp_table->DisplayClockTable[disp_clock][i].Vid =
1958 				cpu_to_le16(vid);
1959 		i++;
1960 	}
1961 
1962 	return 0;
1963 }
1964 
1965 static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
1966 {
1967 	uint32_t i;
1968 
1969 	for (i = 0; i < DSPCLK_COUNT; i++) {
1970 		PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
1971 				"Failed to populate Clock in DisplayClockTable!",
1972 				return -1);
1973 	}
1974 
1975 	return 0;
1976 }
1977 
1978 static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
1979 		uint32_t eclock, uint8_t *current_eclk_did,
1980 		uint8_t *current_soc_vol)
1981 {
1982 	struct phm_ppt_v2_information *table_info =
1983 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
1984 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
1985 			table_info->mm_dep_table;
1986 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
1987 	uint32_t i;
1988 
1989 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
1990 			COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1991 			eclock, &dividers),
1992 			"Failed to get ECLK clock settings from VBIOS!",
1993 			return -1);
1994 
1995 	*current_eclk_did = (uint8_t)dividers.ulDid;
1996 
1997 	for (i = 0; i < dep_table->count; i++) {
1998 		if (dep_table->entries[i].eclk == eclock)
1999 			*current_soc_vol = dep_table->entries[i].vddcInd;
2000 	}
2001 
2002 	return 0;
2003 }
2004 
2005 static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
2006 {
2007 	struct vega10_hwmgr *data = hwmgr->backend;
2008 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2009 	struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.eclk_table);
2010 	int result = -EINVAL;
2011 	uint32_t i, j;
2012 
2013 	for (i = 0; i < dpm_table->count; i++) {
2014 		result = vega10_populate_single_eclock_level(hwmgr,
2015 				dpm_table->dpm_levels[i].value,
2016 				&(pp_table->EclkDid[i]),
2017 				&(pp_table->VceDpmVoltageIndex[i]));
2018 		if (result)
2019 			return result;
2020 	}
2021 
2022 	j = i - 1;
2023 	while (i < NUM_VCE_DPM_LEVELS) {
2024 		result = vega10_populate_single_eclock_level(hwmgr,
2025 				dpm_table->dpm_levels[j].value,
2026 				&(pp_table->EclkDid[i]),
2027 				&(pp_table->VceDpmVoltageIndex[i]));
2028 		if (result)
2029 			return result;
2030 		i++;
2031 	}
2032 
2033 	return result;
2034 }
2035 
2036 static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
2037 		uint32_t vclock, uint8_t *current_vclk_did)
2038 {
2039 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2040 
2041 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2042 			COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2043 			vclock, &dividers),
2044 			"Failed to get VCLK clock settings from VBIOS!",
2045 			return -EINVAL);
2046 
2047 	*current_vclk_did = (uint8_t)dividers.ulDid;
2048 
2049 	return 0;
2050 }
2051 
2052 static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
2053 		uint32_t dclock, uint8_t *current_dclk_did)
2054 {
2055 	struct pp_atomfwctrl_clock_dividers_soc15 dividers;
2056 
2057 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
2058 			COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2059 			dclock, &dividers),
2060 			"Failed to get DCLK clock settings from VBIOS!",
2061 			return -EINVAL);
2062 
2063 	*current_dclk_did = (uint8_t)dividers.ulDid;
2064 
2065 	return 0;
2066 }
2067 
2068 static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
2069 {
2070 	struct vega10_hwmgr *data = hwmgr->backend;
2071 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2072 	struct vega10_single_dpm_table *vclk_dpm_table =
2073 			&(data->dpm_table.vclk_table);
2074 	struct vega10_single_dpm_table *dclk_dpm_table =
2075 			&(data->dpm_table.dclk_table);
2076 	struct phm_ppt_v2_information *table_info =
2077 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
2078 	struct phm_ppt_v1_mm_clock_voltage_dependency_table *dep_table =
2079 			table_info->mm_dep_table;
2080 	int result = -EINVAL;
2081 	uint32_t i, j;
2082 
2083 	for (i = 0; i < vclk_dpm_table->count; i++) {
2084 		result = vega10_populate_single_vclock_level(hwmgr,
2085 				vclk_dpm_table->dpm_levels[i].value,
2086 				&(pp_table->VclkDid[i]));
2087 		if (result)
2088 			return result;
2089 	}
2090 
2091 	j = i - 1;
2092 	while (i < NUM_UVD_DPM_LEVELS) {
2093 		result = vega10_populate_single_vclock_level(hwmgr,
2094 				vclk_dpm_table->dpm_levels[j].value,
2095 				&(pp_table->VclkDid[i]));
2096 		if (result)
2097 			return result;
2098 		i++;
2099 	}
2100 
2101 	for (i = 0; i < dclk_dpm_table->count; i++) {
2102 		result = vega10_populate_single_dclock_level(hwmgr,
2103 				dclk_dpm_table->dpm_levels[i].value,
2104 				&(pp_table->DclkDid[i]));
2105 		if (result)
2106 			return result;
2107 	}
2108 
2109 	j = i - 1;
2110 	while (i < NUM_UVD_DPM_LEVELS) {
2111 		result = vega10_populate_single_dclock_level(hwmgr,
2112 				dclk_dpm_table->dpm_levels[j].value,
2113 				&(pp_table->DclkDid[i]));
2114 		if (result)
2115 			return result;
2116 		i++;
2117 	}
2118 
2119 	for (i = 0; i < dep_table->count; i++) {
2120 		if (dep_table->entries[i].vclk ==
2121 				vclk_dpm_table->dpm_levels[i].value &&
2122 			dep_table->entries[i].dclk ==
2123 				dclk_dpm_table->dpm_levels[i].value)
2124 			pp_table->UvdDpmVoltageIndex[i] =
2125 					dep_table->entries[i].vddcInd;
2126 		else
2127 			return -1;
2128 	}
2129 
2130 	j = i - 1;
2131 	while (i < NUM_UVD_DPM_LEVELS) {
2132 		pp_table->UvdDpmVoltageIndex[i] = dep_table->entries[j].vddcInd;
2133 		i++;
2134 	}
2135 
2136 	return 0;
2137 }
2138 
2139 static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
2140 {
2141 	struct vega10_hwmgr *data = hwmgr->backend;
2142 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2143 	struct phm_ppt_v2_information *table_info =
2144 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
2145 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2146 			table_info->vdd_dep_on_sclk;
2147 	uint32_t i;
2148 
2149 	for (i = 0; i < dep_table->count; i++) {
2150 		pp_table->CksEnable[i] = dep_table->entries[i].cks_enable;
2151 		pp_table->CksVidOffset[i] = (uint8_t)(dep_table->entries[i].cks_voffset
2152 				* VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2153 	}
2154 
2155 	return 0;
2156 }
2157 
2158 static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
2159 {
2160 	struct vega10_hwmgr *data = hwmgr->backend;
2161 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2162 	struct phm_ppt_v2_information *table_info =
2163 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
2164 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
2165 			table_info->vdd_dep_on_sclk;
2166 	struct pp_atomfwctrl_avfs_parameters avfs_params = {0};
2167 	int result = 0;
2168 	uint32_t i;
2169 
2170 	pp_table->MinVoltageVid = (uint8_t)0xff;
2171 	pp_table->MaxVoltageVid = (uint8_t)0;
2172 
2173 	if (data->smu_features[GNLD_AVFS].supported) {
2174 		result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
2175 		if (!result) {
2176 			pp_table->MinVoltageVid = (uint8_t)
2177 					convert_to_vid((uint16_t)(avfs_params.ulMinVddc));
2178 			pp_table->MaxVoltageVid = (uint8_t)
2179 					convert_to_vid((uint16_t)(avfs_params.ulMaxVddc));
2180 
2181 			pp_table->AConstant[0] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant0);
2182 			pp_table->AConstant[1] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant1);
2183 			pp_table->AConstant[2] = cpu_to_le32(avfs_params.ulMeanNsigmaAcontant2);
2184 			pp_table->DC_tol_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2185 			pp_table->Platform_mean = cpu_to_le16(avfs_params.usMeanNsigmaPlatformMean);
2186 			pp_table->Platform_sigma = cpu_to_le16(avfs_params.usMeanNsigmaDcTolSigma);
2187 			pp_table->PSM_Age_CompFactor = cpu_to_le16(avfs_params.usPsmAgeComfactor);
2188 
2189 			pp_table->BtcGbVdroopTableCksOff.a0 =
2190 					cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA0);
2191 			pp_table->BtcGbVdroopTableCksOff.a0_shift = 20;
2192 			pp_table->BtcGbVdroopTableCksOff.a1 =
2193 					cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA1);
2194 			pp_table->BtcGbVdroopTableCksOff.a1_shift = 20;
2195 			pp_table->BtcGbVdroopTableCksOff.a2 =
2196 					cpu_to_le32(avfs_params.ulGbVdroopTableCksoffA2);
2197 			pp_table->BtcGbVdroopTableCksOff.a2_shift = 20;
2198 
2199 			pp_table->OverrideBtcGbCksOn = avfs_params.ucEnableGbVdroopTableCkson;
2200 			pp_table->BtcGbVdroopTableCksOn.a0 =
2201 					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA0);
2202 			pp_table->BtcGbVdroopTableCksOn.a0_shift = 20;
2203 			pp_table->BtcGbVdroopTableCksOn.a1 =
2204 					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA1);
2205 			pp_table->BtcGbVdroopTableCksOn.a1_shift = 20;
2206 			pp_table->BtcGbVdroopTableCksOn.a2 =
2207 					cpu_to_le32(avfs_params.ulGbVdroopTableCksonA2);
2208 			pp_table->BtcGbVdroopTableCksOn.a2_shift = 20;
2209 
2210 			pp_table->AvfsGbCksOn.m1 =
2211 					cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
2212 			pp_table->AvfsGbCksOn.m2 =
2213 					cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
2214 			pp_table->AvfsGbCksOn.b =
2215 					cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
2216 			pp_table->AvfsGbCksOn.m1_shift = 24;
2217 			pp_table->AvfsGbCksOn.m2_shift = 12;
2218 			pp_table->AvfsGbCksOn.b_shift = 0;
2219 
2220 			pp_table->OverrideAvfsGbCksOn =
2221 					avfs_params.ucEnableGbFuseTableCkson;
2222 			pp_table->AvfsGbCksOff.m1 =
2223 					cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
2224 			pp_table->AvfsGbCksOff.m2 =
2225 					cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
2226 			pp_table->AvfsGbCksOff.b =
2227 					cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
2228 			pp_table->AvfsGbCksOff.m1_shift = 24;
2229 			pp_table->AvfsGbCksOff.m2_shift = 12;
2230 			pp_table->AvfsGbCksOff.b_shift = 0;
2231 
2232 			for (i = 0; i < dep_table->count; i++)
2233 				pp_table->StaticVoltageOffsetVid[i] =
2234 						convert_to_vid((uint8_t)(dep_table->entries[i].sclk_offset));
2235 
2236 			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2237 					data->disp_clk_quad_eqn_a) &&
2238 				(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2239 					data->disp_clk_quad_eqn_b)) {
2240 				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2241 						(int32_t)data->disp_clk_quad_eqn_a;
2242 				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2243 						(int32_t)data->disp_clk_quad_eqn_b;
2244 				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2245 						(int32_t)data->disp_clk_quad_eqn_c;
2246 			} else {
2247 				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1 =
2248 						(int32_t)avfs_params.ulDispclk2GfxclkM1;
2249 				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2 =
2250 						(int32_t)avfs_params.ulDispclk2GfxclkM2;
2251 				pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b =
2252 						(int32_t)avfs_params.ulDispclk2GfxclkB;
2253 			}
2254 
2255 			pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m1_shift = 24;
2256 			pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].m2_shift = 12;
2257 			pp_table->DisplayClock2Gfxclk[DSPCLK_DISPCLK].b_shift = 12;
2258 
2259 			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2260 					data->dcef_clk_quad_eqn_a) &&
2261 				(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2262 					data->dcef_clk_quad_eqn_b)) {
2263 				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2264 						(int32_t)data->dcef_clk_quad_eqn_a;
2265 				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2266 						(int32_t)data->dcef_clk_quad_eqn_b;
2267 				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2268 						(int32_t)data->dcef_clk_quad_eqn_c;
2269 			} else {
2270 				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1 =
2271 						(int32_t)avfs_params.ulDcefclk2GfxclkM1;
2272 				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2 =
2273 						(int32_t)avfs_params.ulDcefclk2GfxclkM2;
2274 				pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b =
2275 						(int32_t)avfs_params.ulDcefclk2GfxclkB;
2276 			}
2277 
2278 			pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m1_shift = 24;
2279 			pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].m2_shift = 12;
2280 			pp_table->DisplayClock2Gfxclk[DSPCLK_DCEFCLK].b_shift = 12;
2281 
2282 			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2283 					data->pixel_clk_quad_eqn_a) &&
2284 				(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2285 					data->pixel_clk_quad_eqn_b)) {
2286 				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2287 						(int32_t)data->pixel_clk_quad_eqn_a;
2288 				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2289 						(int32_t)data->pixel_clk_quad_eqn_b;
2290 				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2291 						(int32_t)data->pixel_clk_quad_eqn_c;
2292 			} else {
2293 				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1 =
2294 						(int32_t)avfs_params.ulPixelclk2GfxclkM1;
2295 				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2 =
2296 						(int32_t)avfs_params.ulPixelclk2GfxclkM2;
2297 				pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b =
2298 						(int32_t)avfs_params.ulPixelclk2GfxclkB;
2299 			}
2300 
2301 			pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m1_shift = 24;
2302 			pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].m2_shift = 12;
2303 			pp_table->DisplayClock2Gfxclk[DSPCLK_PIXCLK].b_shift = 12;
2304 			if ((PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2305 					data->phy_clk_quad_eqn_a) &&
2306 				(PPREGKEY_VEGA10QUADRATICEQUATION_DFLT !=
2307 					data->phy_clk_quad_eqn_b)) {
2308 				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2309 						(int32_t)data->phy_clk_quad_eqn_a;
2310 				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2311 						(int32_t)data->phy_clk_quad_eqn_b;
2312 				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2313 						(int32_t)data->phy_clk_quad_eqn_c;
2314 			} else {
2315 				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1 =
2316 						(int32_t)avfs_params.ulPhyclk2GfxclkM1;
2317 				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2 =
2318 						(int32_t)avfs_params.ulPhyclk2GfxclkM2;
2319 				pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b =
2320 						(int32_t)avfs_params.ulPhyclk2GfxclkB;
2321 			}
2322 
2323 			pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m1_shift = 24;
2324 			pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].m2_shift = 12;
2325 			pp_table->DisplayClock2Gfxclk[DSPCLK_PHYCLK].b_shift = 12;
2326 
2327 			pp_table->AcgBtcGbVdroopTable.a0       = avfs_params.ulAcgGbVdroopTableA0;
2328 			pp_table->AcgBtcGbVdroopTable.a0_shift = 20;
2329 			pp_table->AcgBtcGbVdroopTable.a1       = avfs_params.ulAcgGbVdroopTableA1;
2330 			pp_table->AcgBtcGbVdroopTable.a1_shift = 20;
2331 			pp_table->AcgBtcGbVdroopTable.a2       = avfs_params.ulAcgGbVdroopTableA2;
2332 			pp_table->AcgBtcGbVdroopTable.a2_shift = 20;
2333 
2334 			pp_table->AcgAvfsGb.m1                   = avfs_params.ulAcgGbFuseTableM1;
2335 			pp_table->AcgAvfsGb.m2                   = avfs_params.ulAcgGbFuseTableM2;
2336 			pp_table->AcgAvfsGb.b                    = avfs_params.ulAcgGbFuseTableB;
2337 			pp_table->AcgAvfsGb.m1_shift             = 24;
2338 			pp_table->AcgAvfsGb.m2_shift             = 12;
2339 			pp_table->AcgAvfsGb.b_shift              = 0;
2340 
2341 		} else {
2342 			data->smu_features[GNLD_AVFS].supported = false;
2343 		}
2344 	}
2345 
2346 	return 0;
2347 }
2348 
2349 static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
2350 {
2351 	struct vega10_hwmgr *data = hwmgr->backend;
2352 	uint32_t agc_btc_response;
2353 
2354 	if (data->smu_features[GNLD_ACG].supported) {
2355 		if (0 == vega10_enable_smc_features(hwmgr, true,
2356 					data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_bitmap))
2357 			data->smu_features[GNLD_DPM_PREFETCHER].enabled = true;
2358 
2359 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg, NULL);
2360 
2361 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &agc_btc_response);
2362 
2363 		if (1 == agc_btc_response) {
2364 			if (1 == data->acg_loop_state)
2365 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop, NULL);
2366 			else if (2 == data->acg_loop_state)
2367 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop, NULL);
2368 			if (0 == vega10_enable_smc_features(hwmgr, true,
2369 				data->smu_features[GNLD_ACG].smu_feature_bitmap))
2370 					data->smu_features[GNLD_ACG].enabled = true;
2371 		} else {
2372 			pr_info("[ACG_Enable] ACG BTC Returned Failed Status!\n");
2373 			data->smu_features[GNLD_ACG].enabled = false;
2374 		}
2375 	}
2376 
2377 	return 0;
2378 }
2379 
2380 static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
2381 {
2382 	struct vega10_hwmgr *data = hwmgr->backend;
2383 
2384 	if (data->smu_features[GNLD_ACG].supported &&
2385 	    data->smu_features[GNLD_ACG].enabled)
2386 		if (!vega10_enable_smc_features(hwmgr, false,
2387 			data->smu_features[GNLD_ACG].smu_feature_bitmap))
2388 			data->smu_features[GNLD_ACG].enabled = false;
2389 
2390 	return 0;
2391 }
2392 
2393 static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
2394 {
2395 	struct vega10_hwmgr *data = hwmgr->backend;
2396 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2397 	struct pp_atomfwctrl_gpio_parameters gpio_params = {0};
2398 	int result;
2399 
2400 	result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
2401 	if (!result) {
2402 		if (PP_CAP(PHM_PlatformCaps_RegulatorHot) &&
2403 		    data->registry_data.regulator_hot_gpio_support) {
2404 			pp_table->VR0HotGpio = gpio_params.ucVR0HotGpio;
2405 			pp_table->VR0HotPolarity = gpio_params.ucVR0HotPolarity;
2406 			pp_table->VR1HotGpio = gpio_params.ucVR1HotGpio;
2407 			pp_table->VR1HotPolarity = gpio_params.ucVR1HotPolarity;
2408 		} else {
2409 			pp_table->VR0HotGpio = 0;
2410 			pp_table->VR0HotPolarity = 0;
2411 			pp_table->VR1HotGpio = 0;
2412 			pp_table->VR1HotPolarity = 0;
2413 		}
2414 
2415 		if (PP_CAP(PHM_PlatformCaps_AutomaticDCTransition) &&
2416 		    data->registry_data.ac_dc_switch_gpio_support) {
2417 			pp_table->AcDcGpio = gpio_params.ucAcDcGpio;
2418 			pp_table->AcDcPolarity = gpio_params.ucAcDcPolarity;
2419 		} else {
2420 			pp_table->AcDcGpio = 0;
2421 			pp_table->AcDcPolarity = 0;
2422 		}
2423 	}
2424 
2425 	return result;
2426 }
2427 
2428 static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
2429 {
2430 	struct vega10_hwmgr *data = hwmgr->backend;
2431 
2432 	if (data->smu_features[GNLD_AVFS].supported) {
2433 		/* Already enabled or disabled */
2434 		if (!(enable ^ data->smu_features[GNLD_AVFS].enabled))
2435 			return 0;
2436 
2437 		if (enable) {
2438 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2439 					true,
2440 					data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2441 					"[avfs_control] Attempt to Enable AVFS feature Failed!",
2442 					return -1);
2443 			data->smu_features[GNLD_AVFS].enabled = true;
2444 		} else {
2445 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2446 					false,
2447 					data->smu_features[GNLD_AVFS].smu_feature_bitmap),
2448 					"[avfs_control] Attempt to Disable AVFS feature Failed!",
2449 					return -1);
2450 			data->smu_features[GNLD_AVFS].enabled = false;
2451 		}
2452 	}
2453 
2454 	return 0;
2455 }
2456 
2457 static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
2458 {
2459 	struct vega10_hwmgr *data = hwmgr->backend;
2460 
2461 	if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
2462 		vega10_avfs_enable(hwmgr, false);
2463 	} else if (data->need_update_dpm_table) {
2464 		vega10_avfs_enable(hwmgr, false);
2465 		vega10_avfs_enable(hwmgr, true);
2466 	} else {
2467 		vega10_avfs_enable(hwmgr, true);
2468 	}
2469 
2470 	return 0;
2471 }
2472 
2473 static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
2474 {
2475 	int result = 0;
2476 
2477 	uint64_t serial_number = 0;
2478 	uint32_t top32, bottom32;
2479 	struct phm_fuses_default fuse;
2480 
2481 	struct vega10_hwmgr *data = hwmgr->backend;
2482 	AvfsFuseOverride_t *avfs_fuse_table = &(data->smc_state_table.avfs_fuse_override_table);
2483 
2484 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
2485 
2486 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
2487 
2488 	serial_number = ((uint64_t)bottom32 << 32) | top32;
2489 
2490 	if (pp_override_get_default_fuse_value(serial_number, &fuse) == 0) {
2491 		avfs_fuse_table->VFT0_b  = fuse.VFT0_b;
2492 		avfs_fuse_table->VFT0_m1 = fuse.VFT0_m1;
2493 		avfs_fuse_table->VFT0_m2 = fuse.VFT0_m2;
2494 		avfs_fuse_table->VFT1_b  = fuse.VFT1_b;
2495 		avfs_fuse_table->VFT1_m1 = fuse.VFT1_m1;
2496 		avfs_fuse_table->VFT1_m2 = fuse.VFT1_m2;
2497 		avfs_fuse_table->VFT2_b  = fuse.VFT2_b;
2498 		avfs_fuse_table->VFT2_m1 = fuse.VFT2_m1;
2499 		avfs_fuse_table->VFT2_m2 = fuse.VFT2_m2;
2500 		result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
2501 						AVFSFUSETABLE, false);
2502 		PP_ASSERT_WITH_CODE(!result,
2503 			"Failed to upload FuseOVerride!",
2504 			);
2505 	}
2506 
2507 	return result;
2508 }
2509 
2510 static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
2511 {
2512 	struct vega10_hwmgr *data = hwmgr->backend;
2513 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2514 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
2515 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
2516 	struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table;
2517 	uint32_t i;
2518 
2519 	dep_table = table_info->vdd_dep_on_mclk;
2520 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_mclk);
2521 
2522 	for (i = 0; i < dep_table->count; i++) {
2523 		if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2524 			data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK;
2525 			return;
2526 		}
2527 	}
2528 
2529 	dep_table = table_info->vdd_dep_on_sclk;
2530 	odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dep_on_sclk);
2531 	for (i = 0; i < dep_table->count; i++) {
2532 		if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) {
2533 			data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK;
2534 			return;
2535 		}
2536 	}
2537 }
2538 
2539 /**
2540  * vega10_init_smc_table - Initializes the SMC table and uploads it
2541  *
2542  * @hwmgr:  the address of the powerplay hardware manager.
2543  * return:  always 0
2544  */
2545 static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
2546 {
2547 	int result;
2548 	struct vega10_hwmgr *data = hwmgr->backend;
2549 	struct phm_ppt_v2_information *table_info =
2550 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
2551 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2552 	struct pp_atomfwctrl_voltage_table voltage_table;
2553 	struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
2554 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
2555 
2556 	result = vega10_setup_default_dpm_tables(hwmgr);
2557 	PP_ASSERT_WITH_CODE(!result,
2558 			"Failed to setup default DPM tables!",
2559 			return result);
2560 
2561 	if (!hwmgr->not_vf)
2562 		return 0;
2563 
2564 	/* initialize ODN table */
2565 	if (hwmgr->od_enabled) {
2566 		if (odn_table->max_vddc) {
2567 			data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
2568 			vega10_check_dpm_table_updated(hwmgr);
2569 		} else {
2570 			vega10_odn_initial_default_setting(hwmgr);
2571 		}
2572 	}
2573 
2574 	pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
2575 			VOLTAGE_OBJ_SVID2,  &voltage_table);
2576 	pp_table->MaxVidStep = voltage_table.max_vid_step;
2577 
2578 	pp_table->GfxDpmVoltageMode =
2579 			(uint8_t)(table_info->uc_gfx_dpm_voltage_mode);
2580 	pp_table->SocDpmVoltageMode =
2581 			(uint8_t)(table_info->uc_soc_dpm_voltage_mode);
2582 	pp_table->UclkDpmVoltageMode =
2583 			(uint8_t)(table_info->uc_uclk_dpm_voltage_mode);
2584 	pp_table->UvdDpmVoltageMode =
2585 			(uint8_t)(table_info->uc_uvd_dpm_voltage_mode);
2586 	pp_table->VceDpmVoltageMode =
2587 			(uint8_t)(table_info->uc_vce_dpm_voltage_mode);
2588 	pp_table->Mp0DpmVoltageMode =
2589 			(uint8_t)(table_info->uc_mp0_dpm_voltage_mode);
2590 
2591 	pp_table->DisplayDpmVoltageMode =
2592 			(uint8_t)(table_info->uc_dcef_dpm_voltage_mode);
2593 
2594 	data->vddc_voltage_table.psi0_enable = voltage_table.psi0_enable;
2595 	data->vddc_voltage_table.psi1_enable = voltage_table.psi1_enable;
2596 
2597 	if (data->registry_data.ulv_support &&
2598 			table_info->us_ulv_voltage_offset) {
2599 		result = vega10_populate_ulv_state(hwmgr);
2600 		PP_ASSERT_WITH_CODE(!result,
2601 				"Failed to initialize ULV state!",
2602 				return result);
2603 	}
2604 
2605 	result = vega10_populate_smc_link_levels(hwmgr);
2606 	PP_ASSERT_WITH_CODE(!result,
2607 			"Failed to initialize Link Level!",
2608 			return result);
2609 
2610 	result = vega10_override_pcie_parameters(hwmgr);
2611 	PP_ASSERT_WITH_CODE(!result,
2612 			"Failed to override pcie parameters!",
2613 			return result);
2614 
2615 	result = vega10_populate_all_graphic_levels(hwmgr);
2616 	PP_ASSERT_WITH_CODE(!result,
2617 			"Failed to initialize Graphics Level!",
2618 			return result);
2619 
2620 	result = vega10_populate_all_memory_levels(hwmgr);
2621 	PP_ASSERT_WITH_CODE(!result,
2622 			"Failed to initialize Memory Level!",
2623 			return result);
2624 
2625 	vega10_populate_vddc_soc_levels(hwmgr);
2626 
2627 	result = vega10_populate_all_display_clock_levels(hwmgr);
2628 	PP_ASSERT_WITH_CODE(!result,
2629 			"Failed to initialize Display Level!",
2630 			return result);
2631 
2632 	result = vega10_populate_smc_vce_levels(hwmgr);
2633 	PP_ASSERT_WITH_CODE(!result,
2634 			"Failed to initialize VCE Level!",
2635 			return result);
2636 
2637 	result = vega10_populate_smc_uvd_levels(hwmgr);
2638 	PP_ASSERT_WITH_CODE(!result,
2639 			"Failed to initialize UVD Level!",
2640 			return result);
2641 
2642 	if (data->registry_data.clock_stretcher_support) {
2643 		result = vega10_populate_clock_stretcher_table(hwmgr);
2644 		PP_ASSERT_WITH_CODE(!result,
2645 				"Failed to populate Clock Stretcher Table!",
2646 				return result);
2647 	}
2648 
2649 	result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
2650 	if (!result) {
2651 		data->vbios_boot_state.vddc     = boot_up_values.usVddc;
2652 		data->vbios_boot_state.vddci    = boot_up_values.usVddci;
2653 		data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
2654 		data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
2655 		data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
2656 		pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2657 				SMU9_SYSPLL0_SOCCLK_ID, 0, &boot_up_values.ulSocClk);
2658 
2659 		pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
2660 				SMU9_SYSPLL0_DCEFCLK_ID, 0, &boot_up_values.ulDCEFClk);
2661 
2662 		data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
2663 		data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
2664 		if (0 != boot_up_values.usVddc) {
2665 			smum_send_msg_to_smc_with_parameter(hwmgr,
2666 						PPSMC_MSG_SetFloorSocVoltage,
2667 						(boot_up_values.usVddc * 4),
2668 						NULL);
2669 			data->vbios_boot_state.bsoc_vddc_lock = true;
2670 		} else {
2671 			data->vbios_boot_state.bsoc_vddc_lock = false;
2672 		}
2673 		smum_send_msg_to_smc_with_parameter(hwmgr,
2674 				PPSMC_MSG_SetMinDeepSleepDcefclk,
2675 			(uint32_t)(data->vbios_boot_state.dcef_clock / 100),
2676 				NULL);
2677 	}
2678 
2679 	result = vega10_populate_avfs_parameters(hwmgr);
2680 	PP_ASSERT_WITH_CODE(!result,
2681 			"Failed to initialize AVFS Parameters!",
2682 			return result);
2683 
2684 	result = vega10_populate_gpio_parameters(hwmgr);
2685 	PP_ASSERT_WITH_CODE(!result,
2686 			"Failed to initialize GPIO Parameters!",
2687 			return result);
2688 
2689 	pp_table->GfxclkAverageAlpha = (uint8_t)
2690 			(data->gfxclk_average_alpha);
2691 	pp_table->SocclkAverageAlpha = (uint8_t)
2692 			(data->socclk_average_alpha);
2693 	pp_table->UclkAverageAlpha = (uint8_t)
2694 			(data->uclk_average_alpha);
2695 	pp_table->GfxActivityAverageAlpha = (uint8_t)
2696 			(data->gfx_activity_average_alpha);
2697 
2698 	vega10_populate_and_upload_avfs_fuse_override(hwmgr);
2699 
2700 	result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
2701 
2702 	PP_ASSERT_WITH_CODE(!result,
2703 			"Failed to upload PPtable!", return result);
2704 
2705 	result = vega10_avfs_enable(hwmgr, true);
2706 	PP_ASSERT_WITH_CODE(!result, "Attempt to enable AVFS feature Failed!",
2707 					return result);
2708 	vega10_acg_enable(hwmgr);
2709 
2710 	return 0;
2711 }
2712 
2713 static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
2714 {
2715 	struct vega10_hwmgr *data = hwmgr->backend;
2716 
2717 	if (data->smu_features[GNLD_THERMAL].supported) {
2718 		if (data->smu_features[GNLD_THERMAL].enabled)
2719 			pr_info("THERMAL Feature Already enabled!");
2720 
2721 		PP_ASSERT_WITH_CODE(
2722 				!vega10_enable_smc_features(hwmgr,
2723 				true,
2724 				data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2725 				"Enable THERMAL Feature Failed!",
2726 				return -1);
2727 		data->smu_features[GNLD_THERMAL].enabled = true;
2728 	}
2729 
2730 	return 0;
2731 }
2732 
2733 static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
2734 {
2735 	struct vega10_hwmgr *data = hwmgr->backend;
2736 
2737 	if (data->smu_features[GNLD_THERMAL].supported) {
2738 		if (!data->smu_features[GNLD_THERMAL].enabled)
2739 			pr_info("THERMAL Feature Already disabled!");
2740 
2741 		PP_ASSERT_WITH_CODE(
2742 				!vega10_enable_smc_features(hwmgr,
2743 				false,
2744 				data->smu_features[GNLD_THERMAL].smu_feature_bitmap),
2745 				"disable THERMAL Feature Failed!",
2746 				return -1);
2747 		data->smu_features[GNLD_THERMAL].enabled = false;
2748 	}
2749 
2750 	return 0;
2751 }
2752 
2753 static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
2754 {
2755 	struct vega10_hwmgr *data = hwmgr->backend;
2756 
2757 	if (PP_CAP(PHM_PlatformCaps_RegulatorHot)) {
2758 		if (data->smu_features[GNLD_VR0HOT].supported) {
2759 			PP_ASSERT_WITH_CODE(
2760 					!vega10_enable_smc_features(hwmgr,
2761 					true,
2762 					data->smu_features[GNLD_VR0HOT].smu_feature_bitmap),
2763 					"Attempt to Enable VR0 Hot feature Failed!",
2764 					return -1);
2765 			data->smu_features[GNLD_VR0HOT].enabled = true;
2766 		} else {
2767 			if (data->smu_features[GNLD_VR1HOT].supported) {
2768 				PP_ASSERT_WITH_CODE(
2769 						!vega10_enable_smc_features(hwmgr,
2770 						true,
2771 						data->smu_features[GNLD_VR1HOT].smu_feature_bitmap),
2772 						"Attempt to Enable VR0 Hot feature Failed!",
2773 						return -1);
2774 				data->smu_features[GNLD_VR1HOT].enabled = true;
2775 			}
2776 		}
2777 	}
2778 	return 0;
2779 }
2780 
2781 static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
2782 {
2783 	struct vega10_hwmgr *data = hwmgr->backend;
2784 
2785 	if (data->registry_data.ulv_support) {
2786 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2787 				true, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2788 				"Enable ULV Feature Failed!",
2789 				return -1);
2790 		data->smu_features[GNLD_ULV].enabled = true;
2791 	}
2792 
2793 	return 0;
2794 }
2795 
2796 static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
2797 {
2798 	struct vega10_hwmgr *data = hwmgr->backend;
2799 
2800 	if (data->registry_data.ulv_support) {
2801 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2802 				false, data->smu_features[GNLD_ULV].smu_feature_bitmap),
2803 				"disable ULV Feature Failed!",
2804 				return -EINVAL);
2805 		data->smu_features[GNLD_ULV].enabled = false;
2806 	}
2807 
2808 	return 0;
2809 }
2810 
2811 static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2812 {
2813 	struct vega10_hwmgr *data = hwmgr->backend;
2814 
2815 	if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2816 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2817 				true, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2818 				"Attempt to Enable DS_GFXCLK Feature Failed!",
2819 				return -EINVAL);
2820 		data->smu_features[GNLD_DS_GFXCLK].enabled = true;
2821 	}
2822 
2823 	if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2824 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2825 				true, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2826 				"Attempt to Enable DS_SOCCLK Feature Failed!",
2827 				return -EINVAL);
2828 		data->smu_features[GNLD_DS_SOCCLK].enabled = true;
2829 	}
2830 
2831 	if (data->smu_features[GNLD_DS_LCLK].supported) {
2832 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2833 				true, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2834 				"Attempt to Enable DS_LCLK Feature Failed!",
2835 				return -EINVAL);
2836 		data->smu_features[GNLD_DS_LCLK].enabled = true;
2837 	}
2838 
2839 	if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2840 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2841 				true, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2842 				"Attempt to Enable DS_DCEFCLK Feature Failed!",
2843 				return -EINVAL);
2844 		data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
2845 	}
2846 
2847 	return 0;
2848 }
2849 
2850 static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
2851 {
2852 	struct vega10_hwmgr *data = hwmgr->backend;
2853 
2854 	if (data->smu_features[GNLD_DS_GFXCLK].supported) {
2855 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2856 				false, data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap),
2857 				"Attempt to disable DS_GFXCLK Feature Failed!",
2858 				return -EINVAL);
2859 		data->smu_features[GNLD_DS_GFXCLK].enabled = false;
2860 	}
2861 
2862 	if (data->smu_features[GNLD_DS_SOCCLK].supported) {
2863 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2864 				false, data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap),
2865 				"Attempt to disable DS_ Feature Failed!",
2866 				return -EINVAL);
2867 		data->smu_features[GNLD_DS_SOCCLK].enabled = false;
2868 	}
2869 
2870 	if (data->smu_features[GNLD_DS_LCLK].supported) {
2871 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2872 				false, data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap),
2873 				"Attempt to disable DS_LCLK Feature Failed!",
2874 				return -EINVAL);
2875 		data->smu_features[GNLD_DS_LCLK].enabled = false;
2876 	}
2877 
2878 	if (data->smu_features[GNLD_DS_DCEFCLK].supported) {
2879 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2880 				false, data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap),
2881 				"Attempt to disable DS_DCEFCLK Feature Failed!",
2882 				return -EINVAL);
2883 		data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
2884 	}
2885 
2886 	return 0;
2887 }
2888 
2889 static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2890 {
2891 	struct vega10_hwmgr *data = hwmgr->backend;
2892 	uint32_t i, feature_mask = 0;
2893 
2894 	if (!hwmgr->not_vf)
2895 		return 0;
2896 
2897 	if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2898 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2899 				false, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2900 		"Attempt to disable LED DPM feature failed!", return -EINVAL);
2901 		data->smu_features[GNLD_LED_DISPLAY].enabled = false;
2902 	}
2903 
2904 	for (i = 0; i < GNLD_DPM_MAX; i++) {
2905 		if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2906 			if (data->smu_features[i].supported) {
2907 				if (data->smu_features[i].enabled) {
2908 					feature_mask |= data->smu_features[i].
2909 							smu_feature_bitmap;
2910 					data->smu_features[i].enabled = false;
2911 				}
2912 			}
2913 		}
2914 	}
2915 
2916 	vega10_enable_smc_features(hwmgr, false, feature_mask);
2917 
2918 	return 0;
2919 }
2920 
2921 /**
2922  * vega10_start_dpm - Tell SMC to enabled the supported DPMs.
2923  *
2924  * @hwmgr:   the address of the powerplay hardware manager.
2925  * @bitmap:  bitmap for the features to enabled.
2926  * return:  0 on at least one DPM is successfully enabled.
2927  */
2928 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
2929 {
2930 	struct vega10_hwmgr *data = hwmgr->backend;
2931 	uint32_t i, feature_mask = 0;
2932 
2933 	for (i = 0; i < GNLD_DPM_MAX; i++) {
2934 		if (data->smu_features[i].smu_feature_bitmap & bitmap) {
2935 			if (data->smu_features[i].supported) {
2936 				if (!data->smu_features[i].enabled) {
2937 					feature_mask |= data->smu_features[i].
2938 							smu_feature_bitmap;
2939 					data->smu_features[i].enabled = true;
2940 				}
2941 			}
2942 		}
2943 	}
2944 
2945 	if (vega10_enable_smc_features(hwmgr,
2946 			true, feature_mask)) {
2947 		for (i = 0; i < GNLD_DPM_MAX; i++) {
2948 			if (data->smu_features[i].smu_feature_bitmap &
2949 					feature_mask)
2950 				data->smu_features[i].enabled = false;
2951 		}
2952 	}
2953 
2954 	if(data->smu_features[GNLD_LED_DISPLAY].supported == true){
2955 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2956 				true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap),
2957 		"Attempt to Enable LED DPM feature Failed!", return -EINVAL);
2958 		data->smu_features[GNLD_LED_DISPLAY].enabled = true;
2959 	}
2960 
2961 	if (data->vbios_boot_state.bsoc_vddc_lock) {
2962 		smum_send_msg_to_smc_with_parameter(hwmgr,
2963 						PPSMC_MSG_SetFloorSocVoltage, 0,
2964 						NULL);
2965 		data->vbios_boot_state.bsoc_vddc_lock = false;
2966 	}
2967 
2968 	if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
2969 		if (data->smu_features[GNLD_ACDC].supported) {
2970 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2971 					true, data->smu_features[GNLD_ACDC].smu_feature_bitmap),
2972 					"Attempt to Enable DS_GFXCLK Feature Failed!",
2973 					return -1);
2974 			data->smu_features[GNLD_ACDC].enabled = true;
2975 		}
2976 	}
2977 
2978 	if (data->registry_data.pcie_dpm_key_disabled) {
2979 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2980 				false, data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap),
2981 		"Attempt to Disable Link DPM feature Failed!", return -EINVAL);
2982 		data->smu_features[GNLD_DPM_LINK].enabled = false;
2983 		data->smu_features[GNLD_DPM_LINK].supported = false;
2984 	}
2985 
2986 	return 0;
2987 }
2988 
2989 
2990 static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
2991 {
2992 	struct vega10_hwmgr *data = hwmgr->backend;
2993 
2994 	if (data->smu_features[GNLD_PCC_LIMIT].supported) {
2995 		if (enable == data->smu_features[GNLD_PCC_LIMIT].enabled)
2996 			pr_info("GNLD_PCC_LIMIT has been %s \n", enable ? "enabled" : "disabled");
2997 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
2998 				enable, data->smu_features[GNLD_PCC_LIMIT].smu_feature_bitmap),
2999 				"Attempt to Enable PCC Limit feature Failed!",
3000 				return -EINVAL);
3001 		data->smu_features[GNLD_PCC_LIMIT].enabled = enable;
3002 	}
3003 
3004 	return 0;
3005 }
3006 
3007 static void vega10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
3008 {
3009 	struct phm_ppt_v2_information *table_info =
3010 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
3011 
3012 	if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
3013 	    table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
3014 		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
3015 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
3016 	} else {
3017 		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3018 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[0].clk;
3019 	}
3020 
3021 	hwmgr->pstate_sclk_peak = table_info->vdd_dep_on_sclk->entries[table_info->vdd_dep_on_sclk->count - 1].clk;
3022 	hwmgr->pstate_mclk_peak = table_info->vdd_dep_on_mclk->entries[table_info->vdd_dep_on_mclk->count - 1].clk;
3023 
3024 	/* make sure the output is in Mhz */
3025 	hwmgr->pstate_sclk /= 100;
3026 	hwmgr->pstate_mclk /= 100;
3027 	hwmgr->pstate_sclk_peak /= 100;
3028 	hwmgr->pstate_mclk_peak /= 100;
3029 }
3030 
3031 static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3032 {
3033 	struct vega10_hwmgr *data = hwmgr->backend;
3034 	int tmp_result, result = 0;
3035 
3036 	if (hwmgr->not_vf) {
3037 		vega10_enable_disable_PCC_limit_feature(hwmgr, true);
3038 
3039 		smum_send_msg_to_smc_with_parameter(hwmgr,
3040 			PPSMC_MSG_ConfigureTelemetry, data->config_telemetry,
3041 			NULL);
3042 
3043 		tmp_result = vega10_construct_voltage_tables(hwmgr);
3044 		PP_ASSERT_WITH_CODE(!tmp_result,
3045 				    "Failed to construct voltage tables!",
3046 				    result = tmp_result);
3047 	}
3048 
3049 	if (hwmgr->not_vf || hwmgr->pp_one_vf) {
3050 		tmp_result = vega10_init_smc_table(hwmgr);
3051 		PP_ASSERT_WITH_CODE(!tmp_result,
3052 				    "Failed to initialize SMC table!",
3053 				    result = tmp_result);
3054 	}
3055 
3056 	if (hwmgr->not_vf) {
3057 		if (PP_CAP(PHM_PlatformCaps_ThermalController)) {
3058 			tmp_result = vega10_enable_thermal_protection(hwmgr);
3059 			PP_ASSERT_WITH_CODE(!tmp_result,
3060 					    "Failed to enable thermal protection!",
3061 					    result = tmp_result);
3062 		}
3063 
3064 		tmp_result = vega10_enable_vrhot_feature(hwmgr);
3065 		PP_ASSERT_WITH_CODE(!tmp_result,
3066 				    "Failed to enable VR hot feature!",
3067 				    result = tmp_result);
3068 
3069 		tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
3070 		PP_ASSERT_WITH_CODE(!tmp_result,
3071 				    "Failed to enable deep sleep master switch!",
3072 				    result = tmp_result);
3073 	}
3074 
3075 	if (hwmgr->not_vf) {
3076 		tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
3077 		PP_ASSERT_WITH_CODE(!tmp_result,
3078 				    "Failed to start DPM!", result = tmp_result);
3079 	}
3080 
3081 	if (hwmgr->not_vf) {
3082 		/* enable didt, do not abort if failed didt */
3083 		tmp_result = vega10_enable_didt_config(hwmgr);
3084 		PP_ASSERT(!tmp_result,
3085 			  "Failed to enable didt config!");
3086 	}
3087 
3088 	tmp_result = vega10_enable_power_containment(hwmgr);
3089 	PP_ASSERT_WITH_CODE(!tmp_result,
3090 			    "Failed to enable power containment!",
3091 			    result = tmp_result);
3092 
3093 	if (hwmgr->not_vf) {
3094 		tmp_result = vega10_power_control_set_level(hwmgr);
3095 		PP_ASSERT_WITH_CODE(!tmp_result,
3096 				    "Failed to power control set level!",
3097 				    result = tmp_result);
3098 
3099 		tmp_result = vega10_enable_ulv(hwmgr);
3100 		PP_ASSERT_WITH_CODE(!tmp_result,
3101 				    "Failed to enable ULV!",
3102 				    result = tmp_result);
3103 	}
3104 
3105 	vega10_populate_umdpstate_clocks(hwmgr);
3106 
3107 	return result;
3108 }
3109 
3110 static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
3111 {
3112 	return sizeof(struct vega10_power_state);
3113 }
3114 
3115 static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3116 		void *state, struct pp_power_state *power_state,
3117 		void *pp_table, uint32_t classification_flag)
3118 {
3119 	ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_V2;
3120 	struct vega10_power_state *vega10_ps =
3121 			cast_phw_vega10_power_state(&(power_state->hardware));
3122 	struct vega10_performance_level *performance_level;
3123 	ATOM_Vega10_State *state_entry = (ATOM_Vega10_State *)state;
3124 	ATOM_Vega10_POWERPLAYTABLE *powerplay_table =
3125 			(ATOM_Vega10_POWERPLAYTABLE *)pp_table;
3126 	ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
3127 			(ATOM_Vega10_SOCCLK_Dependency_Table *)
3128 			(((unsigned long)powerplay_table) +
3129 			le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
3130 	ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
3131 			(ATOM_Vega10_GFXCLK_Dependency_Table *)
3132 			(((unsigned long)powerplay_table) +
3133 			le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
3134 	ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
3135 			(ATOM_Vega10_MCLK_Dependency_Table *)
3136 			(((unsigned long)powerplay_table) +
3137 			le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3138 
3139 
3140 	/* The following fields are not initialized here:
3141 	 * id orderedList allStatesList
3142 	 */
3143 	power_state->classification.ui_label =
3144 			(le16_to_cpu(state_entry->usClassification) &
3145 			ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3146 			ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3147 	power_state->classification.flags = classification_flag;
3148 	/* NOTE: There is a classification2 flag in BIOS
3149 	 * that is not being used right now
3150 	 */
3151 	power_state->classification.temporary_state = false;
3152 	power_state->classification.to_be_deleted = false;
3153 
3154 	power_state->validation.disallowOnDC =
3155 			((le32_to_cpu(state_entry->ulCapsAndSettings) &
3156 					ATOM_Vega10_DISALLOW_ON_DC) != 0);
3157 
3158 	power_state->display.disableFrameModulation = false;
3159 	power_state->display.limitRefreshrate = false;
3160 	power_state->display.enableVariBright =
3161 			((le32_to_cpu(state_entry->ulCapsAndSettings) &
3162 					ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
3163 
3164 	power_state->validation.supportedPowerLevels = 0;
3165 	power_state->uvd_clocks.VCLK = 0;
3166 	power_state->uvd_clocks.DCLK = 0;
3167 	power_state->temperatures.min = 0;
3168 	power_state->temperatures.max = 0;
3169 
3170 	performance_level = &(vega10_ps->performance_levels
3171 			[vega10_ps->performance_level_count++]);
3172 
3173 	PP_ASSERT_WITH_CODE(
3174 			(vega10_ps->performance_level_count <
3175 					NUM_GFXCLK_DPM_LEVELS),
3176 			"Performance levels exceeds SMC limit!",
3177 			return -1);
3178 
3179 	PP_ASSERT_WITH_CODE(
3180 			(vega10_ps->performance_level_count <
3181 					hwmgr->platform_descriptor.
3182 					hardwareActivityPerformanceLevels),
3183 			"Performance levels exceeds Driver limit!",
3184 			return -1);
3185 
3186 	/* Performance levels are arranged from low to high. */
3187 	performance_level->soc_clock = socclk_dep_table->entries
3188 			[state_entry->ucSocClockIndexLow].ulClk;
3189 	performance_level->gfx_clock = gfxclk_dep_table->entries
3190 			[state_entry->ucGfxClockIndexLow].ulClk;
3191 	performance_level->mem_clock = mclk_dep_table->entries
3192 			[state_entry->ucMemClockIndexLow].ulMemClk;
3193 
3194 	performance_level = &(vega10_ps->performance_levels
3195 				[vega10_ps->performance_level_count++]);
3196 	performance_level->soc_clock = socclk_dep_table->entries
3197 				[state_entry->ucSocClockIndexHigh].ulClk;
3198 	if (gfxclk_dep_table->ucRevId == 0) {
3199 		/* under vega10 pp one vf mode, the gfx clk dpm need be lower
3200 		 * to level-4 due to the limited 110w-power
3201 		 */
3202 		if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3203 			performance_level->gfx_clock =
3204 				gfxclk_dep_table->entries[4].ulClk;
3205 		else
3206 			performance_level->gfx_clock = gfxclk_dep_table->entries
3207 				[state_entry->ucGfxClockIndexHigh].ulClk;
3208 	} else if (gfxclk_dep_table->ucRevId == 1) {
3209 		patom_record_V2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
3210 		if (hwmgr->pp_one_vf && (state_entry->ucGfxClockIndexHigh > 0))
3211 			performance_level->gfx_clock = patom_record_V2[4].ulClk;
3212 		else
3213 			performance_level->gfx_clock =
3214 				patom_record_V2[state_entry->ucGfxClockIndexHigh].ulClk;
3215 	}
3216 
3217 	performance_level->mem_clock = mclk_dep_table->entries
3218 			[state_entry->ucMemClockIndexHigh].ulMemClk;
3219 	return 0;
3220 }
3221 
3222 static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3223 		unsigned long entry_index, struct pp_power_state *state)
3224 {
3225 	int result;
3226 	struct vega10_power_state *vega10_ps;
3227 
3228 	state->hardware.magic = PhwVega10_Magic;
3229 
3230 	vega10_ps = cast_phw_vega10_power_state(&state->hardware);
3231 
3232 	result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
3233 			vega10_get_pp_table_entry_callback_func);
3234 	if (result)
3235 		return result;
3236 
3237 	/*
3238 	 * This is the earliest time we have all the dependency table
3239 	 * and the VBIOS boot state
3240 	 */
3241 	/* set DC compatible flag if this state supports DC */
3242 	if (!state->validation.disallowOnDC)
3243 		vega10_ps->dc_compatible = true;
3244 
3245 	vega10_ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3246 	vega10_ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3247 
3248 	return 0;
3249 }
3250 
3251 static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
3252 	     struct pp_hw_power_state *hw_ps)
3253 {
3254 	return 0;
3255 }
3256 
3257 static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3258 				struct pp_power_state  *request_ps,
3259 			const struct pp_power_state *current_ps)
3260 {
3261 	struct amdgpu_device *adev = hwmgr->adev;
3262 	struct vega10_power_state *vega10_ps;
3263 	uint32_t sclk;
3264 	uint32_t mclk;
3265 	struct PP_Clocks minimum_clocks = {0};
3266 	bool disable_mclk_switching;
3267 	bool disable_mclk_switching_for_frame_lock;
3268 	bool disable_mclk_switching_for_vr;
3269 	bool force_mclk_high;
3270 	const struct phm_clock_and_voltage_limits *max_limits;
3271 	uint32_t i;
3272 	struct vega10_hwmgr *data = hwmgr->backend;
3273 	struct phm_ppt_v2_information *table_info =
3274 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
3275 	int32_t count;
3276 	uint32_t stable_pstate_sclk_dpm_percentage;
3277 	uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3278 	uint32_t latency;
3279 
3280 	vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);
3281 	if (!vega10_ps)
3282 		return -EINVAL;
3283 
3284 	data->battery_state = (PP_StateUILabel_Battery ==
3285 			request_ps->classification.ui_label);
3286 
3287 	if (vega10_ps->performance_level_count != 2)
3288 		pr_info("VI should always have 2 performance levels");
3289 
3290 	max_limits = adev->pm.ac_power ?
3291 			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3292 			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
3293 
3294 	/* Cap clock DPM tables at DC MAX if it is in DC. */
3295 	if (!adev->pm.ac_power) {
3296 		for (i = 0; i < vega10_ps->performance_level_count; i++) {
3297 			if (vega10_ps->performance_levels[i].mem_clock >
3298 				max_limits->mclk)
3299 				vega10_ps->performance_levels[i].mem_clock =
3300 						max_limits->mclk;
3301 			if (vega10_ps->performance_levels[i].gfx_clock >
3302 				max_limits->sclk)
3303 				vega10_ps->performance_levels[i].gfx_clock =
3304 						max_limits->sclk;
3305 		}
3306 	}
3307 
3308 	/* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3309 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
3310 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
3311 
3312 	if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3313 		stable_pstate_sclk_dpm_percentage =
3314 			data->registry_data.stable_pstate_sclk_dpm_percentage;
3315 		PP_ASSERT_WITH_CODE(
3316 			data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 &&
3317 			data->registry_data.stable_pstate_sclk_dpm_percentage <= 100,
3318 			"percent sclk value must range from 1% to 100%, setting default value",
3319 			stable_pstate_sclk_dpm_percentage = 75);
3320 
3321 		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3322 		stable_pstate_sclk = (max_limits->sclk *
3323 				stable_pstate_sclk_dpm_percentage) / 100;
3324 
3325 		for (count = table_info->vdd_dep_on_sclk->count - 1;
3326 				count >= 0; count--) {
3327 			if (stable_pstate_sclk >=
3328 					table_info->vdd_dep_on_sclk->entries[count].clk) {
3329 				stable_pstate_sclk =
3330 						table_info->vdd_dep_on_sclk->entries[count].clk;
3331 				break;
3332 			}
3333 		}
3334 
3335 		if (count < 0)
3336 			stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3337 
3338 		stable_pstate_mclk = max_limits->mclk;
3339 
3340 		minimum_clocks.engineClock = stable_pstate_sclk;
3341 		minimum_clocks.memoryClock = stable_pstate_mclk;
3342 	}
3343 
3344 	disable_mclk_switching_for_frame_lock =
3345 		PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
3346 	disable_mclk_switching_for_vr =
3347 		PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
3348 	force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
3349 
3350 	if (hwmgr->display_config->num_display == 0)
3351 		disable_mclk_switching = false;
3352 	else
3353 		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
3354 					  !hwmgr->display_config->multi_monitor_in_sync) ||
3355 			disable_mclk_switching_for_frame_lock ||
3356 			disable_mclk_switching_for_vr ||
3357 			force_mclk_high;
3358 
3359 	sclk = vega10_ps->performance_levels[0].gfx_clock;
3360 	mclk = vega10_ps->performance_levels[0].mem_clock;
3361 
3362 	if (sclk < minimum_clocks.engineClock)
3363 		sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
3364 				max_limits->sclk : minimum_clocks.engineClock;
3365 
3366 	if (mclk < minimum_clocks.memoryClock)
3367 		mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
3368 				max_limits->mclk : minimum_clocks.memoryClock;
3369 
3370 	vega10_ps->performance_levels[0].gfx_clock = sclk;
3371 	vega10_ps->performance_levels[0].mem_clock = mclk;
3372 
3373 	if (vega10_ps->performance_levels[1].gfx_clock <
3374 			vega10_ps->performance_levels[0].gfx_clock)
3375 		vega10_ps->performance_levels[0].gfx_clock =
3376 				vega10_ps->performance_levels[1].gfx_clock;
3377 
3378 	if (disable_mclk_switching) {
3379 		/* Set Mclk the max of level 0 and level 1 */
3380 		if (mclk < vega10_ps->performance_levels[1].mem_clock)
3381 			mclk = vega10_ps->performance_levels[1].mem_clock;
3382 
3383 		/* Find the lowest MCLK frequency that is within
3384 		 * the tolerable latency defined in DAL
3385 		 */
3386 		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
3387 		for (i = 0; i < data->mclk_latency_table.count; i++) {
3388 			if ((data->mclk_latency_table.entries[i].latency <= latency) &&
3389 				(data->mclk_latency_table.entries[i].frequency >=
3390 						vega10_ps->performance_levels[0].mem_clock) &&
3391 				(data->mclk_latency_table.entries[i].frequency <=
3392 						vega10_ps->performance_levels[1].mem_clock))
3393 				mclk = data->mclk_latency_table.entries[i].frequency;
3394 		}
3395 		vega10_ps->performance_levels[0].mem_clock = mclk;
3396 	} else {
3397 		if (vega10_ps->performance_levels[1].mem_clock <
3398 				vega10_ps->performance_levels[0].mem_clock)
3399 			vega10_ps->performance_levels[0].mem_clock =
3400 					vega10_ps->performance_levels[1].mem_clock;
3401 	}
3402 
3403 	if (PP_CAP(PHM_PlatformCaps_StablePState)) {
3404 		for (i = 0; i < vega10_ps->performance_level_count; i++) {
3405 			vega10_ps->performance_levels[i].gfx_clock = stable_pstate_sclk;
3406 			vega10_ps->performance_levels[i].mem_clock = stable_pstate_mclk;
3407 		}
3408 	}
3409 
3410 	return 0;
3411 }
3412 
3413 static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
3414 {
3415 	struct vega10_hwmgr *data = hwmgr->backend;
3416 	const struct phm_set_power_state_input *states =
3417 			(const struct phm_set_power_state_input *)input;
3418 	const struct vega10_power_state *vega10_ps =
3419 			cast_const_phw_vega10_power_state(states->pnew_state);
3420 	struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
3421 	struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
3422 	uint32_t sclk, mclk;
3423 	uint32_t i;
3424 
3425 	if (vega10_ps == NULL)
3426 		return -EINVAL;
3427 	sclk = vega10_ps->performance_levels
3428 			[vega10_ps->performance_level_count - 1].gfx_clock;
3429 	mclk = vega10_ps->performance_levels
3430 			[vega10_ps->performance_level_count - 1].mem_clock;
3431 
3432 	for (i = 0; i < sclk_table->count; i++) {
3433 		if (sclk == sclk_table->dpm_levels[i].value)
3434 			break;
3435 	}
3436 
3437 	if (i >= sclk_table->count) {
3438 		if (sclk > sclk_table->dpm_levels[i-1].value) {
3439 			data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3440 			sclk_table->dpm_levels[i-1].value = sclk;
3441 		}
3442 	}
3443 
3444 	for (i = 0; i < mclk_table->count; i++) {
3445 		if (mclk == mclk_table->dpm_levels[i].value)
3446 			break;
3447 	}
3448 
3449 	if (i >= mclk_table->count) {
3450 		if (mclk > mclk_table->dpm_levels[i-1].value) {
3451 			data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3452 			mclk_table->dpm_levels[i-1].value = mclk;
3453 		}
3454 	}
3455 
3456 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
3457 		data->need_update_dpm_table |= DPMTABLE_UPDATE_MCLK;
3458 
3459 	return 0;
3460 }
3461 
3462 static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
3463 		struct pp_hwmgr *hwmgr, const void *input)
3464 {
3465 	int result = 0;
3466 	struct vega10_hwmgr *data = hwmgr->backend;
3467 	struct vega10_dpm_table *dpm_table = &data->dpm_table;
3468 	struct vega10_odn_dpm_table *odn_table = &data->odn_dpm_table;
3469 	struct vega10_odn_clock_voltage_dependency_table *odn_clk_table = &odn_table->vdd_dep_on_sclk;
3470 	int count;
3471 
3472 	if (!data->need_update_dpm_table)
3473 		return 0;
3474 
3475 	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
3476 		for (count = 0; count < dpm_table->gfx_table.count; count++)
3477 			dpm_table->gfx_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3478 	}
3479 
3480 	odn_clk_table = &odn_table->vdd_dep_on_mclk;
3481 	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
3482 		for (count = 0; count < dpm_table->mem_table.count; count++)
3483 			dpm_table->mem_table.dpm_levels[count].value = odn_clk_table->entries[count].clk;
3484 	}
3485 
3486 	if (data->need_update_dpm_table &
3487 			(DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) {
3488 		result = vega10_populate_all_graphic_levels(hwmgr);
3489 		PP_ASSERT_WITH_CODE((0 == result),
3490 				"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
3491 				return result);
3492 	}
3493 
3494 	if (data->need_update_dpm_table &
3495 			(DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3496 		result = vega10_populate_all_memory_levels(hwmgr);
3497 		PP_ASSERT_WITH_CODE((0 == result),
3498 				"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
3499 				return result);
3500 	}
3501 
3502 	vega10_populate_vddc_soc_levels(hwmgr);
3503 
3504 	return result;
3505 }
3506 
3507 static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
3508 		struct vega10_single_dpm_table *dpm_table,
3509 		uint32_t low_limit, uint32_t high_limit)
3510 {
3511 	uint32_t i;
3512 
3513 	for (i = 0; i < dpm_table->count; i++) {
3514 		if ((dpm_table->dpm_levels[i].value < low_limit) ||
3515 		    (dpm_table->dpm_levels[i].value > high_limit))
3516 			dpm_table->dpm_levels[i].enabled = false;
3517 		else
3518 			dpm_table->dpm_levels[i].enabled = true;
3519 	}
3520 	return 0;
3521 }
3522 
3523 static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
3524 		struct vega10_single_dpm_table *dpm_table,
3525 		uint32_t low_limit, uint32_t high_limit,
3526 		uint32_t disable_dpm_mask)
3527 {
3528 	uint32_t i;
3529 
3530 	for (i = 0; i < dpm_table->count; i++) {
3531 		if ((dpm_table->dpm_levels[i].value < low_limit) ||
3532 		    (dpm_table->dpm_levels[i].value > high_limit))
3533 			dpm_table->dpm_levels[i].enabled = false;
3534 		else if (!((1 << i) & disable_dpm_mask))
3535 			dpm_table->dpm_levels[i].enabled = false;
3536 		else
3537 			dpm_table->dpm_levels[i].enabled = true;
3538 	}
3539 	return 0;
3540 }
3541 
3542 static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
3543 		const struct vega10_power_state *vega10_ps)
3544 {
3545 	struct vega10_hwmgr *data = hwmgr->backend;
3546 	uint32_t high_limit_count;
3547 
3548 	PP_ASSERT_WITH_CODE((vega10_ps->performance_level_count >= 1),
3549 			"power state did not have any performance level",
3550 			return -1);
3551 
3552 	high_limit_count = (vega10_ps->performance_level_count == 1) ? 0 : 1;
3553 
3554 	vega10_trim_single_dpm_states(hwmgr,
3555 			&(data->dpm_table.soc_table),
3556 			vega10_ps->performance_levels[0].soc_clock,
3557 			vega10_ps->performance_levels[high_limit_count].soc_clock);
3558 
3559 	vega10_trim_single_dpm_states_with_mask(hwmgr,
3560 			&(data->dpm_table.gfx_table),
3561 			vega10_ps->performance_levels[0].gfx_clock,
3562 			vega10_ps->performance_levels[high_limit_count].gfx_clock,
3563 			data->disable_dpm_mask);
3564 
3565 	vega10_trim_single_dpm_states(hwmgr,
3566 			&(data->dpm_table.mem_table),
3567 			vega10_ps->performance_levels[0].mem_clock,
3568 			vega10_ps->performance_levels[high_limit_count].mem_clock);
3569 
3570 	return 0;
3571 }
3572 
3573 static uint32_t vega10_find_lowest_dpm_level(
3574 		struct vega10_single_dpm_table *table)
3575 {
3576 	uint32_t i;
3577 
3578 	for (i = 0; i < table->count; i++) {
3579 		if (table->dpm_levels[i].enabled)
3580 			break;
3581 	}
3582 
3583 	return i;
3584 }
3585 
3586 static uint32_t vega10_find_highest_dpm_level(
3587 		struct vega10_single_dpm_table *table)
3588 {
3589 	uint32_t i = 0;
3590 
3591 	if (table->count <= MAX_REGULAR_DPM_NUMBER) {
3592 		for (i = table->count; i > 0; i--) {
3593 			if (table->dpm_levels[i - 1].enabled)
3594 				return i - 1;
3595 		}
3596 	} else {
3597 		pr_info("DPM Table Has Too Many Entries!");
3598 		return MAX_REGULAR_DPM_NUMBER - 1;
3599 	}
3600 
3601 	return i;
3602 }
3603 
3604 static void vega10_apply_dal_minimum_voltage_request(
3605 		struct pp_hwmgr *hwmgr)
3606 {
3607 	return;
3608 }
3609 
3610 static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
3611 {
3612 	struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table_on_mclk;
3613 	struct phm_ppt_v2_information *table_info =
3614 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
3615 
3616 	vdd_dep_table_on_mclk  = table_info->vdd_dep_on_mclk;
3617 
3618 	return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1;
3619 }
3620 
3621 static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
3622 {
3623 	struct vega10_hwmgr *data = hwmgr->backend;
3624 	uint32_t socclk_idx;
3625 
3626 	vega10_apply_dal_minimum_voltage_request(hwmgr);
3627 
3628 	if (!data->registry_data.sclk_dpm_key_disabled) {
3629 		if (data->smc_state_table.gfx_boot_level !=
3630 				data->dpm_table.gfx_table.dpm_state.soft_min_level) {
3631 			smum_send_msg_to_smc_with_parameter(hwmgr,
3632 				PPSMC_MSG_SetSoftMinGfxclkByIndex,
3633 				data->smc_state_table.gfx_boot_level,
3634 				NULL);
3635 
3636 			data->dpm_table.gfx_table.dpm_state.soft_min_level =
3637 					data->smc_state_table.gfx_boot_level;
3638 		}
3639 	}
3640 
3641 	if (!data->registry_data.mclk_dpm_key_disabled) {
3642 		if (data->smc_state_table.mem_boot_level !=
3643 				data->dpm_table.mem_table.dpm_state.soft_min_level) {
3644 			if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
3645 			    && hwmgr->not_vf) {
3646 				socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
3647 				smum_send_msg_to_smc_with_parameter(hwmgr,
3648 						PPSMC_MSG_SetSoftMinSocclkByIndex,
3649 						socclk_idx,
3650 						NULL);
3651 			} else {
3652 				smum_send_msg_to_smc_with_parameter(hwmgr,
3653 						PPSMC_MSG_SetSoftMinUclkByIndex,
3654 						data->smc_state_table.mem_boot_level,
3655 						NULL);
3656 			}
3657 			data->dpm_table.mem_table.dpm_state.soft_min_level =
3658 					data->smc_state_table.mem_boot_level;
3659 		}
3660 	}
3661 
3662 	if (!hwmgr->not_vf)
3663 		return 0;
3664 
3665 	if (!data->registry_data.socclk_dpm_key_disabled) {
3666 		if (data->smc_state_table.soc_boot_level !=
3667 				data->dpm_table.soc_table.dpm_state.soft_min_level) {
3668 			smum_send_msg_to_smc_with_parameter(hwmgr,
3669 				PPSMC_MSG_SetSoftMinSocclkByIndex,
3670 				data->smc_state_table.soc_boot_level,
3671 				NULL);
3672 			data->dpm_table.soc_table.dpm_state.soft_min_level =
3673 					data->smc_state_table.soc_boot_level;
3674 		}
3675 	}
3676 
3677 	return 0;
3678 }
3679 
3680 static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
3681 {
3682 	struct vega10_hwmgr *data = hwmgr->backend;
3683 
3684 	vega10_apply_dal_minimum_voltage_request(hwmgr);
3685 
3686 	if (!data->registry_data.sclk_dpm_key_disabled) {
3687 		if (data->smc_state_table.gfx_max_level !=
3688 			data->dpm_table.gfx_table.dpm_state.soft_max_level) {
3689 			smum_send_msg_to_smc_with_parameter(hwmgr,
3690 				PPSMC_MSG_SetSoftMaxGfxclkByIndex,
3691 				data->smc_state_table.gfx_max_level,
3692 				NULL);
3693 			data->dpm_table.gfx_table.dpm_state.soft_max_level =
3694 					data->smc_state_table.gfx_max_level;
3695 		}
3696 	}
3697 
3698 	if (!data->registry_data.mclk_dpm_key_disabled) {
3699 		if (data->smc_state_table.mem_max_level !=
3700 			data->dpm_table.mem_table.dpm_state.soft_max_level) {
3701 			smum_send_msg_to_smc_with_parameter(hwmgr,
3702 					PPSMC_MSG_SetSoftMaxUclkByIndex,
3703 					data->smc_state_table.mem_max_level,
3704 					NULL);
3705 			data->dpm_table.mem_table.dpm_state.soft_max_level =
3706 					data->smc_state_table.mem_max_level;
3707 		}
3708 	}
3709 
3710 	if (!hwmgr->not_vf)
3711 		return 0;
3712 
3713 	if (!data->registry_data.socclk_dpm_key_disabled) {
3714 		if (data->smc_state_table.soc_max_level !=
3715 			data->dpm_table.soc_table.dpm_state.soft_max_level) {
3716 			smum_send_msg_to_smc_with_parameter(hwmgr,
3717 				PPSMC_MSG_SetSoftMaxSocclkByIndex,
3718 				data->smc_state_table.soc_max_level,
3719 				NULL);
3720 			data->dpm_table.soc_table.dpm_state.soft_max_level =
3721 					data->smc_state_table.soc_max_level;
3722 		}
3723 	}
3724 
3725 	return 0;
3726 }
3727 
3728 static int vega10_generate_dpm_level_enable_mask(
3729 		struct pp_hwmgr *hwmgr, const void *input)
3730 {
3731 	struct vega10_hwmgr *data = hwmgr->backend;
3732 	const struct phm_set_power_state_input *states =
3733 			(const struct phm_set_power_state_input *)input;
3734 	const struct vega10_power_state *vega10_ps =
3735 			cast_const_phw_vega10_power_state(states->pnew_state);
3736 	int i;
3737 
3738 	if (vega10_ps == NULL)
3739 		return -EINVAL;
3740 
3741 	PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
3742 			"Attempt to Trim DPM States Failed!",
3743 			return -1);
3744 
3745 	data->smc_state_table.gfx_boot_level =
3746 			vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
3747 	data->smc_state_table.gfx_max_level =
3748 			vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
3749 	data->smc_state_table.mem_boot_level =
3750 			vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
3751 	data->smc_state_table.mem_max_level =
3752 			vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
3753 	data->smc_state_table.soc_boot_level =
3754 			vega10_find_lowest_dpm_level(&(data->dpm_table.soc_table));
3755 	data->smc_state_table.soc_max_level =
3756 			vega10_find_highest_dpm_level(&(data->dpm_table.soc_table));
3757 
3758 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
3759 			"Attempt to upload DPM Bootup Levels Failed!",
3760 			return -1);
3761 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
3762 			"Attempt to upload DPM Max Levels Failed!",
3763 			return -1);
3764 	for(i = data->smc_state_table.gfx_boot_level; i < data->smc_state_table.gfx_max_level; i++)
3765 		data->dpm_table.gfx_table.dpm_levels[i].enabled = true;
3766 
3767 
3768 	for(i = data->smc_state_table.mem_boot_level; i < data->smc_state_table.mem_max_level; i++)
3769 		data->dpm_table.mem_table.dpm_levels[i].enabled = true;
3770 
3771 	for (i = data->smc_state_table.soc_boot_level; i < data->smc_state_table.soc_max_level; i++)
3772 		data->dpm_table.soc_table.dpm_levels[i].enabled = true;
3773 
3774 	return 0;
3775 }
3776 
3777 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
3778 {
3779 	struct vega10_hwmgr *data = hwmgr->backend;
3780 
3781 	if (data->smu_features[GNLD_DPM_VCE].supported) {
3782 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
3783 				enable,
3784 				data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
3785 				"Attempt to Enable/Disable DPM VCE Failed!",
3786 				return -1);
3787 		data->smu_features[GNLD_DPM_VCE].enabled = enable;
3788 	}
3789 
3790 	return 0;
3791 }
3792 
3793 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
3794 {
3795 	struct vega10_hwmgr *data = hwmgr->backend;
3796 	uint32_t low_sclk_interrupt_threshold = 0;
3797 
3798 	if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) &&
3799 		(data->low_sclk_interrupt_threshold != 0)) {
3800 		low_sclk_interrupt_threshold =
3801 				data->low_sclk_interrupt_threshold;
3802 
3803 		data->smc_state_table.pp_table.LowGfxclkInterruptThreshold =
3804 				cpu_to_le32(low_sclk_interrupt_threshold);
3805 
3806 		/* This message will also enable SmcToHost Interrupt */
3807 		smum_send_msg_to_smc_with_parameter(hwmgr,
3808 				PPSMC_MSG_SetLowGfxclkInterruptThreshold,
3809 				(uint32_t)low_sclk_interrupt_threshold,
3810 				NULL);
3811 	}
3812 
3813 	return 0;
3814 }
3815 
3816 static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
3817 		const void *input)
3818 {
3819 	int tmp_result, result = 0;
3820 	struct vega10_hwmgr *data = hwmgr->backend;
3821 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
3822 
3823 	tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
3824 	PP_ASSERT_WITH_CODE(!tmp_result,
3825 			"Failed to find DPM states clocks in DPM table!",
3826 			result = tmp_result);
3827 
3828 	tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
3829 	PP_ASSERT_WITH_CODE(!tmp_result,
3830 			"Failed to populate and upload SCLK MCLK DPM levels!",
3831 			result = tmp_result);
3832 
3833 	tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
3834 	PP_ASSERT_WITH_CODE(!tmp_result,
3835 			"Failed to generate DPM level enabled mask!",
3836 			result = tmp_result);
3837 
3838 	tmp_result = vega10_update_sclk_threshold(hwmgr);
3839 	PP_ASSERT_WITH_CODE(!tmp_result,
3840 			"Failed to update SCLK threshold!",
3841 			result = tmp_result);
3842 
3843 	result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
3844 	PP_ASSERT_WITH_CODE(!result,
3845 			"Failed to upload PPtable!", return result);
3846 
3847 	/*
3848 	 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag.
3849 	 * That effectively disables AVFS feature.
3850 	 */
3851 	if(hwmgr->hardcode_pp_table != NULL)
3852 		data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
3853 
3854 	vega10_update_avfs(hwmgr);
3855 
3856 	/*
3857 	 * Clear all OD flags except DPMTABLE_OD_UPDATE_VDDC.
3858 	 * That will help to keep AVFS disabled.
3859 	 */
3860 	data->need_update_dpm_table &= DPMTABLE_OD_UPDATE_VDDC;
3861 
3862 	return 0;
3863 }
3864 
3865 static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
3866 {
3867 	struct pp_power_state *ps;
3868 	struct vega10_power_state *vega10_ps;
3869 
3870 	if (hwmgr == NULL)
3871 		return -EINVAL;
3872 
3873 	ps = hwmgr->request_ps;
3874 
3875 	if (ps == NULL)
3876 		return -EINVAL;
3877 
3878 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3879 
3880 	if (low)
3881 		return vega10_ps->performance_levels[0].gfx_clock;
3882 	else
3883 		return vega10_ps->performance_levels
3884 				[vega10_ps->performance_level_count - 1].gfx_clock;
3885 }
3886 
3887 static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
3888 {
3889 	struct pp_power_state *ps;
3890 	struct vega10_power_state *vega10_ps;
3891 
3892 	if (hwmgr == NULL)
3893 		return -EINVAL;
3894 
3895 	ps = hwmgr->request_ps;
3896 
3897 	if (ps == NULL)
3898 		return -EINVAL;
3899 
3900 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
3901 
3902 	if (low)
3903 		return vega10_ps->performance_levels[0].mem_clock;
3904 	else
3905 		return vega10_ps->performance_levels
3906 				[vega10_ps->performance_level_count-1].mem_clock;
3907 }
3908 
3909 static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
3910 		uint32_t *query)
3911 {
3912 	uint32_t value;
3913 
3914 	if (!query)
3915 		return -EINVAL;
3916 
3917 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr, &value);
3918 
3919 	/* SMC returning actual watts, keep consistent with legacy asics, low 8 bit as 8 fractional bits */
3920 	*query = value << 8;
3921 
3922 	return 0;
3923 }
3924 
3925 static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
3926 			      void *value, int *size)
3927 {
3928 	struct amdgpu_device *adev = hwmgr->adev;
3929 	uint32_t sclk_mhz, mclk_idx, activity_percent = 0;
3930 	struct vega10_hwmgr *data = hwmgr->backend;
3931 	struct vega10_dpm_table *dpm_table = &data->dpm_table;
3932 	int ret = 0;
3933 	uint32_t val_vid;
3934 
3935 	switch (idx) {
3936 	case AMDGPU_PP_SENSOR_GFX_SCLK:
3937 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency, &sclk_mhz);
3938 		*((uint32_t *)value) = sclk_mhz * 100;
3939 		break;
3940 	case AMDGPU_PP_SENSOR_GFX_MCLK:
3941 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &mclk_idx);
3942 		if (mclk_idx < dpm_table->mem_table.count) {
3943 			*((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
3944 			*size = 4;
3945 		} else {
3946 			ret = -EINVAL;
3947 		}
3948 		break;
3949 	case AMDGPU_PP_SENSOR_GPU_LOAD:
3950 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0,
3951 						&activity_percent);
3952 		*((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
3953 		*size = 4;
3954 		break;
3955 	case AMDGPU_PP_SENSOR_GPU_TEMP:
3956 		*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
3957 		*size = 4;
3958 		break;
3959 	case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
3960 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot, (uint32_t *)value);
3961 		*((uint32_t *)value) = *((uint32_t *)value) *
3962 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3963 		*size = 4;
3964 		break;
3965 	case AMDGPU_PP_SENSOR_MEM_TEMP:
3966 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM, (uint32_t *)value);
3967 		*((uint32_t *)value) = *((uint32_t *)value) *
3968 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
3969 		*size = 4;
3970 		break;
3971 	case AMDGPU_PP_SENSOR_UVD_POWER:
3972 		*((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
3973 		*size = 4;
3974 		break;
3975 	case AMDGPU_PP_SENSOR_VCE_POWER:
3976 		*((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
3977 		*size = 4;
3978 		break;
3979 	case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
3980 		ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
3981 		break;
3982 	case AMDGPU_PP_SENSOR_VDDGFX:
3983 		val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_PLANE0_CURRENTVID) &
3984 			SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK) >>
3985 			SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT;
3986 		*((uint32_t *)value) = (uint32_t)convert_to_vddc((uint8_t)val_vid);
3987 		return 0;
3988 	case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
3989 		ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
3990 		if (!ret)
3991 			*size = 8;
3992 		break;
3993 	default:
3994 		ret = -EOPNOTSUPP;
3995 		break;
3996 	}
3997 
3998 	return ret;
3999 }
4000 
4001 static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
4002 		bool has_disp)
4003 {
4004 	smum_send_msg_to_smc_with_parameter(hwmgr,
4005 			PPSMC_MSG_SetUclkFastSwitch,
4006 			has_disp ? 1 : 0,
4007 			NULL);
4008 }
4009 
4010 static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
4011 		struct pp_display_clock_request *clock_req)
4012 {
4013 	int result = 0;
4014 	enum amd_pp_clock_type clk_type = clock_req->clock_type;
4015 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
4016 	DSPCLK_e clk_select = 0;
4017 	uint32_t clk_request = 0;
4018 
4019 	switch (clk_type) {
4020 	case amd_pp_dcef_clock:
4021 		clk_select = DSPCLK_DCEFCLK;
4022 		break;
4023 	case amd_pp_disp_clock:
4024 		clk_select = DSPCLK_DISPCLK;
4025 		break;
4026 	case amd_pp_pixel_clock:
4027 		clk_select = DSPCLK_PIXCLK;
4028 		break;
4029 	case amd_pp_phy_clock:
4030 		clk_select = DSPCLK_PHYCLK;
4031 		break;
4032 	default:
4033 		pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
4034 		result = -1;
4035 		break;
4036 	}
4037 
4038 	if (!result) {
4039 		clk_request = (clk_freq << 16) | clk_select;
4040 		smum_send_msg_to_smc_with_parameter(hwmgr,
4041 				PPSMC_MSG_RequestDisplayClockByFreq,
4042 				clk_request,
4043 				NULL);
4044 	}
4045 
4046 	return result;
4047 }
4048 
4049 static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
4050 			struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table,
4051 						uint32_t frequency)
4052 {
4053 	uint8_t count;
4054 	uint8_t i;
4055 
4056 	if (mclk_table == NULL || mclk_table->count == 0)
4057 		return 0;
4058 
4059 	count = (uint8_t)(mclk_table->count);
4060 
4061 	for(i = 0; i < count; i++) {
4062 		if(mclk_table->entries[i].clk >= frequency)
4063 			return i;
4064 	}
4065 
4066 	return i-1;
4067 }
4068 
4069 static int vega10_notify_smc_display_config_after_ps_adjustment(
4070 		struct pp_hwmgr *hwmgr)
4071 {
4072 	struct vega10_hwmgr *data = hwmgr->backend;
4073 	struct vega10_single_dpm_table *dpm_table =
4074 			&data->dpm_table.dcef_table;
4075 	struct phm_ppt_v2_information *table_info =
4076 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4077 	struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = table_info->vdd_dep_on_mclk;
4078 	uint32_t idx;
4079 	struct PP_Clocks min_clocks = {0};
4080 	uint32_t i;
4081 	struct pp_display_clock_request clock_req;
4082 
4083 	if ((hwmgr->display_config->num_display > 1) &&
4084 	     !hwmgr->display_config->multi_monitor_in_sync &&
4085 	     !hwmgr->display_config->nb_pstate_switch_disable)
4086 		vega10_notify_smc_display_change(hwmgr, false);
4087 	else
4088 		vega10_notify_smc_display_change(hwmgr, true);
4089 
4090 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
4091 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
4092 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
4093 
4094 	for (i = 0; i < dpm_table->count; i++) {
4095 		if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock)
4096 			break;
4097 	}
4098 
4099 	if (i < dpm_table->count) {
4100 		clock_req.clock_type = amd_pp_dcef_clock;
4101 		clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 10;
4102 		if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
4103 			smum_send_msg_to_smc_with_parameter(
4104 					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
4105 					min_clocks.dcefClockInSR / 100,
4106 					NULL);
4107 		} else {
4108 			pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
4109 		}
4110 	} else {
4111 		pr_debug("Cannot find requested DCEFCLK!");
4112 	}
4113 
4114 	if (min_clocks.memoryClock != 0) {
4115 		idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
4116 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx,
4117 						NULL);
4118 		data->dpm_table.mem_table.dpm_state.soft_min_level= idx;
4119 	}
4120 
4121 	return 0;
4122 }
4123 
4124 static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
4125 {
4126 	struct vega10_hwmgr *data = hwmgr->backend;
4127 
4128 	data->smc_state_table.gfx_boot_level =
4129 	data->smc_state_table.gfx_max_level =
4130 			vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4131 	data->smc_state_table.mem_boot_level =
4132 	data->smc_state_table.mem_max_level =
4133 			vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4134 
4135 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4136 			"Failed to upload boot level to highest!",
4137 			return -1);
4138 
4139 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4140 			"Failed to upload dpm max level to highest!",
4141 			return -1);
4142 
4143 	return 0;
4144 }
4145 
4146 static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
4147 {
4148 	struct vega10_hwmgr *data = hwmgr->backend;
4149 
4150 	data->smc_state_table.gfx_boot_level =
4151 	data->smc_state_table.gfx_max_level =
4152 			vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4153 	data->smc_state_table.mem_boot_level =
4154 	data->smc_state_table.mem_max_level =
4155 			vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4156 
4157 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4158 			"Failed to upload boot level to highest!",
4159 			return -1);
4160 
4161 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4162 			"Failed to upload dpm max level to highest!",
4163 			return -1);
4164 
4165 	return 0;
4166 
4167 }
4168 
4169 static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
4170 {
4171 	struct vega10_hwmgr *data = hwmgr->backend;
4172 
4173 	data->smc_state_table.gfx_boot_level =
4174 			vega10_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
4175 	data->smc_state_table.gfx_max_level =
4176 			vega10_find_highest_dpm_level(&(data->dpm_table.gfx_table));
4177 	data->smc_state_table.mem_boot_level =
4178 			vega10_find_lowest_dpm_level(&(data->dpm_table.mem_table));
4179 	data->smc_state_table.mem_max_level =
4180 			vega10_find_highest_dpm_level(&(data->dpm_table.mem_table));
4181 
4182 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4183 			"Failed to upload DPM Bootup Levels!",
4184 			return -1);
4185 
4186 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4187 			"Failed to upload DPM Max Levels!",
4188 			return -1);
4189 	return 0;
4190 }
4191 
4192 static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
4193 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
4194 {
4195 	struct phm_ppt_v2_information *table_info =
4196 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
4197 
4198 	if (table_info->vdd_dep_on_sclk->count > VEGA10_UMD_PSTATE_GFXCLK_LEVEL &&
4199 		table_info->vdd_dep_on_socclk->count > VEGA10_UMD_PSTATE_SOCCLK_LEVEL &&
4200 		table_info->vdd_dep_on_mclk->count > VEGA10_UMD_PSTATE_MCLK_LEVEL) {
4201 		*sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
4202 		*soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL;
4203 		*mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL;
4204 	}
4205 
4206 	if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
4207 		*sclk_mask = 0;
4208 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
4209 		*mclk_mask = 0;
4210 	} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
4211 		/* under vega10  pp one vf mode, the gfx clk dpm need be lower
4212 		 * to level-4 due to the limited power
4213 		 */
4214 		if (hwmgr->pp_one_vf)
4215 			*sclk_mask = 4;
4216 		else
4217 			*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
4218 		*soc_mask = table_info->vdd_dep_on_socclk->count - 1;
4219 		*mclk_mask = table_info->vdd_dep_on_mclk->count - 1;
4220 	}
4221 
4222 	return 0;
4223 }
4224 
4225 static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
4226 {
4227 	if (!hwmgr->not_vf)
4228 		return;
4229 
4230 	switch (mode) {
4231 	case AMD_FAN_CTRL_NONE:
4232 		vega10_fan_ctrl_set_fan_speed_pwm(hwmgr, 255);
4233 		break;
4234 	case AMD_FAN_CTRL_MANUAL:
4235 		if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4236 			vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
4237 		break;
4238 	case AMD_FAN_CTRL_AUTO:
4239 		if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
4240 			vega10_fan_ctrl_start_smc_fan_control(hwmgr);
4241 		break;
4242 	default:
4243 		break;
4244 	}
4245 }
4246 
4247 static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
4248 		enum pp_clock_type type, uint32_t mask)
4249 {
4250 	struct vega10_hwmgr *data = hwmgr->backend;
4251 
4252 	switch (type) {
4253 	case PP_SCLK:
4254 		data->smc_state_table.gfx_boot_level = mask ? (ffs(mask) - 1) : 0;
4255 		data->smc_state_table.gfx_max_level = mask ? (fls(mask) - 1) : 0;
4256 
4257 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4258 			"Failed to upload boot level to lowest!",
4259 			return -EINVAL);
4260 
4261 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4262 			"Failed to upload dpm max level to highest!",
4263 			return -EINVAL);
4264 		break;
4265 
4266 	case PP_MCLK:
4267 		data->smc_state_table.mem_boot_level = mask ? (ffs(mask) - 1) : 0;
4268 		data->smc_state_table.mem_max_level = mask ? (fls(mask) - 1) : 0;
4269 
4270 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4271 			"Failed to upload boot level to lowest!",
4272 			return -EINVAL);
4273 
4274 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4275 			"Failed to upload dpm max level to highest!",
4276 			return -EINVAL);
4277 
4278 		break;
4279 
4280 	case PP_SOCCLK:
4281 		data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
4282 		data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
4283 
4284 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
4285 			"Failed to upload boot level to lowest!",
4286 			return -EINVAL);
4287 
4288 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
4289 			"Failed to upload dpm max level to highest!",
4290 			return -EINVAL);
4291 
4292 		break;
4293 
4294 	case PP_DCEFCLK:
4295 		pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
4296 		break;
4297 
4298 	case PP_PCIE:
4299 	default:
4300 		break;
4301 	}
4302 
4303 	return 0;
4304 }
4305 
4306 static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
4307 				enum amd_dpm_forced_level level)
4308 {
4309 	int ret = 0;
4310 	uint32_t sclk_mask = 0;
4311 	uint32_t mclk_mask = 0;
4312 	uint32_t soc_mask = 0;
4313 
4314 	switch (level) {
4315 	case AMD_DPM_FORCED_LEVEL_HIGH:
4316 		ret = vega10_force_dpm_highest(hwmgr);
4317 		break;
4318 	case AMD_DPM_FORCED_LEVEL_LOW:
4319 		ret = vega10_force_dpm_lowest(hwmgr);
4320 		break;
4321 	case AMD_DPM_FORCED_LEVEL_AUTO:
4322 		ret = vega10_unforce_dpm_levels(hwmgr);
4323 		break;
4324 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
4325 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
4326 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
4327 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
4328 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
4329 		if (ret)
4330 			return ret;
4331 		vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
4332 		vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
4333 		break;
4334 	case AMD_DPM_FORCED_LEVEL_MANUAL:
4335 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
4336 	default:
4337 		break;
4338 	}
4339 
4340 	if (!hwmgr->not_vf)
4341 		return ret;
4342 
4343 	if (!ret) {
4344 		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4345 			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
4346 		else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
4347 			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
4348 	}
4349 
4350 	return ret;
4351 }
4352 
4353 static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
4354 {
4355 	struct vega10_hwmgr *data = hwmgr->backend;
4356 
4357 	if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
4358 		return AMD_FAN_CTRL_MANUAL;
4359 	else
4360 		return AMD_FAN_CTRL_AUTO;
4361 }
4362 
4363 static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
4364 		struct amd_pp_simple_clock_info *info)
4365 {
4366 	struct phm_ppt_v2_information *table_info =
4367 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4368 	struct phm_clock_and_voltage_limits *max_limits =
4369 			&table_info->max_clock_voltage_on_ac;
4370 
4371 	info->engine_max_clock = max_limits->sclk;
4372 	info->memory_max_clock = max_limits->mclk;
4373 
4374 	return 0;
4375 }
4376 
4377 static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
4378 		struct pp_clock_levels_with_latency *clocks)
4379 {
4380 	struct phm_ppt_v2_information *table_info =
4381 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4382 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4383 			table_info->vdd_dep_on_sclk;
4384 	uint32_t i;
4385 
4386 	clocks->num_levels = 0;
4387 	for (i = 0; i < dep_table->count; i++) {
4388 		if (dep_table->entries[i].clk) {
4389 			clocks->data[clocks->num_levels].clocks_in_khz =
4390 					dep_table->entries[i].clk * 10;
4391 			clocks->num_levels++;
4392 		}
4393 	}
4394 
4395 }
4396 
4397 static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
4398 		struct pp_clock_levels_with_latency *clocks)
4399 {
4400 	struct phm_ppt_v2_information *table_info =
4401 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4402 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4403 			table_info->vdd_dep_on_mclk;
4404 	struct vega10_hwmgr *data = hwmgr->backend;
4405 	uint32_t j = 0;
4406 	uint32_t i;
4407 
4408 	for (i = 0; i < dep_table->count; i++) {
4409 		if (dep_table->entries[i].clk) {
4410 
4411 			clocks->data[j].clocks_in_khz =
4412 						dep_table->entries[i].clk * 10;
4413 			data->mclk_latency_table.entries[j].frequency =
4414 							dep_table->entries[i].clk;
4415 			clocks->data[j].latency_in_us =
4416 				data->mclk_latency_table.entries[j].latency = 25;
4417 			j++;
4418 		}
4419 	}
4420 	clocks->num_levels = data->mclk_latency_table.count = j;
4421 }
4422 
4423 static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
4424 		struct pp_clock_levels_with_latency *clocks)
4425 {
4426 	struct phm_ppt_v2_information *table_info =
4427 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4428 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4429 			table_info->vdd_dep_on_dcefclk;
4430 	uint32_t i;
4431 
4432 	for (i = 0; i < dep_table->count; i++) {
4433 		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4434 		clocks->data[i].latency_in_us = 0;
4435 		clocks->num_levels++;
4436 	}
4437 }
4438 
4439 static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
4440 		struct pp_clock_levels_with_latency *clocks)
4441 {
4442 	struct phm_ppt_v2_information *table_info =
4443 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4444 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table =
4445 			table_info->vdd_dep_on_socclk;
4446 	uint32_t i;
4447 
4448 	for (i = 0; i < dep_table->count; i++) {
4449 		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
4450 		clocks->data[i].latency_in_us = 0;
4451 		clocks->num_levels++;
4452 	}
4453 }
4454 
4455 static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
4456 		enum amd_pp_clock_type type,
4457 		struct pp_clock_levels_with_latency *clocks)
4458 {
4459 	switch (type) {
4460 	case amd_pp_sys_clock:
4461 		vega10_get_sclks(hwmgr, clocks);
4462 		break;
4463 	case amd_pp_mem_clock:
4464 		vega10_get_memclocks(hwmgr, clocks);
4465 		break;
4466 	case amd_pp_dcef_clock:
4467 		vega10_get_dcefclocks(hwmgr, clocks);
4468 		break;
4469 	case amd_pp_soc_clock:
4470 		vega10_get_socclocks(hwmgr, clocks);
4471 		break;
4472 	default:
4473 		return -1;
4474 	}
4475 
4476 	return 0;
4477 }
4478 
4479 static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
4480 		enum amd_pp_clock_type type,
4481 		struct pp_clock_levels_with_voltage *clocks)
4482 {
4483 	struct phm_ppt_v2_information *table_info =
4484 			(struct phm_ppt_v2_information *)hwmgr->pptable;
4485 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table;
4486 	uint32_t i;
4487 
4488 	switch (type) {
4489 	case amd_pp_mem_clock:
4490 		dep_table = table_info->vdd_dep_on_mclk;
4491 		break;
4492 	case amd_pp_dcef_clock:
4493 		dep_table = table_info->vdd_dep_on_dcefclk;
4494 		break;
4495 	case amd_pp_disp_clock:
4496 		dep_table = table_info->vdd_dep_on_dispclk;
4497 		break;
4498 	case amd_pp_pixel_clock:
4499 		dep_table = table_info->vdd_dep_on_pixclk;
4500 		break;
4501 	case amd_pp_phy_clock:
4502 		dep_table = table_info->vdd_dep_on_phyclk;
4503 		break;
4504 	default:
4505 		return -1;
4506 	}
4507 
4508 	for (i = 0; i < dep_table->count; i++) {
4509 		clocks->data[i].clocks_in_khz = dep_table->entries[i].clk  * 10;
4510 		clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
4511 				entries[dep_table->entries[i].vddInd].us_vdd);
4512 		clocks->num_levels++;
4513 	}
4514 
4515 	if (i < dep_table->count)
4516 		return -1;
4517 
4518 	return 0;
4519 }
4520 
4521 static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
4522 							void *clock_range)
4523 {
4524 	struct vega10_hwmgr *data = hwmgr->backend;
4525 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
4526 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
4527 
4528 	if (!data->registry_data.disable_water_mark) {
4529 		smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
4530 		data->water_marks_bitmap = WaterMarksExist;
4531 	}
4532 
4533 	return 0;
4534 }
4535 
4536 static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
4537 {
4538 	static const char *ppfeature_name[] = {
4539 				"DPM_PREFETCHER",
4540 				"GFXCLK_DPM",
4541 				"UCLK_DPM",
4542 				"SOCCLK_DPM",
4543 				"UVD_DPM",
4544 				"VCE_DPM",
4545 				"ULV",
4546 				"MP0CLK_DPM",
4547 				"LINK_DPM",
4548 				"DCEFCLK_DPM",
4549 				"AVFS",
4550 				"GFXCLK_DS",
4551 				"SOCCLK_DS",
4552 				"LCLK_DS",
4553 				"PPT",
4554 				"TDC",
4555 				"THERMAL",
4556 				"GFX_PER_CU_CG",
4557 				"RM",
4558 				"DCEFCLK_DS",
4559 				"ACDC",
4560 				"VR0HOT",
4561 				"VR1HOT",
4562 				"FW_CTF",
4563 				"LED_DISPLAY",
4564 				"FAN_CONTROL",
4565 				"FAST_PPT",
4566 				"DIDT",
4567 				"ACG",
4568 				"PCC_LIMIT"};
4569 	static const char *output_title[] = {
4570 				"FEATURES",
4571 				"BITMASK",
4572 				"ENABLEMENT"};
4573 	uint64_t features_enabled;
4574 	int i;
4575 	int ret = 0;
4576 	int size = 0;
4577 
4578 	phm_get_sysfs_buf(&buf, &size);
4579 
4580 	ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4581 	PP_ASSERT_WITH_CODE(!ret,
4582 			"[EnableAllSmuFeatures] Failed to get enabled smc features!",
4583 			return ret);
4584 
4585 	size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
4586 	size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
4587 				output_title[0],
4588 				output_title[1],
4589 				output_title[2]);
4590 	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
4591 		size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
4592 					ppfeature_name[i],
4593 					1ULL << i,
4594 					(features_enabled & (1ULL << i)) ? "Y" : "N");
4595 	}
4596 
4597 	return size;
4598 }
4599 
4600 static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
4601 {
4602 	uint64_t features_enabled;
4603 	uint64_t features_to_enable;
4604 	uint64_t features_to_disable;
4605 	int ret = 0;
4606 
4607 	if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
4608 		return -EINVAL;
4609 
4610 	ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
4611 	if (ret)
4612 		return ret;
4613 
4614 	features_to_disable =
4615 		features_enabled & ~new_ppfeature_masks;
4616 	features_to_enable =
4617 		~features_enabled & new_ppfeature_masks;
4618 
4619 	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
4620 	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
4621 
4622 	if (features_to_disable) {
4623 		ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
4624 		if (ret)
4625 			return ret;
4626 	}
4627 
4628 	if (features_to_enable) {
4629 		ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
4630 		if (ret)
4631 			return ret;
4632 	}
4633 
4634 	return 0;
4635 }
4636 
4637 static int vega10_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
4638 {
4639 	struct amdgpu_device *adev = hwmgr->adev;
4640 
4641 	return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
4642 		PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
4643 		>> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
4644 }
4645 
4646 static int vega10_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
4647 {
4648 	struct amdgpu_device *adev = hwmgr->adev;
4649 
4650 	return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
4651 		PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
4652 		>> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
4653 }
4654 
4655 static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr,
4656 				    enum pp_clock_type type, char *buf, int *offset)
4657 {
4658 	struct vega10_hwmgr *data = hwmgr->backend;
4659 	struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4660 	struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4661 	struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4662 	struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4663 	struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4664 	uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4665 	PPTable_t *pptable = &(data->smc_state_table.pp_table);
4666 
4667 	uint32_t i, now, count = 0;
4668 	int ret = 0;
4669 
4670 	switch (type) {
4671 	case PP_SCLK:
4672 		if (data->registry_data.sclk_dpm_key_disabled)
4673 			return -EOPNOTSUPP;
4674 
4675 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4676 		if (unlikely(ret != 0))
4677 			return ret;
4678 
4679 		if (hwmgr->pp_one_vf &&
4680 		    (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4681 			count = 5;
4682 		else
4683 			count = sclk_table->count;
4684 		for (i = 0; i < count; i++)
4685 			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4686 					i, sclk_table->dpm_levels[i].value / 100,
4687 					(i == now) ? "*" : "");
4688 		break;
4689 	case PP_MCLK:
4690 		if (data->registry_data.mclk_dpm_key_disabled)
4691 			return -EOPNOTSUPP;
4692 
4693 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4694 		if (unlikely(ret != 0))
4695 			return ret;
4696 
4697 		for (i = 0; i < mclk_table->count; i++)
4698 			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4699 					i, mclk_table->dpm_levels[i].value / 100,
4700 					(i == now) ? "*" : "");
4701 		break;
4702 	case PP_SOCCLK:
4703 		if (data->registry_data.socclk_dpm_key_disabled)
4704 			return -EOPNOTSUPP;
4705 
4706 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4707 		if (unlikely(ret != 0))
4708 			return ret;
4709 
4710 		for (i = 0; i < soc_table->count; i++)
4711 			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4712 					i, soc_table->dpm_levels[i].value / 100,
4713 					(i == now) ? "*" : "");
4714 		break;
4715 	case PP_DCEFCLK:
4716 		if (data->registry_data.dcefclk_dpm_key_disabled)
4717 			return -EOPNOTSUPP;
4718 
4719 		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
4720 							  PPSMC_MSG_GetClockFreqMHz,
4721 							  CLK_DCEFCLK, &now);
4722 		if (unlikely(ret != 0))
4723 			return ret;
4724 
4725 		for (i = 0; i < dcef_table->count; i++)
4726 			*offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n",
4727 					i, dcef_table->dpm_levels[i].value / 100,
4728 					(dcef_table->dpm_levels[i].value / 100 == now) ?
4729 					"*" : "");
4730 		break;
4731 	case PP_PCIE:
4732 		current_gen_speed =
4733 			vega10_get_current_pcie_link_speed_level(hwmgr);
4734 		current_lane_width =
4735 			vega10_get_current_pcie_link_width_level(hwmgr);
4736 		for (i = 0; i < NUM_LINK_LEVELS; i++) {
4737 			gen_speed = pptable->PcieGenSpeed[i];
4738 			lane_width = pptable->PcieLaneCount[i];
4739 
4740 			*offset += sysfs_emit_at(buf, *offset, "%d: %s %s %s\n", i,
4741 					(gen_speed == 0) ? "2.5GT/s," :
4742 					(gen_speed == 1) ? "5.0GT/s," :
4743 					(gen_speed == 2) ? "8.0GT/s," :
4744 					(gen_speed == 3) ? "16.0GT/s," : "",
4745 					(lane_width == 1) ? "x1" :
4746 					(lane_width == 2) ? "x2" :
4747 					(lane_width == 3) ? "x4" :
4748 					(lane_width == 4) ? "x8" :
4749 					(lane_width == 5) ? "x12" :
4750 					(lane_width == 6) ? "x16" : "",
4751 					(current_gen_speed == gen_speed) &&
4752 					(current_lane_width == lane_width) ?
4753 					"*" : "");
4754 		}
4755 		break;
4756 
4757 	case OD_SCLK:
4758 		if (!hwmgr->od_enabled)
4759 			return -EOPNOTSUPP;
4760 
4761 		*offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK");
4762 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4763 		for (i = 0; i < podn_vdd_dep->count; i++)
4764 			*offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4765 						 i, podn_vdd_dep->entries[i].clk / 100,
4766 						 podn_vdd_dep->entries[i].vddc);
4767 		break;
4768 	case OD_MCLK:
4769 		if (!hwmgr->od_enabled)
4770 			return -EOPNOTSUPP;
4771 
4772 		*offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK");
4773 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4774 		for (i = 0; i < podn_vdd_dep->count; i++)
4775 			*offset += sysfs_emit_at(buf, *offset, "%d: %10uMhz %10umV\n",
4776 						 i, podn_vdd_dep->entries[i].clk/100,
4777 						 podn_vdd_dep->entries[i].vddc);
4778 		break;
4779 	case OD_RANGE:
4780 		if (!hwmgr->od_enabled)
4781 			return -EOPNOTSUPP;
4782 
4783 		*offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
4784 		*offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMHz %10uMHz\n",
4785 					 data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4786 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4787 		*offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMHz %10uMHz\n",
4788 					 data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4789 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4790 		*offset += sysfs_emit_at(buf, *offset, "VDDC: %7umV %11umV\n",
4791 					 data->odn_dpm_table.min_vddc,
4792 					 data->odn_dpm_table.max_vddc);
4793 		break;
4794 	default:
4795 		ret = -ENOENT;
4796 		break;
4797 	}
4798 	return ret;
4799 }
4800 
4801 static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
4802 		enum pp_clock_type type, char *buf)
4803 {
4804 	struct vega10_hwmgr *data = hwmgr->backend;
4805 	struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4806 	struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4807 	struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
4808 	struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
4809 	struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
4810 	uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width;
4811 	PPTable_t *pptable = &(data->smc_state_table.pp_table);
4812 
4813 	int i, now, size = 0, count = 0;
4814 
4815 	switch (type) {
4816 	case PP_SCLK:
4817 		if (data->registry_data.sclk_dpm_key_disabled)
4818 			break;
4819 
4820 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now);
4821 
4822 		if (hwmgr->pp_one_vf &&
4823 		    (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK))
4824 			count = 5;
4825 		else
4826 			count = sclk_table->count;
4827 		for (i = 0; i < count; i++)
4828 			size += sprintf(buf + size, "%d: %uMhz %s\n",
4829 					i, sclk_table->dpm_levels[i].value / 100,
4830 					(i == now) ? "*" : "");
4831 		break;
4832 	case PP_MCLK:
4833 		if (data->registry_data.mclk_dpm_key_disabled)
4834 			break;
4835 
4836 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now);
4837 
4838 		for (i = 0; i < mclk_table->count; i++)
4839 			size += sprintf(buf + size, "%d: %uMhz %s\n",
4840 					i, mclk_table->dpm_levels[i].value / 100,
4841 					(i == now) ? "*" : "");
4842 		break;
4843 	case PP_SOCCLK:
4844 		if (data->registry_data.socclk_dpm_key_disabled)
4845 			break;
4846 
4847 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now);
4848 
4849 		for (i = 0; i < soc_table->count; i++)
4850 			size += sprintf(buf + size, "%d: %uMhz %s\n",
4851 					i, soc_table->dpm_levels[i].value / 100,
4852 					(i == now) ? "*" : "");
4853 		break;
4854 	case PP_DCEFCLK:
4855 		if (data->registry_data.dcefclk_dpm_key_disabled)
4856 			break;
4857 
4858 		smum_send_msg_to_smc_with_parameter(hwmgr,
4859 				PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now);
4860 
4861 		for (i = 0; i < dcef_table->count; i++)
4862 			size += sprintf(buf + size, "%d: %uMhz %s\n",
4863 					i, dcef_table->dpm_levels[i].value / 100,
4864 					(dcef_table->dpm_levels[i].value / 100 == now) ?
4865 					"*" : "");
4866 		break;
4867 	case PP_PCIE:
4868 		current_gen_speed =
4869 			vega10_get_current_pcie_link_speed_level(hwmgr);
4870 		current_lane_width =
4871 			vega10_get_current_pcie_link_width_level(hwmgr);
4872 		for (i = 0; i < NUM_LINK_LEVELS; i++) {
4873 			gen_speed = pptable->PcieGenSpeed[i];
4874 			lane_width = pptable->PcieLaneCount[i];
4875 
4876 			size += sprintf(buf + size, "%d: %s %s %s\n", i,
4877 					(gen_speed == 0) ? "2.5GT/s," :
4878 					(gen_speed == 1) ? "5.0GT/s," :
4879 					(gen_speed == 2) ? "8.0GT/s," :
4880 					(gen_speed == 3) ? "16.0GT/s," : "",
4881 					(lane_width == 1) ? "x1" :
4882 					(lane_width == 2) ? "x2" :
4883 					(lane_width == 3) ? "x4" :
4884 					(lane_width == 4) ? "x8" :
4885 					(lane_width == 5) ? "x12" :
4886 					(lane_width == 6) ? "x16" : "",
4887 					(current_gen_speed == gen_speed) &&
4888 					(current_lane_width == lane_width) ?
4889 					"*" : "");
4890 		}
4891 		break;
4892 
4893 	case OD_SCLK:
4894 		if (hwmgr->od_enabled) {
4895 			size += sprintf(buf + size, "%s:\n", "OD_SCLK");
4896 			podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
4897 			for (i = 0; i < podn_vdd_dep->count; i++)
4898 				size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4899 					i, podn_vdd_dep->entries[i].clk / 100,
4900 						podn_vdd_dep->entries[i].vddc);
4901 		}
4902 		break;
4903 	case OD_MCLK:
4904 		if (hwmgr->od_enabled) {
4905 			size += sprintf(buf + size, "%s:\n", "OD_MCLK");
4906 			podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
4907 			for (i = 0; i < podn_vdd_dep->count; i++)
4908 				size += sprintf(buf + size, "%d: %10uMhz %10umV\n",
4909 					i, podn_vdd_dep->entries[i].clk/100,
4910 						podn_vdd_dep->entries[i].vddc);
4911 		}
4912 		break;
4913 	case OD_RANGE:
4914 		if (hwmgr->od_enabled) {
4915 			size += sprintf(buf + size, "%s:\n", "OD_RANGE");
4916 			size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
4917 				data->golden_dpm_table.gfx_table.dpm_levels[0].value/100,
4918 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
4919 			size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n",
4920 				data->golden_dpm_table.mem_table.dpm_levels[0].value/100,
4921 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
4922 			size += sprintf(buf + size, "VDDC: %7umV %11umV\n",
4923 				data->odn_dpm_table.min_vddc,
4924 				data->odn_dpm_table.max_vddc);
4925 		}
4926 		break;
4927 	default:
4928 		break;
4929 	}
4930 	return size;
4931 }
4932 
4933 static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4934 {
4935 	struct vega10_hwmgr *data = hwmgr->backend;
4936 	Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
4937 	int result = 0;
4938 
4939 	if ((data->water_marks_bitmap & WaterMarksExist) &&
4940 			!(data->water_marks_bitmap & WaterMarksLoaded)) {
4941 		result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
4942 		PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
4943 		data->water_marks_bitmap |= WaterMarksLoaded;
4944 	}
4945 
4946 	if (data->water_marks_bitmap & WaterMarksLoaded) {
4947 		smum_send_msg_to_smc_with_parameter(hwmgr,
4948 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
4949 			NULL);
4950 	}
4951 
4952 	return result;
4953 }
4954 
4955 static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4956 {
4957 	struct vega10_hwmgr *data = hwmgr->backend;
4958 
4959 	if (data->smu_features[GNLD_DPM_UVD].supported) {
4960 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
4961 				enable,
4962 				data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
4963 				"Attempt to Enable/Disable DPM UVD Failed!",
4964 				return -1);
4965 		data->smu_features[GNLD_DPM_UVD].enabled = enable;
4966 	}
4967 	return 0;
4968 }
4969 
4970 static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
4971 {
4972 	struct vega10_hwmgr *data = hwmgr->backend;
4973 
4974 	data->vce_power_gated = bgate;
4975 	vega10_enable_disable_vce_dpm(hwmgr, !bgate);
4976 }
4977 
4978 static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
4979 {
4980 	struct vega10_hwmgr *data = hwmgr->backend;
4981 
4982 	data->uvd_power_gated = bgate;
4983 	vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
4984 }
4985 
4986 static inline bool vega10_are_power_levels_equal(
4987 				const struct vega10_performance_level *pl1,
4988 				const struct vega10_performance_level *pl2)
4989 {
4990 	return ((pl1->soc_clock == pl2->soc_clock) &&
4991 			(pl1->gfx_clock == pl2->gfx_clock) &&
4992 			(pl1->mem_clock == pl2->mem_clock));
4993 }
4994 
4995 static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
4996 				const struct pp_hw_power_state *pstate1,
4997 			const struct pp_hw_power_state *pstate2, bool *equal)
4998 {
4999 	const struct vega10_power_state *vega10_psa;
5000 	const struct vega10_power_state *vega10_psb;
5001 	int i;
5002 
5003 	if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
5004 		return -EINVAL;
5005 
5006 	vega10_psa = cast_const_phw_vega10_power_state(pstate1);
5007 	vega10_psb = cast_const_phw_vega10_power_state(pstate2);
5008 	if (vega10_psa == NULL || vega10_psb == NULL)
5009 		return -EINVAL;
5010 
5011 	/* If the two states don't even have the same number of performance levels
5012 	 * they cannot be the same state.
5013 	 */
5014 	if (vega10_psa->performance_level_count != vega10_psb->performance_level_count) {
5015 		*equal = false;
5016 		return 0;
5017 	}
5018 
5019 	for (i = 0; i < vega10_psa->performance_level_count; i++) {
5020 		if (!vega10_are_power_levels_equal(&(vega10_psa->performance_levels[i]),
5021 						   &(vega10_psb->performance_levels[i]))) {
5022 			/* If we have found even one performance level pair
5023 			 * that is different the states are different.
5024 			 */
5025 			*equal = false;
5026 			return 0;
5027 		}
5028 	}
5029 
5030 	/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5031 	*equal = ((vega10_psa->uvd_clks.vclk == vega10_psb->uvd_clks.vclk) &&
5032 		  (vega10_psa->uvd_clks.dclk == vega10_psb->uvd_clks.dclk));
5033 	*equal &= ((vega10_psa->vce_clks.evclk == vega10_psb->vce_clks.evclk) &&
5034 		   (vega10_psa->vce_clks.ecclk == vega10_psb->vce_clks.ecclk));
5035 	*equal &= (vega10_psa->sclk_threshold == vega10_psb->sclk_threshold);
5036 
5037 	return 0;
5038 }
5039 
5040 static bool
5041 vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5042 {
5043 	struct vega10_hwmgr *data = hwmgr->backend;
5044 	bool is_update_required = false;
5045 
5046 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
5047 		is_update_required = true;
5048 
5049 	if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
5050 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
5051 			is_update_required = true;
5052 	}
5053 
5054 	return is_update_required;
5055 }
5056 
5057 static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
5058 {
5059 	int tmp_result, result = 0;
5060 
5061 	if (!hwmgr->not_vf)
5062 		return 0;
5063 
5064 	if (PP_CAP(PHM_PlatformCaps_ThermalController))
5065 		vega10_disable_thermal_protection(hwmgr);
5066 
5067 	tmp_result = vega10_disable_power_containment(hwmgr);
5068 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5069 			"Failed to disable power containment!", result = tmp_result);
5070 
5071 	tmp_result = vega10_disable_didt_config(hwmgr);
5072 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5073 			"Failed to disable didt config!", result = tmp_result);
5074 
5075 	tmp_result = vega10_avfs_enable(hwmgr, false);
5076 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5077 			"Failed to disable AVFS!", result = tmp_result);
5078 
5079 	tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
5080 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5081 			"Failed to stop DPM!", result = tmp_result);
5082 
5083 	tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
5084 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5085 			"Failed to disable deep sleep!", result = tmp_result);
5086 
5087 	tmp_result = vega10_disable_ulv(hwmgr);
5088 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5089 			"Failed to disable ulv!", result = tmp_result);
5090 
5091 	tmp_result =  vega10_acg_disable(hwmgr);
5092 	PP_ASSERT_WITH_CODE((tmp_result == 0),
5093 			"Failed to disable acg!", result = tmp_result);
5094 
5095 	vega10_enable_disable_PCC_limit_feature(hwmgr, false);
5096 	return result;
5097 }
5098 
5099 static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
5100 {
5101 	struct vega10_hwmgr *data = hwmgr->backend;
5102 	int result;
5103 
5104 	result = vega10_disable_dpm_tasks(hwmgr);
5105 	PP_ASSERT_WITH_CODE((0 == result),
5106 			"[disable_dpm_tasks] Failed to disable DPM!",
5107 			);
5108 	data->water_marks_bitmap &= ~(WaterMarksLoaded);
5109 
5110 	return result;
5111 }
5112 
5113 static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
5114 {
5115 	struct vega10_hwmgr *data = hwmgr->backend;
5116 	struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
5117 	struct vega10_single_dpm_table *golden_sclk_table =
5118 			&(data->golden_dpm_table.gfx_table);
5119 	int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
5120 	int golden_value = golden_sclk_table->dpm_levels
5121 			[golden_sclk_table->count - 1].value;
5122 
5123 	value -= golden_value;
5124 	value = DIV_ROUND_UP(value * 100, golden_value);
5125 
5126 	return value;
5127 }
5128 
5129 static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5130 {
5131 	struct vega10_hwmgr *data = hwmgr->backend;
5132 	struct vega10_single_dpm_table *golden_sclk_table =
5133 			&(data->golden_dpm_table.gfx_table);
5134 	struct pp_power_state *ps;
5135 	struct vega10_power_state *vega10_ps;
5136 
5137 	ps = hwmgr->request_ps;
5138 
5139 	if (ps == NULL)
5140 		return -EINVAL;
5141 
5142 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5143 	if (vega10_ps == NULL)
5144 		return -EINVAL;
5145 
5146 	vega10_ps->performance_levels
5147 	[vega10_ps->performance_level_count - 1].gfx_clock =
5148 			golden_sclk_table->dpm_levels
5149 			[golden_sclk_table->count - 1].value *
5150 			value / 100 +
5151 			golden_sclk_table->dpm_levels
5152 			[golden_sclk_table->count - 1].value;
5153 
5154 	if (vega10_ps->performance_levels
5155 			[vega10_ps->performance_level_count - 1].gfx_clock >
5156 			hwmgr->platform_descriptor.overdriveLimit.engineClock) {
5157 		vega10_ps->performance_levels
5158 		[vega10_ps->performance_level_count - 1].gfx_clock =
5159 				hwmgr->platform_descriptor.overdriveLimit.engineClock;
5160 		pr_warn("max sclk supported by vbios is %d\n",
5161 				hwmgr->platform_descriptor.overdriveLimit.engineClock);
5162 	}
5163 	return 0;
5164 }
5165 
5166 static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
5167 {
5168 	struct vega10_hwmgr *data = hwmgr->backend;
5169 	struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
5170 	struct vega10_single_dpm_table *golden_mclk_table =
5171 			&(data->golden_dpm_table.mem_table);
5172 	int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
5173 	int golden_value = golden_mclk_table->dpm_levels
5174 			[golden_mclk_table->count - 1].value;
5175 
5176 	value -= golden_value;
5177 	value = DIV_ROUND_UP(value * 100, golden_value);
5178 
5179 	return value;
5180 }
5181 
5182 static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
5183 {
5184 	struct vega10_hwmgr *data = hwmgr->backend;
5185 	struct vega10_single_dpm_table *golden_mclk_table =
5186 			&(data->golden_dpm_table.mem_table);
5187 	struct pp_power_state  *ps;
5188 	struct vega10_power_state  *vega10_ps;
5189 
5190 	ps = hwmgr->request_ps;
5191 
5192 	if (ps == NULL)
5193 		return -EINVAL;
5194 
5195 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5196 	if (vega10_ps == NULL)
5197 		return -EINVAL;
5198 
5199 	vega10_ps->performance_levels
5200 	[vega10_ps->performance_level_count - 1].mem_clock =
5201 			golden_mclk_table->dpm_levels
5202 			[golden_mclk_table->count - 1].value *
5203 			value / 100 +
5204 			golden_mclk_table->dpm_levels
5205 			[golden_mclk_table->count - 1].value;
5206 
5207 	if (vega10_ps->performance_levels
5208 			[vega10_ps->performance_level_count - 1].mem_clock >
5209 			hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
5210 		vega10_ps->performance_levels
5211 		[vega10_ps->performance_level_count - 1].mem_clock =
5212 				hwmgr->platform_descriptor.overdriveLimit.memoryClock;
5213 		pr_warn("max mclk supported by vbios is %d\n",
5214 				hwmgr->platform_descriptor.overdriveLimit.memoryClock);
5215 	}
5216 
5217 	return 0;
5218 }
5219 
5220 static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
5221 					uint32_t virtual_addr_low,
5222 					uint32_t virtual_addr_hi,
5223 					uint32_t mc_addr_low,
5224 					uint32_t mc_addr_hi,
5225 					uint32_t size)
5226 {
5227 	smum_send_msg_to_smc_with_parameter(hwmgr,
5228 					PPSMC_MSG_SetSystemVirtualDramAddrHigh,
5229 					virtual_addr_hi,
5230 					NULL);
5231 	smum_send_msg_to_smc_with_parameter(hwmgr,
5232 					PPSMC_MSG_SetSystemVirtualDramAddrLow,
5233 					virtual_addr_low,
5234 					NULL);
5235 	smum_send_msg_to_smc_with_parameter(hwmgr,
5236 					PPSMC_MSG_DramLogSetDramAddrHigh,
5237 					mc_addr_hi,
5238 					NULL);
5239 
5240 	smum_send_msg_to_smc_with_parameter(hwmgr,
5241 					PPSMC_MSG_DramLogSetDramAddrLow,
5242 					mc_addr_low,
5243 					NULL);
5244 
5245 	smum_send_msg_to_smc_with_parameter(hwmgr,
5246 					PPSMC_MSG_DramLogSetDramSize,
5247 					size,
5248 					NULL);
5249 	return 0;
5250 }
5251 
5252 static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
5253 		struct PP_TemperatureRange *thermal_data)
5254 {
5255 	struct vega10_hwmgr *data = hwmgr->backend;
5256 	PPTable_t *pp_table = &(data->smc_state_table.pp_table);
5257 	struct phm_ppt_v2_information *pp_table_info =
5258 		(struct phm_ppt_v2_information *)(hwmgr->pptable);
5259 	struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
5260 
5261 	memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
5262 
5263 	thermal_data->max = pp_table->TedgeLimit *
5264 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5265 	thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
5266 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5267 	thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
5268 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5269 	thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
5270 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5271 	thermal_data->mem_crit_max = pp_table->ThbmLimit *
5272 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5273 	thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
5274 		PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5275 
5276 	if (tdp_table->usSoftwareShutdownTemp > pp_table->ThotspotLimit &&
5277 	    tdp_table->usSoftwareShutdownTemp < VEGA10_THERMAL_MAXIMUM_ALERT_TEMP)
5278 		thermal_data->sw_ctf_threshold = tdp_table->usSoftwareShutdownTemp;
5279 	else
5280 		thermal_data->sw_ctf_threshold = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
5281 	thermal_data->sw_ctf_threshold *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
5282 
5283 	return 0;
5284 }
5285 
5286 static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
5287 {
5288 	struct vega10_hwmgr *data = hwmgr->backend;
5289 	uint32_t i, size = 0;
5290 	static const uint8_t profile_mode_setting[6][4] = {{70, 60, 0, 0,},
5291 						{70, 60, 1, 3,},
5292 						{90, 60, 0, 0,},
5293 						{70, 60, 0, 0,},
5294 						{70, 90, 0, 0,},
5295 						{30, 60, 0, 6,},
5296 						};
5297 	static const char *title[6] = {"NUM",
5298 			"MODE_NAME",
5299 			"BUSY_SET_POINT",
5300 			"FPS",
5301 			"USE_RLC_BUSY",
5302 			"MIN_ACTIVE_LEVEL"};
5303 
5304 	if (!buf)
5305 		return -EINVAL;
5306 
5307 	phm_get_sysfs_buf(&buf, &size);
5308 
5309 	size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
5310 			title[1], title[2], title[3], title[4], title[5]);
5311 
5312 	for (i = 0; i < PP_SMC_POWER_PROFILE_CUSTOM; i++)
5313 		size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n",
5314 			i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5315 			profile_mode_setting[i][0], profile_mode_setting[i][1],
5316 			profile_mode_setting[i][2], profile_mode_setting[i][3]);
5317 
5318 	size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", i,
5319 			amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
5320 			data->custom_profile_mode[0], data->custom_profile_mode[1],
5321 			data->custom_profile_mode[2], data->custom_profile_mode[3]);
5322 	return size;
5323 }
5324 
5325 static bool vega10_get_power_profile_mode_quirks(struct pp_hwmgr *hwmgr)
5326 {
5327 	struct amdgpu_device *adev = hwmgr->adev;
5328 
5329 	return (adev->pdev->device == 0x6860);
5330 }
5331 
5332 static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
5333 {
5334 	struct vega10_hwmgr *data = hwmgr->backend;
5335 	uint8_t busy_set_point;
5336 	uint8_t FPS;
5337 	uint8_t use_rlc_busy;
5338 	uint8_t min_active_level;
5339 	uint32_t power_profile_mode = input[size];
5340 
5341 	if (power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
5342 		if (size != 0 && size != 4)
5343 			return -EINVAL;
5344 
5345 		/* If size = 0 and the CUSTOM profile has been set already
5346 		 * then just apply the profile. The copy stored in the hwmgr
5347 		 * is zeroed out on init
5348 		 */
5349 		if (size == 0) {
5350 			if (data->custom_profile_mode[0] != 0)
5351 				goto out;
5352 			else
5353 				return -EINVAL;
5354 		}
5355 
5356 		data->custom_profile_mode[0] = busy_set_point = input[0];
5357 		data->custom_profile_mode[1] = FPS = input[1];
5358 		data->custom_profile_mode[2] = use_rlc_busy = input[2];
5359 		data->custom_profile_mode[3] = min_active_level = input[3];
5360 		smum_send_msg_to_smc_with_parameter(hwmgr,
5361 					PPSMC_MSG_SetCustomGfxDpmParameters,
5362 					busy_set_point | FPS<<8 |
5363 					use_rlc_busy << 16 | min_active_level<<24,
5364 					NULL);
5365 	}
5366 
5367 out:
5368 	if (vega10_get_power_profile_mode_quirks(hwmgr))
5369 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5370 						1 << power_profile_mode,
5371 						NULL);
5372 	else
5373 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
5374 						(!power_profile_mode) ? 0 : 1 << (power_profile_mode - 1),
5375 						NULL);
5376 
5377 	hwmgr->power_profile_mode = power_profile_mode;
5378 
5379 	return 0;
5380 }
5381 
5382 
5383 static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
5384 					enum PP_OD_DPM_TABLE_COMMAND type,
5385 					uint32_t clk,
5386 					uint32_t voltage)
5387 {
5388 	struct vega10_hwmgr *data = hwmgr->backend;
5389 	struct vega10_odn_dpm_table *odn_table = &(data->odn_dpm_table);
5390 	struct vega10_single_dpm_table *golden_table;
5391 
5392 	if (voltage < odn_table->min_vddc || voltage > odn_table->max_vddc) {
5393 		pr_info("OD voltage is out of range [%d - %d] mV\n", odn_table->min_vddc, odn_table->max_vddc);
5394 		return false;
5395 	}
5396 
5397 	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5398 		golden_table = &(data->golden_dpm_table.gfx_table);
5399 		if (golden_table->dpm_levels[0].value > clk ||
5400 			hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
5401 			pr_info("OD engine clock is out of range [%d - %d] MHz\n",
5402 				golden_table->dpm_levels[0].value/100,
5403 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
5404 			return false;
5405 		}
5406 	} else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5407 		golden_table = &(data->golden_dpm_table.mem_table);
5408 		if (golden_table->dpm_levels[0].value > clk ||
5409 			hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
5410 			pr_info("OD memory clock is out of range [%d - %d] MHz\n",
5411 				golden_table->dpm_levels[0].value/100,
5412 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
5413 			return false;
5414 		}
5415 	} else {
5416 		return false;
5417 	}
5418 
5419 	return true;
5420 }
5421 
5422 static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
5423 {
5424 	struct vega10_hwmgr *data = hwmgr->backend;
5425 	struct pp_power_state *ps = hwmgr->request_ps;
5426 	struct vega10_power_state *vega10_ps;
5427 	struct vega10_single_dpm_table *gfx_dpm_table =
5428 		&data->dpm_table.gfx_table;
5429 	struct vega10_single_dpm_table *soc_dpm_table =
5430 		&data->dpm_table.soc_table;
5431 	struct vega10_single_dpm_table *mem_dpm_table =
5432 		&data->dpm_table.mem_table;
5433 	int max_level;
5434 
5435 	if (!ps)
5436 		return;
5437 
5438 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5439 	if (vega10_ps == NULL)
5440 		return;
5441 
5442 	max_level = vega10_ps->performance_level_count - 1;
5443 
5444 	if (vega10_ps->performance_levels[max_level].gfx_clock !=
5445 	    gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5446 		vega10_ps->performance_levels[max_level].gfx_clock =
5447 			gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5448 
5449 	if (vega10_ps->performance_levels[max_level].soc_clock !=
5450 	    soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5451 		vega10_ps->performance_levels[max_level].soc_clock =
5452 			soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5453 
5454 	if (vega10_ps->performance_levels[max_level].mem_clock !=
5455 	    mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5456 		vega10_ps->performance_levels[max_level].mem_clock =
5457 			mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5458 
5459 	if (!hwmgr->ps)
5460 		return;
5461 
5462 	ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
5463 	vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
5464 	if (vega10_ps == NULL)
5465 		return;
5466 
5467 	max_level = vega10_ps->performance_level_count - 1;
5468 
5469 	if (vega10_ps->performance_levels[max_level].gfx_clock !=
5470 	    gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value)
5471 		vega10_ps->performance_levels[max_level].gfx_clock =
5472 			gfx_dpm_table->dpm_levels[gfx_dpm_table->count - 1].value;
5473 
5474 	if (vega10_ps->performance_levels[max_level].soc_clock !=
5475 	    soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value)
5476 		vega10_ps->performance_levels[max_level].soc_clock =
5477 			soc_dpm_table->dpm_levels[soc_dpm_table->count - 1].value;
5478 
5479 	if (vega10_ps->performance_levels[max_level].mem_clock !=
5480 	    mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value)
5481 		vega10_ps->performance_levels[max_level].mem_clock =
5482 			mem_dpm_table->dpm_levels[mem_dpm_table->count - 1].value;
5483 }
5484 
5485 static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
5486 						enum PP_OD_DPM_TABLE_COMMAND type)
5487 {
5488 	struct vega10_hwmgr *data = hwmgr->backend;
5489 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
5490 	struct phm_ppt_v1_clock_voltage_dependency_table *dep_table = table_info->vdd_dep_on_socclk;
5491 	struct vega10_single_dpm_table *dpm_table = &data->golden_dpm_table.mem_table;
5492 
5493 	struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_on_socclk =
5494 							&data->odn_dpm_table.vdd_dep_on_socclk;
5495 	struct vega10_odn_vddc_lookup_table *od_vddc_lookup_table = &data->odn_dpm_table.vddc_lookup_table;
5496 
5497 	struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep;
5498 	uint8_t i, j;
5499 
5500 	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
5501 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk;
5502 		for (i = 0; i < podn_vdd_dep->count; i++)
5503 			od_vddc_lookup_table->entries[i].us_vdd = podn_vdd_dep->entries[i].vddc;
5504 	} else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) {
5505 		podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk;
5506 		for (i = 0; i < dpm_table->count; i++) {
5507 			for (j = 0; j < od_vddc_lookup_table->count; j++) {
5508 				if (od_vddc_lookup_table->entries[j].us_vdd >
5509 					podn_vdd_dep->entries[i].vddc)
5510 					break;
5511 			}
5512 			if (j == od_vddc_lookup_table->count) {
5513 				j = od_vddc_lookup_table->count - 1;
5514 				od_vddc_lookup_table->entries[j].us_vdd =
5515 					podn_vdd_dep->entries[i].vddc;
5516 				data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
5517 			}
5518 			podn_vdd_dep->entries[i].vddInd = j;
5519 		}
5520 		dpm_table = &data->dpm_table.soc_table;
5521 		for (i = 0; i < dep_table->count; i++) {
5522 			if (dep_table->entries[i].vddInd == podn_vdd_dep->entries[podn_vdd_dep->count-1].vddInd &&
5523 					dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count-1].clk) {
5524 				data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5525 				for (; (i < dep_table->count) &&
5526 				       (dep_table->entries[i].clk < podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk); i++) {
5527 					podn_vdd_dep_on_socclk->entries[i].clk = podn_vdd_dep->entries[podn_vdd_dep->count-1].clk;
5528 					dpm_table->dpm_levels[i].value = podn_vdd_dep_on_socclk->entries[i].clk;
5529 				}
5530 				break;
5531 			} else {
5532 				dpm_table->dpm_levels[i].value = dep_table->entries[i].clk;
5533 				podn_vdd_dep_on_socclk->entries[i].vddc = dep_table->entries[i].vddc;
5534 				podn_vdd_dep_on_socclk->entries[i].vddInd = dep_table->entries[i].vddInd;
5535 				podn_vdd_dep_on_socclk->entries[i].clk = dep_table->entries[i].clk;
5536 			}
5537 		}
5538 		if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk <
5539 					podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk) {
5540 			data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5541 			podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].clk =
5542 				podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5543 			dpm_table->dpm_levels[podn_vdd_dep_on_socclk->count - 1].value =
5544 				podn_vdd_dep->entries[podn_vdd_dep->count - 1].clk;
5545 		}
5546 		if (podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd <
5547 					podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd) {
5548 			data->need_update_dpm_table |= DPMTABLE_UPDATE_SOCCLK;
5549 			podn_vdd_dep_on_socclk->entries[podn_vdd_dep_on_socclk->count - 1].vddInd =
5550 				podn_vdd_dep->entries[podn_vdd_dep->count - 1].vddInd;
5551 		}
5552 	}
5553 	vega10_odn_update_power_state(hwmgr);
5554 }
5555 
5556 static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
5557 					enum PP_OD_DPM_TABLE_COMMAND type,
5558 					long *input, uint32_t size)
5559 {
5560 	struct vega10_hwmgr *data = hwmgr->backend;
5561 	struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep_table;
5562 	struct vega10_single_dpm_table *dpm_table;
5563 
5564 	uint32_t input_clk;
5565 	uint32_t input_vol;
5566 	uint32_t input_level;
5567 	uint32_t i;
5568 
5569 	PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
5570 				return -EINVAL);
5571 
5572 	if (!hwmgr->od_enabled) {
5573 		pr_info("OverDrive feature not enabled\n");
5574 		return -EINVAL;
5575 	}
5576 
5577 	if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) {
5578 		dpm_table = &data->dpm_table.gfx_table;
5579 		podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_sclk;
5580 		data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
5581 	} else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) {
5582 		dpm_table = &data->dpm_table.mem_table;
5583 		podn_vdd_dep_table = &data->odn_dpm_table.vdd_dep_on_mclk;
5584 		data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
5585 	} else if (PP_OD_RESTORE_DEFAULT_TABLE == type) {
5586 		memcpy(&(data->dpm_table), &(data->golden_dpm_table), sizeof(struct vega10_dpm_table));
5587 		vega10_odn_initial_default_setting(hwmgr);
5588 		vega10_odn_update_power_state(hwmgr);
5589 		/* force to update all clock tables */
5590 		data->need_update_dpm_table = DPMTABLE_UPDATE_SCLK |
5591 					      DPMTABLE_UPDATE_MCLK |
5592 					      DPMTABLE_UPDATE_SOCCLK;
5593 		return 0;
5594 	} else if (PP_OD_COMMIT_DPM_TABLE == type) {
5595 		vega10_check_dpm_table_updated(hwmgr);
5596 		return 0;
5597 	} else {
5598 		return -EINVAL;
5599 	}
5600 
5601 	for (i = 0; i < size; i += 3) {
5602 		if (i + 3 > size || input[i] >= podn_vdd_dep_table->count) {
5603 			pr_info("invalid clock voltage input\n");
5604 			return 0;
5605 		}
5606 		input_level = input[i];
5607 		input_clk = input[i+1] * 100;
5608 		input_vol = input[i+2];
5609 
5610 		if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
5611 			dpm_table->dpm_levels[input_level].value = input_clk;
5612 			podn_vdd_dep_table->entries[input_level].clk = input_clk;
5613 			podn_vdd_dep_table->entries[input_level].vddc = input_vol;
5614 		} else {
5615 			return -EINVAL;
5616 		}
5617 	}
5618 	vega10_odn_update_soc_table(hwmgr, type);
5619 	return 0;
5620 }
5621 
5622 static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
5623 				enum pp_mp1_state mp1_state)
5624 {
5625 	uint16_t msg;
5626 	int ret;
5627 
5628 	switch (mp1_state) {
5629 	case PP_MP1_STATE_UNLOAD:
5630 		msg = PPSMC_MSG_PrepareMp1ForUnload;
5631 		break;
5632 	case PP_MP1_STATE_SHUTDOWN:
5633 	case PP_MP1_STATE_RESET:
5634 	case PP_MP1_STATE_NONE:
5635 	default:
5636 		return 0;
5637 	}
5638 
5639 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
5640 			    "[PrepareMp1] Failed!",
5641 			    return ret);
5642 
5643 	return 0;
5644 }
5645 
5646 static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
5647 				PHM_PerformanceLevelDesignation designation, uint32_t index,
5648 				PHM_PerformanceLevel *level)
5649 {
5650 	const struct vega10_power_state *vega10_ps;
5651 	uint32_t i;
5652 
5653 	if (level == NULL || hwmgr == NULL || state == NULL)
5654 		return -EINVAL;
5655 
5656 	vega10_ps = cast_const_phw_vega10_power_state(state);
5657 	if (vega10_ps == NULL)
5658 		return -EINVAL;
5659 
5660 	i = index > vega10_ps->performance_level_count - 1 ?
5661 			vega10_ps->performance_level_count - 1 : index;
5662 
5663 	level->coreClock = vega10_ps->performance_levels[i].gfx_clock;
5664 	level->memory_clock = vega10_ps->performance_levels[i].mem_clock;
5665 
5666 	return 0;
5667 }
5668 
5669 static int vega10_disable_power_features_for_compute_performance(struct pp_hwmgr *hwmgr, bool disable)
5670 {
5671 	struct vega10_hwmgr *data = hwmgr->backend;
5672 	uint32_t feature_mask = 0;
5673 
5674 	if (disable) {
5675 		feature_mask |= data->smu_features[GNLD_ULV].enabled ?
5676 			data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5677 		feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
5678 			data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5679 		feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
5680 			data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5681 		feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
5682 			data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5683 		feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
5684 			data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5685 	} else {
5686 		feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
5687 			data->smu_features[GNLD_ULV].smu_feature_bitmap : 0;
5688 		feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
5689 			data->smu_features[GNLD_DS_GFXCLK].smu_feature_bitmap : 0;
5690 		feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
5691 			data->smu_features[GNLD_DS_SOCCLK].smu_feature_bitmap : 0;
5692 		feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
5693 			data->smu_features[GNLD_DS_LCLK].smu_feature_bitmap : 0;
5694 		feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
5695 			data->smu_features[GNLD_DS_DCEFCLK].smu_feature_bitmap : 0;
5696 	}
5697 
5698 	if (feature_mask)
5699 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
5700 				!disable, feature_mask),
5701 				"enable/disable power features for compute performance Failed!",
5702 				return -EINVAL);
5703 
5704 	if (disable) {
5705 		data->smu_features[GNLD_ULV].enabled = false;
5706 		data->smu_features[GNLD_DS_GFXCLK].enabled = false;
5707 		data->smu_features[GNLD_DS_SOCCLK].enabled = false;
5708 		data->smu_features[GNLD_DS_LCLK].enabled = false;
5709 		data->smu_features[GNLD_DS_DCEFCLK].enabled = false;
5710 	} else {
5711 		data->smu_features[GNLD_ULV].enabled = true;
5712 		data->smu_features[GNLD_DS_GFXCLK].enabled = true;
5713 		data->smu_features[GNLD_DS_SOCCLK].enabled = true;
5714 		data->smu_features[GNLD_DS_LCLK].enabled = true;
5715 		data->smu_features[GNLD_DS_DCEFCLK].enabled = true;
5716 	}
5717 
5718 	return 0;
5719 
5720 }
5721 
5722 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
5723 	.backend_init = vega10_hwmgr_backend_init,
5724 	.backend_fini = vega10_hwmgr_backend_fini,
5725 	.asic_setup = vega10_setup_asic_task,
5726 	.dynamic_state_management_enable = vega10_enable_dpm_tasks,
5727 	.dynamic_state_management_disable = vega10_disable_dpm_tasks,
5728 	.get_num_of_pp_table_entries =
5729 			vega10_get_number_of_powerplay_table_entries,
5730 	.get_power_state_size = vega10_get_power_state_size,
5731 	.get_pp_table_entry = vega10_get_pp_table_entry,
5732 	.patch_boot_state = vega10_patch_boot_state,
5733 	.apply_state_adjust_rules = vega10_apply_state_adjust_rules,
5734 	.power_state_set = vega10_set_power_state_tasks,
5735 	.get_sclk = vega10_dpm_get_sclk,
5736 	.get_mclk = vega10_dpm_get_mclk,
5737 	.notify_smc_display_config_after_ps_adjustment =
5738 			vega10_notify_smc_display_config_after_ps_adjustment,
5739 	.force_dpm_level = vega10_dpm_force_dpm_level,
5740 	.stop_thermal_controller = vega10_thermal_stop_thermal_controller,
5741 	.get_fan_speed_info = vega10_fan_ctrl_get_fan_speed_info,
5742 	.get_fan_speed_pwm = vega10_fan_ctrl_get_fan_speed_pwm,
5743 	.set_fan_speed_pwm = vega10_fan_ctrl_set_fan_speed_pwm,
5744 	.reset_fan_speed_to_default =
5745 			vega10_fan_ctrl_reset_fan_speed_to_default,
5746 	.get_fan_speed_rpm = vega10_fan_ctrl_get_fan_speed_rpm,
5747 	.set_fan_speed_rpm = vega10_fan_ctrl_set_fan_speed_rpm,
5748 	.uninitialize_thermal_controller =
5749 			vega10_thermal_ctrl_uninitialize_thermal_controller,
5750 	.set_fan_control_mode = vega10_set_fan_control_mode,
5751 	.get_fan_control_mode = vega10_get_fan_control_mode,
5752 	.read_sensor = vega10_read_sensor,
5753 	.get_dal_power_level = vega10_get_dal_power_level,
5754 	.get_clock_by_type_with_latency = vega10_get_clock_by_type_with_latency,
5755 	.get_clock_by_type_with_voltage = vega10_get_clock_by_type_with_voltage,
5756 	.set_watermarks_for_clocks_ranges = vega10_set_watermarks_for_clocks_ranges,
5757 	.display_clock_voltage_request = vega10_display_clock_voltage_request,
5758 	.force_clock_level = vega10_force_clock_level,
5759 	.emit_clock_levels = vega10_emit_clock_levels,
5760 	.print_clock_levels = vega10_print_clock_levels,
5761 	.display_config_changed = vega10_display_configuration_changed_task,
5762 	.powergate_uvd = vega10_power_gate_uvd,
5763 	.powergate_vce = vega10_power_gate_vce,
5764 	.check_states_equal = vega10_check_states_equal,
5765 	.check_smc_update_required_for_display_configuration =
5766 			vega10_check_smc_update_required_for_display_configuration,
5767 	.power_off_asic = vega10_power_off_asic,
5768 	.disable_smc_firmware_ctf = vega10_thermal_disable_alert,
5769 	.get_sclk_od = vega10_get_sclk_od,
5770 	.set_sclk_od = vega10_set_sclk_od,
5771 	.get_mclk_od = vega10_get_mclk_od,
5772 	.set_mclk_od = vega10_set_mclk_od,
5773 	.avfs_control = vega10_avfs_enable,
5774 	.notify_cac_buffer_info = vega10_notify_cac_buffer_info,
5775 	.get_thermal_temperature_range = vega10_get_thermal_temperature_range,
5776 	.register_irq_handlers = smu9_register_irq_handlers,
5777 	.start_thermal_controller = vega10_start_thermal_controller,
5778 	.get_power_profile_mode = vega10_get_power_profile_mode,
5779 	.set_power_profile_mode = vega10_set_power_profile_mode,
5780 	.set_power_limit = vega10_set_power_limit,
5781 	.odn_edit_dpm_table = vega10_odn_edit_dpm_table,
5782 	.get_performance_level = vega10_get_performance_level,
5783 	.get_asic_baco_capability = smu9_baco_get_capability,
5784 	.get_asic_baco_state = smu9_baco_get_state,
5785 	.set_asic_baco_state = vega10_baco_set_state,
5786 	.enable_mgpu_fan_boost = vega10_enable_mgpu_fan_boost,
5787 	.get_ppfeature_status = vega10_get_ppfeature_status,
5788 	.set_ppfeature_status = vega10_set_ppfeature_status,
5789 	.set_mp1_state = vega10_set_mp1_state,
5790 	.disable_power_features_for_compute_performance =
5791 			vega10_disable_power_features_for_compute_performance,
5792 };
5793 
5794 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
5795 {
5796 	struct amdgpu_device *adev = hwmgr->adev;
5797 
5798 	hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
5799 	hwmgr->pptable_func = &vega10_pptable_funcs;
5800 	if (amdgpu_passthrough(adev))
5801 		return vega10_baco_set_cap(hwmgr);
5802 
5803 	return 0;
5804 }
5805