1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include "atom-types.h" 28 #include "atombios.h" 29 #include "processpptables.h" 30 #include "cgs_common.h" 31 #include "smu/smu_8_0_d.h" 32 #include "smu8_fusion.h" 33 #include "smu/smu_8_0_sh_mask.h" 34 #include "smumgr.h" 35 #include "hwmgr.h" 36 #include "hardwaremanager.h" 37 #include "cz_ppsmc.h" 38 #include "smu8_hwmgr.h" 39 #include "power_state.h" 40 #include "pp_thermal.h" 41 42 #define ixSMUSVI_NB_CURRENTVID 0xD8230044 43 #define CURRENT_NB_VID_MASK 0xff000000 44 #define CURRENT_NB_VID__SHIFT 24 45 #define ixSMUSVI_GFX_CURRENTVID 0xD8230048 46 #define CURRENT_GFX_VID_MASK 0xff000000 47 #define CURRENT_GFX_VID__SHIFT 24 48 49 static const unsigned long smu8_magic = (unsigned long) PHM_Cz_Magic; 50 51 static struct smu8_power_state *cast_smu8_power_state(struct pp_hw_power_state *hw_ps) 52 { 53 if (smu8_magic != hw_ps->magic) 54 return NULL; 55 56 return (struct smu8_power_state *)hw_ps; 57 } 58 59 static const struct smu8_power_state *cast_const_smu8_power_state( 60 const struct pp_hw_power_state *hw_ps) 61 { 62 if (smu8_magic != hw_ps->magic) 63 return NULL; 64 65 return (struct smu8_power_state *)hw_ps; 66 } 67 68 static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr, 69 uint32_t clock, uint32_t msg) 70 { 71 int i = 0; 72 struct phm_vce_clock_voltage_dependency_table *ptable = 73 hwmgr->dyn_state.vce_clock_voltage_dependency_table; 74 75 switch (msg) { 76 case PPSMC_MSG_SetEclkSoftMin: 77 case PPSMC_MSG_SetEclkHardMin: 78 for (i = 0; i < (int)ptable->count; i++) { 79 if (clock <= ptable->entries[i].ecclk) 80 break; 81 } 82 break; 83 84 case PPSMC_MSG_SetEclkSoftMax: 85 case PPSMC_MSG_SetEclkHardMax: 86 for (i = ptable->count - 1; i >= 0; i--) { 87 if (clock >= ptable->entries[i].ecclk) 88 break; 89 } 90 break; 91 92 default: 93 break; 94 } 95 96 return i; 97 } 98 99 static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr, 100 uint32_t clock, uint32_t msg) 101 { 102 int i = 0; 103 struct phm_clock_voltage_dependency_table *table = 104 hwmgr->dyn_state.vddc_dependency_on_sclk; 105 106 switch (msg) { 107 case PPSMC_MSG_SetSclkSoftMin: 108 case PPSMC_MSG_SetSclkHardMin: 109 for (i = 0; i < (int)table->count; i++) { 110 if (clock <= table->entries[i].clk) 111 break; 112 } 113 break; 114 115 case PPSMC_MSG_SetSclkSoftMax: 116 case PPSMC_MSG_SetSclkHardMax: 117 for (i = table->count - 1; i >= 0; i--) { 118 if (clock >= table->entries[i].clk) 119 break; 120 } 121 break; 122 123 default: 124 break; 125 } 126 return i; 127 } 128 129 static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr, 130 uint32_t clock, uint32_t msg) 131 { 132 int i = 0; 133 struct phm_uvd_clock_voltage_dependency_table *ptable = 134 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; 135 136 switch (msg) { 137 case PPSMC_MSG_SetUvdSoftMin: 138 case PPSMC_MSG_SetUvdHardMin: 139 for (i = 0; i < (int)ptable->count; i++) { 140 if (clock <= ptable->entries[i].vclk) 141 break; 142 } 143 break; 144 145 case PPSMC_MSG_SetUvdSoftMax: 146 case PPSMC_MSG_SetUvdHardMax: 147 for (i = ptable->count - 1; i >= 0; i--) { 148 if (clock >= ptable->entries[i].vclk) 149 break; 150 } 151 break; 152 153 default: 154 break; 155 } 156 157 return i; 158 } 159 160 static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr) 161 { 162 struct smu8_hwmgr *data = hwmgr->backend; 163 164 if (data->max_sclk_level == 0) { 165 smum_send_msg_to_smc(hwmgr, 166 PPSMC_MSG_GetMaxSclkLevel, 167 &data->max_sclk_level); 168 data->max_sclk_level += 1; 169 } 170 171 return data->max_sclk_level; 172 } 173 174 static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) 175 { 176 struct smu8_hwmgr *data = hwmgr->backend; 177 struct amdgpu_device *adev = hwmgr->adev; 178 179 data->gfx_ramp_step = 256*25/100; 180 data->gfx_ramp_delay = 1; /* by default, we delay 1us */ 181 182 data->mgcg_cgtt_local0 = 0x00000000; 183 data->mgcg_cgtt_local1 = 0x00000000; 184 data->clock_slow_down_freq = 25000; 185 data->skip_clock_slow_down = 1; 186 data->enable_nb_ps_policy = 1; /* disable until UNB is ready, Enabled */ 187 data->voltage_drop_in_dce_power_gating = 0; /* disable until fully verified */ 188 data->voting_rights_clients = 0x00C00033; 189 data->static_screen_threshold = 8; 190 data->ddi_power_gating_disabled = 0; 191 data->bapm_enabled = 1; 192 data->voltage_drop_threshold = 0; 193 data->gfx_power_gating_threshold = 500; 194 data->vce_slow_sclk_threshold = 20000; 195 data->dce_slow_sclk_threshold = 30000; 196 data->disable_driver_thermal_policy = 1; 197 data->disable_nb_ps3_in_battery = 0; 198 199 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 200 PHM_PlatformCaps_ABM); 201 202 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 203 PHM_PlatformCaps_NonABMSupportInPPLib); 204 205 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 206 PHM_PlatformCaps_DynamicM3Arbiter); 207 208 data->override_dynamic_mgpg = 1; 209 210 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 211 PHM_PlatformCaps_DynamicPatchPowerState); 212 213 data->thermal_auto_throttling_treshold = 0; 214 data->tdr_clock = 0; 215 data->disable_gfx_power_gating_in_uvd = 0; 216 217 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 218 PHM_PlatformCaps_DynamicUVDState); 219 220 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 221 PHM_PlatformCaps_UVDDPM); 222 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 223 PHM_PlatformCaps_VCEDPM); 224 225 data->cc6_settings.cpu_cc6_disable = false; 226 data->cc6_settings.cpu_pstate_disable = false; 227 data->cc6_settings.nb_pstate_switch_disable = false; 228 data->cc6_settings.cpu_pstate_separation_time = 0; 229 230 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 231 PHM_PlatformCaps_DisableVoltageIsland); 232 233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 234 PHM_PlatformCaps_UVDPowerGating); 235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 236 PHM_PlatformCaps_VCEPowerGating); 237 238 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 239 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 240 PHM_PlatformCaps_UVDPowerGating); 241 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 242 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 243 PHM_PlatformCaps_VCEPowerGating); 244 245 246 return 0; 247 } 248 249 /* convert form 8bit vid to real voltage in mV*4 */ 250 static uint32_t smu8_convert_8Bit_index_to_voltage( 251 struct pp_hwmgr *hwmgr, uint16_t voltage) 252 { 253 return 6200 - (voltage * 25); 254 } 255 256 static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, 257 struct phm_clock_and_voltage_limits *table) 258 { 259 struct smu8_hwmgr *data = hwmgr->backend; 260 struct smu8_sys_info *sys_info = &data->sys_info; 261 struct phm_clock_voltage_dependency_table *dep_table = 262 hwmgr->dyn_state.vddc_dependency_on_sclk; 263 264 if (dep_table->count > 0) { 265 table->sclk = dep_table->entries[dep_table->count-1].clk; 266 table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr, 267 (uint16_t)dep_table->entries[dep_table->count-1].v); 268 } 269 table->mclk = sys_info->nbp_memory_clock[0]; 270 return 0; 271 } 272 273 static int smu8_init_dynamic_state_adjustment_rule_settings( 274 struct pp_hwmgr *hwmgr, 275 ATOM_CLK_VOLT_CAPABILITY *disp_voltage_table) 276 { 277 struct phm_clock_voltage_dependency_table *table_clk_vlt; 278 279 table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, 8), 280 GFP_KERNEL); 281 282 if (NULL == table_clk_vlt) { 283 pr_err("Can not allocate memory!\n"); 284 return -ENOMEM; 285 } 286 287 table_clk_vlt->count = 8; 288 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; 289 table_clk_vlt->entries[0].v = 0; 290 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; 291 table_clk_vlt->entries[1].v = 1; 292 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; 293 table_clk_vlt->entries[2].v = 2; 294 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; 295 table_clk_vlt->entries[3].v = 3; 296 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; 297 table_clk_vlt->entries[4].v = 4; 298 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; 299 table_clk_vlt->entries[5].v = 5; 300 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; 301 table_clk_vlt->entries[6].v = 6; 302 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; 303 table_clk_vlt->entries[7].v = 7; 304 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; 305 306 return 0; 307 } 308 309 static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr) 310 { 311 struct smu8_hwmgr *data = hwmgr->backend; 312 ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *info = NULL; 313 uint32_t i; 314 int result = 0; 315 uint8_t frev, crev; 316 uint16_t size; 317 318 info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev, 319 GetIndexIntoMasterTable(DATA, IntegratedSystemInfo), 320 &size, &frev, &crev); 321 322 if (info == NULL) { 323 pr_err("Could not retrieve the Integrated System Info Table!\n"); 324 return -EINVAL; 325 } 326 327 if (crev != 9) { 328 pr_err("Unsupported IGP table: %d %d\n", frev, crev); 329 return -EINVAL; 330 } 331 332 data->sys_info.bootup_uma_clock = 333 le32_to_cpu(info->ulBootUpUMAClock); 334 335 data->sys_info.bootup_engine_clock = 336 le32_to_cpu(info->ulBootUpEngineClock); 337 338 data->sys_info.dentist_vco_freq = 339 le32_to_cpu(info->ulDentistVCOFreq); 340 341 data->sys_info.system_config = 342 le32_to_cpu(info->ulSystemConfig); 343 344 data->sys_info.bootup_nb_voltage_index = 345 le16_to_cpu(info->usBootUpNBVoltage); 346 347 data->sys_info.htc_hyst_lmt = 348 (info->ucHtcHystLmt == 0) ? 5 : info->ucHtcHystLmt; 349 350 data->sys_info.htc_tmp_lmt = 351 (info->ucHtcTmpLmt == 0) ? 203 : info->ucHtcTmpLmt; 352 353 if (data->sys_info.htc_tmp_lmt <= 354 data->sys_info.htc_hyst_lmt) { 355 pr_err("The htcTmpLmt should be larger than htcHystLmt.\n"); 356 return -EINVAL; 357 } 358 359 data->sys_info.nb_dpm_enable = 360 data->enable_nb_ps_policy && 361 (le32_to_cpu(info->ulSystemConfig) >> 3 & 0x1); 362 363 for (i = 0; i < SMU8_NUM_NBPSTATES; i++) { 364 if (i < SMU8_NUM_NBPMEMORYCLOCK) { 365 data->sys_info.nbp_memory_clock[i] = 366 le32_to_cpu(info->ulNbpStateMemclkFreq[i]); 367 } 368 data->sys_info.nbp_n_clock[i] = 369 le32_to_cpu(info->ulNbpStateNClkFreq[i]); 370 } 371 372 for (i = 0; i < MAX_DISPLAY_CLOCK_LEVEL; i++) { 373 data->sys_info.display_clock[i] = 374 le32_to_cpu(info->sDispClkVoltageMapping[i].ulMaximumSupportedCLK); 375 } 376 377 /* Here use 4 levels, make sure not exceed */ 378 for (i = 0; i < SMU8_NUM_NBPSTATES; i++) { 379 data->sys_info.nbp_voltage_index[i] = 380 le16_to_cpu(info->usNBPStateVoltage[i]); 381 } 382 383 if (!data->sys_info.nb_dpm_enable) { 384 for (i = 1; i < SMU8_NUM_NBPSTATES; i++) { 385 if (i < SMU8_NUM_NBPMEMORYCLOCK) { 386 data->sys_info.nbp_memory_clock[i] = 387 data->sys_info.nbp_memory_clock[0]; 388 } 389 data->sys_info.nbp_n_clock[i] = 390 data->sys_info.nbp_n_clock[0]; 391 data->sys_info.nbp_voltage_index[i] = 392 data->sys_info.nbp_voltage_index[0]; 393 } 394 } 395 396 if (le32_to_cpu(info->ulGPUCapInfo) & 397 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) { 398 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 399 PHM_PlatformCaps_EnableDFSBypass); 400 } 401 402 data->sys_info.uma_channel_number = info->ucUMAChannelNumber; 403 404 smu8_construct_max_power_limits_table (hwmgr, 405 &hwmgr->dyn_state.max_clock_voltage_on_ac); 406 407 smu8_init_dynamic_state_adjustment_rule_settings(hwmgr, 408 &info->sDISPCLK_Voltage[0]); 409 410 return result; 411 } 412 413 static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr) 414 { 415 struct smu8_hwmgr *data = hwmgr->backend; 416 417 data->boot_power_level.engineClock = 418 data->sys_info.bootup_engine_clock; 419 420 data->boot_power_level.vddcIndex = 421 (uint8_t)data->sys_info.bootup_nb_voltage_index; 422 423 data->boot_power_level.dsDividerIndex = 0; 424 data->boot_power_level.ssDividerIndex = 0; 425 data->boot_power_level.allowGnbSlow = 1; 426 data->boot_power_level.forceNBPstate = 0; 427 data->boot_power_level.hysteresis_up = 0; 428 data->boot_power_level.numSIMDToPowerDown = 0; 429 data->boot_power_level.display_wm = 0; 430 data->boot_power_level.vce_wm = 0; 431 432 return 0; 433 } 434 435 static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr) 436 { 437 struct SMU8_Fusion_ClkTable *clock_table; 438 int ret; 439 uint32_t i; 440 void *table = NULL; 441 pp_atomctrl_clock_dividers_kong dividers; 442 443 struct phm_clock_voltage_dependency_table *vddc_table = 444 hwmgr->dyn_state.vddc_dependency_on_sclk; 445 struct phm_clock_voltage_dependency_table *vdd_gfx_table = 446 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; 447 struct phm_acp_clock_voltage_dependency_table *acp_table = 448 hwmgr->dyn_state.acp_clock_voltage_dependency_table; 449 struct phm_uvd_clock_voltage_dependency_table *uvd_table = 450 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; 451 struct phm_vce_clock_voltage_dependency_table *vce_table = 452 hwmgr->dyn_state.vce_clock_voltage_dependency_table; 453 454 if (!hwmgr->need_pp_table_upload) 455 return 0; 456 457 ret = smum_download_powerplay_table(hwmgr, &table); 458 459 PP_ASSERT_WITH_CODE((0 == ret && NULL != table), 460 "Fail to get clock table from SMU!", return -EINVAL;); 461 462 clock_table = (struct SMU8_Fusion_ClkTable *)table; 463 464 /* patch clock table */ 465 PP_ASSERT_WITH_CODE((vddc_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), 466 "Dependency table entry exceeds max limit!", return -EINVAL;); 467 PP_ASSERT_WITH_CODE((vdd_gfx_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), 468 "Dependency table entry exceeds max limit!", return -EINVAL;); 469 PP_ASSERT_WITH_CODE((acp_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), 470 "Dependency table entry exceeds max limit!", return -EINVAL;); 471 PP_ASSERT_WITH_CODE((uvd_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), 472 "Dependency table entry exceeds max limit!", return -EINVAL;); 473 PP_ASSERT_WITH_CODE((vce_table->count <= SMU8_MAX_HARDWARE_POWERLEVELS), 474 "Dependency table entry exceeds max limit!", return -EINVAL;); 475 476 for (i = 0; i < SMU8_MAX_HARDWARE_POWERLEVELS; i++) { 477 478 /* vddc_sclk */ 479 clock_table->SclkBreakdownTable.ClkLevel[i].GnbVid = 480 (i < vddc_table->count) ? (uint8_t)vddc_table->entries[i].v : 0; 481 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency = 482 (i < vddc_table->count) ? vddc_table->entries[i].clk : 0; 483 484 atomctrl_get_engine_pll_dividers_kong(hwmgr, 485 clock_table->SclkBreakdownTable.ClkLevel[i].Frequency, 486 ÷rs); 487 488 clock_table->SclkBreakdownTable.ClkLevel[i].DfsDid = 489 (uint8_t)dividers.pll_post_divider; 490 491 /* vddgfx_sclk */ 492 clock_table->SclkBreakdownTable.ClkLevel[i].GfxVid = 493 (i < vdd_gfx_table->count) ? (uint8_t)vdd_gfx_table->entries[i].v : 0; 494 495 /* acp breakdown */ 496 clock_table->AclkBreakdownTable.ClkLevel[i].GfxVid = 497 (i < acp_table->count) ? (uint8_t)acp_table->entries[i].v : 0; 498 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency = 499 (i < acp_table->count) ? acp_table->entries[i].acpclk : 0; 500 501 atomctrl_get_engine_pll_dividers_kong(hwmgr, 502 clock_table->AclkBreakdownTable.ClkLevel[i].Frequency, 503 ÷rs); 504 505 clock_table->AclkBreakdownTable.ClkLevel[i].DfsDid = 506 (uint8_t)dividers.pll_post_divider; 507 508 509 /* uvd breakdown */ 510 clock_table->VclkBreakdownTable.ClkLevel[i].GfxVid = 511 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; 512 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency = 513 (i < uvd_table->count) ? uvd_table->entries[i].vclk : 0; 514 515 atomctrl_get_engine_pll_dividers_kong(hwmgr, 516 clock_table->VclkBreakdownTable.ClkLevel[i].Frequency, 517 ÷rs); 518 519 clock_table->VclkBreakdownTable.ClkLevel[i].DfsDid = 520 (uint8_t)dividers.pll_post_divider; 521 522 clock_table->DclkBreakdownTable.ClkLevel[i].GfxVid = 523 (i < uvd_table->count) ? (uint8_t)uvd_table->entries[i].v : 0; 524 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency = 525 (i < uvd_table->count) ? uvd_table->entries[i].dclk : 0; 526 527 atomctrl_get_engine_pll_dividers_kong(hwmgr, 528 clock_table->DclkBreakdownTable.ClkLevel[i].Frequency, 529 ÷rs); 530 531 clock_table->DclkBreakdownTable.ClkLevel[i].DfsDid = 532 (uint8_t)dividers.pll_post_divider; 533 534 /* vce breakdown */ 535 clock_table->EclkBreakdownTable.ClkLevel[i].GfxVid = 536 (i < vce_table->count) ? (uint8_t)vce_table->entries[i].v : 0; 537 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency = 538 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; 539 540 541 atomctrl_get_engine_pll_dividers_kong(hwmgr, 542 clock_table->EclkBreakdownTable.ClkLevel[i].Frequency, 543 ÷rs); 544 545 clock_table->EclkBreakdownTable.ClkLevel[i].DfsDid = 546 (uint8_t)dividers.pll_post_divider; 547 548 } 549 ret = smum_upload_powerplay_table(hwmgr); 550 551 return ret; 552 } 553 554 static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr) 555 { 556 struct smu8_hwmgr *data = hwmgr->backend; 557 struct phm_clock_voltage_dependency_table *table = 558 hwmgr->dyn_state.vddc_dependency_on_sclk; 559 unsigned long clock = 0, level; 560 561 if (NULL == table || table->count <= 0) 562 return -EINVAL; 563 564 data->sclk_dpm.soft_min_clk = table->entries[0].clk; 565 data->sclk_dpm.hard_min_clk = table->entries[0].clk; 566 567 level = smu8_get_max_sclk_level(hwmgr) - 1; 568 569 if (level < table->count) 570 clock = table->entries[level].clk; 571 else 572 clock = table->entries[table->count - 1].clk; 573 574 data->sclk_dpm.soft_max_clk = clock; 575 data->sclk_dpm.hard_max_clk = clock; 576 577 return 0; 578 } 579 580 static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr) 581 { 582 struct smu8_hwmgr *data = hwmgr->backend; 583 struct phm_uvd_clock_voltage_dependency_table *table = 584 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; 585 unsigned long clock = 0; 586 uint32_t level; 587 588 if (NULL == table || table->count <= 0) 589 return -EINVAL; 590 591 data->uvd_dpm.soft_min_clk = 0; 592 data->uvd_dpm.hard_min_clk = 0; 593 594 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel, &level); 595 596 if (level < table->count) 597 clock = table->entries[level].vclk; 598 else 599 clock = table->entries[table->count - 1].vclk; 600 601 data->uvd_dpm.soft_max_clk = clock; 602 data->uvd_dpm.hard_max_clk = clock; 603 604 return 0; 605 } 606 607 static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr) 608 { 609 struct smu8_hwmgr *data = hwmgr->backend; 610 struct phm_vce_clock_voltage_dependency_table *table = 611 hwmgr->dyn_state.vce_clock_voltage_dependency_table; 612 unsigned long clock = 0; 613 uint32_t level; 614 615 if (NULL == table || table->count <= 0) 616 return -EINVAL; 617 618 data->vce_dpm.soft_min_clk = 0; 619 data->vce_dpm.hard_min_clk = 0; 620 621 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel, &level); 622 623 if (level < table->count) 624 clock = table->entries[level].ecclk; 625 else 626 clock = table->entries[table->count - 1].ecclk; 627 628 data->vce_dpm.soft_max_clk = clock; 629 data->vce_dpm.hard_max_clk = clock; 630 631 return 0; 632 } 633 634 static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr) 635 { 636 struct smu8_hwmgr *data = hwmgr->backend; 637 struct phm_acp_clock_voltage_dependency_table *table = 638 hwmgr->dyn_state.acp_clock_voltage_dependency_table; 639 unsigned long clock = 0; 640 uint32_t level; 641 642 if (NULL == table || table->count <= 0) 643 return -EINVAL; 644 645 data->acp_dpm.soft_min_clk = 0; 646 data->acp_dpm.hard_min_clk = 0; 647 648 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel, &level); 649 650 if (level < table->count) 651 clock = table->entries[level].acpclk; 652 else 653 clock = table->entries[table->count - 1].acpclk; 654 655 data->acp_dpm.soft_max_clk = clock; 656 data->acp_dpm.hard_max_clk = clock; 657 return 0; 658 } 659 660 static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr) 661 { 662 struct smu8_hwmgr *data = hwmgr->backend; 663 664 data->uvd_power_gated = false; 665 data->vce_power_gated = false; 666 data->samu_power_gated = false; 667 #ifdef CONFIG_DRM_AMD_ACP 668 data->acp_power_gated = false; 669 #else 670 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); 671 data->acp_power_gated = true; 672 #endif 673 674 } 675 676 static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr) 677 { 678 struct smu8_hwmgr *data = hwmgr->backend; 679 680 data->low_sclk_interrupt_threshold = 0; 681 } 682 683 static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr) 684 { 685 struct smu8_hwmgr *data = hwmgr->backend; 686 struct phm_clock_voltage_dependency_table *table = 687 hwmgr->dyn_state.vddc_dependency_on_sclk; 688 689 unsigned long clock = 0; 690 unsigned long level; 691 unsigned long stable_pstate_sclk; 692 unsigned long percentage; 693 694 data->sclk_dpm.soft_min_clk = table->entries[0].clk; 695 level = smu8_get_max_sclk_level(hwmgr) - 1; 696 697 if (level < table->count) 698 data->sclk_dpm.soft_max_clk = table->entries[level].clk; 699 else 700 data->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk; 701 702 clock = hwmgr->display_config->min_core_set_clock; 703 if (clock == 0) 704 pr_debug("min_core_set_clock not set\n"); 705 706 if (data->sclk_dpm.hard_min_clk != clock) { 707 data->sclk_dpm.hard_min_clk = clock; 708 709 smum_send_msg_to_smc_with_parameter(hwmgr, 710 PPSMC_MSG_SetSclkHardMin, 711 smu8_get_sclk_level(hwmgr, 712 data->sclk_dpm.hard_min_clk, 713 PPSMC_MSG_SetSclkHardMin), 714 NULL); 715 } 716 717 clock = data->sclk_dpm.soft_min_clk; 718 719 /* update minimum clocks for Stable P-State feature */ 720 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 721 PHM_PlatformCaps_StablePState)) { 722 percentage = 75; 723 /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table */ 724 stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 725 percentage) / 100; 726 727 if (clock < stable_pstate_sclk) 728 clock = stable_pstate_sclk; 729 } 730 731 if (data->sclk_dpm.soft_min_clk != clock) { 732 data->sclk_dpm.soft_min_clk = clock; 733 smum_send_msg_to_smc_with_parameter(hwmgr, 734 PPSMC_MSG_SetSclkSoftMin, 735 smu8_get_sclk_level(hwmgr, 736 data->sclk_dpm.soft_min_clk, 737 PPSMC_MSG_SetSclkSoftMin), 738 NULL); 739 } 740 741 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 742 PHM_PlatformCaps_StablePState) && 743 data->sclk_dpm.soft_max_clk != clock) { 744 data->sclk_dpm.soft_max_clk = clock; 745 smum_send_msg_to_smc_with_parameter(hwmgr, 746 PPSMC_MSG_SetSclkSoftMax, 747 smu8_get_sclk_level(hwmgr, 748 data->sclk_dpm.soft_max_clk, 749 PPSMC_MSG_SetSclkSoftMax), 750 NULL); 751 } 752 753 return 0; 754 } 755 756 static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) 757 { 758 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 759 PHM_PlatformCaps_SclkDeepSleep)) { 760 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; 761 if (clks == 0) 762 clks = SMU8_MIN_DEEP_SLEEP_SCLK; 763 764 PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks); 765 766 smum_send_msg_to_smc_with_parameter(hwmgr, 767 PPSMC_MSG_SetMinDeepSleepSclk, 768 clks, 769 NULL); 770 } 771 772 return 0; 773 } 774 775 static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr) 776 { 777 struct smu8_hwmgr *data = 778 hwmgr->backend; 779 780 smum_send_msg_to_smc_with_parameter(hwmgr, 781 PPSMC_MSG_SetWatermarkFrequency, 782 data->sclk_dpm.soft_max_clk, 783 NULL); 784 785 return 0; 786 } 787 788 static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock) 789 { 790 struct smu8_hwmgr *hw_data = hwmgr->backend; 791 792 if (hw_data->is_nb_dpm_enabled) { 793 if (enable) { 794 PP_DBG_LOG("enable Low Memory PState.\n"); 795 796 return smum_send_msg_to_smc_with_parameter(hwmgr, 797 PPSMC_MSG_EnableLowMemoryPstate, 798 (lock ? 1 : 0), 799 NULL); 800 } else { 801 PP_DBG_LOG("disable Low Memory PState.\n"); 802 803 return smum_send_msg_to_smc_with_parameter(hwmgr, 804 PPSMC_MSG_DisableLowMemoryPstate, 805 (lock ? 1 : 0), 806 NULL); 807 } 808 } 809 810 return 0; 811 } 812 813 static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr) 814 { 815 int ret = 0; 816 817 struct smu8_hwmgr *data = hwmgr->backend; 818 unsigned long dpm_features = 0; 819 820 if (data->is_nb_dpm_enabled) { 821 smu8_nbdpm_pstate_enable_disable(hwmgr, true, true); 822 dpm_features |= NB_DPM_MASK; 823 ret = smum_send_msg_to_smc_with_parameter( 824 hwmgr, 825 PPSMC_MSG_DisableAllSmuFeatures, 826 dpm_features, 827 NULL); 828 if (ret == 0) 829 data->is_nb_dpm_enabled = false; 830 } 831 832 return ret; 833 } 834 835 static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr) 836 { 837 int ret = 0; 838 839 struct smu8_hwmgr *data = hwmgr->backend; 840 unsigned long dpm_features = 0; 841 842 if (!data->is_nb_dpm_enabled) { 843 PP_DBG_LOG("enabling ALL SMU features.\n"); 844 dpm_features |= NB_DPM_MASK; 845 ret = smum_send_msg_to_smc_with_parameter( 846 hwmgr, 847 PPSMC_MSG_EnableAllSmuFeatures, 848 dpm_features, 849 NULL); 850 if (ret == 0) 851 data->is_nb_dpm_enabled = true; 852 } 853 854 return ret; 855 } 856 857 static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input) 858 { 859 bool disable_switch; 860 bool enable_low_mem_state; 861 struct smu8_hwmgr *hw_data = hwmgr->backend; 862 const struct phm_set_power_state_input *states = (struct phm_set_power_state_input *)input; 863 const struct smu8_power_state *pnew_state = cast_const_smu8_power_state(states->pnew_state); 864 865 if (hw_data->sys_info.nb_dpm_enable) { 866 disable_switch = hw_data->cc6_settings.nb_pstate_switch_disable ? true : false; 867 enable_low_mem_state = hw_data->cc6_settings.nb_pstate_switch_disable ? false : true; 868 869 if (pnew_state->action == FORCE_HIGH) 870 smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch); 871 else if (pnew_state->action == CANCEL_FORCE_HIGH) 872 smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch); 873 else 874 smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch); 875 } 876 return 0; 877 } 878 879 static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 880 { 881 int ret = 0; 882 883 smu8_update_sclk_limit(hwmgr); 884 smu8_set_deep_sleep_sclk_threshold(hwmgr); 885 smu8_set_watermark_threshold(hwmgr); 886 ret = smu8_enable_nb_dpm(hwmgr); 887 if (ret) 888 return ret; 889 smu8_update_low_mem_pstate(hwmgr, input); 890 891 return 0; 892 } 893 894 895 static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr) 896 { 897 int ret; 898 899 ret = smu8_upload_pptable_to_smu(hwmgr); 900 if (ret) 901 return ret; 902 ret = smu8_init_sclk_limit(hwmgr); 903 if (ret) 904 return ret; 905 ret = smu8_init_uvd_limit(hwmgr); 906 if (ret) 907 return ret; 908 ret = smu8_init_vce_limit(hwmgr); 909 if (ret) 910 return ret; 911 ret = smu8_init_acp_limit(hwmgr); 912 if (ret) 913 return ret; 914 915 smu8_init_power_gate_state(hwmgr); 916 smu8_init_sclk_threshold(hwmgr); 917 918 return 0; 919 } 920 921 static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr) 922 { 923 struct smu8_hwmgr *hw_data = hwmgr->backend; 924 925 hw_data->disp_clk_bypass_pending = false; 926 hw_data->disp_clk_bypass = false; 927 } 928 929 static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr) 930 { 931 struct smu8_hwmgr *hw_data = hwmgr->backend; 932 933 hw_data->is_nb_dpm_enabled = false; 934 } 935 936 static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr) 937 { 938 struct smu8_hwmgr *hw_data = hwmgr->backend; 939 940 hw_data->cc6_settings.cc6_setting_changed = false; 941 hw_data->cc6_settings.cpu_pstate_separation_time = 0; 942 hw_data->cc6_settings.cpu_cc6_disable = false; 943 hw_data->cc6_settings.cpu_pstate_disable = false; 944 } 945 946 static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr) 947 { 948 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 949 ixCG_FREQ_TRAN_VOTING_0, 950 SMU8_VOTINGRIGHTSCLIENTS_DFLT0); 951 } 952 953 static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr) 954 { 955 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 956 ixCG_FREQ_TRAN_VOTING_0, 0); 957 } 958 959 static int smu8_start_dpm(struct pp_hwmgr *hwmgr) 960 { 961 struct smu8_hwmgr *data = hwmgr->backend; 962 963 data->dpm_flags |= DPMFlags_SCLK_Enabled; 964 965 return smum_send_msg_to_smc_with_parameter(hwmgr, 966 PPSMC_MSG_EnableAllSmuFeatures, 967 SCLK_DPM_MASK, 968 NULL); 969 } 970 971 static int smu8_stop_dpm(struct pp_hwmgr *hwmgr) 972 { 973 int ret = 0; 974 struct smu8_hwmgr *data = hwmgr->backend; 975 unsigned long dpm_features = 0; 976 977 if (data->dpm_flags & DPMFlags_SCLK_Enabled) { 978 dpm_features |= SCLK_DPM_MASK; 979 data->dpm_flags &= ~DPMFlags_SCLK_Enabled; 980 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 981 PPSMC_MSG_DisableAllSmuFeatures, 982 dpm_features, 983 NULL); 984 } 985 return ret; 986 } 987 988 static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr) 989 { 990 struct smu8_hwmgr *data = hwmgr->backend; 991 992 data->sclk_dpm.soft_min_clk = data->sys_info.bootup_engine_clock; 993 data->sclk_dpm.soft_max_clk = data->sys_info.bootup_engine_clock; 994 995 smum_send_msg_to_smc_with_parameter(hwmgr, 996 PPSMC_MSG_SetSclkSoftMin, 997 smu8_get_sclk_level(hwmgr, 998 data->sclk_dpm.soft_min_clk, 999 PPSMC_MSG_SetSclkSoftMin), 1000 NULL); 1001 1002 smum_send_msg_to_smc_with_parameter(hwmgr, 1003 PPSMC_MSG_SetSclkSoftMax, 1004 smu8_get_sclk_level(hwmgr, 1005 data->sclk_dpm.soft_max_clk, 1006 PPSMC_MSG_SetSclkSoftMax), 1007 NULL); 1008 1009 return 0; 1010 } 1011 1012 static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr) 1013 { 1014 struct smu8_hwmgr *data = hwmgr->backend; 1015 1016 data->acp_boot_level = 0xff; 1017 } 1018 1019 static void smu8_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1020 { 1021 struct phm_clock_voltage_dependency_table *table = 1022 hwmgr->dyn_state.vddc_dependency_on_sclk; 1023 1024 hwmgr->pstate_sclk = table->entries[0].clk / 100; 1025 hwmgr->pstate_mclk = 0; 1026 1027 hwmgr->pstate_sclk_peak = table->entries[table->count - 1].clk / 100; 1028 hwmgr->pstate_mclk_peak = 0; 1029 } 1030 1031 static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1032 { 1033 smu8_program_voting_clients(hwmgr); 1034 if (smu8_start_dpm(hwmgr)) 1035 return -EINVAL; 1036 smu8_program_bootup_state(hwmgr); 1037 smu8_reset_acp_boot_level(hwmgr); 1038 1039 smu8_populate_umdpstate_clocks(hwmgr); 1040 1041 return 0; 1042 } 1043 1044 static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 1045 { 1046 smu8_disable_nb_dpm(hwmgr); 1047 1048 smu8_clear_voting_clients(hwmgr); 1049 if (smu8_stop_dpm(hwmgr)) 1050 return -EINVAL; 1051 1052 return 0; 1053 } 1054 1055 static int smu8_power_off_asic(struct pp_hwmgr *hwmgr) 1056 { 1057 smu8_disable_dpm_tasks(hwmgr); 1058 smu8_power_up_display_clock_sys_pll(hwmgr); 1059 smu8_clear_nb_dpm_flag(hwmgr); 1060 smu8_reset_cc6_data(hwmgr); 1061 return 0; 1062 } 1063 1064 static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 1065 struct pp_power_state *prequest_ps, 1066 const struct pp_power_state *pcurrent_ps) 1067 { 1068 struct smu8_power_state *smu8_ps; 1069 const struct smu8_power_state *smu8_current_ps; 1070 struct smu8_hwmgr *data = hwmgr->backend; 1071 struct PP_Clocks clocks = {0, 0, 0, 0}; 1072 bool force_high; 1073 1074 smu8_ps = cast_smu8_power_state(&prequest_ps->hardware); 1075 smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware); 1076 1077 if (!smu8_ps || !smu8_current_ps) 1078 return -EINVAL; 1079 1080 smu8_ps->need_dfs_bypass = true; 1081 1082 data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); 1083 1084 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? 1085 hwmgr->display_config->min_mem_set_clock : 1086 data->sys_info.nbp_memory_clock[1]; 1087 1088 1089 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) 1090 clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; 1091 1092 force_high = (clocks.memoryClock > data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]) 1093 || (hwmgr->display_config->num_display >= 3); 1094 1095 smu8_ps->action = smu8_current_ps->action; 1096 1097 if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 1098 smu8_nbdpm_pstate_enable_disable(hwmgr, false, false); 1099 else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) 1100 smu8_nbdpm_pstate_enable_disable(hwmgr, false, true); 1101 else if (!force_high && (smu8_ps->action == FORCE_HIGH)) 1102 smu8_ps->action = CANCEL_FORCE_HIGH; 1103 else if (force_high && (smu8_ps->action != FORCE_HIGH)) 1104 smu8_ps->action = FORCE_HIGH; 1105 else 1106 smu8_ps->action = DO_NOTHING; 1107 1108 return 0; 1109 } 1110 1111 static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 1112 { 1113 int result = 0; 1114 struct smu8_hwmgr *data; 1115 1116 data = kzalloc(sizeof(struct smu8_hwmgr), GFP_KERNEL); 1117 if (data == NULL) 1118 return -ENOMEM; 1119 1120 hwmgr->backend = data; 1121 1122 result = smu8_initialize_dpm_defaults(hwmgr); 1123 if (result != 0) { 1124 pr_err("smu8_initialize_dpm_defaults failed\n"); 1125 return result; 1126 } 1127 1128 result = smu8_get_system_info_data(hwmgr); 1129 if (result != 0) { 1130 pr_err("smu8_get_system_info_data failed\n"); 1131 return result; 1132 } 1133 1134 smu8_construct_boot_state(hwmgr); 1135 1136 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = SMU8_MAX_HARDWARE_POWERLEVELS; 1137 1138 return result; 1139 } 1140 1141 static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 1142 { 1143 if (hwmgr != NULL) { 1144 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 1145 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 1146 1147 kfree(hwmgr->backend); 1148 hwmgr->backend = NULL; 1149 } 1150 return 0; 1151 } 1152 1153 static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr) 1154 { 1155 struct smu8_hwmgr *data = hwmgr->backend; 1156 1157 smum_send_msg_to_smc_with_parameter(hwmgr, 1158 PPSMC_MSG_SetSclkSoftMin, 1159 smu8_get_sclk_level(hwmgr, 1160 data->sclk_dpm.soft_max_clk, 1161 PPSMC_MSG_SetSclkSoftMin), 1162 NULL); 1163 1164 smum_send_msg_to_smc_with_parameter(hwmgr, 1165 PPSMC_MSG_SetSclkSoftMax, 1166 smu8_get_sclk_level(hwmgr, 1167 data->sclk_dpm.soft_max_clk, 1168 PPSMC_MSG_SetSclkSoftMax), 1169 NULL); 1170 1171 return 0; 1172 } 1173 1174 static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 1175 { 1176 struct smu8_hwmgr *data = hwmgr->backend; 1177 struct phm_clock_voltage_dependency_table *table = 1178 hwmgr->dyn_state.vddc_dependency_on_sclk; 1179 unsigned long clock = 0, level; 1180 1181 if (NULL == table || table->count <= 0) 1182 return -EINVAL; 1183 1184 data->sclk_dpm.soft_min_clk = table->entries[0].clk; 1185 data->sclk_dpm.hard_min_clk = table->entries[0].clk; 1186 1187 level = smu8_get_max_sclk_level(hwmgr) - 1; 1188 1189 if (level < table->count) 1190 clock = table->entries[level].clk; 1191 else 1192 clock = table->entries[table->count - 1].clk; 1193 1194 data->sclk_dpm.soft_max_clk = clock; 1195 data->sclk_dpm.hard_max_clk = clock; 1196 1197 smum_send_msg_to_smc_with_parameter(hwmgr, 1198 PPSMC_MSG_SetSclkSoftMin, 1199 smu8_get_sclk_level(hwmgr, 1200 data->sclk_dpm.soft_min_clk, 1201 PPSMC_MSG_SetSclkSoftMin), 1202 NULL); 1203 1204 smum_send_msg_to_smc_with_parameter(hwmgr, 1205 PPSMC_MSG_SetSclkSoftMax, 1206 smu8_get_sclk_level(hwmgr, 1207 data->sclk_dpm.soft_max_clk, 1208 PPSMC_MSG_SetSclkSoftMax), 1209 NULL); 1210 1211 return 0; 1212 } 1213 1214 static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr) 1215 { 1216 struct smu8_hwmgr *data = hwmgr->backend; 1217 1218 smum_send_msg_to_smc_with_parameter(hwmgr, 1219 PPSMC_MSG_SetSclkSoftMax, 1220 smu8_get_sclk_level(hwmgr, 1221 data->sclk_dpm.soft_min_clk, 1222 PPSMC_MSG_SetSclkSoftMax), 1223 NULL); 1224 1225 smum_send_msg_to_smc_with_parameter(hwmgr, 1226 PPSMC_MSG_SetSclkSoftMin, 1227 smu8_get_sclk_level(hwmgr, 1228 data->sclk_dpm.soft_min_clk, 1229 PPSMC_MSG_SetSclkSoftMin), 1230 NULL); 1231 1232 return 0; 1233 } 1234 1235 static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 1236 enum amd_dpm_forced_level level) 1237 { 1238 int ret = 0; 1239 1240 switch (level) { 1241 case AMD_DPM_FORCED_LEVEL_HIGH: 1242 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 1243 ret = smu8_phm_force_dpm_highest(hwmgr); 1244 break; 1245 case AMD_DPM_FORCED_LEVEL_LOW: 1246 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 1247 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 1248 ret = smu8_phm_force_dpm_lowest(hwmgr); 1249 break; 1250 case AMD_DPM_FORCED_LEVEL_AUTO: 1251 ret = smu8_phm_unforce_dpm_levels(hwmgr); 1252 break; 1253 case AMD_DPM_FORCED_LEVEL_MANUAL: 1254 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 1255 default: 1256 break; 1257 } 1258 1259 return ret; 1260 } 1261 1262 static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr) 1263 { 1264 if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) 1265 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF, NULL); 1266 return 0; 1267 } 1268 1269 static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr) 1270 { 1271 if (PP_CAP(PHM_PlatformCaps_UVDPowerGating)) { 1272 return smum_send_msg_to_smc_with_parameter( 1273 hwmgr, 1274 PPSMC_MSG_UVDPowerON, 1275 PP_CAP(PHM_PlatformCaps_UVDDynamicPowerGating) ? 1 : 0, 1276 NULL); 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) 1283 { 1284 struct smu8_hwmgr *data = hwmgr->backend; 1285 struct phm_vce_clock_voltage_dependency_table *ptable = 1286 hwmgr->dyn_state.vce_clock_voltage_dependency_table; 1287 1288 /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */ 1289 if (PP_CAP(PHM_PlatformCaps_StablePState) || 1290 hwmgr->en_umd_pstate) { 1291 data->vce_dpm.hard_min_clk = 1292 ptable->entries[ptable->count - 1].ecclk; 1293 1294 smum_send_msg_to_smc_with_parameter(hwmgr, 1295 PPSMC_MSG_SetEclkHardMin, 1296 smu8_get_eclk_level(hwmgr, 1297 data->vce_dpm.hard_min_clk, 1298 PPSMC_MSG_SetEclkHardMin), 1299 NULL); 1300 } else { 1301 1302 smum_send_msg_to_smc_with_parameter(hwmgr, 1303 PPSMC_MSG_SetEclkHardMin, 1304 0, 1305 NULL); 1306 /* disable ECLK DPM 0. Otherwise VCE could hang if 1307 * switching SCLK from DPM 0 to 6/7 */ 1308 smum_send_msg_to_smc_with_parameter(hwmgr, 1309 PPSMC_MSG_SetEclkSoftMin, 1310 1, 1311 NULL); 1312 } 1313 return 0; 1314 } 1315 1316 static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr) 1317 { 1318 if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) 1319 return smum_send_msg_to_smc(hwmgr, 1320 PPSMC_MSG_VCEPowerOFF, 1321 NULL); 1322 return 0; 1323 } 1324 1325 static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr) 1326 { 1327 if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) 1328 return smum_send_msg_to_smc(hwmgr, 1329 PPSMC_MSG_VCEPowerON, 1330 NULL); 1331 return 0; 1332 } 1333 1334 static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 1335 { 1336 struct smu8_hwmgr *data = hwmgr->backend; 1337 1338 return data->sys_info.bootup_uma_clock; 1339 } 1340 1341 static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 1342 { 1343 struct pp_power_state *ps; 1344 struct smu8_power_state *smu8_ps; 1345 1346 if (hwmgr == NULL) 1347 return -EINVAL; 1348 1349 ps = hwmgr->request_ps; 1350 1351 if (ps == NULL) 1352 return -EINVAL; 1353 1354 smu8_ps = cast_smu8_power_state(&ps->hardware); 1355 1356 if (low) 1357 return smu8_ps->levels[0].engineClock; 1358 else 1359 return smu8_ps->levels[smu8_ps->level-1].engineClock; 1360 } 1361 1362 static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 1363 struct pp_hw_power_state *hw_ps) 1364 { 1365 struct smu8_hwmgr *data = hwmgr->backend; 1366 struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); 1367 1368 smu8_ps->level = 1; 1369 smu8_ps->nbps_flags = 0; 1370 smu8_ps->bapm_flags = 0; 1371 smu8_ps->levels[0] = data->boot_power_level; 1372 1373 return 0; 1374 } 1375 1376 static int smu8_dpm_get_pp_table_entry_callback( 1377 struct pp_hwmgr *hwmgr, 1378 struct pp_hw_power_state *hw_ps, 1379 unsigned int index, 1380 const void *clock_info) 1381 { 1382 struct smu8_power_state *smu8_ps = cast_smu8_power_state(hw_ps); 1383 1384 const ATOM_PPLIB_CZ_CLOCK_INFO *smu8_clock_info = clock_info; 1385 1386 struct phm_clock_voltage_dependency_table *table = 1387 hwmgr->dyn_state.vddc_dependency_on_sclk; 1388 uint8_t clock_info_index = smu8_clock_info->index; 1389 1390 if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) 1391 clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1); 1392 1393 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; 1394 smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v; 1395 1396 smu8_ps->level = index + 1; 1397 1398 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 1399 smu8_ps->levels[index].dsDividerIndex = 5; 1400 smu8_ps->levels[index].ssDividerIndex = 5; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) 1407 { 1408 int result; 1409 unsigned long ret = 0; 1410 1411 result = pp_tables_get_num_of_entries(hwmgr, &ret); 1412 1413 return result ? 0 : ret; 1414 } 1415 1416 static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, 1417 unsigned long entry, struct pp_power_state *ps) 1418 { 1419 int result; 1420 struct smu8_power_state *smu8_ps; 1421 1422 ps->hardware.magic = smu8_magic; 1423 1424 smu8_ps = cast_smu8_power_state(&(ps->hardware)); 1425 1426 result = pp_tables_get_entry(hwmgr, entry, ps, 1427 smu8_dpm_get_pp_table_entry_callback); 1428 1429 smu8_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; 1430 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; 1431 1432 return result; 1433 } 1434 1435 static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr) 1436 { 1437 return sizeof(struct smu8_power_state); 1438 } 1439 1440 static void smu8_hw_print_display_cfg( 1441 const struct cc6_settings *cc6_settings) 1442 { 1443 PP_DBG_LOG("New Display Configuration:\n"); 1444 1445 PP_DBG_LOG(" cpu_cc6_disable: %d\n", 1446 cc6_settings->cpu_cc6_disable); 1447 PP_DBG_LOG(" cpu_pstate_disable: %d\n", 1448 cc6_settings->cpu_pstate_disable); 1449 PP_DBG_LOG(" nb_pstate_switch_disable: %d\n", 1450 cc6_settings->nb_pstate_switch_disable); 1451 PP_DBG_LOG(" cpu_pstate_separation_time: %d\n\n", 1452 cc6_settings->cpu_pstate_separation_time); 1453 } 1454 1455 static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr) 1456 { 1457 struct smu8_hwmgr *hw_data = hwmgr->backend; 1458 uint32_t data = 0; 1459 1460 if (hw_data->cc6_settings.cc6_setting_changed) { 1461 1462 hw_data->cc6_settings.cc6_setting_changed = false; 1463 1464 smu8_hw_print_display_cfg(&hw_data->cc6_settings); 1465 1466 data |= (hw_data->cc6_settings.cpu_pstate_separation_time 1467 & PWRMGT_SEPARATION_TIME_MASK) 1468 << PWRMGT_SEPARATION_TIME_SHIFT; 1469 1470 data |= (hw_data->cc6_settings.cpu_cc6_disable ? 0x1 : 0x0) 1471 << PWRMGT_DISABLE_CPU_CSTATES_SHIFT; 1472 1473 data |= (hw_data->cc6_settings.cpu_pstate_disable ? 0x1 : 0x0) 1474 << PWRMGT_DISABLE_CPU_PSTATES_SHIFT; 1475 1476 PP_DBG_LOG("SetDisplaySizePowerParams data: 0x%X\n", 1477 data); 1478 1479 smum_send_msg_to_smc_with_parameter(hwmgr, 1480 PPSMC_MSG_SetDisplaySizePowerParams, 1481 data, 1482 NULL); 1483 } 1484 1485 return 0; 1486 } 1487 1488 1489 static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, 1490 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) 1491 { 1492 struct smu8_hwmgr *hw_data = hwmgr->backend; 1493 1494 if (separation_time != 1495 hw_data->cc6_settings.cpu_pstate_separation_time || 1496 cc6_disable != hw_data->cc6_settings.cpu_cc6_disable || 1497 pstate_disable != hw_data->cc6_settings.cpu_pstate_disable || 1498 pstate_switch_disable != hw_data->cc6_settings.nb_pstate_switch_disable) { 1499 1500 hw_data->cc6_settings.cc6_setting_changed = true; 1501 1502 hw_data->cc6_settings.cpu_pstate_separation_time = 1503 separation_time; 1504 hw_data->cc6_settings.cpu_cc6_disable = 1505 cc6_disable; 1506 hw_data->cc6_settings.cpu_pstate_disable = 1507 pstate_disable; 1508 hw_data->cc6_settings.nb_pstate_switch_disable = 1509 pstate_switch_disable; 1510 1511 } 1512 1513 return 0; 1514 } 1515 1516 static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr, 1517 struct amd_pp_simple_clock_info *info) 1518 { 1519 uint32_t i; 1520 const struct phm_clock_voltage_dependency_table *table = 1521 hwmgr->dyn_state.vddc_dep_on_dal_pwrl; 1522 const struct phm_clock_and_voltage_limits *limits = 1523 &hwmgr->dyn_state.max_clock_voltage_on_ac; 1524 1525 info->engine_max_clock = limits->sclk; 1526 info->memory_max_clock = limits->mclk; 1527 1528 for (i = table->count - 1; i > 0; i--) { 1529 if (limits->vddc >= table->entries[i].v) { 1530 info->level = table->entries[i].clk; 1531 return 0; 1532 } 1533 } 1534 return -EINVAL; 1535 } 1536 1537 static int smu8_force_clock_level(struct pp_hwmgr *hwmgr, 1538 enum pp_clock_type type, uint32_t mask) 1539 { 1540 switch (type) { 1541 case PP_SCLK: 1542 smum_send_msg_to_smc_with_parameter(hwmgr, 1543 PPSMC_MSG_SetSclkSoftMin, 1544 mask, 1545 NULL); 1546 smum_send_msg_to_smc_with_parameter(hwmgr, 1547 PPSMC_MSG_SetSclkSoftMax, 1548 mask, 1549 NULL); 1550 break; 1551 default: 1552 break; 1553 } 1554 1555 return 0; 1556 } 1557 1558 static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, 1559 enum pp_clock_type type, char *buf) 1560 { 1561 struct smu8_hwmgr *data = hwmgr->backend; 1562 struct phm_clock_voltage_dependency_table *sclk_table = 1563 hwmgr->dyn_state.vddc_dependency_on_sclk; 1564 uint32_t i, now; 1565 int size = 0; 1566 1567 switch (type) { 1568 case PP_SCLK: 1569 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, 1570 CGS_IND_REG__SMC, 1571 ixTARGET_AND_CURRENT_PROFILE_INDEX), 1572 TARGET_AND_CURRENT_PROFILE_INDEX, 1573 CURR_SCLK_INDEX); 1574 1575 for (i = 0; i < sclk_table->count; i++) 1576 size += sprintf(buf + size, "%d: %uMhz %s\n", 1577 i, sclk_table->entries[i].clk / 100, 1578 (i == now) ? "*" : ""); 1579 break; 1580 case PP_MCLK: 1581 now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, 1582 CGS_IND_REG__SMC, 1583 ixTARGET_AND_CURRENT_PROFILE_INDEX), 1584 TARGET_AND_CURRENT_PROFILE_INDEX, 1585 CURR_MCLK_INDEX); 1586 1587 for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--) 1588 size += sprintf(buf + size, "%d: %uMhz %s\n", 1589 SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100, 1590 (SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : ""); 1591 break; 1592 default: 1593 break; 1594 } 1595 return size; 1596 } 1597 1598 static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 1599 PHM_PerformanceLevelDesignation designation, uint32_t index, 1600 PHM_PerformanceLevel *level) 1601 { 1602 const struct smu8_power_state *ps; 1603 struct smu8_hwmgr *data; 1604 uint32_t level_index; 1605 uint32_t i; 1606 1607 if (level == NULL || hwmgr == NULL || state == NULL) 1608 return -EINVAL; 1609 1610 data = hwmgr->backend; 1611 ps = cast_const_smu8_power_state(state); 1612 1613 level_index = index > ps->level - 1 ? ps->level - 1 : index; 1614 level->coreClock = ps->levels[level_index].engineClock; 1615 1616 if (designation == PHM_PerformanceLevelDesignation_PowerContainment) { 1617 for (i = 1; i < ps->level; i++) { 1618 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { 1619 level->coreClock = ps->levels[i].engineClock; 1620 break; 1621 } 1622 } 1623 } 1624 1625 if (level_index == 0) 1626 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; 1627 else 1628 level->memory_clock = data->sys_info.nbp_memory_clock[0]; 1629 1630 level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4; 1631 level->nonLocalMemoryFreq = 0; 1632 level->nonLocalMemoryWidth = 0; 1633 1634 return 0; 1635 } 1636 1637 static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, 1638 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) 1639 { 1640 const struct smu8_power_state *ps = cast_const_smu8_power_state(state); 1641 1642 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); 1643 clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1].ssDividerIndex)); 1644 1645 return 0; 1646 } 1647 1648 static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, 1649 struct amd_pp_clocks *clocks) 1650 { 1651 struct smu8_hwmgr *data = hwmgr->backend; 1652 int i; 1653 struct phm_clock_voltage_dependency_table *table; 1654 1655 clocks->count = smu8_get_max_sclk_level(hwmgr); 1656 switch (type) { 1657 case amd_pp_disp_clock: 1658 for (i = 0; i < clocks->count; i++) 1659 clocks->clock[i] = data->sys_info.display_clock[i] * 10; 1660 break; 1661 case amd_pp_sys_clock: 1662 table = hwmgr->dyn_state.vddc_dependency_on_sclk; 1663 for (i = 0; i < clocks->count; i++) 1664 clocks->clock[i] = table->entries[i].clk * 10; 1665 break; 1666 case amd_pp_mem_clock: 1667 clocks->count = SMU8_NUM_NBPMEMORYCLOCK; 1668 for (i = 0; i < clocks->count; i++) 1669 clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10; 1670 break; 1671 default: 1672 return -1; 1673 } 1674 1675 return 0; 1676 } 1677 1678 static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) 1679 { 1680 struct phm_clock_voltage_dependency_table *table = 1681 hwmgr->dyn_state.vddc_dependency_on_sclk; 1682 unsigned long level; 1683 const struct phm_clock_and_voltage_limits *limits = 1684 &hwmgr->dyn_state.max_clock_voltage_on_ac; 1685 1686 if ((NULL == table) || (table->count <= 0) || (clocks == NULL)) 1687 return -EINVAL; 1688 1689 level = smu8_get_max_sclk_level(hwmgr) - 1; 1690 1691 if (level < table->count) 1692 clocks->engine_max_clock = table->entries[level].clk; 1693 else 1694 clocks->engine_max_clock = table->entries[table->count - 1].clk; 1695 1696 clocks->memory_max_clock = limits->mclk; 1697 1698 return 0; 1699 } 1700 1701 static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr) 1702 { 1703 int actual_temp = 0; 1704 uint32_t val = cgs_read_ind_register(hwmgr->device, 1705 CGS_IND_REG__SMC, ixTHM_TCON_CUR_TMP); 1706 uint32_t temp = PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP); 1707 1708 if (PHM_GET_FIELD(val, THM_TCON_CUR_TMP, CUR_TEMP_RANGE_SEL)) 1709 actual_temp = ((temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1710 else 1711 actual_temp = (temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1712 1713 return actual_temp; 1714 } 1715 1716 static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1717 void *value, int *size) 1718 { 1719 struct smu8_hwmgr *data = hwmgr->backend; 1720 1721 struct phm_clock_voltage_dependency_table *table = 1722 hwmgr->dyn_state.vddc_dependency_on_sclk; 1723 1724 struct phm_vce_clock_voltage_dependency_table *vce_table = 1725 hwmgr->dyn_state.vce_clock_voltage_dependency_table; 1726 1727 struct phm_uvd_clock_voltage_dependency_table *uvd_table = 1728 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; 1729 1730 uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX), 1731 TARGET_AND_CURRENT_PROFILE_INDEX, CURR_SCLK_INDEX); 1732 uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), 1733 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_UVD_INDEX); 1734 uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2), 1735 TARGET_AND_CURRENT_PROFILE_INDEX_2, CURR_VCE_INDEX); 1736 1737 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; 1738 uint16_t vddnb, vddgfx; 1739 int result; 1740 1741 /* size must be at least 4 bytes for all sensors */ 1742 if (*size < 4) 1743 return -EINVAL; 1744 *size = 4; 1745 1746 switch (idx) { 1747 case AMDGPU_PP_SENSOR_GFX_SCLK: 1748 if (sclk_index < NUM_SCLK_LEVELS) { 1749 sclk = table->entries[sclk_index].clk; 1750 *((uint32_t *)value) = sclk; 1751 return 0; 1752 } 1753 return -EINVAL; 1754 case AMDGPU_PP_SENSOR_VDDNB: 1755 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & 1756 CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; 1757 vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4; 1758 *((uint32_t *)value) = vddnb; 1759 return 0; 1760 case AMDGPU_PP_SENSOR_VDDGFX: 1761 tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & 1762 CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; 1763 vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4; 1764 *((uint32_t *)value) = vddgfx; 1765 return 0; 1766 case AMDGPU_PP_SENSOR_UVD_VCLK: 1767 if (!data->uvd_power_gated) { 1768 if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { 1769 return -EINVAL; 1770 } else { 1771 vclk = uvd_table->entries[uvd_index].vclk; 1772 *((uint32_t *)value) = vclk; 1773 return 0; 1774 } 1775 } 1776 *((uint32_t *)value) = 0; 1777 return 0; 1778 case AMDGPU_PP_SENSOR_UVD_DCLK: 1779 if (!data->uvd_power_gated) { 1780 if (uvd_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { 1781 return -EINVAL; 1782 } else { 1783 dclk = uvd_table->entries[uvd_index].dclk; 1784 *((uint32_t *)value) = dclk; 1785 return 0; 1786 } 1787 } 1788 *((uint32_t *)value) = 0; 1789 return 0; 1790 case AMDGPU_PP_SENSOR_VCE_ECCLK: 1791 if (!data->vce_power_gated) { 1792 if (vce_index >= SMU8_MAX_HARDWARE_POWERLEVELS) { 1793 return -EINVAL; 1794 } else { 1795 ecclk = vce_table->entries[vce_index].ecclk; 1796 *((uint32_t *)value) = ecclk; 1797 return 0; 1798 } 1799 } 1800 *((uint32_t *)value) = 0; 1801 return 0; 1802 case AMDGPU_PP_SENSOR_GPU_LOAD: 1803 result = smum_send_msg_to_smc(hwmgr, 1804 PPSMC_MSG_GetAverageGraphicsActivity, 1805 &activity_percent); 1806 if (0 == result) 1807 activity_percent = activity_percent > 100 ? 100 : activity_percent; 1808 else 1809 return -EIO; 1810 *((uint32_t *)value) = activity_percent; 1811 return 0; 1812 case AMDGPU_PP_SENSOR_UVD_POWER: 1813 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 1814 return 0; 1815 case AMDGPU_PP_SENSOR_VCE_POWER: 1816 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 1817 return 0; 1818 case AMDGPU_PP_SENSOR_GPU_TEMP: 1819 *((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr); 1820 return 0; 1821 default: 1822 return -EOPNOTSUPP; 1823 } 1824 } 1825 1826 static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 1827 uint32_t virtual_addr_low, 1828 uint32_t virtual_addr_hi, 1829 uint32_t mc_addr_low, 1830 uint32_t mc_addr_hi, 1831 uint32_t size) 1832 { 1833 smum_send_msg_to_smc_with_parameter(hwmgr, 1834 PPSMC_MSG_DramAddrHiVirtual, 1835 mc_addr_hi, 1836 NULL); 1837 smum_send_msg_to_smc_with_parameter(hwmgr, 1838 PPSMC_MSG_DramAddrLoVirtual, 1839 mc_addr_low, 1840 NULL); 1841 smum_send_msg_to_smc_with_parameter(hwmgr, 1842 PPSMC_MSG_DramAddrHiPhysical, 1843 virtual_addr_hi, 1844 NULL); 1845 smum_send_msg_to_smc_with_parameter(hwmgr, 1846 PPSMC_MSG_DramAddrLoPhysical, 1847 virtual_addr_low, 1848 NULL); 1849 1850 smum_send_msg_to_smc_with_parameter(hwmgr, 1851 PPSMC_MSG_DramBufferSize, 1852 size, 1853 NULL); 1854 return 0; 1855 } 1856 1857 static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 1858 struct PP_TemperatureRange *thermal_data) 1859 { 1860 struct smu8_hwmgr *data = hwmgr->backend; 1861 1862 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); 1863 1864 thermal_data->max = (data->thermal_auto_throttling_treshold + 1865 data->sys_info.htc_hyst_lmt) * 1866 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1867 1868 return 0; 1869 } 1870 1871 static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) 1872 { 1873 struct smu8_hwmgr *data = hwmgr->backend; 1874 uint32_t dpm_features = 0; 1875 1876 if (enable && 1877 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1878 PHM_PlatformCaps_UVDDPM)) { 1879 data->dpm_flags |= DPMFlags_UVD_Enabled; 1880 dpm_features |= UVD_DPM_MASK; 1881 smum_send_msg_to_smc_with_parameter(hwmgr, 1882 PPSMC_MSG_EnableAllSmuFeatures, 1883 dpm_features, 1884 NULL); 1885 } else { 1886 dpm_features |= UVD_DPM_MASK; 1887 data->dpm_flags &= ~DPMFlags_UVD_Enabled; 1888 smum_send_msg_to_smc_with_parameter(hwmgr, 1889 PPSMC_MSG_DisableAllSmuFeatures, 1890 dpm_features, 1891 NULL); 1892 } 1893 return 0; 1894 } 1895 1896 static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) 1897 { 1898 struct smu8_hwmgr *data = hwmgr->backend; 1899 struct phm_uvd_clock_voltage_dependency_table *ptable = 1900 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; 1901 1902 if (!bgate) { 1903 /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */ 1904 if (PP_CAP(PHM_PlatformCaps_StablePState) || 1905 hwmgr->en_umd_pstate) { 1906 data->uvd_dpm.hard_min_clk = 1907 ptable->entries[ptable->count - 1].vclk; 1908 1909 smum_send_msg_to_smc_with_parameter(hwmgr, 1910 PPSMC_MSG_SetUvdHardMin, 1911 smu8_get_uvd_level(hwmgr, 1912 data->uvd_dpm.hard_min_clk, 1913 PPSMC_MSG_SetUvdHardMin), 1914 NULL); 1915 1916 smu8_enable_disable_uvd_dpm(hwmgr, true); 1917 } else { 1918 smu8_enable_disable_uvd_dpm(hwmgr, true); 1919 } 1920 } else { 1921 smu8_enable_disable_uvd_dpm(hwmgr, false); 1922 } 1923 1924 return 0; 1925 } 1926 1927 static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) 1928 { 1929 struct smu8_hwmgr *data = hwmgr->backend; 1930 uint32_t dpm_features = 0; 1931 1932 if (enable && phm_cap_enabled( 1933 hwmgr->platform_descriptor.platformCaps, 1934 PHM_PlatformCaps_VCEDPM)) { 1935 data->dpm_flags |= DPMFlags_VCE_Enabled; 1936 dpm_features |= VCE_DPM_MASK; 1937 smum_send_msg_to_smc_with_parameter(hwmgr, 1938 PPSMC_MSG_EnableAllSmuFeatures, 1939 dpm_features, 1940 NULL); 1941 } else { 1942 dpm_features |= VCE_DPM_MASK; 1943 data->dpm_flags &= ~DPMFlags_VCE_Enabled; 1944 smum_send_msg_to_smc_with_parameter(hwmgr, 1945 PPSMC_MSG_DisableAllSmuFeatures, 1946 dpm_features, 1947 NULL); 1948 } 1949 1950 return 0; 1951 } 1952 1953 1954 static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate) 1955 { 1956 struct smu8_hwmgr *data = hwmgr->backend; 1957 1958 if (data->acp_power_gated == bgate) 1959 return; 1960 1961 if (bgate) 1962 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF, NULL); 1963 else 1964 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON, NULL); 1965 } 1966 1967 #define WIDTH_4K 3840 1968 1969 static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) 1970 { 1971 struct smu8_hwmgr *data = hwmgr->backend; 1972 struct amdgpu_device *adev = hwmgr->adev; 1973 1974 data->uvd_power_gated = bgate; 1975 1976 if (bgate) { 1977 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 1978 AMD_IP_BLOCK_TYPE_UVD, 1979 AMD_PG_STATE_GATE); 1980 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, 1981 AMD_IP_BLOCK_TYPE_UVD, 1982 AMD_CG_STATE_GATE); 1983 smu8_dpm_update_uvd_dpm(hwmgr, true); 1984 smu8_dpm_powerdown_uvd(hwmgr); 1985 } else { 1986 smu8_dpm_powerup_uvd(hwmgr); 1987 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, 1988 AMD_IP_BLOCK_TYPE_UVD, 1989 AMD_CG_STATE_UNGATE); 1990 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 1991 AMD_IP_BLOCK_TYPE_UVD, 1992 AMD_PG_STATE_UNGATE); 1993 smu8_dpm_update_uvd_dpm(hwmgr, false); 1994 } 1995 1996 /* enable/disable Low Memory PState for UVD (4k videos) */ 1997 if (adev->asic_type == CHIP_STONEY && 1998 adev->uvd.decode_image_width >= WIDTH_4K) 1999 smu8_nbdpm_pstate_enable_disable(hwmgr, 2000 bgate, 2001 true); 2002 } 2003 2004 static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) 2005 { 2006 struct smu8_hwmgr *data = hwmgr->backend; 2007 2008 if (bgate) { 2009 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 2010 AMD_IP_BLOCK_TYPE_VCE, 2011 AMD_PG_STATE_GATE); 2012 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, 2013 AMD_IP_BLOCK_TYPE_VCE, 2014 AMD_CG_STATE_GATE); 2015 smu8_enable_disable_vce_dpm(hwmgr, false); 2016 smu8_dpm_powerdown_vce(hwmgr); 2017 data->vce_power_gated = true; 2018 } else { 2019 smu8_dpm_powerup_vce(hwmgr); 2020 data->vce_power_gated = false; 2021 amdgpu_device_ip_set_clockgating_state(hwmgr->adev, 2022 AMD_IP_BLOCK_TYPE_VCE, 2023 AMD_CG_STATE_UNGATE); 2024 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 2025 AMD_IP_BLOCK_TYPE_VCE, 2026 AMD_PG_STATE_UNGATE); 2027 smu8_dpm_update_vce_dpm(hwmgr); 2028 smu8_enable_disable_vce_dpm(hwmgr, true); 2029 } 2030 } 2031 2032 static const struct pp_hwmgr_func smu8_hwmgr_funcs = { 2033 .backend_init = smu8_hwmgr_backend_init, 2034 .backend_fini = smu8_hwmgr_backend_fini, 2035 .apply_state_adjust_rules = smu8_apply_state_adjust_rules, 2036 .force_dpm_level = smu8_dpm_force_dpm_level, 2037 .get_power_state_size = smu8_get_power_state_size, 2038 .powerdown_uvd = smu8_dpm_powerdown_uvd, 2039 .powergate_uvd = smu8_dpm_powergate_uvd, 2040 .powergate_vce = smu8_dpm_powergate_vce, 2041 .powergate_acp = smu8_dpm_powergate_acp, 2042 .get_mclk = smu8_dpm_get_mclk, 2043 .get_sclk = smu8_dpm_get_sclk, 2044 .patch_boot_state = smu8_dpm_patch_boot_state, 2045 .get_pp_table_entry = smu8_dpm_get_pp_table_entry, 2046 .get_num_of_pp_table_entries = smu8_dpm_get_num_of_pp_table_entries, 2047 .set_cpu_power_state = smu8_set_cpu_power_state, 2048 .store_cc6_data = smu8_store_cc6_data, 2049 .force_clock_level = smu8_force_clock_level, 2050 .print_clock_levels = smu8_print_clock_levels, 2051 .get_dal_power_level = smu8_get_dal_power_level, 2052 .get_performance_level = smu8_get_performance_level, 2053 .get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks, 2054 .get_clock_by_type = smu8_get_clock_by_type, 2055 .get_max_high_clocks = smu8_get_max_high_clocks, 2056 .read_sensor = smu8_read_sensor, 2057 .power_off_asic = smu8_power_off_asic, 2058 .asic_setup = smu8_setup_asic_task, 2059 .dynamic_state_management_enable = smu8_enable_dpm_tasks, 2060 .power_state_set = smu8_set_power_state_tasks, 2061 .dynamic_state_management_disable = smu8_disable_dpm_tasks, 2062 .notify_cac_buffer_info = smu8_notify_cac_buffer_info, 2063 .get_thermal_temperature_range = smu8_get_thermal_temperature_range, 2064 }; 2065 2066 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr) 2067 { 2068 hwmgr->hwmgr_func = &smu8_hwmgr_funcs; 2069 hwmgr->pptable_func = &pptable_funcs; 2070 return 0; 2071 } 2072