1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2015 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan #ifndef _SMU7_POWERTUNE_H 24e098bc96SEvan Quan #define _SMU7_POWERTUNE_H 25e098bc96SEvan Quan 26e098bc96SEvan Quan #define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xfffc0000 27e098bc96SEvan Quan #define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x12 28e098bc96SEvan Quan #define DIDT_TD_CTRL0__UNUSED_0_MASK 0xfffc0000 29e098bc96SEvan Quan #define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x12 30e098bc96SEvan Quan #define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xfffc0000 31e098bc96SEvan Quan #define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x12 32e098bc96SEvan Quan #define DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK 0xc0000000 33e098bc96SEvan Quan #define DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e 34e098bc96SEvan Quan #define DIDT_TD_TUNING_CTRL__UNUSED_0_MASK 0xc0000000 35e098bc96SEvan Quan #define DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e 36e098bc96SEvan Quan #define DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK 0xc0000000 37e098bc96SEvan Quan #define DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT 0x0000001e 38e098bc96SEvan Quan 39e098bc96SEvan Quan /* PowerContainment Features */ 40e098bc96SEvan Quan #define POWERCONTAINMENT_FEATURE_DTE 0x00000001 41e098bc96SEvan Quan #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 42e098bc96SEvan Quan #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 43e098bc96SEvan Quan 44e098bc96SEvan Quan #define ixGC_CAC_CNTL 0x0000 45e098bc96SEvan Quan #define ixDIDT_SQ_STALL_CTRL 0x0004 46e098bc96SEvan Quan #define ixDIDT_SQ_TUNING_CTRL 0x0005 47e098bc96SEvan Quan #define ixDIDT_TD_STALL_CTRL 0x0044 48e098bc96SEvan Quan #define ixDIDT_TD_TUNING_CTRL 0x0045 49e098bc96SEvan Quan #define ixDIDT_TCP_STALL_CTRL 0x0064 50e098bc96SEvan Quan #define ixDIDT_TCP_TUNING_CTRL 0x0065 51e098bc96SEvan Quan 52e098bc96SEvan Quan 53e098bc96SEvan Quan int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr); 54e098bc96SEvan Quan int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr); 55e098bc96SEvan Quan int smu7_enable_power_containment(struct pp_hwmgr *hwmgr); 56e098bc96SEvan Quan int smu7_disable_power_containment(struct pp_hwmgr *hwmgr); 57e098bc96SEvan Quan int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); 58e098bc96SEvan Quan int smu7_power_control_set_level(struct pp_hwmgr *hwmgr); 59e098bc96SEvan Quan int smu7_enable_didt_config(struct pp_hwmgr *hwmgr); 60e098bc96SEvan Quan int smu7_disable_didt_config(struct pp_hwmgr *hwmgr); 61e098bc96SEvan Quan #endif /* DGPU_POWERTUNE_H */ 62e098bc96SEvan Quan 63