1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/delay.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 #include <linux/slab.h> 28 #include <asm/div64.h> 29 #if IS_ENABLED(CONFIG_X86_64) 30 #include <asm/intel-family.h> 31 #endif 32 #include <drm/amdgpu_drm.h> 33 #include "ppatomctrl.h" 34 #include "atombios.h" 35 #include "pptable_v1_0.h" 36 #include "pppcielanes.h" 37 #include "amd_pcie_helpers.h" 38 #include "hardwaremanager.h" 39 #include "process_pptables_v1_0.h" 40 #include "cgs_common.h" 41 42 #include "smu7_common.h" 43 44 #include "hwmgr.h" 45 #include "smu7_hwmgr.h" 46 #include "smu_ucode_xfer_vi.h" 47 #include "smu7_powertune.h" 48 #include "smu7_dyn_defaults.h" 49 #include "smu7_thermal.h" 50 #include "smu7_clockpowergating.h" 51 #include "processpptables.h" 52 #include "pp_thermal.h" 53 #include "smu7_baco.h" 54 #include "smu7_smumgr.h" 55 #include "polaris10_smumgr.h" 56 57 #include "ivsrcid/ivsrcid_vislands30.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define MC_CG_SEQ_DRAMCONF_S0 0x05 65 #define MC_CG_SEQ_DRAMCONF_S1 0x06 66 #define MC_CG_SEQ_YCLK_SUSPEND 0x04 67 #define MC_CG_SEQ_YCLK_RESUME 0x0a 68 69 #define SMC_CG_IND_START 0xc0030000 70 #define SMC_CG_IND_END 0xc0040000 71 72 #define MEM_FREQ_LOW_LATENCY 25000 73 #define MEM_FREQ_HIGH_LATENCY 80000 74 75 #define MEM_LATENCY_HIGH 45 76 #define MEM_LATENCY_LOW 35 77 #define MEM_LATENCY_ERR 0xFFFF 78 79 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 80 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 81 #define MC_SEQ_MISC0_GDDR5_VALUE 5 82 83 #define PCIE_BUS_CLK 10000 84 #define TCLK (PCIE_BUS_CLK / 10) 85 86 static struct profile_mode_setting smu7_profiling[7] = 87 {{0, 0, 0, 0, 0, 0, 0, 0}, 88 {1, 0, 100, 30, 1, 0, 100, 10}, 89 {1, 10, 0, 30, 0, 0, 0, 0}, 90 {0, 0, 0, 0, 1, 10, 16, 31}, 91 {1, 0, 11, 50, 1, 0, 100, 10}, 92 {1, 0, 5, 30, 0, 0, 0, 0}, 93 {0, 0, 0, 0, 0, 0, 0, 0}, 94 }; 95 96 #define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310) 97 98 #define ixPWR_SVI2_PLANE1_LOAD 0xC0200280 99 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L 100 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L 101 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005 102 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006 103 104 #define STRAP_EVV_REVISION_MSB 2211 105 #define STRAP_EVV_REVISION_LSB 2208 106 107 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ 108 enum DPM_EVENT_SRC { 109 DPM_EVENT_SRC_ANALOG = 0, 110 DPM_EVENT_SRC_EXTERNAL = 1, 111 DPM_EVENT_SRC_DIGITAL = 2, 112 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 113 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 114 }; 115 116 #define ixDIDT_SQ_EDC_CTRL 0x0013 117 #define ixDIDT_SQ_EDC_THRESHOLD 0x0014 118 #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 0x0015 119 #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 0x0016 120 #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 0x0017 121 #define ixDIDT_SQ_EDC_STALL_PATTERN_7 0x0018 122 123 #define ixDIDT_TD_EDC_CTRL 0x0053 124 #define ixDIDT_TD_EDC_THRESHOLD 0x0054 125 #define ixDIDT_TD_EDC_STALL_PATTERN_1_2 0x0055 126 #define ixDIDT_TD_EDC_STALL_PATTERN_3_4 0x0056 127 #define ixDIDT_TD_EDC_STALL_PATTERN_5_6 0x0057 128 #define ixDIDT_TD_EDC_STALL_PATTERN_7 0x0058 129 130 #define ixDIDT_TCP_EDC_CTRL 0x0073 131 #define ixDIDT_TCP_EDC_THRESHOLD 0x0074 132 #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 0x0075 133 #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 0x0076 134 #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 0x0077 135 #define ixDIDT_TCP_EDC_STALL_PATTERN_7 0x0078 136 137 #define ixDIDT_DB_EDC_CTRL 0x0033 138 #define ixDIDT_DB_EDC_THRESHOLD 0x0034 139 #define ixDIDT_DB_EDC_STALL_PATTERN_1_2 0x0035 140 #define ixDIDT_DB_EDC_STALL_PATTERN_3_4 0x0036 141 #define ixDIDT_DB_EDC_STALL_PATTERN_5_6 0x0037 142 #define ixDIDT_DB_EDC_STALL_PATTERN_7 0x0038 143 144 uint32_t DIDTEDCConfig_P12[] = { 145 ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 146 ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 147 ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 148 ixDIDT_SQ_EDC_STALL_PATTERN_7, 149 ixDIDT_SQ_EDC_THRESHOLD, 150 ixDIDT_SQ_EDC_CTRL, 151 ixDIDT_TD_EDC_STALL_PATTERN_1_2, 152 ixDIDT_TD_EDC_STALL_PATTERN_3_4, 153 ixDIDT_TD_EDC_STALL_PATTERN_5_6, 154 ixDIDT_TD_EDC_STALL_PATTERN_7, 155 ixDIDT_TD_EDC_THRESHOLD, 156 ixDIDT_TD_EDC_CTRL, 157 ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 158 ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 159 ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 160 ixDIDT_TCP_EDC_STALL_PATTERN_7, 161 ixDIDT_TCP_EDC_THRESHOLD, 162 ixDIDT_TCP_EDC_CTRL, 163 ixDIDT_DB_EDC_STALL_PATTERN_1_2, 164 ixDIDT_DB_EDC_STALL_PATTERN_3_4, 165 ixDIDT_DB_EDC_STALL_PATTERN_5_6, 166 ixDIDT_DB_EDC_STALL_PATTERN_7, 167 ixDIDT_DB_EDC_THRESHOLD, 168 ixDIDT_DB_EDC_CTRL, 169 0xFFFFFFFF // End of list 170 }; 171 172 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic); 173 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 174 enum pp_clock_type type, uint32_t mask); 175 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr); 176 177 static struct smu7_power_state *cast_phw_smu7_power_state( 178 struct pp_hw_power_state *hw_ps) 179 { 180 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 181 "Invalid Powerstate Type!", 182 return NULL); 183 184 return (struct smu7_power_state *)hw_ps; 185 } 186 187 static const struct smu7_power_state *cast_const_phw_smu7_power_state( 188 const struct pp_hw_power_state *hw_ps) 189 { 190 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 191 "Invalid Powerstate Type!", 192 return NULL); 193 194 return (const struct smu7_power_state *)hw_ps; 195 } 196 197 /** 198 * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct 199 * 200 * @hwmgr: the address of the powerplay hardware manager. 201 * Return: always 0 202 */ 203 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) 204 { 205 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 206 207 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 208 209 return 0; 210 } 211 212 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) 213 { 214 uint32_t speedCntl = 0; 215 216 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 217 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, 218 ixPCIE_LC_SPEED_CNTL); 219 return((uint16_t)PHM_GET_FIELD(speedCntl, 220 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); 221 } 222 223 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) 224 { 225 uint32_t link_width; 226 227 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 228 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 229 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); 230 231 PP_ASSERT_WITH_CODE((7 >= link_width), 232 "Invalid PCIe lane width!", return 0); 233 234 return decode_pcie_lane_width(link_width); 235 } 236 237 /** 238 * smu7_enable_smc_voltage_controller - Enable voltage control 239 * 240 * @hwmgr: the address of the powerplay hardware manager. 241 * Return: always PP_Result_OK 242 */ 243 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) 244 { 245 if (hwmgr->chip_id >= CHIP_POLARIS10 && 246 hwmgr->chip_id <= CHIP_VEGAM) { 247 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 248 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0); 249 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 250 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0); 251 } 252 253 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) 254 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable, NULL); 255 256 return 0; 257 } 258 259 /** 260 * smu7_voltage_control - Checks if we want to support voltage control 261 * 262 * @hwmgr: the address of the powerplay hardware manager. 263 */ 264 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) 265 { 266 const struct smu7_hwmgr *data = 267 (const struct smu7_hwmgr *)(hwmgr->backend); 268 269 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control); 270 } 271 272 /** 273 * smu7_enable_voltage_control - Enable voltage control 274 * 275 * @hwmgr: the address of the powerplay hardware manager. 276 * Return: always 0 277 */ 278 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) 279 { 280 /* enable voltage control */ 281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 282 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); 283 284 return 0; 285 } 286 287 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table, 288 struct phm_clock_voltage_dependency_table *voltage_dependency_table 289 ) 290 { 291 uint32_t i; 292 293 PP_ASSERT_WITH_CODE((NULL != voltage_table), 294 "Voltage Dependency Table empty.", return -EINVAL;); 295 296 voltage_table->mask_low = 0; 297 voltage_table->phase_delay = 0; 298 voltage_table->count = voltage_dependency_table->count; 299 300 for (i = 0; i < voltage_dependency_table->count; i++) { 301 voltage_table->entries[i].value = 302 voltage_dependency_table->entries[i].v; 303 voltage_table->entries[i].smio_low = 0; 304 } 305 306 return 0; 307 } 308 309 310 /** 311 * smu7_construct_voltage_tables - Create Voltage Tables. 312 * 313 * @hwmgr: the address of the powerplay hardware manager. 314 * Return: always 0 315 */ 316 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) 317 { 318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 319 struct phm_ppt_v1_information *table_info = 320 (struct phm_ppt_v1_information *)hwmgr->pptable; 321 int result = 0; 322 uint32_t tmp; 323 324 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 325 result = atomctrl_get_voltage_table_v3(hwmgr, 326 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, 327 &(data->mvdd_voltage_table)); 328 PP_ASSERT_WITH_CODE((0 == result), 329 "Failed to retrieve MVDD table.", 330 return result); 331 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { 332 if (hwmgr->pp_table_version == PP_TABLE_V1) 333 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), 334 table_info->vdd_dep_on_mclk); 335 else if (hwmgr->pp_table_version == PP_TABLE_V0) 336 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table), 337 hwmgr->dyn_state.mvdd_dependency_on_mclk); 338 339 PP_ASSERT_WITH_CODE((0 == result), 340 "Failed to retrieve SVI2 MVDD table from dependency table.", 341 return result;); 342 } 343 344 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 345 result = atomctrl_get_voltage_table_v3(hwmgr, 346 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, 347 &(data->vddci_voltage_table)); 348 PP_ASSERT_WITH_CODE((0 == result), 349 "Failed to retrieve VDDCI table.", 350 return result); 351 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 352 if (hwmgr->pp_table_version == PP_TABLE_V1) 353 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), 354 table_info->vdd_dep_on_mclk); 355 else if (hwmgr->pp_table_version == PP_TABLE_V0) 356 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table), 357 hwmgr->dyn_state.vddci_dependency_on_mclk); 358 PP_ASSERT_WITH_CODE((0 == result), 359 "Failed to retrieve SVI2 VDDCI table from dependency table.", 360 return result); 361 } 362 363 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { 364 /* VDDGFX has only SVI2 voltage control */ 365 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table), 366 table_info->vddgfx_lookup_table); 367 PP_ASSERT_WITH_CODE((0 == result), 368 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); 369 } 370 371 372 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { 373 result = atomctrl_get_voltage_table_v3(hwmgr, 374 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT, 375 &data->vddc_voltage_table); 376 PP_ASSERT_WITH_CODE((0 == result), 377 "Failed to retrieve VDDC table.", return result;); 378 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 379 380 if (hwmgr->pp_table_version == PP_TABLE_V0) 381 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table, 382 hwmgr->dyn_state.vddc_dependency_on_mclk); 383 else if (hwmgr->pp_table_version == PP_TABLE_V1) 384 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), 385 table_info->vddc_lookup_table); 386 387 PP_ASSERT_WITH_CODE((0 == result), 388 "Failed to retrieve SVI2 VDDC table from dependency table.", return result;); 389 } 390 391 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC); 392 PP_ASSERT_WITH_CODE( 393 (data->vddc_voltage_table.count <= tmp), 394 "Too many voltage values for VDDC. Trimming to fit state table.", 395 phm_trim_voltage_table_to_fit_state_table(tmp, 396 &(data->vddc_voltage_table))); 397 398 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 399 PP_ASSERT_WITH_CODE( 400 (data->vddgfx_voltage_table.count <= tmp), 401 "Too many voltage values for VDDC. Trimming to fit state table.", 402 phm_trim_voltage_table_to_fit_state_table(tmp, 403 &(data->vddgfx_voltage_table))); 404 405 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI); 406 PP_ASSERT_WITH_CODE( 407 (data->vddci_voltage_table.count <= tmp), 408 "Too many voltage values for VDDCI. Trimming to fit state table.", 409 phm_trim_voltage_table_to_fit_state_table(tmp, 410 &(data->vddci_voltage_table))); 411 412 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD); 413 PP_ASSERT_WITH_CODE( 414 (data->mvdd_voltage_table.count <= tmp), 415 "Too many voltage values for MVDD. Trimming to fit state table.", 416 phm_trim_voltage_table_to_fit_state_table(tmp, 417 &(data->mvdd_voltage_table))); 418 419 return 0; 420 } 421 422 /** 423 * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters 424 * 425 * @hwmgr: the address of the powerplay hardware manager. 426 * Return: always 0 427 */ 428 static int smu7_program_static_screen_threshold_parameters( 429 struct pp_hwmgr *hwmgr) 430 { 431 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 432 433 /* Set static screen threshold unit */ 434 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 435 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, 436 data->static_screen_threshold_unit); 437 /* Set static screen threshold */ 438 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 439 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, 440 data->static_screen_threshold); 441 442 return 0; 443 } 444 445 /** 446 * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching. 447 * 448 * @hwmgr: the address of the powerplay hardware manager. 449 * Return: always 0 450 */ 451 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) 452 { 453 uint32_t display_gap = 454 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 455 ixCG_DISPLAY_GAP_CNTL); 456 457 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 458 DISP_GAP, DISPLAY_GAP_IGNORE); 459 460 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 461 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); 462 463 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 464 ixCG_DISPLAY_GAP_CNTL, display_gap); 465 466 return 0; 467 } 468 469 /** 470 * smu7_program_voting_clients - Programs activity state transition voting clients 471 * 472 * @hwmgr: the address of the powerplay hardware manager. 473 * Return: always 0 474 */ 475 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) 476 { 477 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 478 int i; 479 480 /* Clear reset for voting clients before enabling DPM */ 481 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 482 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); 483 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 484 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); 485 486 for (i = 0; i < 8; i++) 487 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 488 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 489 data->voting_rights_clients[i]); 490 return 0; 491 } 492 493 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) 494 { 495 int i; 496 497 /* Reset voting clients before disabling DPM */ 498 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 499 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); 500 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 501 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); 502 503 for (i = 0; i < 8; i++) 504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 505 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0); 506 507 return 0; 508 } 509 510 /* Copy one arb setting to another and then switch the active set. 511 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. 512 */ 513 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, 514 uint32_t arb_src, uint32_t arb_dest) 515 { 516 uint32_t mc_arb_dram_timing; 517 uint32_t mc_arb_dram_timing2; 518 uint32_t burst_time; 519 uint32_t mc_cg_config; 520 521 switch (arb_src) { 522 case MC_CG_ARB_FREQ_F0: 523 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 524 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 525 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); 526 break; 527 case MC_CG_ARB_FREQ_F1: 528 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); 529 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); 530 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); 531 break; 532 default: 533 return -EINVAL; 534 } 535 536 switch (arb_dest) { 537 case MC_CG_ARB_FREQ_F0: 538 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); 539 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 540 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); 541 break; 542 case MC_CG_ARB_FREQ_F1: 543 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 544 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 545 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); 552 mc_cg_config |= 0x0000000F; 553 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); 554 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); 555 556 return 0; 557 } 558 559 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) 560 { 561 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults, NULL); 562 } 563 564 /** 565 * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1 566 * 567 * @hwmgr: the address of the powerplay hardware manager. 568 * Return: always 0 569 * This function is to be called from the SetPowerState table. 570 */ 571 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) 572 { 573 return smu7_copy_and_switch_arb_sets(hwmgr, 574 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 575 } 576 577 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) 578 { 579 uint32_t tmp; 580 581 tmp = (cgs_read_ind_register(hwmgr->device, 582 CGS_IND_REG__SMC, ixSMC_SCRATCH9) & 583 0x0000ff00) >> 8; 584 585 if (tmp == MC_CG_ARB_FREQ_F0) 586 return 0; 587 588 return smu7_copy_and_switch_arb_sets(hwmgr, 589 tmp, MC_CG_ARB_FREQ_F0); 590 } 591 592 static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr) 593 { 594 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 595 uint16_t pcie_gen = 0; 596 597 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 && 598 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4) 599 pcie_gen = 3; 600 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 && 601 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 602 pcie_gen = 2; 603 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 && 604 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2) 605 pcie_gen = 1; 606 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 && 607 adev->pm.pcie_gen_mask & CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1) 608 pcie_gen = 0; 609 610 return pcie_gen; 611 } 612 613 static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr) 614 { 615 struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); 616 uint16_t pcie_width = 0; 617 618 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 619 pcie_width = 16; 620 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12) 621 pcie_width = 12; 622 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8) 623 pcie_width = 8; 624 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4) 625 pcie_width = 4; 626 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2) 627 pcie_width = 2; 628 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1) 629 pcie_width = 1; 630 631 return pcie_width; 632 } 633 634 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 635 { 636 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 637 638 struct phm_ppt_v1_information *table_info = 639 (struct phm_ppt_v1_information *)(hwmgr->pptable); 640 struct phm_ppt_v1_pcie_table *pcie_table = NULL; 641 642 uint32_t i, max_entry; 643 uint32_t tmp; 644 645 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || 646 data->use_pcie_power_saving_levels), "No pcie performance levels!", 647 return -EINVAL); 648 649 if (table_info != NULL) 650 pcie_table = table_info->pcie_table; 651 652 if (data->use_pcie_performance_levels && 653 !data->use_pcie_power_saving_levels) { 654 data->pcie_gen_power_saving = data->pcie_gen_performance; 655 data->pcie_lane_power_saving = data->pcie_lane_performance; 656 } else if (!data->use_pcie_performance_levels && 657 data->use_pcie_power_saving_levels) { 658 data->pcie_gen_performance = data->pcie_gen_power_saving; 659 data->pcie_lane_performance = data->pcie_lane_power_saving; 660 } 661 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK); 662 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, 663 tmp, 664 MAX_REGULAR_DPM_NUMBER); 665 666 if (pcie_table != NULL) { 667 /* max_entry is used to make sure we reserve one PCIE level 668 * for boot level (fix for A+A PSPP issue). 669 * If PCIE table from PPTable have ULV entry + 8 entries, 670 * then ignore the last entry.*/ 671 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count; 672 for (i = 1; i < max_entry; i++) { 673 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, 674 get_pcie_gen_support(data->pcie_gen_cap, 675 pcie_table->entries[i].gen_speed), 676 get_pcie_lane_support(data->pcie_lane_cap, 677 pcie_table->entries[i].lane_width)); 678 } 679 data->dpm_table.pcie_speed_table.count = max_entry - 1; 680 smum_update_smc_table(hwmgr, SMU_BIF_TABLE); 681 } else { 682 /* Hardcode Pcie Table */ 683 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, 684 get_pcie_gen_support(data->pcie_gen_cap, 685 PP_Min_PCIEGen), 686 get_pcie_lane_support(data->pcie_lane_cap, 687 PP_Max_PCIELane)); 688 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, 689 get_pcie_gen_support(data->pcie_gen_cap, 690 PP_Min_PCIEGen), 691 get_pcie_lane_support(data->pcie_lane_cap, 692 PP_Max_PCIELane)); 693 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, 694 get_pcie_gen_support(data->pcie_gen_cap, 695 PP_Max_PCIEGen), 696 get_pcie_lane_support(data->pcie_lane_cap, 697 PP_Max_PCIELane)); 698 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, 699 get_pcie_gen_support(data->pcie_gen_cap, 700 PP_Max_PCIEGen), 701 get_pcie_lane_support(data->pcie_lane_cap, 702 PP_Max_PCIELane)); 703 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, 704 get_pcie_gen_support(data->pcie_gen_cap, 705 PP_Max_PCIEGen), 706 get_pcie_lane_support(data->pcie_lane_cap, 707 PP_Max_PCIELane)); 708 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, 709 get_pcie_gen_support(data->pcie_gen_cap, 710 PP_Max_PCIEGen), 711 get_pcie_lane_support(data->pcie_lane_cap, 712 PP_Max_PCIELane)); 713 714 data->dpm_table.pcie_speed_table.count = 6; 715 } 716 /* Populate last level for boot PCIE level, but do not increment count. */ 717 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 718 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) 719 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i, 720 get_pcie_gen_support(data->pcie_gen_cap, 721 PP_Max_PCIEGen), 722 data->vbios_boot_state.pcie_lane_bootup_value); 723 } else { 724 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 725 data->dpm_table.pcie_speed_table.count, 726 get_pcie_gen_support(data->pcie_gen_cap, 727 PP_Min_PCIEGen), 728 get_pcie_lane_support(data->pcie_lane_cap, 729 PP_Max_PCIELane)); 730 731 if (data->pcie_dpm_key_disabled) 732 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 733 data->dpm_table.pcie_speed_table.count, 734 smu7_override_pcie_speed(hwmgr), smu7_override_pcie_width(hwmgr)); 735 } 736 return 0; 737 } 738 739 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) 740 { 741 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 742 743 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); 744 745 phm_reset_single_dpm_table( 746 &data->dpm_table.sclk_table, 747 smum_get_mac_definition(hwmgr, 748 SMU_MAX_LEVELS_GRAPHICS), 749 MAX_REGULAR_DPM_NUMBER); 750 phm_reset_single_dpm_table( 751 &data->dpm_table.mclk_table, 752 smum_get_mac_definition(hwmgr, 753 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); 754 755 phm_reset_single_dpm_table( 756 &data->dpm_table.vddc_table, 757 smum_get_mac_definition(hwmgr, 758 SMU_MAX_LEVELS_VDDC), 759 MAX_REGULAR_DPM_NUMBER); 760 phm_reset_single_dpm_table( 761 &data->dpm_table.vddci_table, 762 smum_get_mac_definition(hwmgr, 763 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); 764 765 phm_reset_single_dpm_table( 766 &data->dpm_table.mvdd_table, 767 smum_get_mac_definition(hwmgr, 768 SMU_MAX_LEVELS_MVDD), 769 MAX_REGULAR_DPM_NUMBER); 770 return 0; 771 } 772 /* 773 * This function is to initialize all DPM state tables 774 * for SMU7 based on the dependency table. 775 * Dynamic state patching function will then trim these 776 * state tables to the allowed range based 777 * on the power policy or external client requests, 778 * such as UVD request, etc. 779 */ 780 781 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) 782 { 783 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 784 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table = 785 hwmgr->dyn_state.vddc_dependency_on_sclk; 786 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table = 787 hwmgr->dyn_state.vddc_dependency_on_mclk; 788 struct phm_cac_leakage_table *std_voltage_table = 789 hwmgr->dyn_state.cac_leakage_table; 790 uint32_t i; 791 792 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, 793 "SCLK dependency table is missing. This table is mandatory", return -EINVAL); 794 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, 795 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 796 797 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 798 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 799 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, 800 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 801 802 803 /* Initialize Sclk DPM table based on allow Sclk values*/ 804 data->dpm_table.sclk_table.count = 0; 805 806 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 807 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != 808 allowed_vdd_sclk_table->entries[i].clk) { 809 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 810 allowed_vdd_sclk_table->entries[i].clk; 811 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; 812 data->dpm_table.sclk_table.count++; 813 } 814 } 815 816 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 817 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 818 /* Initialize Mclk DPM table based on allow Mclk values */ 819 data->dpm_table.mclk_table.count = 0; 820 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 821 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != 822 allowed_vdd_mclk_table->entries[i].clk) { 823 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 824 allowed_vdd_mclk_table->entries[i].clk; 825 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; 826 data->dpm_table.mclk_table.count++; 827 } 828 } 829 830 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ 831 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 832 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 833 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; 834 /* param1 is for corresponding std voltage */ 835 data->dpm_table.vddc_table.dpm_levels[i].enabled = true; 836 } 837 838 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; 839 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 840 841 if (NULL != allowed_vdd_mclk_table) { 842 /* Initialize Vddci DPM table based on allow Mclk values */ 843 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 844 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 845 data->dpm_table.vddci_table.dpm_levels[i].enabled = true; 846 } 847 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count; 848 } 849 850 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; 851 852 if (NULL != allowed_vdd_mclk_table) { 853 /* 854 * Initialize MVDD DPM table based on allow Mclk 855 * values 856 */ 857 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 858 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 859 data->dpm_table.mvdd_table.dpm_levels[i].enabled = true; 860 } 861 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; 862 } 863 864 return 0; 865 } 866 867 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) 868 { 869 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 870 struct phm_ppt_v1_information *table_info = 871 (struct phm_ppt_v1_information *)(hwmgr->pptable); 872 uint32_t i; 873 874 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 875 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 876 877 if (table_info == NULL) 878 return -EINVAL; 879 880 dep_sclk_table = table_info->vdd_dep_on_sclk; 881 dep_mclk_table = table_info->vdd_dep_on_mclk; 882 883 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, 884 "SCLK dependency table is missing.", 885 return -EINVAL); 886 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, 887 "SCLK dependency table count is 0.", 888 return -EINVAL); 889 890 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, 891 "MCLK dependency table is missing.", 892 return -EINVAL); 893 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 894 "MCLK dependency table count is 0", 895 return -EINVAL); 896 897 /* Initialize Sclk DPM table based on allow Sclk values */ 898 data->dpm_table.sclk_table.count = 0; 899 for (i = 0; i < dep_sclk_table->count; i++) { 900 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != 901 dep_sclk_table->entries[i].clk) { 902 903 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 904 dep_sclk_table->entries[i].clk; 905 906 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 907 (i == 0) ? true : false; 908 data->dpm_table.sclk_table.count++; 909 } 910 } 911 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 912 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; 913 /* Initialize Mclk DPM table based on allow Mclk values */ 914 data->dpm_table.mclk_table.count = 0; 915 for (i = 0; i < dep_mclk_table->count; i++) { 916 if (i == 0 || data->dpm_table.mclk_table.dpm_levels 917 [data->dpm_table.mclk_table.count - 1].value != 918 dep_mclk_table->entries[i].clk) { 919 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 920 dep_mclk_table->entries[i].clk; 921 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 922 (i == 0) ? true : false; 923 data->dpm_table.mclk_table.count++; 924 } 925 } 926 927 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 928 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; 929 return 0; 930 } 931 932 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 933 { 934 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 935 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 936 struct phm_ppt_v1_information *table_info = 937 (struct phm_ppt_v1_information *)(hwmgr->pptable); 938 uint32_t i; 939 940 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 941 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 942 struct phm_odn_performance_level *entries; 943 944 if (table_info == NULL) 945 return -EINVAL; 946 947 dep_sclk_table = table_info->vdd_dep_on_sclk; 948 dep_mclk_table = table_info->vdd_dep_on_mclk; 949 950 odn_table->odn_core_clock_dpm_levels.num_of_pl = 951 data->golden_dpm_table.sclk_table.count; 952 entries = odn_table->odn_core_clock_dpm_levels.entries; 953 for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) { 954 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; 955 entries[i].enabled = true; 956 entries[i].vddc = dep_sclk_table->entries[i].vddc; 957 } 958 959 smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table, 960 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk)); 961 962 odn_table->odn_memory_clock_dpm_levels.num_of_pl = 963 data->golden_dpm_table.mclk_table.count; 964 entries = odn_table->odn_memory_clock_dpm_levels.entries; 965 for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) { 966 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; 967 entries[i].enabled = true; 968 entries[i].vddc = dep_mclk_table->entries[i].vddc; 969 } 970 971 smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table, 972 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk)); 973 974 return 0; 975 } 976 977 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr) 978 { 979 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 980 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 981 struct phm_ppt_v1_information *table_info = 982 (struct phm_ppt_v1_information *)(hwmgr->pptable); 983 uint32_t min_vddc = 0; 984 uint32_t max_vddc = 0; 985 986 if (!table_info) 987 return; 988 989 dep_sclk_table = table_info->vdd_dep_on_sclk; 990 991 atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc); 992 993 if (min_vddc == 0 || min_vddc > 2000 994 || min_vddc > dep_sclk_table->entries[0].vddc) 995 min_vddc = dep_sclk_table->entries[0].vddc; 996 997 if (max_vddc == 0 || max_vddc > 2000 998 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) 999 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; 1000 1001 data->odn_dpm_table.min_vddc = min_vddc; 1002 data->odn_dpm_table.max_vddc = max_vddc; 1003 } 1004 1005 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 1006 { 1007 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1008 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 1009 struct phm_ppt_v1_information *table_info = 1010 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1011 uint32_t i; 1012 1013 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 1014 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 1015 1016 if (table_info == NULL) 1017 return; 1018 1019 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { 1020 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock != 1021 data->dpm_table.sclk_table.dpm_levels[i].value) { 1022 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 1023 break; 1024 } 1025 } 1026 1027 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 1028 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock != 1029 data->dpm_table.mclk_table.dpm_levels[i].value) { 1030 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 1031 break; 1032 } 1033 } 1034 1035 dep_table = table_info->vdd_dep_on_mclk; 1036 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk); 1037 1038 for (i = 0; i < dep_table->count; i++) { 1039 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 1040 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 1041 return; 1042 } 1043 } 1044 1045 dep_table = table_info->vdd_dep_on_sclk; 1046 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); 1047 for (i = 0; i < dep_table->count; i++) { 1048 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 1049 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 1050 return; 1051 } 1052 } 1053 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1054 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; 1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 1056 } 1057 } 1058 1059 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 1060 { 1061 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1062 1063 smu7_reset_dpm_tables(hwmgr); 1064 1065 if (hwmgr->pp_table_version == PP_TABLE_V1) 1066 smu7_setup_dpm_tables_v1(hwmgr); 1067 else if (hwmgr->pp_table_version == PP_TABLE_V0) 1068 smu7_setup_dpm_tables_v0(hwmgr); 1069 1070 smu7_setup_default_pcie_table(hwmgr); 1071 1072 /* save a copy of the default DPM table */ 1073 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 1074 sizeof(struct smu7_dpm_table)); 1075 1076 /* initialize ODN table */ 1077 if (hwmgr->od_enabled) { 1078 if (data->odn_dpm_table.max_vddc) { 1079 smu7_check_dpm_table_updated(hwmgr); 1080 } else { 1081 smu7_setup_voltage_range_from_vbios(hwmgr); 1082 smu7_odn_initial_default_setting(hwmgr); 1083 } 1084 } 1085 return 0; 1086 } 1087 1088 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) 1089 { 1090 1091 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1092 PHM_PlatformCaps_RegulatorHot)) 1093 return smum_send_msg_to_smc(hwmgr, 1094 PPSMC_MSG_EnableVRHotGPIOInterrupt, 1095 NULL); 1096 1097 return 0; 1098 } 1099 1100 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) 1101 { 1102 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1103 SCLK_PWRMGT_OFF, 0); 1104 return 0; 1105 } 1106 1107 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) 1108 { 1109 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1110 1111 if (data->ulv_supported) 1112 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV, NULL); 1113 1114 return 0; 1115 } 1116 1117 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) 1118 { 1119 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1120 1121 if (data->ulv_supported) 1122 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV, NULL); 1123 1124 return 0; 1125 } 1126 1127 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1128 { 1129 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1130 PHM_PlatformCaps_SclkDeepSleep)) { 1131 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON, NULL)) 1132 PP_ASSERT_WITH_CODE(false, 1133 "Attempt to enable Master Deep Sleep switch failed!", 1134 return -EINVAL); 1135 } else { 1136 if (smum_send_msg_to_smc(hwmgr, 1137 PPSMC_MSG_MASTER_DeepSleep_OFF, 1138 NULL)) { 1139 PP_ASSERT_WITH_CODE(false, 1140 "Attempt to disable Master Deep Sleep switch failed!", 1141 return -EINVAL); 1142 } 1143 } 1144 1145 return 0; 1146 } 1147 1148 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1149 { 1150 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1151 PHM_PlatformCaps_SclkDeepSleep)) { 1152 if (smum_send_msg_to_smc(hwmgr, 1153 PPSMC_MSG_MASTER_DeepSleep_OFF, 1154 NULL)) { 1155 PP_ASSERT_WITH_CODE(false, 1156 "Attempt to disable Master Deep Sleep switch failed!", 1157 return -EINVAL); 1158 } 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr) 1165 { 1166 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1167 uint32_t soft_register_value = 0; 1168 uint32_t handshake_disables_offset = data->soft_regs_start 1169 + smum_get_offsetof(hwmgr, 1170 SMU_SoftRegisters, HandshakeDisables); 1171 1172 soft_register_value = cgs_read_ind_register(hwmgr->device, 1173 CGS_IND_REG__SMC, handshake_disables_offset); 1174 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE; 1175 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1176 handshake_disables_offset, soft_register_value); 1177 return 0; 1178 } 1179 1180 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) 1181 { 1182 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1183 uint32_t soft_register_value = 0; 1184 uint32_t handshake_disables_offset = data->soft_regs_start 1185 + smum_get_offsetof(hwmgr, 1186 SMU_SoftRegisters, HandshakeDisables); 1187 1188 soft_register_value = cgs_read_ind_register(hwmgr->device, 1189 CGS_IND_REG__SMC, handshake_disables_offset); 1190 soft_register_value |= smum_get_mac_definition(hwmgr, 1191 SMU_UVD_MCLK_HANDSHAKE_DISABLE); 1192 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1193 handshake_disables_offset, soft_register_value); 1194 return 0; 1195 } 1196 1197 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1198 { 1199 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1200 1201 /* enable SCLK dpm */ 1202 if (!data->sclk_dpm_key_disabled) { 1203 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1204 hwmgr->chip_id <= CHIP_VEGAM) 1205 smu7_disable_sclk_vce_handshake(hwmgr); 1206 1207 PP_ASSERT_WITH_CODE( 1208 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable, NULL)), 1209 "Failed to enable SCLK DPM during DPM Start Function!", 1210 return -EINVAL); 1211 } 1212 1213 /* enable MCLK dpm */ 1214 if (0 == data->mclk_dpm_key_disabled) { 1215 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) 1216 smu7_disable_handshake_uvd(hwmgr); 1217 1218 PP_ASSERT_WITH_CODE( 1219 (0 == smum_send_msg_to_smc(hwmgr, 1220 PPSMC_MSG_MCLKDPM_Enable, 1221 NULL)), 1222 "Failed to enable MCLK DPM during DPM Start Function!", 1223 return -EINVAL); 1224 1225 if ((hwmgr->chip_family == AMDGPU_FAMILY_CI) || 1226 (hwmgr->chip_id == CHIP_POLARIS10) || 1227 (hwmgr->chip_id == CHIP_POLARIS11) || 1228 (hwmgr->chip_id == CHIP_POLARIS12) || 1229 (hwmgr->chip_id == CHIP_TONGA) || 1230 (hwmgr->chip_id == CHIP_TOPAZ)) 1231 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); 1232 1233 1234 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1235 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); 1236 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); 1237 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); 1238 udelay(10); 1239 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); 1240 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); 1241 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005); 1242 } else { 1243 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); 1244 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); 1245 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); 1246 udelay(10); 1247 if (hwmgr->chip_id == CHIP_VEGAM) { 1248 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009); 1249 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009); 1250 } else { 1251 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); 1252 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); 1253 } 1254 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); 1255 } 1256 } 1257 1258 return 0; 1259 } 1260 1261 static int smu7_start_dpm(struct pp_hwmgr *hwmgr) 1262 { 1263 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1264 1265 /*enable general power management */ 1266 1267 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1268 GLOBAL_PWRMGT_EN, 1); 1269 1270 /* enable sclk deep sleep */ 1271 1272 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1273 DYNAMIC_PM_EN, 1); 1274 1275 /* prepare for PCIE DPM */ 1276 1277 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1278 data->soft_regs_start + 1279 smum_get_offsetof(hwmgr, SMU_SoftRegisters, 1280 VoltageChangeTimeout), 0x1000); 1281 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 1282 SWRST_COMMAND_1, RESETLC, 0x0); 1283 1284 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) 1285 cgs_write_register(hwmgr->device, 0x1488, 1286 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); 1287 1288 if (smu7_enable_sclk_mclk_dpm(hwmgr)) { 1289 pr_err("Failed to enable Sclk DPM and Mclk DPM!"); 1290 return -EINVAL; 1291 } 1292 1293 /* enable PCIE dpm */ 1294 if (0 == data->pcie_dpm_key_disabled) { 1295 PP_ASSERT_WITH_CODE( 1296 (0 == smum_send_msg_to_smc(hwmgr, 1297 PPSMC_MSG_PCIeDPM_Enable, 1298 NULL)), 1299 "Failed to enable pcie DPM during DPM Start Function!", 1300 return -EINVAL); 1301 } else { 1302 PP_ASSERT_WITH_CODE( 1303 (0 == smum_send_msg_to_smc(hwmgr, 1304 PPSMC_MSG_PCIeDPM_Disable, 1305 NULL)), 1306 "Failed to disable pcie DPM during DPM Start Function!", 1307 return -EINVAL); 1308 } 1309 1310 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1311 PHM_PlatformCaps_Falcon_QuickTransition)) { 1312 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, 1313 PPSMC_MSG_EnableACDCGPIOInterrupt, 1314 NULL)), 1315 "Failed to enable AC DC GPIO Interrupt!", 1316 ); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1323 { 1324 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1325 1326 /* disable SCLK dpm */ 1327 if (!data->sclk_dpm_key_disabled) { 1328 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1329 "Trying to disable SCLK DPM when DPM is disabled", 1330 return 0); 1331 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable, NULL); 1332 } 1333 1334 /* disable MCLK dpm */ 1335 if (!data->mclk_dpm_key_disabled) { 1336 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1337 "Trying to disable MCLK DPM when DPM is disabled", 1338 return 0); 1339 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable, NULL); 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) 1346 { 1347 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1348 1349 /* disable general power management */ 1350 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1351 GLOBAL_PWRMGT_EN, 0); 1352 /* disable sclk deep sleep */ 1353 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1354 DYNAMIC_PM_EN, 0); 1355 1356 /* disable PCIE dpm */ 1357 if (!data->pcie_dpm_key_disabled) { 1358 PP_ASSERT_WITH_CODE( 1359 (smum_send_msg_to_smc(hwmgr, 1360 PPSMC_MSG_PCIeDPM_Disable, 1361 NULL) == 0), 1362 "Failed to disable pcie DPM during DPM Stop Function!", 1363 return -EINVAL); 1364 } 1365 1366 smu7_disable_sclk_mclk_dpm(hwmgr); 1367 1368 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1369 "Trying to disable voltage DPM when DPM is disabled", 1370 return 0); 1371 1372 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable, NULL); 1373 1374 return 0; 1375 } 1376 1377 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) 1378 { 1379 bool protection; 1380 enum DPM_EVENT_SRC src; 1381 1382 switch (sources) { 1383 default: 1384 pr_err("Unknown throttling event sources."); 1385 fallthrough; 1386 case 0: 1387 protection = false; 1388 /* src is unused */ 1389 break; 1390 case (1 << PHM_AutoThrottleSource_Thermal): 1391 protection = true; 1392 src = DPM_EVENT_SRC_DIGITAL; 1393 break; 1394 case (1 << PHM_AutoThrottleSource_External): 1395 protection = true; 1396 src = DPM_EVENT_SRC_EXTERNAL; 1397 break; 1398 case (1 << PHM_AutoThrottleSource_External) | 1399 (1 << PHM_AutoThrottleSource_Thermal): 1400 protection = true; 1401 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; 1402 break; 1403 } 1404 /* Order matters - don't enable thermal protection for the wrong source. */ 1405 if (protection) { 1406 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, 1407 DPM_EVENT_SRC, src); 1408 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1409 THERMAL_PROTECTION_DIS, 1410 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1411 PHM_PlatformCaps_ThermalController)); 1412 } else 1413 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1414 THERMAL_PROTECTION_DIS, 1); 1415 } 1416 1417 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1418 PHM_AutoThrottleSource source) 1419 { 1420 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1421 1422 if (!(data->active_auto_throttle_sources & (1 << source))) { 1423 data->active_auto_throttle_sources |= 1 << source; 1424 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1425 } 1426 return 0; 1427 } 1428 1429 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1430 { 1431 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1432 } 1433 1434 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1435 PHM_AutoThrottleSource source) 1436 { 1437 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1438 1439 if (data->active_auto_throttle_sources & (1 << source)) { 1440 data->active_auto_throttle_sources &= ~(1 << source); 1441 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1442 } 1443 return 0; 1444 } 1445 1446 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1447 { 1448 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1449 } 1450 1451 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) 1452 { 1453 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1454 data->pcie_performance_request = true; 1455 1456 return 0; 1457 } 1458 1459 static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr, 1460 uint32_t *cac_config_regs, 1461 AtomCtrl_EDCLeakgeTable *edc_leakage_table) 1462 { 1463 uint32_t data, i = 0; 1464 1465 while (cac_config_regs[i] != 0xFFFFFFFF) { 1466 data = edc_leakage_table->DIDT_REG[i]; 1467 cgs_write_ind_register(hwmgr->device, 1468 CGS_IND_REG__DIDT, 1469 cac_config_regs[i], 1470 data); 1471 i++; 1472 } 1473 1474 return 0; 1475 } 1476 1477 static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr) 1478 { 1479 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1480 int ret = 0; 1481 1482 if (!data->disable_edc_leakage_controller && 1483 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset && 1484 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) { 1485 ret = smu7_program_edc_didt_registers(hwmgr, 1486 DIDTEDCConfig_P12, 1487 &data->edc_leakage_table); 1488 if (ret) 1489 return ret; 1490 1491 ret = smum_send_msg_to_smc(hwmgr, 1492 (PPSMC_Msg)PPSMC_MSG_EnableEDCController, 1493 NULL); 1494 } else { 1495 ret = smum_send_msg_to_smc(hwmgr, 1496 (PPSMC_Msg)PPSMC_MSG_DisableEDCController, 1497 NULL); 1498 } 1499 1500 return ret; 1501 } 1502 1503 static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 1504 { 1505 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1506 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 1507 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk = 1508 hwmgr->dyn_state.vddc_dependency_on_sclk; 1509 struct phm_ppt_v1_information *table_info = 1510 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1511 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk = 1512 table_info->vdd_dep_on_sclk; 1513 int32_t tmp_sclk, count, percentage; 1514 1515 if (golden_dpm_table->mclk_table.count == 1) { 1516 percentage = 70; 1517 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[0].value; 1518 } else { 1519 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 1520 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1521 hwmgr->pstate_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 1522 } 1523 1524 tmp_sclk = hwmgr->pstate_mclk * percentage / 100; 1525 1526 if (hwmgr->pp_table_version == PP_TABLE_V0) { 1527 for (count = vddc_dependency_on_sclk->count - 1; count >= 0; count--) { 1528 if (tmp_sclk >= vddc_dependency_on_sclk->entries[count].clk) { 1529 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[count].clk; 1530 break; 1531 } 1532 } 1533 if (count < 0) 1534 hwmgr->pstate_sclk = vddc_dependency_on_sclk->entries[0].clk; 1535 1536 hwmgr->pstate_sclk_peak = 1537 vddc_dependency_on_sclk->entries[vddc_dependency_on_sclk->count - 1].clk; 1538 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 1539 for (count = vdd_dep_on_sclk->count - 1; count >= 0; count--) { 1540 if (tmp_sclk >= vdd_dep_on_sclk->entries[count].clk) { 1541 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[count].clk; 1542 break; 1543 } 1544 } 1545 if (count < 0) 1546 hwmgr->pstate_sclk = vdd_dep_on_sclk->entries[0].clk; 1547 1548 hwmgr->pstate_sclk_peak = 1549 vdd_dep_on_sclk->entries[vdd_dep_on_sclk->count - 1].clk; 1550 } 1551 1552 hwmgr->pstate_mclk_peak = 1553 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 1554 1555 /* make sure the output is in Mhz */ 1556 hwmgr->pstate_sclk /= 100; 1557 hwmgr->pstate_mclk /= 100; 1558 hwmgr->pstate_sclk_peak /= 100; 1559 hwmgr->pstate_mclk_peak /= 100; 1560 } 1561 1562 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1563 { 1564 int tmp_result = 0; 1565 int result = 0; 1566 1567 if (smu7_voltage_control(hwmgr)) { 1568 tmp_result = smu7_enable_voltage_control(hwmgr); 1569 PP_ASSERT_WITH_CODE(tmp_result == 0, 1570 "Failed to enable voltage control!", 1571 result = tmp_result); 1572 1573 tmp_result = smu7_construct_voltage_tables(hwmgr); 1574 PP_ASSERT_WITH_CODE((0 == tmp_result), 1575 "Failed to construct voltage tables!", 1576 result = tmp_result); 1577 } 1578 smum_initialize_mc_reg_table(hwmgr); 1579 1580 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1581 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) 1582 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1583 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); 1584 1585 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1586 PHM_PlatformCaps_ThermalController)) 1587 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1588 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); 1589 1590 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr); 1591 PP_ASSERT_WITH_CODE((0 == tmp_result), 1592 "Failed to program static screen threshold parameters!", 1593 result = tmp_result); 1594 1595 tmp_result = smu7_enable_display_gap(hwmgr); 1596 PP_ASSERT_WITH_CODE((0 == tmp_result), 1597 "Failed to enable display gap!", result = tmp_result); 1598 1599 tmp_result = smu7_program_voting_clients(hwmgr); 1600 PP_ASSERT_WITH_CODE((0 == tmp_result), 1601 "Failed to program voting clients!", result = tmp_result); 1602 1603 tmp_result = smum_process_firmware_header(hwmgr); 1604 PP_ASSERT_WITH_CODE((0 == tmp_result), 1605 "Failed to process firmware header!", result = tmp_result); 1606 1607 if (hwmgr->chip_id != CHIP_VEGAM) { 1608 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr); 1609 PP_ASSERT_WITH_CODE((0 == tmp_result), 1610 "Failed to initialize switch from ArbF0 to F1!", 1611 result = tmp_result); 1612 } 1613 1614 result = smu7_setup_default_dpm_tables(hwmgr); 1615 PP_ASSERT_WITH_CODE(0 == result, 1616 "Failed to setup default DPM tables!", return result); 1617 1618 tmp_result = smum_init_smc_table(hwmgr); 1619 PP_ASSERT_WITH_CODE((0 == tmp_result), 1620 "Failed to initialize SMC table!", result = tmp_result); 1621 1622 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr); 1623 PP_ASSERT_WITH_CODE((0 == tmp_result), 1624 "Failed to enable VR hot GPIO interrupt!", result = tmp_result); 1625 1626 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1627 hwmgr->chip_id <= CHIP_VEGAM) { 1628 tmp_result = smu7_notify_has_display(hwmgr); 1629 PP_ASSERT_WITH_CODE((0 == tmp_result), 1630 "Failed to enable display setting!", result = tmp_result); 1631 } else { 1632 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL); 1633 } 1634 1635 if (hwmgr->chip_id >= CHIP_POLARIS10 && 1636 hwmgr->chip_id <= CHIP_VEGAM) { 1637 tmp_result = smu7_populate_edc_leakage_registers(hwmgr); 1638 PP_ASSERT_WITH_CODE((0 == tmp_result), 1639 "Failed to populate edc leakage registers!", result = tmp_result); 1640 } 1641 1642 tmp_result = smu7_enable_sclk_control(hwmgr); 1643 PP_ASSERT_WITH_CODE((0 == tmp_result), 1644 "Failed to enable SCLK control!", result = tmp_result); 1645 1646 tmp_result = smu7_enable_smc_voltage_controller(hwmgr); 1647 PP_ASSERT_WITH_CODE((0 == tmp_result), 1648 "Failed to enable voltage control!", result = tmp_result); 1649 1650 tmp_result = smu7_enable_ulv(hwmgr); 1651 PP_ASSERT_WITH_CODE((0 == tmp_result), 1652 "Failed to enable ULV!", result = tmp_result); 1653 1654 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr); 1655 PP_ASSERT_WITH_CODE((0 == tmp_result), 1656 "Failed to enable deep sleep master switch!", result = tmp_result); 1657 1658 tmp_result = smu7_enable_didt_config(hwmgr); 1659 PP_ASSERT_WITH_CODE((tmp_result == 0), 1660 "Failed to enable deep sleep master switch!", result = tmp_result); 1661 1662 tmp_result = smu7_start_dpm(hwmgr); 1663 PP_ASSERT_WITH_CODE((0 == tmp_result), 1664 "Failed to start DPM!", result = tmp_result); 1665 1666 tmp_result = smu7_enable_smc_cac(hwmgr); 1667 PP_ASSERT_WITH_CODE((0 == tmp_result), 1668 "Failed to enable SMC CAC!", result = tmp_result); 1669 1670 tmp_result = smu7_enable_power_containment(hwmgr); 1671 PP_ASSERT_WITH_CODE((0 == tmp_result), 1672 "Failed to enable power containment!", result = tmp_result); 1673 1674 tmp_result = smu7_power_control_set_level(hwmgr); 1675 PP_ASSERT_WITH_CODE((0 == tmp_result), 1676 "Failed to power control set level!", result = tmp_result); 1677 1678 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr); 1679 PP_ASSERT_WITH_CODE((0 == tmp_result), 1680 "Failed to enable thermal auto throttle!", result = tmp_result); 1681 1682 tmp_result = smu7_pcie_performance_request(hwmgr); 1683 PP_ASSERT_WITH_CODE((0 == tmp_result), 1684 "pcie performance request failed!", result = tmp_result); 1685 1686 smu7_populate_umdpstate_clocks(hwmgr); 1687 1688 return 0; 1689 } 1690 1691 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 1692 { 1693 if (!hwmgr->avfs_supported) 1694 return 0; 1695 1696 if (enable) { 1697 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1698 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1699 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1700 hwmgr, PPSMC_MSG_EnableAvfs, NULL), 1701 "Failed to enable AVFS!", 1702 return -EINVAL); 1703 } 1704 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1705 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1706 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1707 hwmgr, PPSMC_MSG_DisableAvfs, NULL), 1708 "Failed to disable AVFS!", 1709 return -EINVAL); 1710 } 1711 1712 return 0; 1713 } 1714 1715 static int smu7_update_avfs(struct pp_hwmgr *hwmgr) 1716 { 1717 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1718 1719 if (!hwmgr->avfs_supported) 1720 return 0; 1721 1722 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1723 smu7_avfs_control(hwmgr, false); 1724 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 1725 smu7_avfs_control(hwmgr, false); 1726 smu7_avfs_control(hwmgr, true); 1727 } else { 1728 smu7_avfs_control(hwmgr, true); 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 1735 { 1736 int tmp_result, result = 0; 1737 1738 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1739 PHM_PlatformCaps_ThermalController)) 1740 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1741 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1); 1742 1743 tmp_result = smu7_disable_power_containment(hwmgr); 1744 PP_ASSERT_WITH_CODE((tmp_result == 0), 1745 "Failed to disable power containment!", result = tmp_result); 1746 1747 tmp_result = smu7_disable_smc_cac(hwmgr); 1748 PP_ASSERT_WITH_CODE((tmp_result == 0), 1749 "Failed to disable SMC CAC!", result = tmp_result); 1750 1751 tmp_result = smu7_disable_didt_config(hwmgr); 1752 PP_ASSERT_WITH_CODE((tmp_result == 0), 1753 "Failed to disable DIDT!", result = tmp_result); 1754 1755 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1756 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0); 1757 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1758 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0); 1759 1760 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); 1761 PP_ASSERT_WITH_CODE((tmp_result == 0), 1762 "Failed to disable thermal auto throttle!", result = tmp_result); 1763 1764 tmp_result = smu7_avfs_control(hwmgr, false); 1765 PP_ASSERT_WITH_CODE((tmp_result == 0), 1766 "Failed to disable AVFS!", result = tmp_result); 1767 1768 tmp_result = smu7_stop_dpm(hwmgr); 1769 PP_ASSERT_WITH_CODE((tmp_result == 0), 1770 "Failed to stop DPM!", result = tmp_result); 1771 1772 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); 1773 PP_ASSERT_WITH_CODE((tmp_result == 0), 1774 "Failed to disable deep sleep master switch!", result = tmp_result); 1775 1776 tmp_result = smu7_disable_ulv(hwmgr); 1777 PP_ASSERT_WITH_CODE((tmp_result == 0), 1778 "Failed to disable ULV!", result = tmp_result); 1779 1780 tmp_result = smu7_clear_voting_clients(hwmgr); 1781 PP_ASSERT_WITH_CODE((tmp_result == 0), 1782 "Failed to clear voting clients!", result = tmp_result); 1783 1784 tmp_result = smu7_reset_to_default(hwmgr); 1785 PP_ASSERT_WITH_CODE((tmp_result == 0), 1786 "Failed to reset to default!", result = tmp_result); 1787 1788 tmp_result = smum_stop_smc(hwmgr); 1789 PP_ASSERT_WITH_CODE((tmp_result == 0), 1790 "Failed to stop smc!", result = tmp_result); 1791 1792 tmp_result = smu7_force_switch_to_arbf0(hwmgr); 1793 PP_ASSERT_WITH_CODE((tmp_result == 0), 1794 "Failed to force to switch arbf0!", result = tmp_result); 1795 1796 return result; 1797 } 1798 1799 static bool intel_core_rkl_chk(void) 1800 { 1801 #if IS_ENABLED(CONFIG_X86_64) 1802 struct cpuinfo_x86 *c = &cpu_data(0); 1803 1804 return (c->x86 == 6 && c->x86_model == INTEL_FAM6_ROCKETLAKE); 1805 #else 1806 return false; 1807 #endif 1808 } 1809 1810 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 1811 { 1812 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1813 struct phm_ppt_v1_information *table_info = 1814 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1815 struct amdgpu_device *adev = hwmgr->adev; 1816 uint8_t tmp1, tmp2; 1817 uint16_t tmp3 = 0; 1818 1819 data->dll_default_on = false; 1820 data->mclk_dpm0_activity_target = 0xa; 1821 data->vddc_vddgfx_delta = 300; 1822 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; 1823 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; 1824 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; 1825 data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1; 1826 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; 1827 data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3; 1828 data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4; 1829 data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5; 1830 data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6; 1831 data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7; 1832 1833 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 1834 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 1835 data->pcie_dpm_key_disabled = 1836 intel_core_rkl_chk() || !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1837 /* need to set voltage control types before EVV patching */ 1838 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; 1839 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE; 1840 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; 1841 data->enable_tdc_limit_feature = true; 1842 data->enable_pkg_pwr_tracking_feature = true; 1843 data->force_pcie_gen = PP_PCIEGenInvalid; 1844 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; 1845 data->current_profile_setting.bupdate_sclk = 1; 1846 data->current_profile_setting.sclk_up_hyst = 0; 1847 data->current_profile_setting.sclk_down_hyst = 100; 1848 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT; 1849 data->current_profile_setting.bupdate_mclk = 1; 1850 if (hwmgr->chip_id >= CHIP_POLARIS10) { 1851 if (adev->gmc.vram_width == 256) { 1852 data->current_profile_setting.mclk_up_hyst = 10; 1853 data->current_profile_setting.mclk_down_hyst = 60; 1854 data->current_profile_setting.mclk_activity = 25; 1855 } else if (adev->gmc.vram_width == 128) { 1856 data->current_profile_setting.mclk_up_hyst = 5; 1857 data->current_profile_setting.mclk_down_hyst = 16; 1858 data->current_profile_setting.mclk_activity = 20; 1859 } else if (adev->gmc.vram_width == 64) { 1860 data->current_profile_setting.mclk_up_hyst = 3; 1861 data->current_profile_setting.mclk_down_hyst = 16; 1862 data->current_profile_setting.mclk_activity = 20; 1863 } 1864 } else { 1865 data->current_profile_setting.mclk_up_hyst = 0; 1866 data->current_profile_setting.mclk_down_hyst = 100; 1867 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT; 1868 } 1869 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1870 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1871 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1872 1873 if (hwmgr->chip_id == CHIP_HAWAII) { 1874 data->thermal_temp_setting.temperature_low = 94500; 1875 data->thermal_temp_setting.temperature_high = 95000; 1876 data->thermal_temp_setting.temperature_shutdown = 104000; 1877 } else { 1878 data->thermal_temp_setting.temperature_low = 99500; 1879 data->thermal_temp_setting.temperature_high = 100000; 1880 data->thermal_temp_setting.temperature_shutdown = 104000; 1881 } 1882 1883 data->fast_watermark_threshold = 100; 1884 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1885 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 1886 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1887 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1888 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 1889 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1890 1891 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1892 PHM_PlatformCaps_ControlVDDGFX)) { 1893 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1894 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { 1895 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1896 } 1897 } 1898 1899 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1900 PHM_PlatformCaps_EnableMVDDControl)) { 1901 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1902 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 1903 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1904 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1905 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 1906 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1907 } 1908 1909 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) 1910 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1911 PHM_PlatformCaps_ControlVDDGFX); 1912 1913 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1914 PHM_PlatformCaps_ControlVDDCI)) { 1915 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1916 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 1917 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1918 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1919 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 1920 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1921 } 1922 1923 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) 1924 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1925 PHM_PlatformCaps_EnableMVDDControl); 1926 1927 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) 1928 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1929 PHM_PlatformCaps_ControlVDDCI); 1930 1931 data->vddc_phase_shed_control = 1; 1932 if ((hwmgr->chip_id == CHIP_POLARIS12) || 1933 ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) || 1934 ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 1935 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) || 1936 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) { 1937 if (data->voltage_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1938 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, 1939 &tmp3); 1940 tmp3 = (tmp3 >> 5) & 0x3; 1941 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; 1942 } 1943 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1944 data->vddc_phase_shed_control = 1; 1945 } 1946 1947 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) 1948 && (table_info->cac_dtp_table->usClockStretchAmount != 0)) 1949 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1950 PHM_PlatformCaps_ClockStretcher); 1951 1952 data->pcie_gen_performance.max = PP_PCIEGen1; 1953 data->pcie_gen_performance.min = PP_PCIEGen3; 1954 data->pcie_gen_power_saving.max = PP_PCIEGen1; 1955 data->pcie_gen_power_saving.min = PP_PCIEGen3; 1956 data->pcie_lane_performance.max = 0; 1957 data->pcie_lane_performance.min = 16; 1958 data->pcie_lane_power_saving.max = 0; 1959 data->pcie_lane_power_saving.min = 16; 1960 1961 1962 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1963 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1964 PHM_PlatformCaps_UVDPowerGating); 1965 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 1966 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1967 PHM_PlatformCaps_VCEPowerGating); 1968 1969 data->disable_edc_leakage_controller = true; 1970 if (((adev->asic_type == CHIP_POLARIS10) && hwmgr->is_kicker) || 1971 ((adev->asic_type == CHIP_POLARIS11) && hwmgr->is_kicker) || 1972 (adev->asic_type == CHIP_POLARIS12) || 1973 (adev->asic_type == CHIP_VEGAM)) 1974 data->disable_edc_leakage_controller = false; 1975 1976 if (!atomctrl_is_asic_internal_ss_supported(hwmgr)) { 1977 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1978 PHM_PlatformCaps_MemorySpreadSpectrumSupport); 1979 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1980 PHM_PlatformCaps_EngineSpreadSpectrumSupport); 1981 } 1982 1983 if ((adev->pdev->device == 0x699F) && 1984 (adev->pdev->revision == 0xCF)) { 1985 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1986 PHM_PlatformCaps_PowerContainment); 1987 data->enable_tdc_limit_feature = false; 1988 data->enable_pkg_pwr_tracking_feature = false; 1989 data->disable_edc_leakage_controller = true; 1990 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1991 PHM_PlatformCaps_ClockStretcher); 1992 } 1993 } 1994 1995 static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr) 1996 { 1997 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1998 struct amdgpu_device *adev = hwmgr->adev; 1999 uint32_t asicrev1, evv_revision, max = 0, min = 0; 2000 2001 atomctrl_read_efuse(hwmgr, STRAP_EVV_REVISION_LSB, STRAP_EVV_REVISION_MSB, 2002 &evv_revision); 2003 2004 atomctrl_read_efuse(hwmgr, 568, 579, &asicrev1); 2005 2006 if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) || 2007 ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) { 2008 min = 1200; 2009 max = 2500; 2010 } else if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 2011 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) { 2012 min = 900; 2013 max= 2100; 2014 } else if (hwmgr->chip_id == CHIP_POLARIS10) { 2015 if (adev->pdev->subsystem_vendor == 0x106B) { 2016 min = 1000; 2017 max = 2300; 2018 } else { 2019 if (evv_revision == 0) { 2020 min = 1000; 2021 max = 2300; 2022 } else if (evv_revision == 1) { 2023 if (asicrev1 == 326) { 2024 min = 1200; 2025 max = 2500; 2026 /* TODO: PATCH RO in VBIOS */ 2027 } else { 2028 min = 1200; 2029 max = 2000; 2030 } 2031 } else if (evv_revision == 2) { 2032 min = 1200; 2033 max = 2500; 2034 } 2035 } 2036 } else { 2037 min = 1100; 2038 max = 2100; 2039 } 2040 2041 data->ro_range_minimum = min; 2042 data->ro_range_maximum = max; 2043 2044 /* TODO: PATCH RO in VBIOS here */ 2045 2046 return 0; 2047 } 2048 2049 /** 2050 * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID. 2051 * 2052 * @hwmgr: the address of the powerplay hardware manager. 2053 * Return: always 0 2054 */ 2055 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) 2056 { 2057 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2058 uint16_t vv_id; 2059 uint16_t vddc = 0; 2060 uint16_t vddgfx = 0; 2061 uint16_t i, j; 2062 uint32_t sclk = 0; 2063 struct phm_ppt_v1_information *table_info = 2064 (struct phm_ppt_v1_information *)hwmgr->pptable; 2065 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; 2066 2067 if (hwmgr->chip_id == CHIP_POLARIS10 || 2068 hwmgr->chip_id == CHIP_POLARIS11 || 2069 hwmgr->chip_id == CHIP_POLARIS12) 2070 smu7_calculate_ro_range(hwmgr); 2071 2072 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2073 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2074 2075 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2076 if ((hwmgr->pp_table_version == PP_TABLE_V1) 2077 && !phm_get_sclk_for_voltage_evv(hwmgr, 2078 table_info->vddgfx_lookup_table, vv_id, &sclk)) { 2079 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2080 PHM_PlatformCaps_ClockStretcher)) { 2081 sclk_table = table_info->vdd_dep_on_sclk; 2082 2083 for (j = 1; j < sclk_table->count; j++) { 2084 if (sclk_table->entries[j].clk == sclk && 2085 sclk_table->entries[j].cks_enable == 0) { 2086 sclk += 5000; 2087 break; 2088 } 2089 } 2090 } 2091 if (0 == atomctrl_get_voltage_evv_on_sclk 2092 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, 2093 vv_id, &vddgfx)) { 2094 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ 2095 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL); 2096 2097 /* the voltage should not be zero nor equal to leakage ID */ 2098 if (vddgfx != 0 && vddgfx != vv_id) { 2099 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; 2100 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id; 2101 data->vddcgfx_leakage.count++; 2102 } 2103 } else { 2104 pr_info("Error retrieving EVV voltage value!\n"); 2105 } 2106 } 2107 } else { 2108 if ((hwmgr->pp_table_version == PP_TABLE_V0) 2109 || !phm_get_sclk_for_voltage_evv(hwmgr, 2110 table_info->vddc_lookup_table, vv_id, &sclk)) { 2111 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2112 PHM_PlatformCaps_ClockStretcher)) { 2113 if (table_info == NULL) 2114 return -EINVAL; 2115 sclk_table = table_info->vdd_dep_on_sclk; 2116 2117 for (j = 1; j < sclk_table->count; j++) { 2118 if (sclk_table->entries[j].clk == sclk && 2119 sclk_table->entries[j].cks_enable == 0) { 2120 sclk += 5000; 2121 break; 2122 } 2123 } 2124 } 2125 2126 if (phm_get_voltage_evv_on_sclk(hwmgr, 2127 VOLTAGE_TYPE_VDDC, 2128 sclk, vv_id, &vddc) == 0) { 2129 if (vddc >= 2000 || vddc == 0) 2130 return -EINVAL; 2131 } else { 2132 pr_debug("failed to retrieving EVV voltage!\n"); 2133 continue; 2134 } 2135 2136 /* the voltage should not be zero nor equal to leakage ID */ 2137 if (vddc != 0 && vddc != vv_id) { 2138 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc); 2139 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 2140 data->vddc_leakage.count++; 2141 } 2142 } 2143 } 2144 } 2145 2146 return 0; 2147 } 2148 2149 /** 2150 * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value. 2151 * 2152 * @hwmgr: the address of the powerplay hardware manager. 2153 * @voltage: pointer to changing voltage 2154 * @leakage_table: pointer to leakage table 2155 */ 2156 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2157 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table) 2158 { 2159 uint32_t index; 2160 2161 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2162 for (index = 0; index < leakage_table->count; index++) { 2163 /* if this voltage matches a leakage voltage ID */ 2164 /* patch with actual leakage voltage */ 2165 if (leakage_table->leakage_id[index] == *voltage) { 2166 *voltage = leakage_table->actual_voltage[index]; 2167 break; 2168 } 2169 } 2170 2171 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2172 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 2173 } 2174 2175 /** 2176 * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. 2177 * 2178 * @hwmgr: the address of the powerplay hardware manager. 2179 * @lookup_table: pointer to voltage lookup table 2180 * @leakage_table: pointer to leakage table 2181 * Return: always 0 2182 */ 2183 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 2184 phm_ppt_v1_voltage_lookup_table *lookup_table, 2185 struct smu7_leakage_voltage *leakage_table) 2186 { 2187 uint32_t i; 2188 2189 for (i = 0; i < lookup_table->count; i++) 2190 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2191 &lookup_table->entries[i].us_vdd, leakage_table); 2192 2193 return 0; 2194 } 2195 2196 static int smu7_patch_clock_voltage_limits_with_vddc_leakage( 2197 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, 2198 uint16_t *vddc) 2199 { 2200 struct phm_ppt_v1_information *table_info = 2201 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2202 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 2203 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = 2204 table_info->max_clock_voltage_on_dc.vddc; 2205 return 0; 2206 } 2207 2208 static int smu7_patch_voltage_dependency_tables_with_lookup_table( 2209 struct pp_hwmgr *hwmgr) 2210 { 2211 uint8_t entry_id; 2212 uint8_t voltage_id; 2213 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2214 struct phm_ppt_v1_information *table_info = 2215 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2216 2217 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 2218 table_info->vdd_dep_on_sclk; 2219 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 2220 table_info->vdd_dep_on_mclk; 2221 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 2222 table_info->mm_dep_table; 2223 2224 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2225 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2226 voltage_id = sclk_table->entries[entry_id].vddInd; 2227 sclk_table->entries[entry_id].vddgfx = 2228 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd; 2229 } 2230 } else { 2231 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2232 voltage_id = sclk_table->entries[entry_id].vddInd; 2233 sclk_table->entries[entry_id].vddc = 2234 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2235 } 2236 } 2237 2238 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 2239 voltage_id = mclk_table->entries[entry_id].vddInd; 2240 mclk_table->entries[entry_id].vddc = 2241 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2242 } 2243 2244 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 2245 voltage_id = mm_table->entries[entry_id].vddcInd; 2246 mm_table->entries[entry_id].vddc = 2247 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 2248 } 2249 2250 return 0; 2251 2252 } 2253 2254 static int phm_add_voltage(struct pp_hwmgr *hwmgr, 2255 phm_ppt_v1_voltage_lookup_table *look_up_table, 2256 phm_ppt_v1_voltage_lookup_record *record) 2257 { 2258 uint32_t i; 2259 2260 PP_ASSERT_WITH_CODE((NULL != look_up_table), 2261 "Lookup Table empty.", return -EINVAL); 2262 PP_ASSERT_WITH_CODE((0 != look_up_table->count), 2263 "Lookup Table empty.", return -EINVAL); 2264 2265 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 2266 PP_ASSERT_WITH_CODE((i >= look_up_table->count), 2267 "Lookup Table is full.", return -EINVAL); 2268 2269 /* This is to avoid entering duplicate calculated records. */ 2270 for (i = 0; i < look_up_table->count; i++) { 2271 if (look_up_table->entries[i].us_vdd == record->us_vdd) { 2272 if (look_up_table->entries[i].us_calculated == 1) 2273 return 0; 2274 break; 2275 } 2276 } 2277 2278 look_up_table->entries[i].us_calculated = 1; 2279 look_up_table->entries[i].us_vdd = record->us_vdd; 2280 look_up_table->entries[i].us_cac_low = record->us_cac_low; 2281 look_up_table->entries[i].us_cac_mid = record->us_cac_mid; 2282 look_up_table->entries[i].us_cac_high = record->us_cac_high; 2283 /* Only increment the count when we're appending, not replacing duplicate entry. */ 2284 if (i == look_up_table->count) 2285 look_up_table->count++; 2286 2287 return 0; 2288 } 2289 2290 2291 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) 2292 { 2293 uint8_t entry_id; 2294 struct phm_ppt_v1_voltage_lookup_record v_record; 2295 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2296 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 2297 2298 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; 2299 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; 2300 2301 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2302 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 2303 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) 2304 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 2305 sclk_table->entries[entry_id].vdd_offset - 0xFFFF; 2306 else 2307 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 2308 sclk_table->entries[entry_id].vdd_offset; 2309 2310 sclk_table->entries[entry_id].vddc = 2311 v_record.us_cac_low = v_record.us_cac_mid = 2312 v_record.us_cac_high = v_record.us_vdd; 2313 2314 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); 2315 } 2316 2317 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 2318 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) 2319 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 2320 mclk_table->entries[entry_id].vdd_offset - 0xFFFF; 2321 else 2322 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 2323 mclk_table->entries[entry_id].vdd_offset; 2324 2325 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = 2326 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 2327 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 2328 } 2329 } 2330 return 0; 2331 } 2332 2333 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) 2334 { 2335 uint8_t entry_id; 2336 struct phm_ppt_v1_voltage_lookup_record v_record; 2337 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2338 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 2339 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; 2340 2341 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2342 for (entry_id = 0; entry_id < mm_table->count; entry_id++) { 2343 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15)) 2344 v_record.us_vdd = mm_table->entries[entry_id].vddc + 2345 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF; 2346 else 2347 v_record.us_vdd = mm_table->entries[entry_id].vddc + 2348 mm_table->entries[entry_id].vddgfx_offset; 2349 2350 /* Add the calculated VDDGFX to the VDDGFX lookup table */ 2351 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low = 2352 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 2353 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 2354 } 2355 } 2356 return 0; 2357 } 2358 2359 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, 2360 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 2361 { 2362 uint32_t table_size, i, j; 2363 table_size = lookup_table->count; 2364 2365 PP_ASSERT_WITH_CODE(0 != lookup_table->count, 2366 "Lookup table is empty", return -EINVAL); 2367 2368 /* Sorting voltages */ 2369 for (i = 0; i < table_size - 1; i++) { 2370 for (j = i + 1; j > 0; j--) { 2371 if (lookup_table->entries[j].us_vdd < 2372 lookup_table->entries[j - 1].us_vdd) { 2373 swap(lookup_table->entries[j - 1], 2374 lookup_table->entries[j]); 2375 } 2376 } 2377 } 2378 2379 return 0; 2380 } 2381 2382 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) 2383 { 2384 int result = 0; 2385 int tmp_result; 2386 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2387 struct phm_ppt_v1_information *table_info = 2388 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2389 2390 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2391 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2392 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); 2393 if (tmp_result != 0) 2394 result = tmp_result; 2395 2396 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2397 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage)); 2398 } else { 2399 2400 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2401 table_info->vddc_lookup_table, &(data->vddc_leakage)); 2402 if (tmp_result) 2403 result = tmp_result; 2404 2405 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 2406 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 2407 if (tmp_result) 2408 result = tmp_result; 2409 } 2410 2411 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 2412 if (tmp_result) 2413 result = tmp_result; 2414 2415 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr); 2416 if (tmp_result) 2417 result = tmp_result; 2418 2419 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr); 2420 if (tmp_result) 2421 result = tmp_result; 2422 2423 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table); 2424 if (tmp_result) 2425 result = tmp_result; 2426 2427 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 2428 if (tmp_result) 2429 result = tmp_result; 2430 2431 return result; 2432 } 2433 2434 static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr) 2435 { 2436 struct phm_ppt_v1_information *table_info = 2437 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2438 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2439 table_info->vdd_dep_on_sclk; 2440 struct phm_ppt_v1_voltage_lookup_table *lookup_table = 2441 table_info->vddc_lookup_table; 2442 uint16_t highest_voltage; 2443 uint32_t i; 2444 2445 highest_voltage = allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2446 2447 for (i = 0; i < lookup_table->count; i++) { 2448 if (lookup_table->entries[i].us_vdd < ATOM_VIRTUAL_VOLTAGE_ID0 && 2449 lookup_table->entries[i].us_vdd > highest_voltage) 2450 highest_voltage = lookup_table->entries[i].us_vdd; 2451 } 2452 2453 return highest_voltage; 2454 } 2455 2456 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) 2457 { 2458 struct phm_ppt_v1_information *table_info = 2459 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2460 2461 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2462 table_info->vdd_dep_on_sclk; 2463 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 2464 table_info->vdd_dep_on_mclk; 2465 2466 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, 2467 "VDD dependency on SCLK table is missing.", 2468 return -EINVAL); 2469 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 2470 "VDD dependency on SCLK table has to have is missing.", 2471 return -EINVAL); 2472 2473 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2474 "VDD dependency on MCLK table is missing", 2475 return -EINVAL); 2476 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2477 "VDD dependency on MCLK table has to have is missing.", 2478 return -EINVAL); 2479 2480 table_info->max_clock_voltage_on_ac.sclk = 2481 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 2482 table_info->max_clock_voltage_on_ac.mclk = 2483 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2484 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) 2485 table_info->max_clock_voltage_on_ac.vddc = 2486 smu7_find_highest_vddc(hwmgr); 2487 else 2488 table_info->max_clock_voltage_on_ac.vddc = 2489 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2490 table_info->max_clock_voltage_on_ac.vddci = 2491 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 2492 2493 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; 2494 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; 2495 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; 2496 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; 2497 2498 return 0; 2499 } 2500 2501 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) 2502 { 2503 struct phm_ppt_v1_information *table_info = 2504 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2505 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 2506 struct phm_ppt_v1_voltage_lookup_table *lookup_table; 2507 uint32_t i; 2508 uint32_t hw_revision, sub_vendor_id, sub_sys_id; 2509 struct amdgpu_device *adev = hwmgr->adev; 2510 2511 if (table_info != NULL) { 2512 dep_mclk_table = table_info->vdd_dep_on_mclk; 2513 lookup_table = table_info->vddc_lookup_table; 2514 } else 2515 return 0; 2516 2517 hw_revision = adev->pdev->revision; 2518 sub_sys_id = adev->pdev->subsystem_device; 2519 sub_vendor_id = adev->pdev->subsystem_vendor; 2520 2521 if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 && 2522 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) || 2523 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) || 2524 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) { 2525 2526 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 2527 CGS_IND_REG__SMC, 2528 PWR_CKS_CNTL, 2529 CKS_STRETCH_AMOUNT, 2530 0x3); 2531 2532 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) 2533 return 0; 2534 2535 for (i = 0; i < lookup_table->count; i++) { 2536 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { 2537 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; 2538 return 0; 2539 } 2540 } 2541 } 2542 return 0; 2543 } 2544 2545 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) 2546 { 2547 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 2548 uint32_t temp_reg; 2549 struct phm_ppt_v1_information *table_info = 2550 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2551 2552 2553 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { 2554 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); 2555 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { 2556 case 0: 2557 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); 2558 break; 2559 case 1: 2560 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); 2561 break; 2562 case 2: 2563 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); 2564 break; 2565 case 3: 2566 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); 2567 break; 2568 case 4: 2569 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); 2570 break; 2571 default: 2572 break; 2573 } 2574 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); 2575 } 2576 2577 if (table_info == NULL) 2578 return 0; 2579 2580 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 && 2581 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { 2582 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = 2583 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2584 2585 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = 2586 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2587 2588 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; 2589 2590 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; 2591 2592 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = 2593 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2594 2595 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; 2596 2597 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ? 2598 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0; 2599 2600 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2601 table_info->cac_dtp_table->usOperatingTempStep = 1; 2602 table_info->cac_dtp_table->usOperatingTempHyst = 1; 2603 2604 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = 2605 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2606 2607 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 2608 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; 2609 2610 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = 2611 table_info->cac_dtp_table->usOperatingTempMinLimit; 2612 2613 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = 2614 table_info->cac_dtp_table->usOperatingTempMaxLimit; 2615 2616 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = 2617 table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2618 2619 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = 2620 table_info->cac_dtp_table->usOperatingTempStep; 2621 2622 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = 2623 table_info->cac_dtp_table->usTargetOperatingTemp; 2624 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) 2625 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2626 PHM_PlatformCaps_ODFuzzyFanControlSupport); 2627 } 2628 2629 return 0; 2630 } 2631 2632 /** 2633 * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value. 2634 * 2635 * @hwmgr: the address of the powerplay hardware manager. 2636 * @voltage: pointer to changing voltage 2637 * @leakage_table: pointer to leakage table 2638 */ 2639 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2640 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) 2641 { 2642 uint32_t index; 2643 2644 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2645 for (index = 0; index < leakage_table->count; index++) { 2646 /* if this voltage matches a leakage voltage ID */ 2647 /* patch with actual leakage voltage */ 2648 if (leakage_table->leakage_id[index] == *voltage) { 2649 *voltage = leakage_table->actual_voltage[index]; 2650 break; 2651 } 2652 } 2653 2654 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2655 pr_info("Voltage value looks like a Leakage ID but it's not patched\n"); 2656 } 2657 2658 2659 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, 2660 struct phm_clock_voltage_dependency_table *tab) 2661 { 2662 uint16_t i; 2663 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2664 2665 if (tab) 2666 for (i = 0; i < tab->count; i++) 2667 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2668 &data->vddc_leakage); 2669 2670 return 0; 2671 } 2672 2673 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, 2674 struct phm_clock_voltage_dependency_table *tab) 2675 { 2676 uint16_t i; 2677 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2678 2679 if (tab) 2680 for (i = 0; i < tab->count; i++) 2681 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2682 &data->vddci_leakage); 2683 2684 return 0; 2685 } 2686 2687 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, 2688 struct phm_vce_clock_voltage_dependency_table *tab) 2689 { 2690 uint16_t i; 2691 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2692 2693 if (tab) 2694 for (i = 0; i < tab->count; i++) 2695 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2696 &data->vddc_leakage); 2697 2698 return 0; 2699 } 2700 2701 2702 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, 2703 struct phm_uvd_clock_voltage_dependency_table *tab) 2704 { 2705 uint16_t i; 2706 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2707 2708 if (tab) 2709 for (i = 0; i < tab->count; i++) 2710 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2711 &data->vddc_leakage); 2712 2713 return 0; 2714 } 2715 2716 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, 2717 struct phm_phase_shedding_limits_table *tab) 2718 { 2719 uint16_t i; 2720 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2721 2722 if (tab) 2723 for (i = 0; i < tab->count; i++) 2724 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, 2725 &data->vddc_leakage); 2726 2727 return 0; 2728 } 2729 2730 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, 2731 struct phm_samu_clock_voltage_dependency_table *tab) 2732 { 2733 uint16_t i; 2734 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2735 2736 if (tab) 2737 for (i = 0; i < tab->count; i++) 2738 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2739 &data->vddc_leakage); 2740 2741 return 0; 2742 } 2743 2744 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, 2745 struct phm_acp_clock_voltage_dependency_table *tab) 2746 { 2747 uint16_t i; 2748 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2749 2750 if (tab) 2751 for (i = 0; i < tab->count; i++) 2752 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2753 &data->vddc_leakage); 2754 2755 return 0; 2756 } 2757 2758 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, 2759 struct phm_clock_and_voltage_limits *tab) 2760 { 2761 uint32_t vddc, vddci; 2762 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2763 2764 if (tab) { 2765 vddc = tab->vddc; 2766 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, 2767 &data->vddc_leakage); 2768 tab->vddc = vddc; 2769 vddci = tab->vddci; 2770 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, 2771 &data->vddci_leakage); 2772 tab->vddci = vddci; 2773 } 2774 2775 return 0; 2776 } 2777 2778 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) 2779 { 2780 uint32_t i; 2781 uint32_t vddc; 2782 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2783 2784 if (tab) { 2785 for (i = 0; i < tab->count; i++) { 2786 vddc = (uint32_t)(tab->entries[i].Vddc); 2787 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); 2788 tab->entries[i].Vddc = (uint16_t)vddc; 2789 } 2790 } 2791 2792 return 0; 2793 } 2794 2795 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) 2796 { 2797 int tmp; 2798 2799 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); 2800 if (tmp) 2801 return -EINVAL; 2802 2803 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); 2804 if (tmp) 2805 return -EINVAL; 2806 2807 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2808 if (tmp) 2809 return -EINVAL; 2810 2811 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); 2812 if (tmp) 2813 return -EINVAL; 2814 2815 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); 2816 if (tmp) 2817 return -EINVAL; 2818 2819 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); 2820 if (tmp) 2821 return -EINVAL; 2822 2823 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); 2824 if (tmp) 2825 return -EINVAL; 2826 2827 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); 2828 if (tmp) 2829 return -EINVAL; 2830 2831 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); 2832 if (tmp) 2833 return -EINVAL; 2834 2835 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); 2836 if (tmp) 2837 return -EINVAL; 2838 2839 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); 2840 if (tmp) 2841 return -EINVAL; 2842 2843 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); 2844 if (tmp) 2845 return -EINVAL; 2846 2847 return 0; 2848 } 2849 2850 2851 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) 2852 { 2853 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2854 2855 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 2856 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 2857 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 2858 2859 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, 2860 "VDDC dependency on SCLK table is missing. This table is mandatory", 2861 return -EINVAL); 2862 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, 2863 "VDDC dependency on SCLK table has to have is missing. This table is mandatory", 2864 return -EINVAL); 2865 2866 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, 2867 "VDDC dependency on MCLK table is missing. This table is mandatory", 2868 return -EINVAL); 2869 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, 2870 "VDD dependency on MCLK table has to have is missing. This table is mandatory", 2871 return -EINVAL); 2872 2873 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; 2874 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2875 2876 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 2877 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 2878 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 2879 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; 2880 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 2881 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2882 2883 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) { 2884 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v; 2885 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 2886 } 2887 2888 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) 2889 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; 2890 2891 return 0; 2892 } 2893 2894 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 2895 { 2896 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2897 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 2898 kfree(hwmgr->backend); 2899 hwmgr->backend = NULL; 2900 2901 return 0; 2902 } 2903 2904 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) 2905 { 2906 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; 2907 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2908 int i; 2909 2910 if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) { 2911 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2912 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2913 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci, 2914 virtual_voltage_id, 2915 efuse_voltage_id) == 0) { 2916 if (vddc != 0 && vddc != virtual_voltage_id) { 2917 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; 2918 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; 2919 data->vddc_leakage.count++; 2920 } 2921 if (vddci != 0 && vddci != virtual_voltage_id) { 2922 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci; 2923 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id; 2924 data->vddci_leakage.count++; 2925 } 2926 } 2927 } 2928 } 2929 return 0; 2930 } 2931 2932 #define LEAKAGE_ID_MSB 463 2933 #define LEAKAGE_ID_LSB 454 2934 2935 static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr) 2936 { 2937 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2938 uint32_t efuse; 2939 uint16_t offset; 2940 int ret = 0; 2941 2942 if (data->disable_edc_leakage_controller) 2943 return 0; 2944 2945 ret = atomctrl_get_edc_hilo_leakage_offset_table(hwmgr, 2946 &data->edc_hilo_leakage_offset_from_vbios); 2947 if (ret) 2948 return ret; 2949 2950 if (data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset && 2951 data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset) { 2952 atomctrl_read_efuse(hwmgr, LEAKAGE_ID_LSB, LEAKAGE_ID_MSB, &efuse); 2953 if (efuse < data->edc_hilo_leakage_offset_from_vbios.usHiLoLeakageThreshold) 2954 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtLoDpm7TableOffset; 2955 else 2956 offset = data->edc_hilo_leakage_offset_from_vbios.usEdcDidtHiDpm7TableOffset; 2957 2958 ret = atomctrl_get_edc_leakage_table(hwmgr, 2959 &data->edc_leakage_table, 2960 offset); 2961 if (ret) 2962 return ret; 2963 } 2964 2965 return ret; 2966 } 2967 2968 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 2969 { 2970 struct smu7_hwmgr *data; 2971 int result = 0; 2972 2973 data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL); 2974 if (data == NULL) 2975 return -ENOMEM; 2976 2977 hwmgr->backend = data; 2978 smu7_patch_voltage_workaround(hwmgr); 2979 smu7_init_dpm_defaults(hwmgr); 2980 2981 /* Get leakage voltage based on leakage ID. */ 2982 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2983 PHM_PlatformCaps_EVV)) { 2984 result = smu7_get_evv_voltages(hwmgr); 2985 if (result) { 2986 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); 2987 return -EINVAL; 2988 } 2989 } else { 2990 smu7_get_elb_voltages(hwmgr); 2991 } 2992 2993 if (hwmgr->pp_table_version == PP_TABLE_V1) { 2994 smu7_complete_dependency_tables(hwmgr); 2995 smu7_set_private_data_based_on_pptable_v1(hwmgr); 2996 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 2997 smu7_patch_dependency_tables_with_leakage(hwmgr); 2998 smu7_set_private_data_based_on_pptable_v0(hwmgr); 2999 } 3000 3001 /* Initalize Dynamic State Adjustment Rule Settings */ 3002 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); 3003 3004 if (0 == result) { 3005 struct amdgpu_device *adev = hwmgr->adev; 3006 3007 data->is_tlu_enabled = false; 3008 3009 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 3010 SMU7_MAX_HARDWARE_POWERLEVELS; 3011 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 3012 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 3013 3014 data->pcie_gen_cap = adev->pm.pcie_gen_mask; 3015 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 3016 data->pcie_spc_cap = 20; 3017 else 3018 data->pcie_spc_cap = 16; 3019 data->pcie_lane_cap = adev->pm.pcie_mlw_mask; 3020 3021 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 3022 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 3023 hwmgr->platform_descriptor.clockStep.engineClock = 500; 3024 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 3025 smu7_thermal_parameter_init(hwmgr); 3026 } else { 3027 /* Ignore return value in here, we are cleaning up a mess. */ 3028 smu7_hwmgr_backend_fini(hwmgr); 3029 } 3030 3031 result = smu7_update_edc_leakage_table(hwmgr); 3032 if (result) 3033 return result; 3034 3035 return 0; 3036 } 3037 3038 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) 3039 { 3040 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3041 uint32_t level, tmp; 3042 3043 if (!data->pcie_dpm_key_disabled) { 3044 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3045 level = 0; 3046 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; 3047 while (tmp >>= 1) 3048 level++; 3049 3050 if (level) 3051 smum_send_msg_to_smc_with_parameter(hwmgr, 3052 PPSMC_MSG_PCIeDPM_ForceLevel, level, 3053 NULL); 3054 } 3055 } 3056 3057 if (!data->sclk_dpm_key_disabled) { 3058 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3059 level = 0; 3060 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 3061 while (tmp >>= 1) 3062 level++; 3063 3064 if (level) 3065 smum_send_msg_to_smc_with_parameter(hwmgr, 3066 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3067 (1 << level), 3068 NULL); 3069 } 3070 } 3071 3072 if (!data->mclk_dpm_key_disabled) { 3073 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3074 level = 0; 3075 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; 3076 while (tmp >>= 1) 3077 level++; 3078 3079 if (level) 3080 smum_send_msg_to_smc_with_parameter(hwmgr, 3081 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3082 (1 << level), 3083 NULL); 3084 } 3085 } 3086 3087 return 0; 3088 } 3089 3090 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) 3091 { 3092 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3093 3094 if (hwmgr->pp_table_version == PP_TABLE_V1) 3095 phm_apply_dal_min_voltage_request(hwmgr); 3096 /* TO DO for v0 iceland and Ci*/ 3097 3098 if (!data->sclk_dpm_key_disabled) { 3099 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) 3100 smum_send_msg_to_smc_with_parameter(hwmgr, 3101 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3102 data->dpm_level_enable_mask.sclk_dpm_enable_mask, 3103 NULL); 3104 } 3105 3106 if (!data->mclk_dpm_key_disabled) { 3107 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) 3108 smum_send_msg_to_smc_with_parameter(hwmgr, 3109 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3110 data->dpm_level_enable_mask.mclk_dpm_enable_mask, 3111 NULL); 3112 } 3113 3114 return 0; 3115 } 3116 3117 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 3118 { 3119 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3120 3121 if (!smum_is_dpm_running(hwmgr)) 3122 return -EINVAL; 3123 3124 if (!data->pcie_dpm_key_disabled) { 3125 smum_send_msg_to_smc(hwmgr, 3126 PPSMC_MSG_PCIeDPM_UnForceLevel, 3127 NULL); 3128 } 3129 3130 return smu7_upload_dpm_level_enable_mask(hwmgr); 3131 } 3132 3133 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) 3134 { 3135 struct smu7_hwmgr *data = 3136 (struct smu7_hwmgr *)(hwmgr->backend); 3137 uint32_t level; 3138 3139 if (!data->sclk_dpm_key_disabled) 3140 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 3141 level = phm_get_lowest_enabled_level(hwmgr, 3142 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 3143 smum_send_msg_to_smc_with_parameter(hwmgr, 3144 PPSMC_MSG_SCLKDPM_SetEnabledMask, 3145 (1 << level), 3146 NULL); 3147 3148 } 3149 3150 if (!data->mclk_dpm_key_disabled) { 3151 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 3152 level = phm_get_lowest_enabled_level(hwmgr, 3153 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 3154 smum_send_msg_to_smc_with_parameter(hwmgr, 3155 PPSMC_MSG_MCLKDPM_SetEnabledMask, 3156 (1 << level), 3157 NULL); 3158 } 3159 } 3160 3161 if (!data->pcie_dpm_key_disabled) { 3162 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 3163 level = phm_get_lowest_enabled_level(hwmgr, 3164 data->dpm_level_enable_mask.pcie_dpm_enable_mask); 3165 smum_send_msg_to_smc_with_parameter(hwmgr, 3166 PPSMC_MSG_PCIeDPM_ForceLevel, 3167 (level), 3168 NULL); 3169 } 3170 } 3171 3172 return 0; 3173 } 3174 3175 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 3176 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) 3177 { 3178 uint32_t percentage; 3179 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3180 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 3181 int32_t tmp_mclk; 3182 int32_t tmp_sclk; 3183 int32_t count; 3184 3185 if (golden_dpm_table->mclk_table.count < 1) 3186 return -EINVAL; 3187 3188 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 3189 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 3190 3191 if (golden_dpm_table->mclk_table.count == 1) { 3192 percentage = 70; 3193 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 3194 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3195 } else { 3196 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 3197 *mclk_mask = golden_dpm_table->mclk_table.count - 2; 3198 } 3199 3200 tmp_sclk = tmp_mclk * percentage / 100; 3201 3202 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3203 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3204 count >= 0; count--) { 3205 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { 3206 *sclk_mask = count; 3207 break; 3208 } 3209 } 3210 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3211 *sclk_mask = 0; 3212 3213 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3214 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3215 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3216 struct phm_ppt_v1_information *table_info = 3217 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3218 3219 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { 3220 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { 3221 *sclk_mask = count; 3222 break; 3223 } 3224 } 3225 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) 3226 *sclk_mask = 0; 3227 3228 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3229 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 3230 } 3231 3232 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) 3233 *mclk_mask = 0; 3234 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3235 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 3236 3237 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; 3238 3239 return 0; 3240 } 3241 3242 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, 3243 enum amd_dpm_forced_level level) 3244 { 3245 int ret = 0; 3246 uint32_t sclk_mask = 0; 3247 uint32_t mclk_mask = 0; 3248 uint32_t pcie_mask = 0; 3249 3250 switch (level) { 3251 case AMD_DPM_FORCED_LEVEL_HIGH: 3252 ret = smu7_force_dpm_highest(hwmgr); 3253 break; 3254 case AMD_DPM_FORCED_LEVEL_LOW: 3255 ret = smu7_force_dpm_lowest(hwmgr); 3256 break; 3257 case AMD_DPM_FORCED_LEVEL_AUTO: 3258 ret = smu7_unforce_dpm_levels(hwmgr); 3259 break; 3260 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 3261 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 3262 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 3263 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 3264 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 3265 if (ret) 3266 return ret; 3267 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 3268 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 3269 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); 3270 break; 3271 case AMD_DPM_FORCED_LEVEL_MANUAL: 3272 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 3273 default: 3274 break; 3275 } 3276 3277 if (!ret) { 3278 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3279 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 3280 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 3281 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); 3282 } 3283 return ret; 3284 } 3285 3286 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) 3287 { 3288 return sizeof(struct smu7_power_state); 3289 } 3290 3291 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, 3292 uint32_t vblank_time_us) 3293 { 3294 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3295 uint32_t switch_limit_us; 3296 3297 switch (hwmgr->chip_id) { 3298 case CHIP_POLARIS10: 3299 case CHIP_POLARIS11: 3300 case CHIP_POLARIS12: 3301 if (hwmgr->is_kicker || (hwmgr->chip_id == CHIP_POLARIS12)) 3302 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 3303 else 3304 switch_limit_us = data->is_memory_gddr5 ? 200 : 150; 3305 break; 3306 case CHIP_VEGAM: 3307 switch_limit_us = 30; 3308 break; 3309 default: 3310 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 3311 break; 3312 } 3313 3314 if (vblank_time_us < switch_limit_us) 3315 return true; 3316 else 3317 return false; 3318 } 3319 3320 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 3321 struct pp_power_state *request_ps, 3322 const struct pp_power_state *current_ps) 3323 { 3324 struct amdgpu_device *adev = hwmgr->adev; 3325 struct smu7_power_state *smu7_ps = 3326 cast_phw_smu7_power_state(&request_ps->hardware); 3327 uint32_t sclk; 3328 uint32_t mclk; 3329 struct PP_Clocks minimum_clocks = {0}; 3330 bool disable_mclk_switching; 3331 bool disable_mclk_switching_for_frame_lock; 3332 bool disable_mclk_switching_for_display; 3333 const struct phm_clock_and_voltage_limits *max_limits; 3334 uint32_t i; 3335 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3336 struct phm_ppt_v1_information *table_info = 3337 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3338 int32_t count; 3339 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 3340 uint32_t latency; 3341 bool latency_allowed = false; 3342 3343 data->battery_state = (PP_StateUILabel_Battery == 3344 request_ps->classification.ui_label); 3345 data->mclk_ignore_signal = false; 3346 3347 max_limits = adev->pm.ac_power ? 3348 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 3349 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 3350 3351 /* Cap clock DPM tables at DC MAX if it is in DC. */ 3352 if (!adev->pm.ac_power) { 3353 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3354 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) 3355 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; 3356 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) 3357 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; 3358 } 3359 } 3360 3361 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 3362 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 3363 3364 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3365 PHM_PlatformCaps_StablePState)) { 3366 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 3367 stable_pstate_sclk = (max_limits->sclk * 75) / 100; 3368 3369 for (count = table_info->vdd_dep_on_sclk->count - 1; 3370 count >= 0; count--) { 3371 if (stable_pstate_sclk >= 3372 table_info->vdd_dep_on_sclk->entries[count].clk) { 3373 stable_pstate_sclk = 3374 table_info->vdd_dep_on_sclk->entries[count].clk; 3375 break; 3376 } 3377 } 3378 3379 if (count < 0) 3380 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 3381 3382 stable_pstate_mclk = max_limits->mclk; 3383 3384 minimum_clocks.engineClock = stable_pstate_sclk; 3385 minimum_clocks.memoryClock = stable_pstate_mclk; 3386 } 3387 3388 disable_mclk_switching_for_frame_lock = phm_cap_enabled( 3389 hwmgr->platform_descriptor.platformCaps, 3390 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 3391 3392 disable_mclk_switching_for_display = ((1 < hwmgr->display_config->num_display) && 3393 !hwmgr->display_config->multi_monitor_in_sync) || 3394 (hwmgr->display_config->num_display && 3395 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); 3396 3397 disable_mclk_switching = disable_mclk_switching_for_frame_lock || 3398 disable_mclk_switching_for_display; 3399 3400 if (hwmgr->display_config->num_display == 0) { 3401 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) 3402 data->mclk_ignore_signal = true; 3403 else 3404 disable_mclk_switching = false; 3405 } 3406 3407 sclk = smu7_ps->performance_levels[0].engine_clock; 3408 mclk = smu7_ps->performance_levels[0].memory_clock; 3409 3410 if (disable_mclk_switching && 3411 (!(hwmgr->chip_id >= CHIP_POLARIS10 && 3412 hwmgr->chip_id <= CHIP_VEGAM))) 3413 mclk = smu7_ps->performance_levels 3414 [smu7_ps->performance_level_count - 1].memory_clock; 3415 3416 if (sclk < minimum_clocks.engineClock) 3417 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 3418 max_limits->sclk : minimum_clocks.engineClock; 3419 3420 if (mclk < minimum_clocks.memoryClock) 3421 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 3422 max_limits->mclk : minimum_clocks.memoryClock; 3423 3424 smu7_ps->performance_levels[0].engine_clock = sclk; 3425 smu7_ps->performance_levels[0].memory_clock = mclk; 3426 3427 smu7_ps->performance_levels[1].engine_clock = 3428 (smu7_ps->performance_levels[1].engine_clock >= 3429 smu7_ps->performance_levels[0].engine_clock) ? 3430 smu7_ps->performance_levels[1].engine_clock : 3431 smu7_ps->performance_levels[0].engine_clock; 3432 3433 if (disable_mclk_switching) { 3434 if (mclk < smu7_ps->performance_levels[1].memory_clock) 3435 mclk = smu7_ps->performance_levels[1].memory_clock; 3436 3437 if (hwmgr->chip_id >= CHIP_POLARIS10 && hwmgr->chip_id <= CHIP_VEGAM) { 3438 if (disable_mclk_switching_for_display) { 3439 /* Find the lowest MCLK frequency that is within 3440 * the tolerable latency defined in DAL 3441 */ 3442 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3443 for (i = 0; i < data->mclk_latency_table.count; i++) { 3444 if (data->mclk_latency_table.entries[i].latency <= latency) { 3445 latency_allowed = true; 3446 3447 if ((data->mclk_latency_table.entries[i].frequency >= 3448 smu7_ps->performance_levels[0].memory_clock) && 3449 (data->mclk_latency_table.entries[i].frequency <= 3450 smu7_ps->performance_levels[1].memory_clock)) { 3451 mclk = data->mclk_latency_table.entries[i].frequency; 3452 break; 3453 } 3454 } 3455 } 3456 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) { 3457 data->mclk_ignore_signal = true; 3458 } else { 3459 data->mclk_ignore_signal = false; 3460 } 3461 } 3462 3463 if (disable_mclk_switching_for_frame_lock) 3464 mclk = smu7_ps->performance_levels[1].memory_clock; 3465 } 3466 3467 smu7_ps->performance_levels[0].memory_clock = mclk; 3468 3469 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 3470 hwmgr->chip_id <= CHIP_VEGAM)) 3471 smu7_ps->performance_levels[1].memory_clock = mclk; 3472 } else { 3473 if (smu7_ps->performance_levels[1].memory_clock < 3474 smu7_ps->performance_levels[0].memory_clock) 3475 smu7_ps->performance_levels[1].memory_clock = 3476 smu7_ps->performance_levels[0].memory_clock; 3477 } 3478 3479 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3480 PHM_PlatformCaps_StablePState)) { 3481 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3482 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; 3483 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk; 3484 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; 3485 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; 3486 } 3487 } 3488 return 0; 3489 } 3490 3491 3492 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3493 { 3494 struct pp_power_state *ps; 3495 struct smu7_power_state *smu7_ps; 3496 3497 if (hwmgr == NULL) 3498 return -EINVAL; 3499 3500 ps = hwmgr->request_ps; 3501 3502 if (ps == NULL) 3503 return -EINVAL; 3504 3505 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3506 3507 if (low) 3508 return smu7_ps->performance_levels[0].memory_clock; 3509 else 3510 return smu7_ps->performance_levels 3511 [smu7_ps->performance_level_count-1].memory_clock; 3512 } 3513 3514 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3515 { 3516 struct pp_power_state *ps; 3517 struct smu7_power_state *smu7_ps; 3518 3519 if (hwmgr == NULL) 3520 return -EINVAL; 3521 3522 ps = hwmgr->request_ps; 3523 3524 if (ps == NULL) 3525 return -EINVAL; 3526 3527 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3528 3529 if (low) 3530 return smu7_ps->performance_levels[0].engine_clock; 3531 else 3532 return smu7_ps->performance_levels 3533 [smu7_ps->performance_level_count-1].engine_clock; 3534 } 3535 3536 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 3537 struct pp_hw_power_state *hw_ps) 3538 { 3539 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3540 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; 3541 ATOM_FIRMWARE_INFO_V2_2 *fw_info; 3542 uint16_t size; 3543 uint8_t frev, crev; 3544 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 3545 3546 /* First retrieve the Boot clocks and VDDC from the firmware info table. 3547 * We assume here that fw_info is unchanged if this call fails. 3548 */ 3549 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index, 3550 &size, &frev, &crev); 3551 if (!fw_info) 3552 /* During a test, there is no firmware info table. */ 3553 return 0; 3554 3555 /* Patch the state. */ 3556 data->vbios_boot_state.sclk_bootup_value = 3557 le32_to_cpu(fw_info->ulDefaultEngineClock); 3558 data->vbios_boot_state.mclk_bootup_value = 3559 le32_to_cpu(fw_info->ulDefaultMemoryClock); 3560 data->vbios_boot_state.mvdd_bootup_value = 3561 le16_to_cpu(fw_info->usBootUpMVDDCVoltage); 3562 data->vbios_boot_state.vddc_bootup_value = 3563 le16_to_cpu(fw_info->usBootUpVDDCVoltage); 3564 data->vbios_boot_state.vddci_bootup_value = 3565 le16_to_cpu(fw_info->usBootUpVDDCIVoltage); 3566 data->vbios_boot_state.pcie_gen_bootup_value = 3567 smu7_get_current_pcie_speed(hwmgr); 3568 3569 data->vbios_boot_state.pcie_lane_bootup_value = 3570 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr); 3571 3572 /* set boot power state */ 3573 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; 3574 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; 3575 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; 3576 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; 3577 3578 return 0; 3579 } 3580 3581 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) 3582 { 3583 int result; 3584 unsigned long ret = 0; 3585 3586 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3587 result = pp_tables_get_num_of_entries(hwmgr, &ret); 3588 return result ? 0 : ret; 3589 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3590 result = get_number_of_powerplay_table_entries_v1_0(hwmgr); 3591 return result; 3592 } 3593 return 0; 3594 } 3595 3596 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, 3597 void *state, struct pp_power_state *power_state, 3598 void *pp_table, uint32_t classification_flag) 3599 { 3600 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3601 struct smu7_power_state *smu7_power_state = 3602 (struct smu7_power_state *)(&(power_state->hardware)); 3603 struct smu7_performance_level *performance_level; 3604 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; 3605 ATOM_Tonga_POWERPLAYTABLE *powerplay_table = 3606 (ATOM_Tonga_POWERPLAYTABLE *)pp_table; 3607 PPTable_Generic_SubTable_Header *sclk_dep_table = 3608 (PPTable_Generic_SubTable_Header *) 3609 (((unsigned long)powerplay_table) + 3610 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); 3611 3612 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = 3613 (ATOM_Tonga_MCLK_Dependency_Table *) 3614 (((unsigned long)powerplay_table) + 3615 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3616 3617 /* The following fields are not initialized here: id orderedList allStatesList */ 3618 power_state->classification.ui_label = 3619 (le16_to_cpu(state_entry->usClassification) & 3620 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3621 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3622 power_state->classification.flags = classification_flag; 3623 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ 3624 3625 power_state->classification.temporary_state = false; 3626 power_state->classification.to_be_deleted = false; 3627 3628 power_state->validation.disallowOnDC = 3629 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3630 ATOM_Tonga_DISALLOW_ON_DC)); 3631 3632 power_state->pcie.lanes = 0; 3633 3634 power_state->display.disableFrameModulation = false; 3635 power_state->display.limitRefreshrate = false; 3636 power_state->display.enableVariBright = 3637 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3638 ATOM_Tonga_ENABLE_VARIBRIGHT)); 3639 3640 power_state->validation.supportedPowerLevels = 0; 3641 power_state->uvd_clocks.VCLK = 0; 3642 power_state->uvd_clocks.DCLK = 0; 3643 power_state->temperatures.min = 0; 3644 power_state->temperatures.max = 0; 3645 3646 performance_level = &(smu7_power_state->performance_levels 3647 [smu7_power_state->performance_level_count++]); 3648 3649 PP_ASSERT_WITH_CODE( 3650 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3651 "Performance levels exceeds SMC limit!", 3652 return -EINVAL); 3653 3654 PP_ASSERT_WITH_CODE( 3655 (smu7_power_state->performance_level_count < 3656 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3657 "Performance levels exceeds Driver limit!", 3658 return -EINVAL); 3659 3660 /* Performance levels are arranged from low to high. */ 3661 performance_level->memory_clock = mclk_dep_table->entries 3662 [state_entry->ucMemoryClockIndexLow].ulMclk; 3663 if (sclk_dep_table->ucRevId == 0) 3664 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3665 [state_entry->ucEngineClockIndexLow].ulSclk; 3666 else if (sclk_dep_table->ucRevId == 1) 3667 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3668 [state_entry->ucEngineClockIndexLow].ulSclk; 3669 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3670 state_entry->ucPCIEGenLow); 3671 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3672 state_entry->ucPCIELaneLow); 3673 3674 performance_level = &(smu7_power_state->performance_levels 3675 [smu7_power_state->performance_level_count++]); 3676 performance_level->memory_clock = mclk_dep_table->entries 3677 [state_entry->ucMemoryClockIndexHigh].ulMclk; 3678 3679 if (sclk_dep_table->ucRevId == 0) 3680 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3681 [state_entry->ucEngineClockIndexHigh].ulSclk; 3682 else if (sclk_dep_table->ucRevId == 1) 3683 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3684 [state_entry->ucEngineClockIndexHigh].ulSclk; 3685 3686 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3687 state_entry->ucPCIEGenHigh); 3688 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3689 state_entry->ucPCIELaneHigh); 3690 3691 return 0; 3692 } 3693 3694 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, 3695 unsigned long entry_index, struct pp_power_state *state) 3696 { 3697 int result; 3698 struct smu7_power_state *ps; 3699 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3700 struct phm_ppt_v1_information *table_info = 3701 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3702 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 3703 table_info->vdd_dep_on_mclk; 3704 3705 state->hardware.magic = PHM_VIslands_Magic; 3706 3707 ps = (struct smu7_power_state *)(&state->hardware); 3708 3709 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state, 3710 smu7_get_pp_table_entry_callback_func_v1); 3711 3712 /* This is the earliest time we have all the dependency table and the VBIOS boot state 3713 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state 3714 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state 3715 */ 3716 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3717 if (dep_mclk_table->entries[0].clk != 3718 data->vbios_boot_state.mclk_bootup_value) 3719 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3720 "does not match VBIOS boot MCLK level"); 3721 if (dep_mclk_table->entries[0].vddci != 3722 data->vbios_boot_state.vddci_bootup_value) 3723 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3724 "does not match VBIOS boot VDDCI level"); 3725 } 3726 3727 /* set DC compatible flag if this state supports DC */ 3728 if (!state->validation.disallowOnDC) 3729 ps->dc_compatible = true; 3730 3731 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3732 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3733 3734 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3735 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3736 3737 if (!result) { 3738 uint32_t i; 3739 3740 switch (state->classification.ui_label) { 3741 case PP_StateUILabel_Performance: 3742 data->use_pcie_performance_levels = true; 3743 for (i = 0; i < ps->performance_level_count; i++) { 3744 if (data->pcie_gen_performance.max < 3745 ps->performance_levels[i].pcie_gen) 3746 data->pcie_gen_performance.max = 3747 ps->performance_levels[i].pcie_gen; 3748 3749 if (data->pcie_gen_performance.min > 3750 ps->performance_levels[i].pcie_gen) 3751 data->pcie_gen_performance.min = 3752 ps->performance_levels[i].pcie_gen; 3753 3754 if (data->pcie_lane_performance.max < 3755 ps->performance_levels[i].pcie_lane) 3756 data->pcie_lane_performance.max = 3757 ps->performance_levels[i].pcie_lane; 3758 if (data->pcie_lane_performance.min > 3759 ps->performance_levels[i].pcie_lane) 3760 data->pcie_lane_performance.min = 3761 ps->performance_levels[i].pcie_lane; 3762 } 3763 break; 3764 case PP_StateUILabel_Battery: 3765 data->use_pcie_power_saving_levels = true; 3766 3767 for (i = 0; i < ps->performance_level_count; i++) { 3768 if (data->pcie_gen_power_saving.max < 3769 ps->performance_levels[i].pcie_gen) 3770 data->pcie_gen_power_saving.max = 3771 ps->performance_levels[i].pcie_gen; 3772 3773 if (data->pcie_gen_power_saving.min > 3774 ps->performance_levels[i].pcie_gen) 3775 data->pcie_gen_power_saving.min = 3776 ps->performance_levels[i].pcie_gen; 3777 3778 if (data->pcie_lane_power_saving.max < 3779 ps->performance_levels[i].pcie_lane) 3780 data->pcie_lane_power_saving.max = 3781 ps->performance_levels[i].pcie_lane; 3782 3783 if (data->pcie_lane_power_saving.min > 3784 ps->performance_levels[i].pcie_lane) 3785 data->pcie_lane_power_saving.min = 3786 ps->performance_levels[i].pcie_lane; 3787 } 3788 break; 3789 default: 3790 break; 3791 } 3792 } 3793 return 0; 3794 } 3795 3796 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, 3797 struct pp_hw_power_state *power_state, 3798 unsigned int index, const void *clock_info) 3799 { 3800 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3801 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state); 3802 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info; 3803 struct smu7_performance_level *performance_level; 3804 uint32_t engine_clock, memory_clock; 3805 uint16_t pcie_gen_from_bios; 3806 3807 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow; 3808 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow; 3809 3810 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) 3811 data->highest_mclk = memory_clock; 3812 3813 PP_ASSERT_WITH_CODE( 3814 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3815 "Performance levels exceeds SMC limit!", 3816 return -EINVAL); 3817 3818 PP_ASSERT_WITH_CODE( 3819 (ps->performance_level_count < 3820 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3821 "Performance levels exceeds Driver limit, Skip!", 3822 return 0); 3823 3824 performance_level = &(ps->performance_levels 3825 [ps->performance_level_count++]); 3826 3827 /* Performance levels are arranged from low to high. */ 3828 performance_level->memory_clock = memory_clock; 3829 performance_level->engine_clock = engine_clock; 3830 3831 pcie_gen_from_bios = visland_clk_info->ucPCIEGen; 3832 3833 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios); 3834 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane); 3835 3836 return 0; 3837 } 3838 3839 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, 3840 unsigned long entry_index, struct pp_power_state *state) 3841 { 3842 int result; 3843 struct smu7_power_state *ps; 3844 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3845 struct phm_clock_voltage_dependency_table *dep_mclk_table = 3846 hwmgr->dyn_state.vddci_dependency_on_mclk; 3847 3848 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state)); 3849 3850 state->hardware.magic = PHM_VIslands_Magic; 3851 3852 ps = (struct smu7_power_state *)(&state->hardware); 3853 3854 result = pp_tables_get_entry(hwmgr, entry_index, state, 3855 smu7_get_pp_table_entry_callback_func_v0); 3856 3857 /* 3858 * This is the earliest time we have all the dependency table 3859 * and the VBIOS boot state as 3860 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot 3861 * state if there is only one VDDCI/MCLK level, check if it's 3862 * the same as VBIOS boot state 3863 */ 3864 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3865 if (dep_mclk_table->entries[0].clk != 3866 data->vbios_boot_state.mclk_bootup_value) 3867 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3868 "does not match VBIOS boot MCLK level"); 3869 if (dep_mclk_table->entries[0].v != 3870 data->vbios_boot_state.vddci_bootup_value) 3871 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3872 "does not match VBIOS boot VDDCI level"); 3873 } 3874 3875 /* set DC compatible flag if this state supports DC */ 3876 if (!state->validation.disallowOnDC) 3877 ps->dc_compatible = true; 3878 3879 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3880 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3881 3882 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3883 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3884 3885 if (!result) { 3886 uint32_t i; 3887 3888 switch (state->classification.ui_label) { 3889 case PP_StateUILabel_Performance: 3890 data->use_pcie_performance_levels = true; 3891 3892 for (i = 0; i < ps->performance_level_count; i++) { 3893 if (data->pcie_gen_performance.max < 3894 ps->performance_levels[i].pcie_gen) 3895 data->pcie_gen_performance.max = 3896 ps->performance_levels[i].pcie_gen; 3897 3898 if (data->pcie_gen_performance.min > 3899 ps->performance_levels[i].pcie_gen) 3900 data->pcie_gen_performance.min = 3901 ps->performance_levels[i].pcie_gen; 3902 3903 if (data->pcie_lane_performance.max < 3904 ps->performance_levels[i].pcie_lane) 3905 data->pcie_lane_performance.max = 3906 ps->performance_levels[i].pcie_lane; 3907 3908 if (data->pcie_lane_performance.min > 3909 ps->performance_levels[i].pcie_lane) 3910 data->pcie_lane_performance.min = 3911 ps->performance_levels[i].pcie_lane; 3912 } 3913 break; 3914 case PP_StateUILabel_Battery: 3915 data->use_pcie_power_saving_levels = true; 3916 3917 for (i = 0; i < ps->performance_level_count; i++) { 3918 if (data->pcie_gen_power_saving.max < 3919 ps->performance_levels[i].pcie_gen) 3920 data->pcie_gen_power_saving.max = 3921 ps->performance_levels[i].pcie_gen; 3922 3923 if (data->pcie_gen_power_saving.min > 3924 ps->performance_levels[i].pcie_gen) 3925 data->pcie_gen_power_saving.min = 3926 ps->performance_levels[i].pcie_gen; 3927 3928 if (data->pcie_lane_power_saving.max < 3929 ps->performance_levels[i].pcie_lane) 3930 data->pcie_lane_power_saving.max = 3931 ps->performance_levels[i].pcie_lane; 3932 3933 if (data->pcie_lane_power_saving.min > 3934 ps->performance_levels[i].pcie_lane) 3935 data->pcie_lane_power_saving.min = 3936 ps->performance_levels[i].pcie_lane; 3937 } 3938 break; 3939 default: 3940 break; 3941 } 3942 } 3943 return 0; 3944 } 3945 3946 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3947 unsigned long entry_index, struct pp_power_state *state) 3948 { 3949 if (hwmgr->pp_table_version == PP_TABLE_V0) 3950 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state); 3951 else if (hwmgr->pp_table_version == PP_TABLE_V1) 3952 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state); 3953 3954 return 0; 3955 } 3956 3957 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) 3958 { 3959 struct amdgpu_device *adev = hwmgr->adev; 3960 int i; 3961 u32 tmp = 0; 3962 3963 if (!query) 3964 return -EINVAL; 3965 3966 /* 3967 * PPSMC_MSG_GetCurrPkgPwr is not supported on: 3968 * - Hawaii 3969 * - Bonaire 3970 * - Fiji 3971 * - Tonga 3972 */ 3973 if ((adev->asic_type != CHIP_HAWAII) && 3974 (adev->asic_type != CHIP_BONAIRE) && 3975 (adev->asic_type != CHIP_FIJI) && 3976 (adev->asic_type != CHIP_TONGA)) { 3977 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0, &tmp); 3978 *query = tmp; 3979 3980 if (tmp != 0) 3981 return 0; 3982 } 3983 3984 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart, NULL); 3985 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 3986 ixSMU_PM_STATUS_95, 0); 3987 3988 for (i = 0; i < 10; i++) { 3989 msleep(500); 3990 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample, NULL); 3991 tmp = cgs_read_ind_register(hwmgr->device, 3992 CGS_IND_REG__SMC, 3993 ixSMU_PM_STATUS_95); 3994 if (tmp != 0) 3995 break; 3996 } 3997 *query = tmp; 3998 3999 return 0; 4000 } 4001 4002 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, 4003 void *value, int *size) 4004 { 4005 uint32_t sclk, mclk, activity_percent; 4006 uint32_t offset, val_vid; 4007 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4008 4009 /* size must be at least 4 bytes for all sensors */ 4010 if (*size < 4) 4011 return -EINVAL; 4012 4013 switch (idx) { 4014 case AMDGPU_PP_SENSOR_GFX_SCLK: 4015 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &sclk); 4016 *((uint32_t *)value) = sclk; 4017 *size = 4; 4018 return 0; 4019 case AMDGPU_PP_SENSOR_GFX_MCLK: 4020 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &mclk); 4021 *((uint32_t *)value) = mclk; 4022 *size = 4; 4023 return 0; 4024 case AMDGPU_PP_SENSOR_GPU_LOAD: 4025 case AMDGPU_PP_SENSOR_MEM_LOAD: 4026 offset = data->soft_regs_start + smum_get_offsetof(hwmgr, 4027 SMU_SoftRegisters, 4028 (idx == AMDGPU_PP_SENSOR_GPU_LOAD) ? 4029 AverageGraphicsActivity: 4030 AverageMemoryActivity); 4031 4032 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); 4033 activity_percent += 0x80; 4034 activity_percent >>= 8; 4035 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 4036 *size = 4; 4037 return 0; 4038 case AMDGPU_PP_SENSOR_GPU_TEMP: 4039 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr); 4040 *size = 4; 4041 return 0; 4042 case AMDGPU_PP_SENSOR_UVD_POWER: 4043 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 4044 *size = 4; 4045 return 0; 4046 case AMDGPU_PP_SENSOR_VCE_POWER: 4047 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 4048 *size = 4; 4049 return 0; 4050 case AMDGPU_PP_SENSOR_GPU_POWER: 4051 return smu7_get_gpu_power(hwmgr, (uint32_t *)value); 4052 case AMDGPU_PP_SENSOR_VDDGFX: 4053 if ((data->vr_config & VRCONF_VDDGFX_MASK) == 4054 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT)) 4055 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 4056 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID); 4057 else 4058 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 4059 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID); 4060 4061 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); 4062 return 0; 4063 default: 4064 return -EOPNOTSUPP; 4065 } 4066 } 4067 4068 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 4069 { 4070 const struct phm_set_power_state_input *states = 4071 (const struct phm_set_power_state_input *)input; 4072 const struct smu7_power_state *smu7_ps = 4073 cast_const_phw_smu7_power_state(states->pnew_state); 4074 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4075 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4076 uint32_t sclk = smu7_ps->performance_levels 4077 [smu7_ps->performance_level_count - 1].engine_clock; 4078 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4079 uint32_t mclk = smu7_ps->performance_levels 4080 [smu7_ps->performance_level_count - 1].memory_clock; 4081 struct PP_Clocks min_clocks = {0}; 4082 uint32_t i; 4083 4084 for (i = 0; i < sclk_table->count; i++) { 4085 if (sclk == sclk_table->dpm_levels[i].value) 4086 break; 4087 } 4088 4089 if (i >= sclk_table->count) { 4090 if (sclk > sclk_table->dpm_levels[i-1].value) { 4091 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 4092 sclk_table->dpm_levels[i-1].value = sclk; 4093 } 4094 } else { 4095 /* TODO: Check SCLK in DAL's minimum clocks 4096 * in case DeepSleep divider update is required. 4097 */ 4098 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && 4099 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || 4100 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4101 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 4102 } 4103 4104 for (i = 0; i < mclk_table->count; i++) { 4105 if (mclk == mclk_table->dpm_levels[i].value) 4106 break; 4107 } 4108 4109 if (i >= mclk_table->count) { 4110 if (mclk > mclk_table->dpm_levels[i-1].value) { 4111 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 4112 mclk_table->dpm_levels[i-1].value = mclk; 4113 } 4114 } 4115 4116 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4117 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 4118 4119 return 0; 4120 } 4121 4122 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, 4123 const struct smu7_power_state *smu7_ps) 4124 { 4125 uint32_t i; 4126 uint32_t sclk, max_sclk = 0; 4127 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4128 struct smu7_dpm_table *dpm_table = &data->dpm_table; 4129 4130 for (i = 0; i < smu7_ps->performance_level_count; i++) { 4131 sclk = smu7_ps->performance_levels[i].engine_clock; 4132 if (max_sclk < sclk) 4133 max_sclk = sclk; 4134 } 4135 4136 for (i = 0; i < dpm_table->sclk_table.count; i++) { 4137 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) 4138 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? 4139 dpm_table->pcie_speed_table.dpm_levels 4140 [dpm_table->pcie_speed_table.count - 1].value : 4141 dpm_table->pcie_speed_table.dpm_levels[i].value); 4142 } 4143 4144 return 0; 4145 } 4146 4147 static int smu7_request_link_speed_change_before_state_change( 4148 struct pp_hwmgr *hwmgr, const void *input) 4149 { 4150 const struct phm_set_power_state_input *states = 4151 (const struct phm_set_power_state_input *)input; 4152 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4153 const struct smu7_power_state *smu7_nps = 4154 cast_const_phw_smu7_power_state(states->pnew_state); 4155 const struct smu7_power_state *polaris10_cps = 4156 cast_const_phw_smu7_power_state(states->pcurrent_state); 4157 4158 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps); 4159 uint16_t current_link_speed; 4160 4161 if (data->force_pcie_gen == PP_PCIEGenInvalid) 4162 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps); 4163 else 4164 current_link_speed = data->force_pcie_gen; 4165 4166 data->force_pcie_gen = PP_PCIEGenInvalid; 4167 data->pspp_notify_required = false; 4168 4169 if (target_link_speed > current_link_speed) { 4170 switch (target_link_speed) { 4171 #ifdef CONFIG_ACPI 4172 case PP_PCIEGen3: 4173 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false)) 4174 break; 4175 data->force_pcie_gen = PP_PCIEGen2; 4176 if (current_link_speed == PP_PCIEGen2) 4177 break; 4178 fallthrough; 4179 case PP_PCIEGen2: 4180 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false)) 4181 break; 4182 fallthrough; 4183 #endif 4184 default: 4185 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr); 4186 break; 4187 } 4188 } else { 4189 if (target_link_speed < current_link_speed) 4190 data->pspp_notify_required = true; 4191 } 4192 4193 return 0; 4194 } 4195 4196 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 4197 { 4198 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4199 4200 if (0 == data->need_update_smu7_dpm_table) 4201 return 0; 4202 4203 if ((0 == data->sclk_dpm_key_disabled) && 4204 (data->need_update_smu7_dpm_table & 4205 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 4206 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4207 "Trying to freeze SCLK DPM when DPM is disabled", 4208 ); 4209 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4210 PPSMC_MSG_SCLKDPM_FreezeLevel, 4211 NULL), 4212 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", 4213 return -EINVAL); 4214 } 4215 4216 if ((0 == data->mclk_dpm_key_disabled) && 4217 !data->mclk_ignore_signal && 4218 (data->need_update_smu7_dpm_table & 4219 DPMTABLE_OD_UPDATE_MCLK)) { 4220 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4221 "Trying to freeze MCLK DPM when DPM is disabled", 4222 ); 4223 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4224 PPSMC_MSG_MCLKDPM_FreezeLevel, 4225 NULL), 4226 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", 4227 return -EINVAL); 4228 } 4229 4230 return 0; 4231 } 4232 4233 static int smu7_populate_and_upload_sclk_mclk_dpm_levels( 4234 struct pp_hwmgr *hwmgr, const void *input) 4235 { 4236 int result = 0; 4237 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4238 struct smu7_dpm_table *dpm_table = &data->dpm_table; 4239 uint32_t count; 4240 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 4241 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 4242 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 4243 4244 if (0 == data->need_update_smu7_dpm_table) 4245 return 0; 4246 4247 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 4248 for (count = 0; count < dpm_table->sclk_table.count; count++) { 4249 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; 4250 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; 4251 } 4252 } 4253 4254 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 4255 for (count = 0; count < dpm_table->mclk_table.count; count++) { 4256 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; 4257 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; 4258 } 4259 } 4260 4261 if (data->need_update_smu7_dpm_table & 4262 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { 4263 result = smum_populate_all_graphic_levels(hwmgr); 4264 PP_ASSERT_WITH_CODE((0 == result), 4265 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 4266 return result); 4267 } 4268 4269 if (data->need_update_smu7_dpm_table & 4270 (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { 4271 /*populate MCLK dpm table to SMU7 */ 4272 result = smum_populate_all_memory_levels(hwmgr); 4273 PP_ASSERT_WITH_CODE((0 == result), 4274 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 4275 return result); 4276 } 4277 4278 return result; 4279 } 4280 4281 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 4282 struct smu7_single_dpm_table *dpm_table, 4283 uint32_t low_limit, uint32_t high_limit) 4284 { 4285 uint32_t i; 4286 4287 /* force the trim if mclk_switching is disabled to prevent flicker */ 4288 bool force_trim = (low_limit == high_limit); 4289 for (i = 0; i < dpm_table->count; i++) { 4290 /*skip the trim if od is enabled*/ 4291 if ((!hwmgr->od_enabled || force_trim) 4292 && (dpm_table->dpm_levels[i].value < low_limit 4293 || dpm_table->dpm_levels[i].value > high_limit)) 4294 dpm_table->dpm_levels[i].enabled = false; 4295 else 4296 dpm_table->dpm_levels[i].enabled = true; 4297 } 4298 4299 return 0; 4300 } 4301 4302 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, 4303 const struct smu7_power_state *smu7_ps) 4304 { 4305 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4306 uint32_t high_limit_count; 4307 4308 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1), 4309 "power state did not have any performance level", 4310 return -EINVAL); 4311 4312 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1; 4313 4314 smu7_trim_single_dpm_states(hwmgr, 4315 &(data->dpm_table.sclk_table), 4316 smu7_ps->performance_levels[0].engine_clock, 4317 smu7_ps->performance_levels[high_limit_count].engine_clock); 4318 4319 smu7_trim_single_dpm_states(hwmgr, 4320 &(data->dpm_table.mclk_table), 4321 smu7_ps->performance_levels[0].memory_clock, 4322 smu7_ps->performance_levels[high_limit_count].memory_clock); 4323 4324 return 0; 4325 } 4326 4327 static int smu7_generate_dpm_level_enable_mask( 4328 struct pp_hwmgr *hwmgr, const void *input) 4329 { 4330 int result = 0; 4331 const struct phm_set_power_state_input *states = 4332 (const struct phm_set_power_state_input *)input; 4333 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4334 const struct smu7_power_state *smu7_ps = 4335 cast_const_phw_smu7_power_state(states->pnew_state); 4336 4337 4338 result = smu7_trim_dpm_states(hwmgr, smu7_ps); 4339 if (result) 4340 return result; 4341 4342 data->dpm_level_enable_mask.sclk_dpm_enable_mask = 4343 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); 4344 data->dpm_level_enable_mask.mclk_dpm_enable_mask = 4345 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); 4346 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 4347 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); 4348 4349 return 0; 4350 } 4351 4352 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 4353 { 4354 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4355 4356 if (0 == data->need_update_smu7_dpm_table) 4357 return 0; 4358 4359 if ((0 == data->sclk_dpm_key_disabled) && 4360 (data->need_update_smu7_dpm_table & 4361 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { 4362 4363 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4364 "Trying to Unfreeze SCLK DPM when DPM is disabled", 4365 ); 4366 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4367 PPSMC_MSG_SCLKDPM_UnfreezeLevel, 4368 NULL), 4369 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", 4370 return -EINVAL); 4371 } 4372 4373 if ((0 == data->mclk_dpm_key_disabled) && 4374 !data->mclk_ignore_signal && 4375 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 4376 4377 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 4378 "Trying to Unfreeze MCLK DPM when DPM is disabled", 4379 ); 4380 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 4381 PPSMC_MSG_MCLKDPM_UnfreezeLevel, 4382 NULL), 4383 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 4384 return -EINVAL); 4385 } 4386 4387 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 4388 4389 return 0; 4390 } 4391 4392 static int smu7_notify_link_speed_change_after_state_change( 4393 struct pp_hwmgr *hwmgr, const void *input) 4394 { 4395 const struct phm_set_power_state_input *states = 4396 (const struct phm_set_power_state_input *)input; 4397 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4398 const struct smu7_power_state *smu7_ps = 4399 cast_const_phw_smu7_power_state(states->pnew_state); 4400 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps); 4401 uint8_t request; 4402 4403 if (data->pspp_notify_required) { 4404 if (target_link_speed == PP_PCIEGen3) 4405 request = PCIE_PERF_REQ_GEN3; 4406 else if (target_link_speed == PP_PCIEGen2) 4407 request = PCIE_PERF_REQ_GEN2; 4408 else 4409 request = PCIE_PERF_REQ_GEN1; 4410 4411 if (request == PCIE_PERF_REQ_GEN1 && 4412 smu7_get_current_pcie_speed(hwmgr) > 0) 4413 return 0; 4414 4415 #ifdef CONFIG_ACPI 4416 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) { 4417 if (PP_PCIEGen2 == target_link_speed) 4418 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!"); 4419 else 4420 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!"); 4421 } 4422 #endif 4423 } 4424 4425 return 0; 4426 } 4427 4428 static int smu7_notify_no_display(struct pp_hwmgr *hwmgr) 4429 { 4430 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay, NULL) == 0) ? 0 : -EINVAL; 4431 } 4432 4433 static int smu7_notify_has_display(struct pp_hwmgr *hwmgr) 4434 { 4435 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4436 4437 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { 4438 if (hwmgr->chip_id == CHIP_VEGAM) 4439 smum_send_msg_to_smc_with_parameter(hwmgr, 4440 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2, 4441 NULL); 4442 else 4443 smum_send_msg_to_smc_with_parameter(hwmgr, 4444 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2, 4445 NULL); 4446 data->last_sent_vbi_timeout = data->frame_time_x2; 4447 } 4448 4449 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay, NULL) == 0) ? 0 : -EINVAL; 4450 } 4451 4452 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) 4453 { 4454 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4455 int result = 0; 4456 4457 if (data->mclk_ignore_signal) 4458 result = smu7_notify_no_display(hwmgr); 4459 else 4460 result = smu7_notify_has_display(hwmgr); 4461 4462 return result; 4463 } 4464 4465 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 4466 { 4467 int tmp_result, result = 0; 4468 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4469 4470 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 4471 PP_ASSERT_WITH_CODE((0 == tmp_result), 4472 "Failed to find DPM states clocks in DPM table!", 4473 result = tmp_result); 4474 4475 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4476 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4477 tmp_result = 4478 smu7_request_link_speed_change_before_state_change(hwmgr, input); 4479 PP_ASSERT_WITH_CODE((0 == tmp_result), 4480 "Failed to request link speed change before state change!", 4481 result = tmp_result); 4482 } 4483 4484 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); 4485 PP_ASSERT_WITH_CODE((0 == tmp_result), 4486 "Failed to freeze SCLK MCLK DPM!", result = tmp_result); 4487 4488 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 4489 PP_ASSERT_WITH_CODE((0 == tmp_result), 4490 "Failed to populate and upload SCLK MCLK DPM levels!", 4491 result = tmp_result); 4492 4493 /* 4494 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 4495 * That effectively disables AVFS feature. 4496 */ 4497 if (hwmgr->hardcode_pp_table != NULL) 4498 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 4499 4500 tmp_result = smu7_update_avfs(hwmgr); 4501 PP_ASSERT_WITH_CODE((0 == tmp_result), 4502 "Failed to update avfs voltages!", 4503 result = tmp_result); 4504 4505 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input); 4506 PP_ASSERT_WITH_CODE((0 == tmp_result), 4507 "Failed to generate DPM level enabled mask!", 4508 result = tmp_result); 4509 4510 tmp_result = smum_update_sclk_threshold(hwmgr); 4511 PP_ASSERT_WITH_CODE((0 == tmp_result), 4512 "Failed to update SCLK threshold!", 4513 result = tmp_result); 4514 4515 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); 4516 PP_ASSERT_WITH_CODE((0 == tmp_result), 4517 "Failed to unfreeze SCLK MCLK DPM!", 4518 result = tmp_result); 4519 4520 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr); 4521 PP_ASSERT_WITH_CODE((0 == tmp_result), 4522 "Failed to upload DPM level enabled mask!", 4523 result = tmp_result); 4524 4525 tmp_result = smu7_notify_smc_display(hwmgr); 4526 PP_ASSERT_WITH_CODE((0 == tmp_result), 4527 "Failed to notify smc display settings!", 4528 result = tmp_result); 4529 4530 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4531 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4532 tmp_result = 4533 smu7_notify_link_speed_change_after_state_change(hwmgr, input); 4534 PP_ASSERT_WITH_CODE((0 == tmp_result), 4535 "Failed to notify link speed change after state change!", 4536 result = tmp_result); 4537 } 4538 data->apply_optimized_settings = false; 4539 return result; 4540 } 4541 4542 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) 4543 { 4544 hwmgr->thermal_controller. 4545 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 4546 4547 return smum_send_msg_to_smc_with_parameter(hwmgr, 4548 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm, 4549 NULL); 4550 } 4551 4552 static int 4553 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 4554 { 4555 return 0; 4556 } 4557 4558 /** 4559 * smu7_program_display_gap - Programs the display gap 4560 * 4561 * @hwmgr: the address of the powerplay hardware manager. 4562 * Return: always OK 4563 */ 4564 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 4565 { 4566 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4567 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); 4568 uint32_t display_gap2; 4569 uint32_t pre_vbi_time_in_us; 4570 uint32_t frame_time_in_us; 4571 uint32_t ref_clock, refresh_rate; 4572 4573 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); 4574 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); 4575 4576 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 4577 refresh_rate = hwmgr->display_config->vrefresh; 4578 4579 if (0 == refresh_rate) 4580 refresh_rate = 60; 4581 4582 frame_time_in_us = 1000000 / refresh_rate; 4583 4584 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time; 4585 4586 data->frame_time_x2 = frame_time_in_us * 2 / 100; 4587 4588 if (data->frame_time_x2 < 280) { 4589 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2); 4590 data->frame_time_x2 = 280; 4591 } 4592 4593 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); 4594 4595 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); 4596 4597 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4598 data->soft_regs_start + smum_get_offsetof(hwmgr, 4599 SMU_SoftRegisters, 4600 PreVBlankGap), 0x64); 4601 4602 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4603 data->soft_regs_start + smum_get_offsetof(hwmgr, 4604 SMU_SoftRegisters, 4605 VBlankTimeout), 4606 (frame_time_in_us - pre_vbi_time_in_us)); 4607 4608 return 0; 4609 } 4610 4611 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4612 { 4613 return smu7_program_display_gap(hwmgr); 4614 } 4615 4616 /** 4617 * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM 4618 * 4619 * @hwmgr: the address of the powerplay hardware manager. 4620 * @us_max_fan_rpm: max operating fan RPM value. 4621 * Return: The response that came from the SMC. 4622 */ 4623 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) 4624 { 4625 hwmgr->thermal_controller. 4626 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 4627 4628 return smum_send_msg_to_smc_with_parameter(hwmgr, 4629 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm, 4630 NULL); 4631 } 4632 4633 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = { 4634 .process = phm_irq_process, 4635 }; 4636 4637 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) 4638 { 4639 struct amdgpu_irq_src *source = 4640 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); 4641 4642 if (!source) 4643 return -ENOMEM; 4644 4645 source->funcs = &smu7_irq_funcs; 4646 4647 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4648 AMDGPU_IRQ_CLIENTID_LEGACY, 4649 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH, 4650 source); 4651 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4652 AMDGPU_IRQ_CLIENTID_LEGACY, 4653 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW, 4654 source); 4655 4656 /* Register CTF(GPIO_19) interrupt */ 4657 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4658 AMDGPU_IRQ_CLIENTID_LEGACY, 4659 VISLANDS30_IV_SRCID_GPIO_19, 4660 source); 4661 4662 return 0; 4663 } 4664 4665 static bool 4666 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 4667 { 4668 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4669 bool is_update_required = false; 4670 4671 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4672 is_update_required = true; 4673 4674 if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh) 4675 is_update_required = true; 4676 4677 if (hwmgr->chip_id >= CHIP_POLARIS10 && 4678 hwmgr->chip_id <= CHIP_VEGAM && 4679 data->last_sent_vbi_timeout != data->frame_time_x2) 4680 is_update_required = true; 4681 4682 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 4683 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr && 4684 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || 4685 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4686 is_update_required = true; 4687 } 4688 return is_update_required; 4689 } 4690 4691 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, 4692 const struct smu7_performance_level *pl2) 4693 { 4694 return ((pl1->memory_clock == pl2->memory_clock) && 4695 (pl1->engine_clock == pl2->engine_clock) && 4696 (pl1->pcie_gen == pl2->pcie_gen) && 4697 (pl1->pcie_lane == pl2->pcie_lane)); 4698 } 4699 4700 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, 4701 const struct pp_hw_power_state *pstate1, 4702 const struct pp_hw_power_state *pstate2, bool *equal) 4703 { 4704 const struct smu7_power_state *psa; 4705 const struct smu7_power_state *psb; 4706 int i; 4707 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4708 4709 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 4710 return -EINVAL; 4711 4712 psa = cast_const_phw_smu7_power_state(pstate1); 4713 psb = cast_const_phw_smu7_power_state(pstate2); 4714 /* If the two states don't even have the same number of performance levels they cannot be the same state. */ 4715 if (psa->performance_level_count != psb->performance_level_count) { 4716 *equal = false; 4717 return 0; 4718 } 4719 4720 for (i = 0; i < psa->performance_level_count; i++) { 4721 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { 4722 /* If we have found even one performance level pair that is different the states are different. */ 4723 *equal = false; 4724 return 0; 4725 } 4726 } 4727 4728 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 4729 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); 4730 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); 4731 *equal &= (psa->sclk_threshold == psb->sclk_threshold); 4732 /* For OD call, set value based on flag */ 4733 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | 4734 DPMTABLE_OD_UPDATE_MCLK | 4735 DPMTABLE_OD_UPDATE_VDDC)); 4736 4737 return 0; 4738 } 4739 4740 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr) 4741 { 4742 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4743 4744 uint32_t tmp; 4745 4746 /* Read MC indirect register offset 0x9F bits [3:0] to see 4747 * if VBIOS has already loaded a full version of MC ucode 4748 * or not. 4749 */ 4750 4751 smu7_get_mc_microcode_version(hwmgr); 4752 4753 data->need_long_memory_training = false; 4754 4755 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 4756 ixMC_IO_DEBUG_UP_13); 4757 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 4758 4759 if (tmp & (1 << 23)) { 4760 data->mem_latency_high = MEM_LATENCY_HIGH; 4761 data->mem_latency_low = MEM_LATENCY_LOW; 4762 if ((hwmgr->chip_id == CHIP_POLARIS10) || 4763 (hwmgr->chip_id == CHIP_POLARIS11) || 4764 (hwmgr->chip_id == CHIP_POLARIS12)) 4765 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC, NULL); 4766 } else { 4767 data->mem_latency_high = 330; 4768 data->mem_latency_low = 330; 4769 if ((hwmgr->chip_id == CHIP_POLARIS10) || 4770 (hwmgr->chip_id == CHIP_POLARIS11) || 4771 (hwmgr->chip_id == CHIP_POLARIS12)) 4772 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC, NULL); 4773 } 4774 4775 return 0; 4776 } 4777 4778 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) 4779 { 4780 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4781 4782 data->clock_registers.vCG_SPLL_FUNC_CNTL = 4783 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); 4784 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = 4785 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); 4786 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = 4787 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); 4788 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = 4789 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); 4790 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = 4791 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); 4792 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = 4793 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); 4794 data->clock_registers.vDLL_CNTL = 4795 cgs_read_register(hwmgr->device, mmDLL_CNTL); 4796 data->clock_registers.vMCLK_PWRMGT_CNTL = 4797 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); 4798 data->clock_registers.vMPLL_AD_FUNC_CNTL = 4799 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); 4800 data->clock_registers.vMPLL_DQ_FUNC_CNTL = 4801 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); 4802 data->clock_registers.vMPLL_FUNC_CNTL = 4803 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); 4804 data->clock_registers.vMPLL_FUNC_CNTL_1 = 4805 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); 4806 data->clock_registers.vMPLL_FUNC_CNTL_2 = 4807 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); 4808 data->clock_registers.vMPLL_SS1 = 4809 cgs_read_register(hwmgr->device, mmMPLL_SS1); 4810 data->clock_registers.vMPLL_SS2 = 4811 cgs_read_register(hwmgr->device, mmMPLL_SS2); 4812 return 0; 4813 4814 } 4815 4816 /** 4817 * smu7_get_memory_type - Find out if memory is GDDR5. 4818 * 4819 * @hwmgr: the address of the powerplay hardware manager. 4820 * Return: always 0 4821 */ 4822 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) 4823 { 4824 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4825 struct amdgpu_device *adev = hwmgr->adev; 4826 4827 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5); 4828 4829 return 0; 4830 } 4831 4832 /** 4833 * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC 4834 * 4835 * @hwmgr: the address of the powerplay hardware manager. 4836 * Return: always 0 4837 */ 4838 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) 4839 { 4840 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 4841 GENERAL_PWRMGT, STATIC_PM_EN, 1); 4842 4843 return 0; 4844 } 4845 4846 /** 4847 * smu7_init_power_gate_state - Initialize PowerGating States for different engines 4848 * 4849 * @hwmgr: the address of the powerplay hardware manager. 4850 * Return: always 0 4851 */ 4852 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) 4853 { 4854 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4855 4856 data->uvd_power_gated = false; 4857 data->vce_power_gated = false; 4858 4859 return 0; 4860 } 4861 4862 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) 4863 { 4864 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4865 4866 data->low_sclk_interrupt_threshold = 0; 4867 return 0; 4868 } 4869 4870 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) 4871 { 4872 int tmp_result, result = 0; 4873 4874 smu7_check_mc_firmware(hwmgr); 4875 4876 tmp_result = smu7_read_clock_registers(hwmgr); 4877 PP_ASSERT_WITH_CODE((0 == tmp_result), 4878 "Failed to read clock registers!", result = tmp_result); 4879 4880 tmp_result = smu7_get_memory_type(hwmgr); 4881 PP_ASSERT_WITH_CODE((0 == tmp_result), 4882 "Failed to get memory type!", result = tmp_result); 4883 4884 tmp_result = smu7_enable_acpi_power_management(hwmgr); 4885 PP_ASSERT_WITH_CODE((0 == tmp_result), 4886 "Failed to enable ACPI power management!", result = tmp_result); 4887 4888 tmp_result = smu7_init_power_gate_state(hwmgr); 4889 PP_ASSERT_WITH_CODE((0 == tmp_result), 4890 "Failed to init power gate state!", result = tmp_result); 4891 4892 tmp_result = smu7_get_mc_microcode_version(hwmgr); 4893 PP_ASSERT_WITH_CODE((0 == tmp_result), 4894 "Failed to get MC microcode version!", result = tmp_result); 4895 4896 tmp_result = smu7_init_sclk_threshold(hwmgr); 4897 PP_ASSERT_WITH_CODE((0 == tmp_result), 4898 "Failed to init sclk threshold!", result = tmp_result); 4899 4900 return result; 4901 } 4902 4903 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 4904 enum pp_clock_type type, uint32_t mask) 4905 { 4906 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4907 4908 if (mask == 0) 4909 return -EINVAL; 4910 4911 switch (type) { 4912 case PP_SCLK: 4913 if (!data->sclk_dpm_key_disabled) 4914 smum_send_msg_to_smc_with_parameter(hwmgr, 4915 PPSMC_MSG_SCLKDPM_SetEnabledMask, 4916 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask, 4917 NULL); 4918 break; 4919 case PP_MCLK: 4920 if (!data->mclk_dpm_key_disabled) 4921 smum_send_msg_to_smc_with_parameter(hwmgr, 4922 PPSMC_MSG_MCLKDPM_SetEnabledMask, 4923 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask, 4924 NULL); 4925 break; 4926 case PP_PCIE: 4927 { 4928 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; 4929 4930 if (!data->pcie_dpm_key_disabled) { 4931 if (fls(tmp) != ffs(tmp)) 4932 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel, 4933 NULL); 4934 else 4935 smum_send_msg_to_smc_with_parameter(hwmgr, 4936 PPSMC_MSG_PCIeDPM_ForceLevel, 4937 fls(tmp) - 1, 4938 NULL); 4939 } 4940 break; 4941 } 4942 default: 4943 break; 4944 } 4945 4946 return 0; 4947 } 4948 4949 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 4950 enum pp_clock_type type, char *buf) 4951 { 4952 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4953 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4954 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4955 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); 4956 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 4957 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 4958 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 4959 int size = 0; 4960 uint32_t i, now, clock, pcie_speed; 4961 4962 switch (type) { 4963 case PP_SCLK: 4964 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency, &clock); 4965 4966 for (i = 0; i < sclk_table->count; i++) { 4967 if (clock > sclk_table->dpm_levels[i].value) 4968 continue; 4969 break; 4970 } 4971 now = i; 4972 4973 for (i = 0; i < sclk_table->count; i++) 4974 size += sprintf(buf + size, "%d: %uMhz %s\n", 4975 i, sclk_table->dpm_levels[i].value / 100, 4976 (i == now) ? "*" : ""); 4977 break; 4978 case PP_MCLK: 4979 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock); 4980 4981 for (i = 0; i < mclk_table->count; i++) { 4982 if (clock > mclk_table->dpm_levels[i].value) 4983 continue; 4984 break; 4985 } 4986 now = i; 4987 4988 for (i = 0; i < mclk_table->count; i++) 4989 size += sprintf(buf + size, "%d: %uMhz %s\n", 4990 i, mclk_table->dpm_levels[i].value / 100, 4991 (i == now) ? "*" : ""); 4992 break; 4993 case PP_PCIE: 4994 pcie_speed = smu7_get_current_pcie_speed(hwmgr); 4995 for (i = 0; i < pcie_table->count; i++) { 4996 if (pcie_speed != pcie_table->dpm_levels[i].value) 4997 continue; 4998 break; 4999 } 5000 now = i; 5001 5002 for (i = 0; i < pcie_table->count; i++) 5003 size += sprintf(buf + size, "%d: %s %s\n", i, 5004 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : 5005 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : 5006 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", 5007 (i == now) ? "*" : ""); 5008 break; 5009 case OD_SCLK: 5010 if (hwmgr->od_enabled) { 5011 size += sprintf(buf + size, "%s:\n", "OD_SCLK"); 5012 for (i = 0; i < odn_sclk_table->num_of_pl; i++) 5013 size += sprintf(buf + size, "%d: %10uMHz %10umV\n", 5014 i, odn_sclk_table->entries[i].clock/100, 5015 odn_sclk_table->entries[i].vddc); 5016 } 5017 break; 5018 case OD_MCLK: 5019 if (hwmgr->od_enabled) { 5020 size += sprintf(buf + size, "%s:\n", "OD_MCLK"); 5021 for (i = 0; i < odn_mclk_table->num_of_pl; i++) 5022 size += sprintf(buf + size, "%d: %10uMHz %10umV\n", 5023 i, odn_mclk_table->entries[i].clock/100, 5024 odn_mclk_table->entries[i].vddc); 5025 } 5026 break; 5027 case OD_RANGE: 5028 if (hwmgr->od_enabled) { 5029 size += sprintf(buf + size, "%s:\n", "OD_RANGE"); 5030 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 5031 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 5032 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5033 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", 5034 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 5035 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5036 size += sprintf(buf + size, "VDDC: %7umV %11umV\n", 5037 data->odn_dpm_table.min_vddc, 5038 data->odn_dpm_table.max_vddc); 5039 } 5040 break; 5041 default: 5042 break; 5043 } 5044 return size; 5045 } 5046 5047 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 5048 { 5049 switch (mode) { 5050 case AMD_FAN_CTRL_NONE: 5051 smu7_fan_ctrl_set_fan_speed_pwm(hwmgr, 255); 5052 break; 5053 case AMD_FAN_CTRL_MANUAL: 5054 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 5055 PHM_PlatformCaps_MicrocodeFanControl)) 5056 smu7_fan_ctrl_stop_smc_fan_control(hwmgr); 5057 break; 5058 case AMD_FAN_CTRL_AUTO: 5059 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode)) 5060 smu7_fan_ctrl_start_smc_fan_control(hwmgr); 5061 break; 5062 default: 5063 break; 5064 } 5065 } 5066 5067 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) 5068 { 5069 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL; 5070 } 5071 5072 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) 5073 { 5074 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5075 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5076 struct smu7_single_dpm_table *golden_sclk_table = 5077 &(data->golden_dpm_table.sclk_table); 5078 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; 5079 int golden_value = golden_sclk_table->dpm_levels 5080 [golden_sclk_table->count - 1].value; 5081 5082 value -= golden_value; 5083 value = DIV_ROUND_UP(value * 100, golden_value); 5084 5085 return value; 5086 } 5087 5088 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5089 { 5090 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5091 struct smu7_single_dpm_table *golden_sclk_table = 5092 &(data->golden_dpm_table.sclk_table); 5093 struct pp_power_state *ps; 5094 struct smu7_power_state *smu7_ps; 5095 5096 if (value > 20) 5097 value = 20; 5098 5099 ps = hwmgr->request_ps; 5100 5101 if (ps == NULL) 5102 return -EINVAL; 5103 5104 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 5105 5106 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock = 5107 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * 5108 value / 100 + 5109 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 5110 5111 return 0; 5112 } 5113 5114 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) 5115 { 5116 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5117 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5118 struct smu7_single_dpm_table *golden_mclk_table = 5119 &(data->golden_dpm_table.mclk_table); 5120 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; 5121 int golden_value = golden_mclk_table->dpm_levels 5122 [golden_mclk_table->count - 1].value; 5123 5124 value -= golden_value; 5125 value = DIV_ROUND_UP(value * 100, golden_value); 5126 5127 return value; 5128 } 5129 5130 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 5131 { 5132 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5133 struct smu7_single_dpm_table *golden_mclk_table = 5134 &(data->golden_dpm_table.mclk_table); 5135 struct pp_power_state *ps; 5136 struct smu7_power_state *smu7_ps; 5137 5138 if (value > 20) 5139 value = 20; 5140 5141 ps = hwmgr->request_ps; 5142 5143 if (ps == NULL) 5144 return -EINVAL; 5145 5146 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 5147 5148 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock = 5149 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * 5150 value / 100 + 5151 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 5152 5153 return 0; 5154 } 5155 5156 5157 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 5158 { 5159 struct phm_ppt_v1_information *table_info = 5160 (struct phm_ppt_v1_information *)hwmgr->pptable; 5161 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; 5162 struct phm_clock_voltage_dependency_table *sclk_table; 5163 int i; 5164 5165 if (hwmgr->pp_table_version == PP_TABLE_V1) { 5166 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) 5167 return -EINVAL; 5168 dep_sclk_table = table_info->vdd_dep_on_sclk; 5169 for (i = 0; i < dep_sclk_table->count; i++) 5170 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; 5171 clocks->count = dep_sclk_table->count; 5172 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 5173 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 5174 for (i = 0; i < sclk_table->count; i++) 5175 clocks->clock[i] = sclk_table->entries[i].clk * 10; 5176 clocks->count = sclk_table->count; 5177 } 5178 5179 return 0; 5180 } 5181 5182 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) 5183 { 5184 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5185 5186 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY) 5187 return data->mem_latency_high; 5188 else if (clk >= MEM_FREQ_HIGH_LATENCY) 5189 return data->mem_latency_low; 5190 else 5191 return MEM_LATENCY_ERR; 5192 } 5193 5194 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 5195 { 5196 struct phm_ppt_v1_information *table_info = 5197 (struct phm_ppt_v1_information *)hwmgr->pptable; 5198 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 5199 int i; 5200 struct phm_clock_voltage_dependency_table *mclk_table; 5201 5202 if (hwmgr->pp_table_version == PP_TABLE_V1) { 5203 if (table_info == NULL) 5204 return -EINVAL; 5205 dep_mclk_table = table_info->vdd_dep_on_mclk; 5206 for (i = 0; i < dep_mclk_table->count; i++) { 5207 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; 5208 clocks->latency[i] = smu7_get_mem_latency(hwmgr, 5209 dep_mclk_table->entries[i].clk); 5210 } 5211 clocks->count = dep_mclk_table->count; 5212 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 5213 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 5214 for (i = 0; i < mclk_table->count; i++) 5215 clocks->clock[i] = mclk_table->entries[i].clk * 10; 5216 clocks->count = mclk_table->count; 5217 } 5218 return 0; 5219 } 5220 5221 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, 5222 struct amd_pp_clocks *clocks) 5223 { 5224 switch (type) { 5225 case amd_pp_sys_clock: 5226 smu7_get_sclks(hwmgr, clocks); 5227 break; 5228 case amd_pp_mem_clock: 5229 smu7_get_mclks(hwmgr, clocks); 5230 break; 5231 default: 5232 return -EINVAL; 5233 } 5234 5235 return 0; 5236 } 5237 5238 static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr, 5239 struct pp_clock_levels_with_latency *clocks) 5240 { 5241 struct phm_ppt_v1_information *table_info = 5242 (struct phm_ppt_v1_information *)hwmgr->pptable; 5243 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = 5244 table_info->vdd_dep_on_sclk; 5245 int i; 5246 5247 clocks->num_levels = 0; 5248 for (i = 0; i < dep_sclk_table->count; i++) { 5249 if (dep_sclk_table->entries[i].clk) { 5250 clocks->data[clocks->num_levels].clocks_in_khz = 5251 dep_sclk_table->entries[i].clk * 10; 5252 clocks->num_levels++; 5253 } 5254 } 5255 5256 return 0; 5257 } 5258 5259 static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr, 5260 struct pp_clock_levels_with_latency *clocks) 5261 { 5262 struct phm_ppt_v1_information *table_info = 5263 (struct phm_ppt_v1_information *)hwmgr->pptable; 5264 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 5265 table_info->vdd_dep_on_mclk; 5266 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5267 int i; 5268 5269 clocks->num_levels = 0; 5270 data->mclk_latency_table.count = 0; 5271 for (i = 0; i < dep_mclk_table->count; i++) { 5272 if (dep_mclk_table->entries[i].clk) { 5273 clocks->data[clocks->num_levels].clocks_in_khz = 5274 dep_mclk_table->entries[i].clk * 10; 5275 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency = 5276 dep_mclk_table->entries[i].clk; 5277 clocks->data[clocks->num_levels].latency_in_us = 5278 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency = 5279 smu7_get_mem_latency(hwmgr, dep_mclk_table->entries[i].clk); 5280 clocks->num_levels++; 5281 data->mclk_latency_table.count++; 5282 } 5283 } 5284 5285 return 0; 5286 } 5287 5288 static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 5289 enum amd_pp_clock_type type, 5290 struct pp_clock_levels_with_latency *clocks) 5291 { 5292 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 5293 hwmgr->chip_id <= CHIP_VEGAM)) 5294 return -EINVAL; 5295 5296 switch (type) { 5297 case amd_pp_sys_clock: 5298 smu7_get_sclks_with_latency(hwmgr, clocks); 5299 break; 5300 case amd_pp_mem_clock: 5301 smu7_get_mclks_with_latency(hwmgr, clocks); 5302 break; 5303 default: 5304 return -EINVAL; 5305 } 5306 5307 return 0; 5308 } 5309 5310 static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 5311 void *clock_range) 5312 { 5313 struct phm_ppt_v1_information *table_info = 5314 (struct phm_ppt_v1_information *)hwmgr->pptable; 5315 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 5316 table_info->vdd_dep_on_mclk; 5317 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = 5318 table_info->vdd_dep_on_sclk; 5319 struct polaris10_smumgr *smu_data = 5320 (struct polaris10_smumgr *)(hwmgr->smu_backend); 5321 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); 5322 struct dm_pp_wm_sets_with_clock_ranges *watermarks = 5323 (struct dm_pp_wm_sets_with_clock_ranges *)clock_range; 5324 uint32_t i, j, k; 5325 bool valid_entry; 5326 5327 if (!(hwmgr->chip_id >= CHIP_POLARIS10 && 5328 hwmgr->chip_id <= CHIP_VEGAM)) 5329 return -EINVAL; 5330 5331 for (i = 0; i < dep_mclk_table->count; i++) { 5332 for (j = 0; j < dep_sclk_table->count; j++) { 5333 valid_entry = false; 5334 for (k = 0; k < watermarks->num_wm_sets; k++) { 5335 if (dep_sclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_eng_clk_in_khz / 10 && 5336 dep_sclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_eng_clk_in_khz / 10 && 5337 dep_mclk_table->entries[i].clk >= watermarks->wm_clk_ranges[k].wm_min_mem_clk_in_khz / 10 && 5338 dep_mclk_table->entries[i].clk < watermarks->wm_clk_ranges[k].wm_max_mem_clk_in_khz / 10) { 5339 valid_entry = true; 5340 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k].wm_set_id; 5341 break; 5342 } 5343 } 5344 PP_ASSERT_WITH_CODE(valid_entry, 5345 "Clock is not in range of specified clock range for watermark from DAL! Using highest water mark set.", 5346 table->DisplayWatermark[i][j] = watermarks->wm_clk_ranges[k - 1].wm_set_id); 5347 } 5348 } 5349 5350 return smu7_copy_bytes_to_smc(hwmgr, 5351 smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, DisplayWatermark), 5352 (uint8_t *)table->DisplayWatermark, 5353 sizeof(uint8_t) * SMU74_MAX_LEVELS_MEMORY * SMU74_MAX_LEVELS_GRAPHICS, 5354 SMC_RAM_END); 5355 } 5356 5357 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 5358 uint32_t virtual_addr_low, 5359 uint32_t virtual_addr_hi, 5360 uint32_t mc_addr_low, 5361 uint32_t mc_addr_hi, 5362 uint32_t size) 5363 { 5364 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5365 5366 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5367 data->soft_regs_start + 5368 smum_get_offsetof(hwmgr, 5369 SMU_SoftRegisters, DRAM_LOG_ADDR_H), 5370 mc_addr_hi); 5371 5372 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5373 data->soft_regs_start + 5374 smum_get_offsetof(hwmgr, 5375 SMU_SoftRegisters, DRAM_LOG_ADDR_L), 5376 mc_addr_low); 5377 5378 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5379 data->soft_regs_start + 5380 smum_get_offsetof(hwmgr, 5381 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H), 5382 virtual_addr_hi); 5383 5384 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5385 data->soft_regs_start + 5386 smum_get_offsetof(hwmgr, 5387 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L), 5388 virtual_addr_low); 5389 5390 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 5391 data->soft_regs_start + 5392 smum_get_offsetof(hwmgr, 5393 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE), 5394 size); 5395 return 0; 5396 } 5397 5398 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr, 5399 struct amd_pp_simple_clock_info *clocks) 5400 { 5401 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5402 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 5403 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 5404 5405 if (clocks == NULL) 5406 return -EINVAL; 5407 5408 clocks->memory_max_clock = mclk_table->count > 1 ? 5409 mclk_table->dpm_levels[mclk_table->count-1].value : 5410 mclk_table->dpm_levels[0].value; 5411 clocks->engine_max_clock = sclk_table->count > 1 ? 5412 sclk_table->dpm_levels[sclk_table->count-1].value : 5413 sclk_table->dpm_levels[0].value; 5414 return 0; 5415 } 5416 5417 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 5418 struct PP_TemperatureRange *thermal_data) 5419 { 5420 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5421 struct phm_ppt_v1_information *table_info = 5422 (struct phm_ppt_v1_information *)hwmgr->pptable; 5423 5424 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); 5425 5426 if (hwmgr->pp_table_version == PP_TABLE_V1) 5427 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * 5428 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5429 else if (hwmgr->pp_table_version == PP_TABLE_V0) 5430 thermal_data->max = data->thermal_temp_setting.temperature_shutdown * 5431 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 5432 5433 return 0; 5434 } 5435 5436 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 5437 enum PP_OD_DPM_TABLE_COMMAND type, 5438 uint32_t clk, 5439 uint32_t voltage) 5440 { 5441 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5442 5443 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) { 5444 pr_info("OD voltage is out of range [%d - %d] mV\n", 5445 data->odn_dpm_table.min_vddc, 5446 data->odn_dpm_table.max_vddc); 5447 return false; 5448 } 5449 5450 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 5451 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk || 5452 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 5453 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 5454 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 5455 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 5456 return false; 5457 } 5458 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 5459 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk || 5460 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 5461 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 5462 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 5463 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 5464 return false; 5465 } 5466 } else { 5467 return false; 5468 } 5469 5470 return true; 5471 } 5472 5473 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 5474 enum PP_OD_DPM_TABLE_COMMAND type, 5475 long *input, uint32_t size) 5476 { 5477 uint32_t i; 5478 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL; 5479 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL; 5480 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5481 5482 uint32_t input_clk; 5483 uint32_t input_vol; 5484 uint32_t input_level; 5485 5486 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 5487 return -EINVAL); 5488 5489 if (!hwmgr->od_enabled) { 5490 pr_info("OverDrive feature not enabled\n"); 5491 return -EINVAL; 5492 } 5493 5494 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 5495 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels; 5496 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk; 5497 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 5498 "Failed to get ODN SCLK and Voltage tables", 5499 return -EINVAL); 5500 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 5501 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels; 5502 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk; 5503 5504 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 5505 "Failed to get ODN MCLK and Voltage tables", 5506 return -EINVAL); 5507 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 5508 smu7_odn_initial_default_setting(hwmgr); 5509 return 0; 5510 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 5511 smu7_check_dpm_table_updated(hwmgr); 5512 return 0; 5513 } else { 5514 return -EINVAL; 5515 } 5516 5517 for (i = 0; i < size; i += 3) { 5518 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) { 5519 pr_info("invalid clock voltage input \n"); 5520 return 0; 5521 } 5522 input_level = input[i]; 5523 input_clk = input[i+1] * 100; 5524 input_vol = input[i+2]; 5525 5526 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 5527 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; 5528 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; 5529 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol; 5530 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol; 5531 podn_vdd_dep_in_backend->entries[input_level].vddgfx = input_vol; 5532 } else { 5533 return -EINVAL; 5534 } 5535 } 5536 5537 return 0; 5538 } 5539 5540 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 5541 { 5542 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5543 uint32_t i, size = 0; 5544 uint32_t len; 5545 5546 static const char *title[8] = {"NUM", 5547 "MODE_NAME", 5548 "SCLK_UP_HYST", 5549 "SCLK_DOWN_HYST", 5550 "SCLK_ACTIVE_LEVEL", 5551 "MCLK_UP_HYST", 5552 "MCLK_DOWN_HYST", 5553 "MCLK_ACTIVE_LEVEL"}; 5554 5555 if (!buf) 5556 return -EINVAL; 5557 5558 phm_get_sysfs_buf(&buf, &size); 5559 5560 size += sysfs_emit_at(buf, size, "%s %16s %16s %16s %16s %16s %16s %16s\n", 5561 title[0], title[1], title[2], title[3], 5562 title[4], title[5], title[6], title[7]); 5563 5564 len = ARRAY_SIZE(smu7_profiling); 5565 5566 for (i = 0; i < len; i++) { 5567 if (i == hwmgr->power_profile_mode) { 5568 size += sysfs_emit_at(buf, size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n", 5569 i, amdgpu_pp_profile_name[i], "*", 5570 data->current_profile_setting.sclk_up_hyst, 5571 data->current_profile_setting.sclk_down_hyst, 5572 data->current_profile_setting.sclk_activity, 5573 data->current_profile_setting.mclk_up_hyst, 5574 data->current_profile_setting.mclk_down_hyst, 5575 data->current_profile_setting.mclk_activity); 5576 continue; 5577 } 5578 if (smu7_profiling[i].bupdate_sclk) 5579 size += sysfs_emit_at(buf, size, "%3d %16s: %8d %16d %16d ", 5580 i, amdgpu_pp_profile_name[i], smu7_profiling[i].sclk_up_hyst, 5581 smu7_profiling[i].sclk_down_hyst, 5582 smu7_profiling[i].sclk_activity); 5583 else 5584 size += sysfs_emit_at(buf, size, "%3d %16s: %8s %16s %16s ", 5585 i, amdgpu_pp_profile_name[i], "-", "-", "-"); 5586 5587 if (smu7_profiling[i].bupdate_mclk) 5588 size += sysfs_emit_at(buf, size, "%16d %16d %16d\n", 5589 smu7_profiling[i].mclk_up_hyst, 5590 smu7_profiling[i].mclk_down_hyst, 5591 smu7_profiling[i].mclk_activity); 5592 else 5593 size += sysfs_emit_at(buf, size, "%16s %16s %16s\n", 5594 "-", "-", "-"); 5595 } 5596 5597 return size; 5598 } 5599 5600 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, 5601 enum PP_SMC_POWER_PROFILE requst) 5602 { 5603 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5604 uint32_t tmp, level; 5605 5606 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) { 5607 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 5608 level = 0; 5609 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 5610 while (tmp >>= 1) 5611 level++; 5612 if (level > 0) 5613 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); 5614 } 5615 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { 5616 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); 5617 } 5618 } 5619 5620 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 5621 { 5622 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 5623 struct profile_mode_setting tmp; 5624 enum PP_SMC_POWER_PROFILE mode; 5625 5626 if (input == NULL) 5627 return -EINVAL; 5628 5629 mode = input[size]; 5630 switch (mode) { 5631 case PP_SMC_POWER_PROFILE_CUSTOM: 5632 if (size < 8 && size != 0) 5633 return -EINVAL; 5634 /* If only CUSTOM is passed in, use the saved values. Check 5635 * that we actually have a CUSTOM profile by ensuring that 5636 * the "use sclk" or the "use mclk" bits are set 5637 */ 5638 tmp = smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM]; 5639 if (size == 0) { 5640 if (tmp.bupdate_sclk == 0 && tmp.bupdate_mclk == 0) 5641 return -EINVAL; 5642 } else { 5643 tmp.bupdate_sclk = input[0]; 5644 tmp.sclk_up_hyst = input[1]; 5645 tmp.sclk_down_hyst = input[2]; 5646 tmp.sclk_activity = input[3]; 5647 tmp.bupdate_mclk = input[4]; 5648 tmp.mclk_up_hyst = input[5]; 5649 tmp.mclk_down_hyst = input[6]; 5650 tmp.mclk_activity = input[7]; 5651 smu7_profiling[PP_SMC_POWER_PROFILE_CUSTOM] = tmp; 5652 } 5653 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5654 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting)); 5655 hwmgr->power_profile_mode = mode; 5656 } 5657 break; 5658 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 5659 case PP_SMC_POWER_PROFILE_POWERSAVING: 5660 case PP_SMC_POWER_PROFILE_VIDEO: 5661 case PP_SMC_POWER_PROFILE_VR: 5662 case PP_SMC_POWER_PROFILE_COMPUTE: 5663 if (mode == hwmgr->power_profile_mode) 5664 return 0; 5665 5666 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting)); 5667 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5668 if (tmp.bupdate_sclk) { 5669 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk; 5670 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst; 5671 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst; 5672 data->current_profile_setting.sclk_activity = tmp.sclk_activity; 5673 } 5674 if (tmp.bupdate_mclk) { 5675 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk; 5676 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst; 5677 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst; 5678 data->current_profile_setting.mclk_activity = tmp.mclk_activity; 5679 } 5680 smu7_patch_compute_profile_mode(hwmgr, mode); 5681 hwmgr->power_profile_mode = mode; 5682 } 5683 break; 5684 default: 5685 return -EINVAL; 5686 } 5687 5688 return 0; 5689 } 5690 5691 static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 5692 PHM_PerformanceLevelDesignation designation, uint32_t index, 5693 PHM_PerformanceLevel *level) 5694 { 5695 const struct smu7_power_state *ps; 5696 uint32_t i; 5697 5698 if (level == NULL || hwmgr == NULL || state == NULL) 5699 return -EINVAL; 5700 5701 ps = cast_const_phw_smu7_power_state(state); 5702 5703 i = index > ps->performance_level_count - 1 ? 5704 ps->performance_level_count - 1 : index; 5705 5706 level->coreClock = ps->performance_levels[i].engine_clock; 5707 level->memory_clock = ps->performance_levels[i].memory_clock; 5708 5709 return 0; 5710 } 5711 5712 static int smu7_power_off_asic(struct pp_hwmgr *hwmgr) 5713 { 5714 int result; 5715 5716 result = smu7_disable_dpm_tasks(hwmgr); 5717 PP_ASSERT_WITH_CODE((0 == result), 5718 "[disable_dpm_tasks] Failed to disable DPM!", 5719 ); 5720 5721 return result; 5722 } 5723 5724 static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 5725 .backend_init = &smu7_hwmgr_backend_init, 5726 .backend_fini = &smu7_hwmgr_backend_fini, 5727 .asic_setup = &smu7_setup_asic_task, 5728 .dynamic_state_management_enable = &smu7_enable_dpm_tasks, 5729 .apply_state_adjust_rules = smu7_apply_state_adjust_rules, 5730 .force_dpm_level = &smu7_force_dpm_level, 5731 .power_state_set = smu7_set_power_state_tasks, 5732 .get_power_state_size = smu7_get_power_state_size, 5733 .get_mclk = smu7_dpm_get_mclk, 5734 .get_sclk = smu7_dpm_get_sclk, 5735 .patch_boot_state = smu7_dpm_patch_boot_state, 5736 .get_pp_table_entry = smu7_get_pp_table_entry, 5737 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries, 5738 .powerdown_uvd = smu7_powerdown_uvd, 5739 .powergate_uvd = smu7_powergate_uvd, 5740 .powergate_vce = smu7_powergate_vce, 5741 .disable_clock_power_gating = smu7_disable_clock_power_gating, 5742 .update_clock_gatings = smu7_update_clock_gatings, 5743 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment, 5744 .display_config_changed = smu7_display_configuration_changed_task, 5745 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output, 5746 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output, 5747 .stop_thermal_controller = smu7_thermal_stop_thermal_controller, 5748 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info, 5749 .get_fan_speed_pwm = smu7_fan_ctrl_get_fan_speed_pwm, 5750 .set_fan_speed_pwm = smu7_fan_ctrl_set_fan_speed_pwm, 5751 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default, 5752 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm, 5753 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm, 5754 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller, 5755 .register_irq_handlers = smu7_register_irq_handlers, 5756 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration, 5757 .check_states_equal = smu7_check_states_equal, 5758 .set_fan_control_mode = smu7_set_fan_control_mode, 5759 .get_fan_control_mode = smu7_get_fan_control_mode, 5760 .force_clock_level = smu7_force_clock_level, 5761 .print_clock_levels = smu7_print_clock_levels, 5762 .powergate_gfx = smu7_powergate_gfx, 5763 .get_sclk_od = smu7_get_sclk_od, 5764 .set_sclk_od = smu7_set_sclk_od, 5765 .get_mclk_od = smu7_get_mclk_od, 5766 .set_mclk_od = smu7_set_mclk_od, 5767 .get_clock_by_type = smu7_get_clock_by_type, 5768 .get_clock_by_type_with_latency = smu7_get_clock_by_type_with_latency, 5769 .set_watermarks_for_clocks_ranges = smu7_set_watermarks_for_clocks_ranges, 5770 .read_sensor = smu7_read_sensor, 5771 .dynamic_state_management_disable = smu7_disable_dpm_tasks, 5772 .avfs_control = smu7_avfs_control, 5773 .disable_smc_firmware_ctf = smu7_thermal_disable_alert, 5774 .start_thermal_controller = smu7_start_thermal_controller, 5775 .notify_cac_buffer_info = smu7_notify_cac_buffer_info, 5776 .get_max_high_clocks = smu7_get_max_high_clocks, 5777 .get_thermal_temperature_range = smu7_get_thermal_temperature_range, 5778 .odn_edit_dpm_table = smu7_odn_edit_dpm_table, 5779 .set_power_limit = smu7_set_power_limit, 5780 .get_power_profile_mode = smu7_get_power_profile_mode, 5781 .set_power_profile_mode = smu7_set_power_profile_mode, 5782 .get_performance_level = smu7_get_performance_level, 5783 .get_asic_baco_capability = smu7_baco_get_capability, 5784 .get_asic_baco_state = smu7_baco_get_state, 5785 .set_asic_baco_state = smu7_baco_set_state, 5786 .power_off_asic = smu7_power_off_asic, 5787 }; 5788 5789 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 5790 uint32_t clock_insr) 5791 { 5792 uint8_t i; 5793 uint32_t temp; 5794 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); 5795 5796 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); 5797 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 5798 temp = clock >> i; 5799 5800 if (temp >= min || i == 0) 5801 break; 5802 } 5803 return i; 5804 } 5805 5806 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr) 5807 { 5808 hwmgr->hwmgr_func = &smu7_hwmgr_funcs; 5809 if (hwmgr->pp_table_version == PP_TABLE_V0) 5810 hwmgr->pptable_func = &pptable_funcs; 5811 else if (hwmgr->pp_table_version == PP_TABLE_V1) 5812 hwmgr->pptable_func = &pptable_v1_0_funcs; 5813 5814 return 0; 5815 } 5816