1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "pp_debug.h"
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
28 #include "atombios.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
31 #include "smumgr.h"
32 #include "hwmgr.h"
33 #include "hardwaremanager.h"
34 #include "rv_ppsmc.h"
35 #include "smu10_hwmgr.h"
36 #include "power_state.h"
37 #include "soc15_common.h"
38 #include "smu10.h"
39 #include "asic_reg/pwr/pwr_10_0_offset.h"
40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
41 
42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
43 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
44 #define SCLK_MIN_DIV_INTV_SHIFT         12
45 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
46 #define SMC_RAM_END                     0x40000
47 
48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
49 
50 
51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
52 		struct pp_display_clock_request *clock_req)
53 {
54 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
55 	enum amd_pp_clock_type clk_type = clock_req->clock_type;
56 	uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
57 	PPSMC_Msg        msg;
58 
59 	switch (clk_type) {
60 	case amd_pp_dcf_clock:
61 		if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
62 			return 0;
63 		msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;
64 		smu10_data->dcf_actual_hard_min_freq = clk_freq;
65 		break;
66 	case amd_pp_soc_clock:
67 		 msg = PPSMC_MSG_SetHardMinSocclkByFreq;
68 		break;
69 	case amd_pp_f_clock:
70 		if (clk_freq == smu10_data->f_actual_hard_min_freq)
71 			return 0;
72 		smu10_data->f_actual_hard_min_freq = clk_freq;
73 		msg = PPSMC_MSG_SetHardMinFclkByFreq;
74 		break;
75 	default:
76 		pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
77 		return -EINVAL;
78 	}
79 	smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
80 
81 	return 0;
82 }
83 
84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
85 {
86 	if (SMU10_Magic != hw_ps->magic)
87 		return NULL;
88 
89 	return (struct smu10_power_state *)hw_ps;
90 }
91 
92 static const struct smu10_power_state *cast_const_smu10_ps(
93 				const struct pp_hw_power_state *hw_ps)
94 {
95 	if (SMU10_Magic != hw_ps->magic)
96 		return NULL;
97 
98 	return (struct smu10_power_state *)hw_ps;
99 }
100 
101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
102 {
103 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
104 
105 	smu10_data->dce_slow_sclk_threshold = 30000;
106 	smu10_data->thermal_auto_throttling_treshold = 0;
107 	smu10_data->is_nb_dpm_enabled = 1;
108 	smu10_data->dpm_flags = 1;
109 	smu10_data->need_min_deep_sleep_dcefclk = true;
110 	smu10_data->num_active_display = 0;
111 	smu10_data->deep_sleep_dcefclk = 0;
112 
113 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
114 					PHM_PlatformCaps_SclkDeepSleep);
115 
116 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
117 				PHM_PlatformCaps_SclkThrottleLowNotification);
118 
119 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
120 				PHM_PlatformCaps_PowerPlaySupport);
121 	return 0;
122 }
123 
124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
125 			struct phm_clock_and_voltage_limits *table)
126 {
127 	return 0;
128 }
129 
130 static int smu10_init_dynamic_state_adjustment_rule_settings(
131 							struct pp_hwmgr *hwmgr)
132 {
133 	int count = 8;
134 	struct phm_clock_voltage_dependency_table *table_clk_vlt;
135 
136 	table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, count),
137 				GFP_KERNEL);
138 
139 	if (NULL == table_clk_vlt) {
140 		pr_err("Can not allocate memory!\n");
141 		return -ENOMEM;
142 	}
143 
144 	table_clk_vlt->count = count;
145 	table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
146 	table_clk_vlt->entries[0].v = 0;
147 	table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
148 	table_clk_vlt->entries[1].v = 1;
149 	table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
150 	table_clk_vlt->entries[2].v = 2;
151 	table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
152 	table_clk_vlt->entries[3].v = 3;
153 	table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
154 	table_clk_vlt->entries[4].v = 4;
155 	table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
156 	table_clk_vlt->entries[5].v = 5;
157 	table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
158 	table_clk_vlt->entries[6].v = 6;
159 	table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
160 	table_clk_vlt->entries[7].v = 7;
161 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
162 
163 	return 0;
164 }
165 
166 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
167 {
168 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
169 
170 	smu10_data->sys_info.htc_hyst_lmt = 5;
171 	smu10_data->sys_info.htc_tmp_lmt = 203;
172 
173 	if (smu10_data->thermal_auto_throttling_treshold == 0)
174 		 smu10_data->thermal_auto_throttling_treshold = 203;
175 
176 	smu10_construct_max_power_limits_table (hwmgr,
177 				    &hwmgr->dyn_state.max_clock_voltage_on_ac);
178 
179 	smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
180 
181 	return 0;
182 }
183 
184 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
185 {
186 	return 0;
187 }
188 
189 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
190 {
191 	struct PP_Clocks clocks = {0};
192 	struct pp_display_clock_request clock_req;
193 
194 	clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
195 	clock_req.clock_type = amd_pp_dcf_clock;
196 	clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
197 
198 	PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
199 				"Attempt to set DCF Clock Failed!", return -EINVAL);
200 
201 	return 0;
202 }
203 
204 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
205 {
206 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
207 
208 	if (clock && smu10_data->deep_sleep_dcefclk != clock) {
209 		smu10_data->deep_sleep_dcefclk = clock;
210 		smum_send_msg_to_smc_with_parameter(hwmgr,
211 					PPSMC_MSG_SetMinDeepSleepDcefclk,
212 					smu10_data->deep_sleep_dcefclk,
213 					NULL);
214 	}
215 	return 0;
216 }
217 
218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
219 {
220 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
221 
222 	if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
223 		smu10_data->dcf_actual_hard_min_freq = clock;
224 		smum_send_msg_to_smc_with_parameter(hwmgr,
225 					PPSMC_MSG_SetHardMinDcefclkByFreq,
226 					smu10_data->dcf_actual_hard_min_freq,
227 					NULL);
228 	}
229 	return 0;
230 }
231 
232 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
233 {
234 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
235 
236 	if (clock && smu10_data->f_actual_hard_min_freq != clock) {
237 		smu10_data->f_actual_hard_min_freq = clock;
238 		smum_send_msg_to_smc_with_parameter(hwmgr,
239 					PPSMC_MSG_SetHardMinFclkByFreq,
240 					smu10_data->f_actual_hard_min_freq,
241 					NULL);
242 	}
243 	return 0;
244 }
245 
246 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
247 {
248 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
249 
250 	if (clock && smu10_data->gfx_actual_soft_min_freq != clock) {
251 		smu10_data->gfx_actual_soft_min_freq = clock;
252 		smum_send_msg_to_smc_with_parameter(hwmgr,
253 					PPSMC_MSG_SetHardMinGfxClk,
254 					clock,
255 					NULL);
256 	}
257 	return 0;
258 }
259 
260 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
261 {
262 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
263 
264 	if (clock && smu10_data->gfx_max_freq_limit != (clock * 100))  {
265 		smu10_data->gfx_max_freq_limit = clock * 100;
266 		smum_send_msg_to_smc_with_parameter(hwmgr,
267 					PPSMC_MSG_SetSoftMaxGfxClk,
268 					clock,
269 					NULL);
270 	}
271 	return 0;
272 }
273 
274 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
275 {
276 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
277 
278 	if (smu10_data->num_active_display != count) {
279 		smu10_data->num_active_display = count;
280 		smum_send_msg_to_smc_with_parameter(hwmgr,
281 				PPSMC_MSG_SetDisplayCount,
282 				smu10_data->num_active_display,
283 				NULL);
284 	}
285 
286 	return 0;
287 }
288 
289 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
290 {
291 	return smu10_set_clock_limit(hwmgr, input);
292 }
293 
294 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
295 {
296 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
297 	struct amdgpu_device *adev = hwmgr->adev;
298 
299 	smu10_data->vcn_power_gated = true;
300 	smu10_data->isp_tileA_power_gated = true;
301 	smu10_data->isp_tileB_power_gated = true;
302 
303 	if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
304 		return smum_send_msg_to_smc_with_parameter(hwmgr,
305 							   PPSMC_MSG_SetGfxCGPG,
306 							   true,
307 							   NULL);
308 	else
309 		return 0;
310 }
311 
312 
313 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
314 {
315 	return smu10_init_power_gate_state(hwmgr);
316 }
317 
318 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
319 {
320 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
321 
322 	smu10_data->separation_time = 0;
323 	smu10_data->cc6_disable = false;
324 	smu10_data->pstate_disable = false;
325 	smu10_data->cc6_setting_changed = false;
326 
327 	return 0;
328 }
329 
330 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
331 {
332 	return smu10_reset_cc6_data(hwmgr);
333 }
334 
335 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
336 {
337 	uint32_t reg;
338 	struct amdgpu_device *adev = hwmgr->adev;
339 
340 	reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
341 	if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
342 	    (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
343 		return true;
344 
345 	return false;
346 }
347 
348 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
349 {
350 	struct amdgpu_device *adev = hwmgr->adev;
351 
352 	if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
353 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
354 
355 		/* confirm gfx is back to "on" state */
356 		while (!smu10_is_gfx_on(hwmgr))
357 			msleep(1);
358 	}
359 
360 	return 0;
361 }
362 
363 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
364 {
365 	return 0;
366 }
367 
368 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
369 {
370 	struct amdgpu_device *adev = hwmgr->adev;
371 
372 	if (adev->pm.pp_feature & PP_GFXOFF_MASK)
373 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
374 
375 	return 0;
376 }
377 
378 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
379 {
380 	return 0;
381 }
382 
383 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
384 {
385 	if (enable)
386 		return smu10_enable_gfx_off(hwmgr);
387 	else
388 		return smu10_disable_gfx_off(hwmgr);
389 }
390 
391 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
392 				struct pp_power_state  *prequest_ps,
393 			const struct pp_power_state *pcurrent_ps)
394 {
395 	return 0;
396 }
397 
398 /* temporary hardcoded clock voltage breakdown tables */
399 static const DpmClock_t VddDcfClk[]= {
400 	{ 300, 2600},
401 	{ 600, 3200},
402 	{ 600, 3600},
403 };
404 
405 static const DpmClock_t VddSocClk[]= {
406 	{ 478, 2600},
407 	{ 722, 3200},
408 	{ 722, 3600},
409 };
410 
411 static const DpmClock_t VddFClk[]= {
412 	{ 400, 2600},
413 	{1200, 3200},
414 	{1200, 3600},
415 };
416 
417 static const DpmClock_t VddDispClk[]= {
418 	{ 435, 2600},
419 	{ 661, 3200},
420 	{1086, 3600},
421 };
422 
423 static const DpmClock_t VddDppClk[]= {
424 	{ 435, 2600},
425 	{ 661, 3200},
426 	{ 661, 3600},
427 };
428 
429 static const DpmClock_t VddPhyClk[]= {
430 	{ 540, 2600},
431 	{ 810, 3200},
432 	{ 810, 3600},
433 };
434 
435 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
436 			struct smu10_voltage_dependency_table **pptable,
437 			uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
438 {
439 	uint32_t i;
440 	struct smu10_voltage_dependency_table *ptable;
441 
442 	ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL);
443 	if (NULL == ptable)
444 		return -ENOMEM;
445 
446 	ptable->count = num_entry;
447 
448 	for (i = 0; i < ptable->count; i++) {
449 		ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;
450 		ptable->entries[i].vol         = pclk_dependency_table->Vol;
451 		pclk_dependency_table++;
452 	}
453 
454 	*pptable = ptable;
455 
456 	return 0;
457 }
458 
459 
460 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
461 {
462 	uint32_t result;
463 
464 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
465 	DpmClocks_t  *table = &(smu10_data->clock_table);
466 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
467 
468 	result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
469 
470 	PP_ASSERT_WITH_CODE((0 == result),
471 			"Attempt to copy clock table from smc failed",
472 			return result);
473 
474 	if (0 == result && table->DcefClocks[0].Freq != 0) {
475 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
476 						NUM_DCEFCLK_DPM_LEVELS,
477 						&smu10_data->clock_table.DcefClocks[0]);
478 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
479 						NUM_SOCCLK_DPM_LEVELS,
480 						&smu10_data->clock_table.SocClocks[0]);
481 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
482 						NUM_FCLK_DPM_LEVELS,
483 						&smu10_data->clock_table.FClocks[0]);
484 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
485 						NUM_MEMCLK_DPM_LEVELS,
486 						&smu10_data->clock_table.MemClocks[0]);
487 	} else {
488 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
489 						ARRAY_SIZE(VddDcfClk),
490 						&VddDcfClk[0]);
491 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
492 						ARRAY_SIZE(VddSocClk),
493 						&VddSocClk[0]);
494 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
495 						ARRAY_SIZE(VddFClk),
496 						&VddFClk[0]);
497 	}
498 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
499 					ARRAY_SIZE(VddDispClk),
500 					&VddDispClk[0]);
501 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
502 					ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
503 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
504 					ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
505 
506 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
507 	smu10_data->gfx_min_freq_limit = result / 10 * 1000;
508 
509 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
510 	smu10_data->gfx_max_freq_limit = result / 10 * 1000;
511 
512 	return 0;
513 }
514 
515 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
516 {
517 	int result = 0;
518 	struct smu10_hwmgr *data;
519 
520 	data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
521 	if (data == NULL)
522 		return -ENOMEM;
523 
524 	hwmgr->backend = data;
525 
526 	result = smu10_initialize_dpm_defaults(hwmgr);
527 	if (result != 0) {
528 		pr_err("smu10_initialize_dpm_defaults failed\n");
529 		return result;
530 	}
531 
532 	smu10_populate_clock_table(hwmgr);
533 
534 	result = smu10_get_system_info_data(hwmgr);
535 	if (result != 0) {
536 		pr_err("smu10_get_system_info_data failed\n");
537 		return result;
538 	}
539 
540 	smu10_construct_boot_state(hwmgr);
541 
542 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
543 						SMU10_MAX_HARDWARE_POWERLEVELS;
544 
545 	hwmgr->platform_descriptor.hardwarePerformanceLevels =
546 						SMU10_MAX_HARDWARE_POWERLEVELS;
547 
548 	hwmgr->platform_descriptor.vbiosInterruptId = 0;
549 
550 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
551 
552 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
553 
554 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
555 
556 	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
557 	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
558 
559 	/* enable the pp_od_clk_voltage sysfs file */
560 	hwmgr->od_enabled = 1;
561 	/* disabled fine grain tuning function by default */
562 	data->fine_grain_enabled = 0;
563 	return result;
564 }
565 
566 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
567 {
568 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
569 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
570 
571 	kfree(pinfo->vdd_dep_on_dcefclk);
572 	pinfo->vdd_dep_on_dcefclk = NULL;
573 	kfree(pinfo->vdd_dep_on_socclk);
574 	pinfo->vdd_dep_on_socclk = NULL;
575 	kfree(pinfo->vdd_dep_on_fclk);
576 	pinfo->vdd_dep_on_fclk = NULL;
577 	kfree(pinfo->vdd_dep_on_dispclk);
578 	pinfo->vdd_dep_on_dispclk = NULL;
579 	kfree(pinfo->vdd_dep_on_dppclk);
580 	pinfo->vdd_dep_on_dppclk = NULL;
581 	kfree(pinfo->vdd_dep_on_phyclk);
582 	pinfo->vdd_dep_on_phyclk = NULL;
583 
584 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
585 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
586 
587 	kfree(hwmgr->backend);
588 	hwmgr->backend = NULL;
589 
590 	return 0;
591 }
592 
593 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
594 				enum amd_dpm_forced_level level)
595 {
596 	struct smu10_hwmgr *data = hwmgr->backend;
597 	uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
598 	uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
599 	uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
600 	uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
601 	uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;
602 
603 	if (hwmgr->smu_version < 0x1E3700) {
604 		pr_info("smu firmware version too old, can not set dpm level\n");
605 		return 0;
606 	}
607 
608 	if (min_sclk < data->gfx_min_freq_limit)
609 		min_sclk = data->gfx_min_freq_limit;
610 
611 	min_sclk /= 100; /* transfer 10KHz to MHz */
612 	if (min_mclk < data->clock_table.FClocks[0].Freq)
613 		min_mclk = data->clock_table.FClocks[0].Freq;
614 
615 	switch (level) {
616 	case AMD_DPM_FORCED_LEVEL_HIGH:
617 	case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
618 		data->fine_grain_enabled = 0;
619 
620 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
621 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
622 
623 		data->gfx_actual_soft_min_freq = fine_grain_min_freq;
624 		data->gfx_actual_soft_max_freq = fine_grain_max_freq;
625 
626 		smum_send_msg_to_smc_with_parameter(hwmgr,
627 						PPSMC_MSG_SetHardMinGfxClk,
628 						data->gfx_max_freq_limit/100,
629 						NULL);
630 		smum_send_msg_to_smc_with_parameter(hwmgr,
631 						PPSMC_MSG_SetHardMinFclkByFreq,
632 						SMU10_UMD_PSTATE_PEAK_FCLK,
633 						NULL);
634 		smum_send_msg_to_smc_with_parameter(hwmgr,
635 						PPSMC_MSG_SetHardMinSocclkByFreq,
636 						SMU10_UMD_PSTATE_PEAK_SOCCLK,
637 						NULL);
638 		smum_send_msg_to_smc_with_parameter(hwmgr,
639 						PPSMC_MSG_SetHardMinVcn,
640 						SMU10_UMD_PSTATE_VCE,
641 						NULL);
642 
643 		smum_send_msg_to_smc_with_parameter(hwmgr,
644 						PPSMC_MSG_SetSoftMaxGfxClk,
645 						data->gfx_max_freq_limit/100,
646 						NULL);
647 		smum_send_msg_to_smc_with_parameter(hwmgr,
648 						PPSMC_MSG_SetSoftMaxFclkByFreq,
649 						SMU10_UMD_PSTATE_PEAK_FCLK,
650 						NULL);
651 		smum_send_msg_to_smc_with_parameter(hwmgr,
652 						PPSMC_MSG_SetSoftMaxSocclkByFreq,
653 						SMU10_UMD_PSTATE_PEAK_SOCCLK,
654 						NULL);
655 		smum_send_msg_to_smc_with_parameter(hwmgr,
656 						PPSMC_MSG_SetSoftMaxVcn,
657 						SMU10_UMD_PSTATE_VCE,
658 						NULL);
659 		break;
660 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
661 		data->fine_grain_enabled = 0;
662 
663 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
664 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
665 
666 		data->gfx_actual_soft_min_freq = fine_grain_min_freq;
667 		data->gfx_actual_soft_max_freq = fine_grain_max_freq;
668 
669 		smum_send_msg_to_smc_with_parameter(hwmgr,
670 						PPSMC_MSG_SetHardMinGfxClk,
671 						min_sclk,
672 						NULL);
673 		smum_send_msg_to_smc_with_parameter(hwmgr,
674 						PPSMC_MSG_SetSoftMaxGfxClk,
675 						min_sclk,
676 						NULL);
677 		break;
678 	case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
679 		data->fine_grain_enabled = 0;
680 
681 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
682 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
683 
684 		data->gfx_actual_soft_min_freq = fine_grain_min_freq;
685 		data->gfx_actual_soft_max_freq = fine_grain_max_freq;
686 
687 		smum_send_msg_to_smc_with_parameter(hwmgr,
688 						PPSMC_MSG_SetHardMinFclkByFreq,
689 						min_mclk,
690 						NULL);
691 		smum_send_msg_to_smc_with_parameter(hwmgr,
692 						PPSMC_MSG_SetSoftMaxFclkByFreq,
693 						min_mclk,
694 						NULL);
695 		break;
696 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
697 		data->fine_grain_enabled = 0;
698 
699 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
700 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
701 
702 		data->gfx_actual_soft_min_freq = fine_grain_min_freq;
703 		data->gfx_actual_soft_max_freq = fine_grain_max_freq;
704 
705 		smum_send_msg_to_smc_with_parameter(hwmgr,
706 						PPSMC_MSG_SetHardMinGfxClk,
707 						SMU10_UMD_PSTATE_GFXCLK,
708 						NULL);
709 		smum_send_msg_to_smc_with_parameter(hwmgr,
710 						PPSMC_MSG_SetHardMinFclkByFreq,
711 						SMU10_UMD_PSTATE_FCLK,
712 						NULL);
713 		smum_send_msg_to_smc_with_parameter(hwmgr,
714 						PPSMC_MSG_SetHardMinSocclkByFreq,
715 						SMU10_UMD_PSTATE_SOCCLK,
716 						NULL);
717 		smum_send_msg_to_smc_with_parameter(hwmgr,
718 						PPSMC_MSG_SetHardMinVcn,
719 						SMU10_UMD_PSTATE_PROFILE_VCE,
720 						NULL);
721 
722 		smum_send_msg_to_smc_with_parameter(hwmgr,
723 						PPSMC_MSG_SetSoftMaxGfxClk,
724 						SMU10_UMD_PSTATE_GFXCLK,
725 						NULL);
726 		smum_send_msg_to_smc_with_parameter(hwmgr,
727 						PPSMC_MSG_SetSoftMaxFclkByFreq,
728 						SMU10_UMD_PSTATE_FCLK,
729 						NULL);
730 		smum_send_msg_to_smc_with_parameter(hwmgr,
731 						PPSMC_MSG_SetSoftMaxSocclkByFreq,
732 						SMU10_UMD_PSTATE_SOCCLK,
733 						NULL);
734 		smum_send_msg_to_smc_with_parameter(hwmgr,
735 						PPSMC_MSG_SetSoftMaxVcn,
736 						SMU10_UMD_PSTATE_PROFILE_VCE,
737 						NULL);
738 		break;
739 	case AMD_DPM_FORCED_LEVEL_AUTO:
740 		data->fine_grain_enabled = 0;
741 
742 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
743 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
744 
745 		data->gfx_actual_soft_min_freq = fine_grain_min_freq;
746 		data->gfx_actual_soft_max_freq = fine_grain_max_freq;
747 
748 		smum_send_msg_to_smc_with_parameter(hwmgr,
749 						PPSMC_MSG_SetHardMinGfxClk,
750 						min_sclk,
751 						NULL);
752 		smum_send_msg_to_smc_with_parameter(hwmgr,
753 						PPSMC_MSG_SetHardMinFclkByFreq,
754 						hwmgr->display_config->num_display > 3 ?
755 						data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
756 						min_mclk,
757 						NULL);
758 
759 		smum_send_msg_to_smc_with_parameter(hwmgr,
760 						PPSMC_MSG_SetHardMinSocclkByFreq,
761 						data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
762 						NULL);
763 		smum_send_msg_to_smc_with_parameter(hwmgr,
764 						PPSMC_MSG_SetHardMinVcn,
765 						SMU10_UMD_PSTATE_MIN_VCE,
766 						NULL);
767 
768 		smum_send_msg_to_smc_with_parameter(hwmgr,
769 						PPSMC_MSG_SetSoftMaxGfxClk,
770 						data->gfx_max_freq_limit/100,
771 						NULL);
772 		smum_send_msg_to_smc_with_parameter(hwmgr,
773 						PPSMC_MSG_SetSoftMaxFclkByFreq,
774 						data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
775 						NULL);
776 		smum_send_msg_to_smc_with_parameter(hwmgr,
777 						PPSMC_MSG_SetSoftMaxSocclkByFreq,
778 						data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
779 						NULL);
780 		smum_send_msg_to_smc_with_parameter(hwmgr,
781 						PPSMC_MSG_SetSoftMaxVcn,
782 						SMU10_UMD_PSTATE_VCE,
783 						NULL);
784 		break;
785 	case AMD_DPM_FORCED_LEVEL_LOW:
786 		data->fine_grain_enabled = 0;
787 
788 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
789 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
790 
791 		data->gfx_actual_soft_min_freq = fine_grain_min_freq;
792 		data->gfx_actual_soft_max_freq = fine_grain_max_freq;
793 
794 		smum_send_msg_to_smc_with_parameter(hwmgr,
795 						PPSMC_MSG_SetHardMinGfxClk,
796 						data->gfx_min_freq_limit/100,
797 						NULL);
798 		smum_send_msg_to_smc_with_parameter(hwmgr,
799 						PPSMC_MSG_SetSoftMaxGfxClk,
800 						data->gfx_min_freq_limit/100,
801 						NULL);
802 		smum_send_msg_to_smc_with_parameter(hwmgr,
803 						PPSMC_MSG_SetHardMinFclkByFreq,
804 						min_mclk,
805 						NULL);
806 		smum_send_msg_to_smc_with_parameter(hwmgr,
807 						PPSMC_MSG_SetSoftMaxFclkByFreq,
808 						min_mclk,
809 						NULL);
810 		break;
811 	case AMD_DPM_FORCED_LEVEL_MANUAL:
812 		data->fine_grain_enabled = 1;
813 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
814 	default:
815 		break;
816 	}
817 	return 0;
818 }
819 
820 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
821 {
822 	struct smu10_hwmgr *data;
823 
824 	if (hwmgr == NULL)
825 		return -EINVAL;
826 
827 	data = (struct smu10_hwmgr *)(hwmgr->backend);
828 
829 	if (low)
830 		return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
831 	else
832 		return data->clock_vol_info.vdd_dep_on_fclk->entries[
833 			data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
834 }
835 
836 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
837 {
838 	struct smu10_hwmgr *data;
839 
840 	if (hwmgr == NULL)
841 		return -EINVAL;
842 
843 	data = (struct smu10_hwmgr *)(hwmgr->backend);
844 
845 	if (low)
846 		return data->gfx_min_freq_limit;
847 	else
848 		return data->gfx_max_freq_limit;
849 }
850 
851 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
852 					struct pp_hw_power_state *hw_ps)
853 {
854 	return 0;
855 }
856 
857 static int smu10_dpm_get_pp_table_entry_callback(
858 						     struct pp_hwmgr *hwmgr,
859 					   struct pp_hw_power_state *hw_ps,
860 							  unsigned int index,
861 						     const void *clock_info)
862 {
863 	struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
864 
865 	smu10_ps->levels[index].engine_clock = 0;
866 
867 	smu10_ps->levels[index].vddc_index = 0;
868 	smu10_ps->level = index + 1;
869 
870 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
871 		smu10_ps->levels[index].ds_divider_index = 5;
872 		smu10_ps->levels[index].ss_divider_index = 5;
873 	}
874 
875 	return 0;
876 }
877 
878 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
879 {
880 	int result;
881 	unsigned long ret = 0;
882 
883 	result = pp_tables_get_num_of_entries(hwmgr, &ret);
884 
885 	return result ? 0 : ret;
886 }
887 
888 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
889 		    unsigned long entry, struct pp_power_state *ps)
890 {
891 	int result;
892 	struct smu10_power_state *smu10_ps;
893 
894 	ps->hardware.magic = SMU10_Magic;
895 
896 	smu10_ps = cast_smu10_ps(&(ps->hardware));
897 
898 	result = pp_tables_get_entry(hwmgr, entry, ps,
899 			smu10_dpm_get_pp_table_entry_callback);
900 
901 	smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
902 	smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
903 
904 	return result;
905 }
906 
907 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
908 {
909 	return sizeof(struct smu10_power_state);
910 }
911 
912 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
913 {
914 	return 0;
915 }
916 
917 
918 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
919 			bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
920 {
921 	struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
922 
923 	if (separation_time != data->separation_time ||
924 			cc6_disable != data->cc6_disable ||
925 			pstate_disable != data->pstate_disable) {
926 		data->separation_time = separation_time;
927 		data->cc6_disable = cc6_disable;
928 		data->pstate_disable = pstate_disable;
929 		data->cc6_setting_changed = true;
930 	}
931 	return 0;
932 }
933 
934 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
935 		struct amd_pp_simple_clock_info *info)
936 {
937 	return -EINVAL;
938 }
939 
940 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
941 		enum pp_clock_type type, uint32_t mask)
942 {
943 	struct smu10_hwmgr *data = hwmgr->backend;
944 	struct smu10_voltage_dependency_table *mclk_table =
945 					data->clock_vol_info.vdd_dep_on_fclk;
946 	uint32_t low, high;
947 
948 	low = mask ? (ffs(mask) - 1) : 0;
949 	high = mask ? (fls(mask) - 1) : 0;
950 
951 	switch (type) {
952 	case PP_SCLK:
953 		if (low > 2 || high > 2) {
954 			pr_info("Currently sclk only support 3 levels on RV\n");
955 			return -EINVAL;
956 		}
957 
958 		smum_send_msg_to_smc_with_parameter(hwmgr,
959 						PPSMC_MSG_SetHardMinGfxClk,
960 						low == 2 ? data->gfx_max_freq_limit/100 :
961 						low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
962 						data->gfx_min_freq_limit/100,
963 						NULL);
964 
965 		smum_send_msg_to_smc_with_parameter(hwmgr,
966 						PPSMC_MSG_SetSoftMaxGfxClk,
967 						high == 0 ? data->gfx_min_freq_limit/100 :
968 						high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
969 						data->gfx_max_freq_limit/100,
970 						NULL);
971 		break;
972 
973 	case PP_MCLK:
974 		if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
975 			return -EINVAL;
976 
977 		smum_send_msg_to_smc_with_parameter(hwmgr,
978 						PPSMC_MSG_SetHardMinFclkByFreq,
979 						mclk_table->entries[low].clk/100,
980 						NULL);
981 
982 		smum_send_msg_to_smc_with_parameter(hwmgr,
983 						PPSMC_MSG_SetSoftMaxFclkByFreq,
984 						mclk_table->entries[high].clk/100,
985 						NULL);
986 		break;
987 
988 	case PP_PCIE:
989 	default:
990 		break;
991 	}
992 	return 0;
993 }
994 
995 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
996 		enum pp_clock_type type, char *buf)
997 {
998 	struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
999 	struct smu10_voltage_dependency_table *mclk_table =
1000 			data->clock_vol_info.vdd_dep_on_fclk;
1001 	uint32_t i, now, size = 0;
1002 	uint32_t min_freq, max_freq = 0;
1003 	uint32_t ret = 0;
1004 
1005 	switch (type) {
1006 	case PP_SCLK:
1007 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
1008 
1009 	/* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
1010 		if (now == data->gfx_max_freq_limit/100)
1011 			i = 2;
1012 		else if (now == data->gfx_min_freq_limit/100)
1013 			i = 0;
1014 		else
1015 			i = 1;
1016 
1017 		size += sprintf(buf + size, "0: %uMhz %s\n",
1018 					data->gfx_min_freq_limit/100,
1019 					i == 0 ? "*" : "");
1020 		size += sprintf(buf + size, "1: %uMhz %s\n",
1021 					i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
1022 					i == 1 ? "*" : "");
1023 		size += sprintf(buf + size, "2: %uMhz %s\n",
1024 					data->gfx_max_freq_limit/100,
1025 					i == 2 ? "*" : "");
1026 		break;
1027 	case PP_MCLK:
1028 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
1029 
1030 		for (i = 0; i < mclk_table->count; i++)
1031 			size += sprintf(buf + size, "%d: %uMhz %s\n",
1032 					i,
1033 					mclk_table->entries[i].clk / 100,
1034 					((mclk_table->entries[i].clk / 100)
1035 					 == now) ? "*" : "");
1036 		break;
1037 	case OD_SCLK:
1038 		if (hwmgr->od_enabled) {
1039 			ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1040 			if (ret)
1041 				return ret;
1042 			ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1043 			if (ret)
1044 				return ret;
1045 
1046 			size = sprintf(buf, "%s:\n", "OD_SCLK");
1047 			size += sprintf(buf + size, "0: %10uMhz\n",
1048 			(data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq);
1049 			size += sprintf(buf + size, "1: %10uMhz\n",
1050 			(data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq);
1051 		}
1052 		break;
1053 	case OD_RANGE:
1054 		if (hwmgr->od_enabled) {
1055 			ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1056 			if (ret)
1057 				return ret;
1058 			ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1059 			if (ret)
1060 				return ret;
1061 
1062 			size = sprintf(buf, "%s:\n", "OD_RANGE");
1063 			size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
1064 				min_freq, max_freq);
1065 		}
1066 		break;
1067 	default:
1068 		break;
1069 	}
1070 
1071 	return size;
1072 }
1073 
1074 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1075 				PHM_PerformanceLevelDesignation designation, uint32_t index,
1076 				PHM_PerformanceLevel *level)
1077 {
1078 	struct smu10_hwmgr *data;
1079 
1080 	if (level == NULL || hwmgr == NULL || state == NULL)
1081 		return -EINVAL;
1082 
1083 	data = (struct smu10_hwmgr *)(hwmgr->backend);
1084 
1085 	if (index == 0) {
1086 		level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
1087 		level->coreClock = data->gfx_min_freq_limit;
1088 	} else {
1089 		level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
1090 			data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
1091 		level->coreClock = data->gfx_max_freq_limit;
1092 	}
1093 
1094 	level->nonLocalMemoryFreq = 0;
1095 	level->nonLocalMemoryWidth = 0;
1096 
1097 	return 0;
1098 }
1099 
1100 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1101 	const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1102 {
1103 	const struct smu10_power_state *ps = cast_const_smu10_ps(state);
1104 
1105 	clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
1106 	clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
1107 
1108 	return 0;
1109 }
1110 
1111 #define MEM_FREQ_LOW_LATENCY        25000
1112 #define MEM_FREQ_HIGH_LATENCY       80000
1113 #define MEM_LATENCY_HIGH            245
1114 #define MEM_LATENCY_LOW             35
1115 #define MEM_LATENCY_ERR             0xFFFF
1116 
1117 
1118 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1119 		uint32_t clock)
1120 {
1121 	if (clock >= MEM_FREQ_LOW_LATENCY &&
1122 			clock < MEM_FREQ_HIGH_LATENCY)
1123 		return MEM_LATENCY_HIGH;
1124 	else if (clock >= MEM_FREQ_HIGH_LATENCY)
1125 		return MEM_LATENCY_LOW;
1126 	else
1127 		return MEM_LATENCY_ERR;
1128 }
1129 
1130 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1131 		enum amd_pp_clock_type type,
1132 		struct pp_clock_levels_with_latency *clocks)
1133 {
1134 	uint32_t i;
1135 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1136 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1137 	struct smu10_voltage_dependency_table *pclk_vol_table;
1138 	bool latency_required = false;
1139 
1140 	if (pinfo == NULL)
1141 		return -EINVAL;
1142 
1143 	switch (type) {
1144 	case amd_pp_mem_clock:
1145 		pclk_vol_table = pinfo->vdd_dep_on_mclk;
1146 		latency_required = true;
1147 		break;
1148 	case amd_pp_f_clock:
1149 		pclk_vol_table = pinfo->vdd_dep_on_fclk;
1150 		latency_required = true;
1151 		break;
1152 	case amd_pp_dcf_clock:
1153 		pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1154 		break;
1155 	case amd_pp_disp_clock:
1156 		pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1157 		break;
1158 	case amd_pp_phy_clock:
1159 		pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1160 		break;
1161 	case amd_pp_dpp_clock:
1162 		pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1163 		break;
1164 	default:
1165 		return -EINVAL;
1166 	}
1167 
1168 	if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1169 		return -EINVAL;
1170 
1171 	clocks->num_levels = 0;
1172 	for (i = 0; i < pclk_vol_table->count; i++) {
1173 		if (pclk_vol_table->entries[i].clk) {
1174 			clocks->data[clocks->num_levels].clocks_in_khz =
1175 				pclk_vol_table->entries[i].clk * 10;
1176 			clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1177 				smu10_get_mem_latency(hwmgr,
1178 						      pclk_vol_table->entries[i].clk) :
1179 				0;
1180 			clocks->num_levels++;
1181 		}
1182 	}
1183 
1184 	return 0;
1185 }
1186 
1187 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1188 		enum amd_pp_clock_type type,
1189 		struct pp_clock_levels_with_voltage *clocks)
1190 {
1191 	uint32_t i;
1192 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1193 	struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1194 	struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1195 
1196 	if (pinfo == NULL)
1197 		return -EINVAL;
1198 
1199 	switch (type) {
1200 	case amd_pp_mem_clock:
1201 		pclk_vol_table = pinfo->vdd_dep_on_mclk;
1202 		break;
1203 	case amd_pp_f_clock:
1204 		pclk_vol_table = pinfo->vdd_dep_on_fclk;
1205 		break;
1206 	case amd_pp_dcf_clock:
1207 		pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1208 		break;
1209 	case amd_pp_soc_clock:
1210 		pclk_vol_table = pinfo->vdd_dep_on_socclk;
1211 		break;
1212 	case amd_pp_disp_clock:
1213 		pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1214 		break;
1215 	case amd_pp_phy_clock:
1216 		pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1217 		break;
1218 	default:
1219 		return -EINVAL;
1220 	}
1221 
1222 	if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1223 		return -EINVAL;
1224 
1225 	clocks->num_levels = 0;
1226 	for (i = 0; i < pclk_vol_table->count; i++) {
1227 		if (pclk_vol_table->entries[i].clk) {
1228 			clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
1229 			clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1230 			clocks->num_levels++;
1231 		}
1232 	}
1233 
1234 	return 0;
1235 }
1236 
1237 
1238 
1239 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1240 {
1241 	clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1242 	return 0;
1243 }
1244 
1245 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1246 {
1247 	struct amdgpu_device *adev = hwmgr->adev;
1248 	uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1249 	int cur_temp =
1250 		(reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1251 
1252 	if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1253 		cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1254 	else
1255 		cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1256 
1257 	return cur_temp;
1258 }
1259 
1260 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1261 			  void *value, int *size)
1262 {
1263 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1264 	struct amdgpu_device *adev = hwmgr->adev;
1265 	uint32_t sclk, mclk, activity_percent;
1266 	bool has_gfx_busy;
1267 	int ret = 0;
1268 
1269 	/* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */
1270 	if ((adev->apu_flags & AMD_APU_IS_PICASSO) &&
1271 	    (hwmgr->smu_version >= 0x41e3b))
1272 		has_gfx_busy = true;
1273 	else if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1274 		 (hwmgr->smu_version >= 0x1e5500))
1275 		has_gfx_busy = true;
1276 	else
1277 		has_gfx_busy = false;
1278 
1279 	switch (idx) {
1280 	case AMDGPU_PP_SENSOR_GFX_SCLK:
1281 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1282 			/* in units of 10KHZ */
1283 		*((uint32_t *)value) = sclk * 100;
1284 		*size = 4;
1285 		break;
1286 	case AMDGPU_PP_SENSOR_GFX_MCLK:
1287 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1288 			/* in units of 10KHZ */
1289 		*((uint32_t *)value) = mclk * 100;
1290 		*size = 4;
1291 		break;
1292 	case AMDGPU_PP_SENSOR_GPU_TEMP:
1293 		*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1294 		break;
1295 	case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1296 		*(uint32_t *)value =  smu10_data->vcn_power_gated ? 0 : 1;
1297 		*size = 4;
1298 		break;
1299 	case AMDGPU_PP_SENSOR_GPU_LOAD:
1300 		if (!has_gfx_busy)
1301 			ret = -EOPNOTSUPP;
1302 		else {
1303 			ret = smum_send_msg_to_smc(hwmgr,
1304 						   PPSMC_MSG_GetGfxBusy,
1305 						   &activity_percent);
1306 			if (!ret)
1307 				*((uint32_t *)value) = min(activity_percent, (u32)100);
1308 			else
1309 				ret = -EIO;
1310 		}
1311 		break;
1312 	default:
1313 		ret = -EOPNOTSUPP;
1314 		break;
1315 	}
1316 
1317 	return ret;
1318 }
1319 
1320 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1321 		void *clock_ranges)
1322 {
1323 	struct smu10_hwmgr *data = hwmgr->backend;
1324 	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1325 	Watermarks_t *table = &(data->water_marks_table);
1326 	struct amdgpu_device *adev = hwmgr->adev;
1327 	int i;
1328 
1329 	smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1330 
1331 	if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1332 		for (i = 0; i < NUM_WM_RANGES; i++)
1333 			table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
1334 
1335 		for (i = 0; i < NUM_WM_RANGES; i++)
1336 			table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
1337 	}
1338 
1339 	smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1340 	data->water_marks_exist = true;
1341 	return 0;
1342 }
1343 
1344 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1345 {
1346 
1347 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1348 }
1349 
1350 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1351 {
1352 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1353 }
1354 
1355 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1356 {
1357 	if (gate)
1358 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1359 	else
1360 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1361 }
1362 
1363 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1364 {
1365 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1366 
1367 	if (bgate) {
1368 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1369 						AMD_IP_BLOCK_TYPE_VCN,
1370 						AMD_PG_STATE_GATE);
1371 		smum_send_msg_to_smc_with_parameter(hwmgr,
1372 					PPSMC_MSG_PowerDownVcn, 0, NULL);
1373 		smu10_data->vcn_power_gated = true;
1374 	} else {
1375 		smum_send_msg_to_smc_with_parameter(hwmgr,
1376 						PPSMC_MSG_PowerUpVcn, 0, NULL);
1377 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1378 						AMD_IP_BLOCK_TYPE_VCN,
1379 						AMD_PG_STATE_UNGATE);
1380 		smu10_data->vcn_power_gated = false;
1381 	}
1382 }
1383 
1384 static int conv_power_profile_to_pplib_workload(int power_profile)
1385 {
1386 	int pplib_workload = 0;
1387 
1388 	switch (power_profile) {
1389 	case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1390 		pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1391 		break;
1392 	case PP_SMC_POWER_PROFILE_VIDEO:
1393 		pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1394 		break;
1395 	case PP_SMC_POWER_PROFILE_VR:
1396 		pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1397 		break;
1398 	case PP_SMC_POWER_PROFILE_COMPUTE:
1399 		pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1400 		break;
1401 	case PP_SMC_POWER_PROFILE_CUSTOM:
1402 		pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
1403 		break;
1404 	}
1405 
1406 	return pplib_workload;
1407 }
1408 
1409 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1410 {
1411 	uint32_t i, size = 0;
1412 	static const uint8_t
1413 		profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1414 						{70, 60, 1, 3,},
1415 						{90, 60, 0, 0,},
1416 						{70, 60, 0, 0,},
1417 						{70, 90, 0, 0,},
1418 						{30, 60, 0, 6,},
1419 						};
1420 	static const char *profile_name[6] = {
1421 					"BOOTUP_DEFAULT",
1422 					"3D_FULL_SCREEN",
1423 					"POWER_SAVING",
1424 					"VIDEO",
1425 					"VR",
1426 					"COMPUTE"};
1427 	static const char *title[6] = {"NUM",
1428 			"MODE_NAME",
1429 			"BUSY_SET_POINT",
1430 			"FPS",
1431 			"USE_RLC_BUSY",
1432 			"MIN_ACTIVE_LEVEL"};
1433 
1434 	if (!buf)
1435 		return -EINVAL;
1436 
1437 	size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
1438 			title[1], title[2], title[3], title[4], title[5]);
1439 
1440 	for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1441 		size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
1442 			i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1443 			profile_mode_setting[i][0], profile_mode_setting[i][1],
1444 			profile_mode_setting[i][2], profile_mode_setting[i][3]);
1445 
1446 	return size;
1447 }
1448 
1449 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1450 {
1451 	struct amdgpu_device *adev = hwmgr->adev;
1452 	if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1453 	    (hwmgr->smu_version >= 0x41e2b))
1454 		return true;
1455 	else
1456 		return false;
1457 }
1458 
1459 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1460 {
1461 	int workload_type = 0;
1462 	int result = 0;
1463 
1464 	if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1465 		pr_err("Invalid power profile mode %ld\n", input[size]);
1466 		return -EINVAL;
1467 	}
1468 	if (hwmgr->power_profile_mode == input[size])
1469 		return 0;
1470 
1471 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1472 	workload_type =
1473 		conv_power_profile_to_pplib_workload(input[size]);
1474 	if (workload_type &&
1475 	    smu10_is_raven1_refresh(hwmgr) &&
1476 	    !hwmgr->gfxoff_state_changed_by_workload) {
1477 		smu10_gfx_off_control(hwmgr, false);
1478 		hwmgr->gfxoff_state_changed_by_workload = true;
1479 	}
1480 	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1481 						1 << workload_type,
1482 						NULL);
1483 	if (!result)
1484 		hwmgr->power_profile_mode = input[size];
1485 	if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1486 		smu10_gfx_off_control(hwmgr, true);
1487 		hwmgr->gfxoff_state_changed_by_workload = false;
1488 	}
1489 
1490 	return 0;
1491 }
1492 
1493 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1494 {
1495 	return smum_send_msg_to_smc_with_parameter(hwmgr,
1496 						   PPSMC_MSG_DeviceDriverReset,
1497 						   mode,
1498 						   NULL);
1499 }
1500 
1501 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
1502 					enum PP_OD_DPM_TABLE_COMMAND type,
1503 					long *input, uint32_t size)
1504 {
1505 	uint32_t min_freq, max_freq = 0;
1506 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1507 	int ret = 0;
1508 
1509 	if (!hwmgr->od_enabled) {
1510 		pr_err("Fine grain not support\n");
1511 		return -EINVAL;
1512 	}
1513 
1514 	if (!smu10_data->fine_grain_enabled) {
1515 		pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1516 		return -EINVAL;
1517 	}
1518 
1519 	if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
1520 		if (size != 2) {
1521 			pr_err("Input parameter number not correct\n");
1522 			return -EINVAL;
1523 		}
1524 
1525 		if (input[0] == 0) {
1526 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1527 			if (input[1] < min_freq) {
1528 				pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1529 					input[1], min_freq);
1530 				return -EINVAL;
1531 			}
1532 			smu10_data->gfx_actual_soft_min_freq = input[1];
1533 		} else if (input[0] == 1) {
1534 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1535 			if (input[1] > max_freq) {
1536 				pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1537 					input[1], max_freq);
1538 				return -EINVAL;
1539 			}
1540 			smu10_data->gfx_actual_soft_max_freq = input[1];
1541 		} else {
1542 			return -EINVAL;
1543 		}
1544 	} else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
1545 		if (size != 0) {
1546 			pr_err("Input parameter number not correct\n");
1547 			return -EINVAL;
1548 		}
1549 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1550 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1551 
1552 		smu10_data->gfx_actual_soft_min_freq = min_freq;
1553 		smu10_data->gfx_actual_soft_max_freq = max_freq;
1554 	} else if (type == PP_OD_COMMIT_DPM_TABLE) {
1555 		if (size != 0) {
1556 			pr_err("Input parameter number not correct\n");
1557 			return -EINVAL;
1558 		}
1559 
1560 		if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) {
1561 			pr_err("The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1562 					smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq);
1563 			return -EINVAL;
1564 		}
1565 
1566 		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1567 					PPSMC_MSG_SetHardMinGfxClk,
1568 					smu10_data->gfx_actual_soft_min_freq,
1569 					NULL);
1570 		if (ret)
1571 			return ret;
1572 
1573 		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1574 					PPSMC_MSG_SetSoftMaxGfxClk,
1575 					smu10_data->gfx_actual_soft_max_freq,
1576 					NULL);
1577 		if (ret)
1578 			return ret;
1579 	} else {
1580 		return -EINVAL;
1581 	}
1582 
1583 	return 0;
1584 }
1585 
1586 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
1587 {
1588 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
1589 
1590 	return 0;
1591 }
1592 
1593 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1594 	.backend_init = smu10_hwmgr_backend_init,
1595 	.backend_fini = smu10_hwmgr_backend_fini,
1596 	.apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1597 	.force_dpm_level = smu10_dpm_force_dpm_level,
1598 	.get_power_state_size = smu10_get_power_state_size,
1599 	.powerdown_uvd = NULL,
1600 	.powergate_uvd = smu10_powergate_vcn,
1601 	.powergate_vce = NULL,
1602 	.get_mclk = smu10_dpm_get_mclk,
1603 	.get_sclk = smu10_dpm_get_sclk,
1604 	.patch_boot_state = smu10_dpm_patch_boot_state,
1605 	.get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1606 	.get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1607 	.set_cpu_power_state = smu10_set_cpu_power_state,
1608 	.store_cc6_data = smu10_store_cc6_data,
1609 	.force_clock_level = smu10_force_clock_level,
1610 	.print_clock_levels = smu10_print_clock_levels,
1611 	.get_dal_power_level = smu10_get_dal_power_level,
1612 	.get_performance_level = smu10_get_performance_level,
1613 	.get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1614 	.get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1615 	.get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1616 	.set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1617 	.get_max_high_clocks = smu10_get_max_high_clocks,
1618 	.read_sensor = smu10_read_sensor,
1619 	.set_active_display_count = smu10_set_active_display_count,
1620 	.set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1621 	.dynamic_state_management_enable = smu10_enable_dpm_tasks,
1622 	.power_off_asic = smu10_power_off_asic,
1623 	.asic_setup = smu10_setup_asic_task,
1624 	.power_state_set = smu10_set_power_state_tasks,
1625 	.dynamic_state_management_disable = smu10_disable_dpm_tasks,
1626 	.powergate_mmhub = smu10_powergate_mmhub,
1627 	.smus_notify_pwe = smu10_smus_notify_pwe,
1628 	.display_clock_voltage_request = smu10_display_clock_voltage_request,
1629 	.powergate_gfx = smu10_gfx_off_control,
1630 	.powergate_sdma = smu10_powergate_sdma,
1631 	.set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1632 	.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1633 	.set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq,
1634 	.set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq,
1635 	.get_power_profile_mode = smu10_get_power_profile_mode,
1636 	.set_power_profile_mode = smu10_set_power_profile_mode,
1637 	.asic_reset = smu10_asic_reset,
1638 	.set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
1639 	.gfx_state_change = smu10_gfx_state_change,
1640 };
1641 
1642 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1643 {
1644 	hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1645 	hwmgr->pptable_func = &pptable_funcs;
1646 	return 0;
1647 }
1648