1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include "atom-types.h" 28 #include "atombios.h" 29 #include "processpptables.h" 30 #include "cgs_common.h" 31 #include "smumgr.h" 32 #include "hwmgr.h" 33 #include "hardwaremanager.h" 34 #include "rv_ppsmc.h" 35 #include "smu10_hwmgr.h" 36 #include "power_state.h" 37 #include "soc15_common.h" 38 #include "smu10.h" 39 #include "asic_reg/pwr/pwr_10_0_offset.h" 40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 41 42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5 43 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */ 44 #define SCLK_MIN_DIV_INTV_SHIFT 12 45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */ 46 #define SMC_RAM_END 0x40000 47 48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic; 49 50 51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 52 struct pp_display_clock_request *clock_req) 53 { 54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 55 enum amd_pp_clock_type clk_type = clock_req->clock_type; 56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 57 PPSMC_Msg msg; 58 59 switch (clk_type) { 60 case amd_pp_dcf_clock: 61 if (clk_freq == smu10_data->dcf_actual_hard_min_freq) 62 return 0; 63 msg = PPSMC_MSG_SetHardMinDcefclkByFreq; 64 smu10_data->dcf_actual_hard_min_freq = clk_freq; 65 break; 66 case amd_pp_soc_clock: 67 msg = PPSMC_MSG_SetHardMinSocclkByFreq; 68 break; 69 case amd_pp_f_clock: 70 if (clk_freq == smu10_data->f_actual_hard_min_freq) 71 return 0; 72 smu10_data->f_actual_hard_min_freq = clk_freq; 73 msg = PPSMC_MSG_SetHardMinFclkByFreq; 74 break; 75 default: 76 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 77 return -EINVAL; 78 } 79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL); 80 81 return 0; 82 } 83 84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps) 85 { 86 if (SMU10_Magic != hw_ps->magic) 87 return NULL; 88 89 return (struct smu10_power_state *)hw_ps; 90 } 91 92 static const struct smu10_power_state *cast_const_smu10_ps( 93 const struct pp_hw_power_state *hw_ps) 94 { 95 if (SMU10_Magic != hw_ps->magic) 96 return NULL; 97 98 return (struct smu10_power_state *)hw_ps; 99 } 100 101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) 102 { 103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 104 105 smu10_data->dce_slow_sclk_threshold = 30000; 106 smu10_data->thermal_auto_throttling_treshold = 0; 107 smu10_data->is_nb_dpm_enabled = 1; 108 smu10_data->dpm_flags = 1; 109 smu10_data->need_min_deep_sleep_dcefclk = true; 110 smu10_data->num_active_display = 0; 111 smu10_data->deep_sleep_dcefclk = 0; 112 113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 114 PHM_PlatformCaps_SclkDeepSleep); 115 116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 117 PHM_PlatformCaps_SclkThrottleLowNotification); 118 119 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 120 PHM_PlatformCaps_PowerPlaySupport); 121 return 0; 122 } 123 124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, 125 struct phm_clock_and_voltage_limits *table) 126 { 127 return 0; 128 } 129 130 static int smu10_init_dynamic_state_adjustment_rule_settings( 131 struct pp_hwmgr *hwmgr) 132 { 133 int count = 8; 134 struct phm_clock_voltage_dependency_table *table_clk_vlt; 135 136 table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, count), 137 GFP_KERNEL); 138 139 if (NULL == table_clk_vlt) { 140 pr_err("Can not allocate memory!\n"); 141 return -ENOMEM; 142 } 143 144 table_clk_vlt->count = count; 145 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; 146 table_clk_vlt->entries[0].v = 0; 147 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; 148 table_clk_vlt->entries[1].v = 1; 149 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; 150 table_clk_vlt->entries[2].v = 2; 151 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3; 152 table_clk_vlt->entries[3].v = 3; 153 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4; 154 table_clk_vlt->entries[4].v = 4; 155 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5; 156 table_clk_vlt->entries[5].v = 5; 157 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6; 158 table_clk_vlt->entries[6].v = 6; 159 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7; 160 table_clk_vlt->entries[7].v = 7; 161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; 162 163 return 0; 164 } 165 166 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr) 167 { 168 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend; 169 170 smu10_data->sys_info.htc_hyst_lmt = 5; 171 smu10_data->sys_info.htc_tmp_lmt = 203; 172 173 if (smu10_data->thermal_auto_throttling_treshold == 0) 174 smu10_data->thermal_auto_throttling_treshold = 203; 175 176 smu10_construct_max_power_limits_table (hwmgr, 177 &hwmgr->dyn_state.max_clock_voltage_on_ac); 178 179 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr); 180 181 return 0; 182 } 183 184 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr) 185 { 186 return 0; 187 } 188 189 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) 190 { 191 struct PP_Clocks clocks = {0}; 192 struct pp_display_clock_request clock_req; 193 194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 195 clock_req.clock_type = amd_pp_dcf_clock; 196 clock_req.clock_freq_in_khz = clocks.dcefClock * 10; 197 198 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), 199 "Attempt to set DCF Clock Failed!", return -EINVAL); 200 201 return 0; 202 } 203 204 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) 205 { 206 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 207 208 if (clock && smu10_data->deep_sleep_dcefclk != clock) { 209 smu10_data->deep_sleep_dcefclk = clock; 210 smum_send_msg_to_smc_with_parameter(hwmgr, 211 PPSMC_MSG_SetMinDeepSleepDcefclk, 212 smu10_data->deep_sleep_dcefclk, 213 NULL); 214 } 215 return 0; 216 } 217 218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 219 { 220 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 221 222 if (clock && smu10_data->dcf_actual_hard_min_freq != clock) { 223 smu10_data->dcf_actual_hard_min_freq = clock; 224 smum_send_msg_to_smc_with_parameter(hwmgr, 225 PPSMC_MSG_SetHardMinDcefclkByFreq, 226 smu10_data->dcf_actual_hard_min_freq, 227 NULL); 228 } 229 return 0; 230 } 231 232 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 233 { 234 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 235 236 if (clock && smu10_data->f_actual_hard_min_freq != clock) { 237 smu10_data->f_actual_hard_min_freq = clock; 238 smum_send_msg_to_smc_with_parameter(hwmgr, 239 PPSMC_MSG_SetHardMinFclkByFreq, 240 smu10_data->f_actual_hard_min_freq, 241 NULL); 242 } 243 return 0; 244 } 245 246 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 247 { 248 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 249 250 if (clock && smu10_data->gfx_actual_soft_min_freq != clock) { 251 smu10_data->gfx_actual_soft_min_freq = clock; 252 smum_send_msg_to_smc_with_parameter(hwmgr, 253 PPSMC_MSG_SetHardMinGfxClk, 254 smu10_data->gfx_actual_soft_min_freq, 255 NULL); 256 } 257 return 0; 258 } 259 260 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 261 { 262 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 263 264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { 265 smu10_data->gfx_max_freq_limit = clock * 100; 266 smum_send_msg_to_smc_with_parameter(hwmgr, 267 PPSMC_MSG_SetSoftMaxGfxClk, 268 clock, 269 NULL); 270 } 271 return 0; 272 } 273 274 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) 275 { 276 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 277 278 if (smu10_data->num_active_display != count) { 279 smu10_data->num_active_display = count; 280 smum_send_msg_to_smc_with_parameter(hwmgr, 281 PPSMC_MSG_SetDisplayCount, 282 smu10_data->num_active_display, 283 NULL); 284 } 285 286 return 0; 287 } 288 289 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 290 { 291 return smu10_set_clock_limit(hwmgr, input); 292 } 293 294 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr) 295 { 296 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 297 struct amdgpu_device *adev = hwmgr->adev; 298 299 smu10_data->vcn_power_gated = true; 300 smu10_data->isp_tileA_power_gated = true; 301 smu10_data->isp_tileB_power_gated = true; 302 303 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) 304 return smum_send_msg_to_smc_with_parameter(hwmgr, 305 PPSMC_MSG_SetGfxCGPG, 306 true, 307 NULL); 308 else 309 return 0; 310 } 311 312 313 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr) 314 { 315 return smu10_init_power_gate_state(hwmgr); 316 } 317 318 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr) 319 { 320 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 321 322 smu10_data->separation_time = 0; 323 smu10_data->cc6_disable = false; 324 smu10_data->pstate_disable = false; 325 smu10_data->cc6_setting_changed = false; 326 327 return 0; 328 } 329 330 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr) 331 { 332 return smu10_reset_cc6_data(hwmgr); 333 } 334 335 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr) 336 { 337 uint32_t reg; 338 struct amdgpu_device *adev = hwmgr->adev; 339 340 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); 341 if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) == 342 (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT)) 343 return true; 344 345 return false; 346 } 347 348 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) 349 { 350 struct amdgpu_device *adev = hwmgr->adev; 351 352 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 353 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL); 354 355 /* confirm gfx is back to "on" state */ 356 while (!smu10_is_gfx_on(hwmgr)) 357 msleep(1); 358 } 359 360 return 0; 361 } 362 363 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 364 { 365 return 0; 366 } 367 368 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) 369 { 370 struct amdgpu_device *adev = hwmgr->adev; 371 372 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 373 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL); 374 375 return 0; 376 } 377 378 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 379 { 380 return 0; 381 } 382 383 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) 384 { 385 if (enable) 386 return smu10_enable_gfx_off(hwmgr); 387 else 388 return smu10_disable_gfx_off(hwmgr); 389 } 390 391 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 392 struct pp_power_state *prequest_ps, 393 const struct pp_power_state *pcurrent_ps) 394 { 395 return 0; 396 } 397 398 /* temporary hardcoded clock voltage breakdown tables */ 399 static const DpmClock_t VddDcfClk[]= { 400 { 300, 2600}, 401 { 600, 3200}, 402 { 600, 3600}, 403 }; 404 405 static const DpmClock_t VddSocClk[]= { 406 { 478, 2600}, 407 { 722, 3200}, 408 { 722, 3600}, 409 }; 410 411 static const DpmClock_t VddFClk[]= { 412 { 400, 2600}, 413 {1200, 3200}, 414 {1200, 3600}, 415 }; 416 417 static const DpmClock_t VddDispClk[]= { 418 { 435, 2600}, 419 { 661, 3200}, 420 {1086, 3600}, 421 }; 422 423 static const DpmClock_t VddDppClk[]= { 424 { 435, 2600}, 425 { 661, 3200}, 426 { 661, 3600}, 427 }; 428 429 static const DpmClock_t VddPhyClk[]= { 430 { 540, 2600}, 431 { 810, 3200}, 432 { 810, 3600}, 433 }; 434 435 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, 436 struct smu10_voltage_dependency_table **pptable, 437 uint32_t num_entry, const DpmClock_t *pclk_dependency_table) 438 { 439 uint32_t i; 440 struct smu10_voltage_dependency_table *ptable; 441 442 ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL); 443 if (NULL == ptable) 444 return -ENOMEM; 445 446 ptable->count = num_entry; 447 448 for (i = 0; i < ptable->count; i++) { 449 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; 450 ptable->entries[i].vol = pclk_dependency_table->Vol; 451 pclk_dependency_table++; 452 } 453 454 *pptable = ptable; 455 456 return 0; 457 } 458 459 460 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr) 461 { 462 uint32_t result; 463 464 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 465 DpmClocks_t *table = &(smu10_data->clock_table); 466 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 467 468 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true); 469 470 PP_ASSERT_WITH_CODE((0 == result), 471 "Attempt to copy clock table from smc failed", 472 return result); 473 474 if (0 == result && table->DcefClocks[0].Freq != 0) { 475 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, 476 NUM_DCEFCLK_DPM_LEVELS, 477 &smu10_data->clock_table.DcefClocks[0]); 478 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, 479 NUM_SOCCLK_DPM_LEVELS, 480 &smu10_data->clock_table.SocClocks[0]); 481 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, 482 NUM_FCLK_DPM_LEVELS, 483 &smu10_data->clock_table.FClocks[0]); 484 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk, 485 NUM_MEMCLK_DPM_LEVELS, 486 &smu10_data->clock_table.MemClocks[0]); 487 } else { 488 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, 489 ARRAY_SIZE(VddDcfClk), 490 &VddDcfClk[0]); 491 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, 492 ARRAY_SIZE(VddSocClk), 493 &VddSocClk[0]); 494 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, 495 ARRAY_SIZE(VddFClk), 496 &VddFClk[0]); 497 } 498 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk, 499 ARRAY_SIZE(VddDispClk), 500 &VddDispClk[0]); 501 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk, 502 ARRAY_SIZE(VddDppClk), &VddDppClk[0]); 503 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk, 504 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]); 505 506 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result); 507 smu10_data->gfx_min_freq_limit = result / 10 * 1000; 508 509 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result); 510 smu10_data->gfx_max_freq_limit = result / 10 * 1000; 511 512 return 0; 513 } 514 515 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 516 { 517 int result = 0; 518 struct smu10_hwmgr *data; 519 520 data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL); 521 if (data == NULL) 522 return -ENOMEM; 523 524 hwmgr->backend = data; 525 526 result = smu10_initialize_dpm_defaults(hwmgr); 527 if (result != 0) { 528 pr_err("smu10_initialize_dpm_defaults failed\n"); 529 return result; 530 } 531 532 smu10_populate_clock_table(hwmgr); 533 534 result = smu10_get_system_info_data(hwmgr); 535 if (result != 0) { 536 pr_err("smu10_get_system_info_data failed\n"); 537 return result; 538 } 539 540 smu10_construct_boot_state(hwmgr); 541 542 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 543 SMU10_MAX_HARDWARE_POWERLEVELS; 544 545 hwmgr->platform_descriptor.hardwarePerformanceLevels = 546 SMU10_MAX_HARDWARE_POWERLEVELS; 547 548 hwmgr->platform_descriptor.vbiosInterruptId = 0; 549 550 hwmgr->platform_descriptor.clockStep.engineClock = 500; 551 552 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 553 554 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 555 556 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100; 557 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100; 558 559 /* enable the pp_od_clk_voltage sysfs file */ 560 hwmgr->od_enabled = 1; 561 562 return result; 563 } 564 565 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 566 { 567 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 568 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 569 570 kfree(pinfo->vdd_dep_on_dcefclk); 571 pinfo->vdd_dep_on_dcefclk = NULL; 572 kfree(pinfo->vdd_dep_on_socclk); 573 pinfo->vdd_dep_on_socclk = NULL; 574 kfree(pinfo->vdd_dep_on_fclk); 575 pinfo->vdd_dep_on_fclk = NULL; 576 kfree(pinfo->vdd_dep_on_dispclk); 577 pinfo->vdd_dep_on_dispclk = NULL; 578 kfree(pinfo->vdd_dep_on_dppclk); 579 pinfo->vdd_dep_on_dppclk = NULL; 580 kfree(pinfo->vdd_dep_on_phyclk); 581 pinfo->vdd_dep_on_phyclk = NULL; 582 583 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 584 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 585 586 kfree(hwmgr->backend); 587 hwmgr->backend = NULL; 588 589 return 0; 590 } 591 592 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 593 enum amd_dpm_forced_level level) 594 { 595 struct smu10_hwmgr *data = hwmgr->backend; 596 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; 597 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; 598 uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1; 599 uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1; 600 601 if (hwmgr->smu_version < 0x1E3700) { 602 pr_info("smu firmware version too old, can not set dpm level\n"); 603 return 0; 604 } 605 606 if (min_sclk < data->gfx_min_freq_limit) 607 min_sclk = data->gfx_min_freq_limit; 608 609 min_sclk /= 100; /* transfer 10KHz to MHz */ 610 if (min_mclk < data->clock_table.FClocks[0].Freq) 611 min_mclk = data->clock_table.FClocks[0].Freq; 612 613 switch (level) { 614 case AMD_DPM_FORCED_LEVEL_HIGH: 615 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 616 smum_send_msg_to_smc_with_parameter(hwmgr, 617 PPSMC_MSG_SetHardMinGfxClk, 618 data->gfx_max_freq_limit/100, 619 NULL); 620 smum_send_msg_to_smc_with_parameter(hwmgr, 621 PPSMC_MSG_SetHardMinFclkByFreq, 622 SMU10_UMD_PSTATE_PEAK_FCLK, 623 NULL); 624 smum_send_msg_to_smc_with_parameter(hwmgr, 625 PPSMC_MSG_SetHardMinSocclkByFreq, 626 SMU10_UMD_PSTATE_PEAK_SOCCLK, 627 NULL); 628 smum_send_msg_to_smc_with_parameter(hwmgr, 629 PPSMC_MSG_SetHardMinVcn, 630 SMU10_UMD_PSTATE_VCE, 631 NULL); 632 633 smum_send_msg_to_smc_with_parameter(hwmgr, 634 PPSMC_MSG_SetSoftMaxGfxClk, 635 data->gfx_max_freq_limit/100, 636 NULL); 637 smum_send_msg_to_smc_with_parameter(hwmgr, 638 PPSMC_MSG_SetSoftMaxFclkByFreq, 639 SMU10_UMD_PSTATE_PEAK_FCLK, 640 NULL); 641 smum_send_msg_to_smc_with_parameter(hwmgr, 642 PPSMC_MSG_SetSoftMaxSocclkByFreq, 643 SMU10_UMD_PSTATE_PEAK_SOCCLK, 644 NULL); 645 smum_send_msg_to_smc_with_parameter(hwmgr, 646 PPSMC_MSG_SetSoftMaxVcn, 647 SMU10_UMD_PSTATE_VCE, 648 NULL); 649 break; 650 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 651 smum_send_msg_to_smc_with_parameter(hwmgr, 652 PPSMC_MSG_SetHardMinGfxClk, 653 min_sclk, 654 NULL); 655 smum_send_msg_to_smc_with_parameter(hwmgr, 656 PPSMC_MSG_SetSoftMaxGfxClk, 657 min_sclk, 658 NULL); 659 break; 660 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 661 smum_send_msg_to_smc_with_parameter(hwmgr, 662 PPSMC_MSG_SetHardMinFclkByFreq, 663 min_mclk, 664 NULL); 665 smum_send_msg_to_smc_with_parameter(hwmgr, 666 PPSMC_MSG_SetSoftMaxFclkByFreq, 667 min_mclk, 668 NULL); 669 break; 670 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 671 smum_send_msg_to_smc_with_parameter(hwmgr, 672 PPSMC_MSG_SetHardMinGfxClk, 673 SMU10_UMD_PSTATE_GFXCLK, 674 NULL); 675 smum_send_msg_to_smc_with_parameter(hwmgr, 676 PPSMC_MSG_SetHardMinFclkByFreq, 677 SMU10_UMD_PSTATE_FCLK, 678 NULL); 679 smum_send_msg_to_smc_with_parameter(hwmgr, 680 PPSMC_MSG_SetHardMinSocclkByFreq, 681 SMU10_UMD_PSTATE_SOCCLK, 682 NULL); 683 smum_send_msg_to_smc_with_parameter(hwmgr, 684 PPSMC_MSG_SetHardMinVcn, 685 SMU10_UMD_PSTATE_PROFILE_VCE, 686 NULL); 687 688 smum_send_msg_to_smc_with_parameter(hwmgr, 689 PPSMC_MSG_SetSoftMaxGfxClk, 690 SMU10_UMD_PSTATE_GFXCLK, 691 NULL); 692 smum_send_msg_to_smc_with_parameter(hwmgr, 693 PPSMC_MSG_SetSoftMaxFclkByFreq, 694 SMU10_UMD_PSTATE_FCLK, 695 NULL); 696 smum_send_msg_to_smc_with_parameter(hwmgr, 697 PPSMC_MSG_SetSoftMaxSocclkByFreq, 698 SMU10_UMD_PSTATE_SOCCLK, 699 NULL); 700 smum_send_msg_to_smc_with_parameter(hwmgr, 701 PPSMC_MSG_SetSoftMaxVcn, 702 SMU10_UMD_PSTATE_PROFILE_VCE, 703 NULL); 704 break; 705 case AMD_DPM_FORCED_LEVEL_AUTO: 706 smum_send_msg_to_smc_with_parameter(hwmgr, 707 PPSMC_MSG_SetHardMinGfxClk, 708 min_sclk, 709 NULL); 710 smum_send_msg_to_smc_with_parameter(hwmgr, 711 PPSMC_MSG_SetHardMinFclkByFreq, 712 hwmgr->display_config->num_display > 3 ? 713 data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk : 714 min_mclk, 715 NULL); 716 717 smum_send_msg_to_smc_with_parameter(hwmgr, 718 PPSMC_MSG_SetHardMinSocclkByFreq, 719 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk, 720 NULL); 721 smum_send_msg_to_smc_with_parameter(hwmgr, 722 PPSMC_MSG_SetHardMinVcn, 723 SMU10_UMD_PSTATE_MIN_VCE, 724 NULL); 725 726 smum_send_msg_to_smc_with_parameter(hwmgr, 727 PPSMC_MSG_SetSoftMaxGfxClk, 728 data->gfx_max_freq_limit/100, 729 NULL); 730 smum_send_msg_to_smc_with_parameter(hwmgr, 731 PPSMC_MSG_SetSoftMaxFclkByFreq, 732 data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk, 733 NULL); 734 smum_send_msg_to_smc_with_parameter(hwmgr, 735 PPSMC_MSG_SetSoftMaxSocclkByFreq, 736 data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk, 737 NULL); 738 smum_send_msg_to_smc_with_parameter(hwmgr, 739 PPSMC_MSG_SetSoftMaxVcn, 740 SMU10_UMD_PSTATE_VCE, 741 NULL); 742 break; 743 case AMD_DPM_FORCED_LEVEL_LOW: 744 smum_send_msg_to_smc_with_parameter(hwmgr, 745 PPSMC_MSG_SetHardMinGfxClk, 746 data->gfx_min_freq_limit/100, 747 NULL); 748 smum_send_msg_to_smc_with_parameter(hwmgr, 749 PPSMC_MSG_SetSoftMaxGfxClk, 750 data->gfx_min_freq_limit/100, 751 NULL); 752 smum_send_msg_to_smc_with_parameter(hwmgr, 753 PPSMC_MSG_SetHardMinFclkByFreq, 754 min_mclk, 755 NULL); 756 smum_send_msg_to_smc_with_parameter(hwmgr, 757 PPSMC_MSG_SetSoftMaxFclkByFreq, 758 min_mclk, 759 NULL); 760 break; 761 case AMD_DPM_FORCED_LEVEL_MANUAL: 762 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 763 default: 764 break; 765 } 766 return 0; 767 } 768 769 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 770 { 771 struct smu10_hwmgr *data; 772 773 if (hwmgr == NULL) 774 return -EINVAL; 775 776 data = (struct smu10_hwmgr *)(hwmgr->backend); 777 778 if (low) 779 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; 780 else 781 return data->clock_vol_info.vdd_dep_on_fclk->entries[ 782 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; 783 } 784 785 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 786 { 787 struct smu10_hwmgr *data; 788 789 if (hwmgr == NULL) 790 return -EINVAL; 791 792 data = (struct smu10_hwmgr *)(hwmgr->backend); 793 794 if (low) 795 return data->gfx_min_freq_limit; 796 else 797 return data->gfx_max_freq_limit; 798 } 799 800 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 801 struct pp_hw_power_state *hw_ps) 802 { 803 return 0; 804 } 805 806 static int smu10_dpm_get_pp_table_entry_callback( 807 struct pp_hwmgr *hwmgr, 808 struct pp_hw_power_state *hw_ps, 809 unsigned int index, 810 const void *clock_info) 811 { 812 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps); 813 814 smu10_ps->levels[index].engine_clock = 0; 815 816 smu10_ps->levels[index].vddc_index = 0; 817 smu10_ps->level = index + 1; 818 819 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 820 smu10_ps->levels[index].ds_divider_index = 5; 821 smu10_ps->levels[index].ss_divider_index = 5; 822 } 823 824 return 0; 825 } 826 827 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) 828 { 829 int result; 830 unsigned long ret = 0; 831 832 result = pp_tables_get_num_of_entries(hwmgr, &ret); 833 834 return result ? 0 : ret; 835 } 836 837 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, 838 unsigned long entry, struct pp_power_state *ps) 839 { 840 int result; 841 struct smu10_power_state *smu10_ps; 842 843 ps->hardware.magic = SMU10_Magic; 844 845 smu10_ps = cast_smu10_ps(&(ps->hardware)); 846 847 result = pp_tables_get_entry(hwmgr, entry, ps, 848 smu10_dpm_get_pp_table_entry_callback); 849 850 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; 851 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; 852 853 return result; 854 } 855 856 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr) 857 { 858 return sizeof(struct smu10_power_state); 859 } 860 861 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr) 862 { 863 return 0; 864 } 865 866 867 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, 868 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) 869 { 870 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); 871 872 if (separation_time != data->separation_time || 873 cc6_disable != data->cc6_disable || 874 pstate_disable != data->pstate_disable) { 875 data->separation_time = separation_time; 876 data->cc6_disable = cc6_disable; 877 data->pstate_disable = pstate_disable; 878 data->cc6_setting_changed = true; 879 } 880 return 0; 881 } 882 883 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr, 884 struct amd_pp_simple_clock_info *info) 885 { 886 return -EINVAL; 887 } 888 889 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, 890 enum pp_clock_type type, uint32_t mask) 891 { 892 struct smu10_hwmgr *data = hwmgr->backend; 893 struct smu10_voltage_dependency_table *mclk_table = 894 data->clock_vol_info.vdd_dep_on_fclk; 895 uint32_t low, high; 896 897 low = mask ? (ffs(mask) - 1) : 0; 898 high = mask ? (fls(mask) - 1) : 0; 899 900 switch (type) { 901 case PP_SCLK: 902 if (low > 2 || high > 2) { 903 pr_info("Currently sclk only support 3 levels on RV\n"); 904 return -EINVAL; 905 } 906 907 smum_send_msg_to_smc_with_parameter(hwmgr, 908 PPSMC_MSG_SetHardMinGfxClk, 909 low == 2 ? data->gfx_max_freq_limit/100 : 910 low == 1 ? SMU10_UMD_PSTATE_GFXCLK : 911 data->gfx_min_freq_limit/100, 912 NULL); 913 914 smum_send_msg_to_smc_with_parameter(hwmgr, 915 PPSMC_MSG_SetSoftMaxGfxClk, 916 high == 0 ? data->gfx_min_freq_limit/100 : 917 high == 1 ? SMU10_UMD_PSTATE_GFXCLK : 918 data->gfx_max_freq_limit/100, 919 NULL); 920 break; 921 922 case PP_MCLK: 923 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) 924 return -EINVAL; 925 926 smum_send_msg_to_smc_with_parameter(hwmgr, 927 PPSMC_MSG_SetHardMinFclkByFreq, 928 mclk_table->entries[low].clk/100, 929 NULL); 930 931 smum_send_msg_to_smc_with_parameter(hwmgr, 932 PPSMC_MSG_SetSoftMaxFclkByFreq, 933 mclk_table->entries[high].clk/100, 934 NULL); 935 break; 936 937 case PP_PCIE: 938 default: 939 break; 940 } 941 return 0; 942 } 943 944 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, 945 enum pp_clock_type type, char *buf) 946 { 947 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); 948 struct smu10_voltage_dependency_table *mclk_table = 949 data->clock_vol_info.vdd_dep_on_fclk; 950 uint32_t i, now, size = 0; 951 952 switch (type) { 953 case PP_SCLK: 954 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now); 955 956 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 957 if (now == data->gfx_max_freq_limit/100) 958 i = 2; 959 else if (now == data->gfx_min_freq_limit/100) 960 i = 0; 961 else 962 i = 1; 963 964 size += sprintf(buf + size, "0: %uMhz %s\n", 965 data->gfx_min_freq_limit/100, 966 i == 0 ? "*" : ""); 967 size += sprintf(buf + size, "1: %uMhz %s\n", 968 i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK, 969 i == 1 ? "*" : ""); 970 size += sprintf(buf + size, "2: %uMhz %s\n", 971 data->gfx_max_freq_limit/100, 972 i == 2 ? "*" : ""); 973 break; 974 case PP_MCLK: 975 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); 976 977 for (i = 0; i < mclk_table->count; i++) 978 size += sprintf(buf + size, "%d: %uMhz %s\n", 979 i, 980 mclk_table->entries[i].clk / 100, 981 ((mclk_table->entries[i].clk / 100) 982 == now) ? "*" : ""); 983 break; 984 case OD_SCLK: 985 if (hwmgr->od_enabled) { 986 size = sprintf(buf, "%s:\n", "OD_SCLK"); 987 988 size += sprintf(buf + size, "0: %10uMhz\n", 989 (data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : data->gfx_min_freq_limit/100); 990 size += sprintf(buf + size, "1: %10uMhz\n", data->gfx_max_freq_limit/100); 991 } 992 break; 993 case OD_RANGE: 994 if (hwmgr->od_enabled) { 995 uint32_t min_freq, max_freq = 0; 996 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); 997 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); 998 999 size = sprintf(buf, "%s:\n", "OD_RANGE"); 1000 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 1001 min_freq, max_freq); 1002 } 1003 break; 1004 default: 1005 break; 1006 } 1007 1008 return size; 1009 } 1010 1011 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 1012 PHM_PerformanceLevelDesignation designation, uint32_t index, 1013 PHM_PerformanceLevel *level) 1014 { 1015 struct smu10_hwmgr *data; 1016 1017 if (level == NULL || hwmgr == NULL || state == NULL) 1018 return -EINVAL; 1019 1020 data = (struct smu10_hwmgr *)(hwmgr->backend); 1021 1022 if (index == 0) { 1023 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; 1024 level->coreClock = data->gfx_min_freq_limit; 1025 } else { 1026 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ 1027 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; 1028 level->coreClock = data->gfx_max_freq_limit; 1029 } 1030 1031 level->nonLocalMemoryFreq = 0; 1032 level->nonLocalMemoryWidth = 0; 1033 1034 return 0; 1035 } 1036 1037 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, 1038 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) 1039 { 1040 const struct smu10_power_state *ps = cast_const_smu10_ps(state); 1041 1042 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); 1043 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); 1044 1045 return 0; 1046 } 1047 1048 #define MEM_FREQ_LOW_LATENCY 25000 1049 #define MEM_FREQ_HIGH_LATENCY 80000 1050 #define MEM_LATENCY_HIGH 245 1051 #define MEM_LATENCY_LOW 35 1052 #define MEM_LATENCY_ERR 0xFFFF 1053 1054 1055 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr, 1056 uint32_t clock) 1057 { 1058 if (clock >= MEM_FREQ_LOW_LATENCY && 1059 clock < MEM_FREQ_HIGH_LATENCY) 1060 return MEM_LATENCY_HIGH; 1061 else if (clock >= MEM_FREQ_HIGH_LATENCY) 1062 return MEM_LATENCY_LOW; 1063 else 1064 return MEM_LATENCY_ERR; 1065 } 1066 1067 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 1068 enum amd_pp_clock_type type, 1069 struct pp_clock_levels_with_latency *clocks) 1070 { 1071 uint32_t i; 1072 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1073 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 1074 struct smu10_voltage_dependency_table *pclk_vol_table; 1075 bool latency_required = false; 1076 1077 if (pinfo == NULL) 1078 return -EINVAL; 1079 1080 switch (type) { 1081 case amd_pp_mem_clock: 1082 pclk_vol_table = pinfo->vdd_dep_on_mclk; 1083 latency_required = true; 1084 break; 1085 case amd_pp_f_clock: 1086 pclk_vol_table = pinfo->vdd_dep_on_fclk; 1087 latency_required = true; 1088 break; 1089 case amd_pp_dcf_clock: 1090 pclk_vol_table = pinfo->vdd_dep_on_dcefclk; 1091 break; 1092 case amd_pp_disp_clock: 1093 pclk_vol_table = pinfo->vdd_dep_on_dispclk; 1094 break; 1095 case amd_pp_phy_clock: 1096 pclk_vol_table = pinfo->vdd_dep_on_phyclk; 1097 break; 1098 case amd_pp_dpp_clock: 1099 pclk_vol_table = pinfo->vdd_dep_on_dppclk; 1100 break; 1101 default: 1102 return -EINVAL; 1103 } 1104 1105 if (pclk_vol_table == NULL || pclk_vol_table->count == 0) 1106 return -EINVAL; 1107 1108 clocks->num_levels = 0; 1109 for (i = 0; i < pclk_vol_table->count; i++) { 1110 if (pclk_vol_table->entries[i].clk) { 1111 clocks->data[clocks->num_levels].clocks_in_khz = 1112 pclk_vol_table->entries[i].clk * 10; 1113 clocks->data[clocks->num_levels].latency_in_us = latency_required ? 1114 smu10_get_mem_latency(hwmgr, 1115 pclk_vol_table->entries[i].clk) : 1116 0; 1117 clocks->num_levels++; 1118 } 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 1125 enum amd_pp_clock_type type, 1126 struct pp_clock_levels_with_voltage *clocks) 1127 { 1128 uint32_t i; 1129 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1130 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 1131 struct smu10_voltage_dependency_table *pclk_vol_table = NULL; 1132 1133 if (pinfo == NULL) 1134 return -EINVAL; 1135 1136 switch (type) { 1137 case amd_pp_mem_clock: 1138 pclk_vol_table = pinfo->vdd_dep_on_mclk; 1139 break; 1140 case amd_pp_f_clock: 1141 pclk_vol_table = pinfo->vdd_dep_on_fclk; 1142 break; 1143 case amd_pp_dcf_clock: 1144 pclk_vol_table = pinfo->vdd_dep_on_dcefclk; 1145 break; 1146 case amd_pp_soc_clock: 1147 pclk_vol_table = pinfo->vdd_dep_on_socclk; 1148 break; 1149 case amd_pp_disp_clock: 1150 pclk_vol_table = pinfo->vdd_dep_on_dispclk; 1151 break; 1152 case amd_pp_phy_clock: 1153 pclk_vol_table = pinfo->vdd_dep_on_phyclk; 1154 break; 1155 default: 1156 return -EINVAL; 1157 } 1158 1159 if (pclk_vol_table == NULL || pclk_vol_table->count == 0) 1160 return -EINVAL; 1161 1162 clocks->num_levels = 0; 1163 for (i = 0; i < pclk_vol_table->count; i++) { 1164 if (pclk_vol_table->entries[i].clk) { 1165 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; 1166 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; 1167 clocks->num_levels++; 1168 } 1169 } 1170 1171 return 0; 1172 } 1173 1174 1175 1176 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) 1177 { 1178 clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */ 1179 return 0; 1180 } 1181 1182 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 1183 { 1184 struct amdgpu_device *adev = hwmgr->adev; 1185 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); 1186 int cur_temp = 1187 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; 1188 1189 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK) 1190 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1191 else 1192 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1193 1194 return cur_temp; 1195 } 1196 1197 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1198 void *value, int *size) 1199 { 1200 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1201 uint32_t sclk, mclk; 1202 int ret = 0; 1203 1204 switch (idx) { 1205 case AMDGPU_PP_SENSOR_GFX_SCLK: 1206 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); 1207 /* in units of 10KHZ */ 1208 *((uint32_t *)value) = sclk * 100; 1209 *size = 4; 1210 break; 1211 case AMDGPU_PP_SENSOR_GFX_MCLK: 1212 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk); 1213 /* in units of 10KHZ */ 1214 *((uint32_t *)value) = mclk * 100; 1215 *size = 4; 1216 break; 1217 case AMDGPU_PP_SENSOR_GPU_TEMP: 1218 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); 1219 break; 1220 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 1221 *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; 1222 *size = 4; 1223 break; 1224 default: 1225 ret = -EINVAL; 1226 break; 1227 } 1228 1229 return ret; 1230 } 1231 1232 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 1233 void *clock_ranges) 1234 { 1235 struct smu10_hwmgr *data = hwmgr->backend; 1236 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 1237 Watermarks_t *table = &(data->water_marks_table); 1238 struct amdgpu_device *adev = hwmgr->adev; 1239 int i; 1240 1241 smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges); 1242 1243 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1244 for (i = 0; i < NUM_WM_RANGES; i++) 1245 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; 1246 1247 for (i = 0; i < NUM_WM_RANGES; i++) 1248 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0; 1249 } 1250 1251 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); 1252 data->water_marks_exist = true; 1253 return 0; 1254 } 1255 1256 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr) 1257 { 1258 1259 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL); 1260 } 1261 1262 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr) 1263 { 1264 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL); 1265 } 1266 1267 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate) 1268 { 1269 if (gate) 1270 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL); 1271 else 1272 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL); 1273 } 1274 1275 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) 1276 { 1277 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1278 1279 if (bgate) { 1280 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 1281 AMD_IP_BLOCK_TYPE_VCN, 1282 AMD_PG_STATE_GATE); 1283 smum_send_msg_to_smc_with_parameter(hwmgr, 1284 PPSMC_MSG_PowerDownVcn, 0, NULL); 1285 smu10_data->vcn_power_gated = true; 1286 } else { 1287 smum_send_msg_to_smc_with_parameter(hwmgr, 1288 PPSMC_MSG_PowerUpVcn, 0, NULL); 1289 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 1290 AMD_IP_BLOCK_TYPE_VCN, 1291 AMD_PG_STATE_UNGATE); 1292 smu10_data->vcn_power_gated = false; 1293 } 1294 } 1295 1296 static int conv_power_profile_to_pplib_workload(int power_profile) 1297 { 1298 int pplib_workload = 0; 1299 1300 switch (power_profile) { 1301 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 1302 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; 1303 break; 1304 case PP_SMC_POWER_PROFILE_VIDEO: 1305 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; 1306 break; 1307 case PP_SMC_POWER_PROFILE_VR: 1308 pplib_workload = WORKLOAD_PPLIB_VR_BIT; 1309 break; 1310 case PP_SMC_POWER_PROFILE_COMPUTE: 1311 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; 1312 break; 1313 case PP_SMC_POWER_PROFILE_CUSTOM: 1314 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; 1315 break; 1316 } 1317 1318 return pplib_workload; 1319 } 1320 1321 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 1322 { 1323 uint32_t i, size = 0; 1324 static const uint8_t 1325 profile_mode_setting[6][4] = {{70, 60, 0, 0,}, 1326 {70, 60, 1, 3,}, 1327 {90, 60, 0, 0,}, 1328 {70, 60, 0, 0,}, 1329 {70, 90, 0, 0,}, 1330 {30, 60, 0, 6,}, 1331 }; 1332 static const char *profile_name[6] = { 1333 "BOOTUP_DEFAULT", 1334 "3D_FULL_SCREEN", 1335 "POWER_SAVING", 1336 "VIDEO", 1337 "VR", 1338 "COMPUTE"}; 1339 static const char *title[6] = {"NUM", 1340 "MODE_NAME", 1341 "BUSY_SET_POINT", 1342 "FPS", 1343 "USE_RLC_BUSY", 1344 "MIN_ACTIVE_LEVEL"}; 1345 1346 if (!buf) 1347 return -EINVAL; 1348 1349 size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0], 1350 title[1], title[2], title[3], title[4], title[5]); 1351 1352 for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++) 1353 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n", 1354 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 1355 profile_mode_setting[i][0], profile_mode_setting[i][1], 1356 profile_mode_setting[i][2], profile_mode_setting[i][3]); 1357 1358 return size; 1359 } 1360 1361 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) 1362 { 1363 struct amdgpu_device *adev = hwmgr->adev; 1364 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 1365 (hwmgr->smu_version >= 0x41e2b)) 1366 return true; 1367 else 1368 return false; 1369 } 1370 1371 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 1372 { 1373 int workload_type = 0; 1374 int result = 0; 1375 1376 if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) { 1377 pr_err("Invalid power profile mode %ld\n", input[size]); 1378 return -EINVAL; 1379 } 1380 if (hwmgr->power_profile_mode == input[size]) 1381 return 0; 1382 1383 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1384 workload_type = 1385 conv_power_profile_to_pplib_workload(input[size]); 1386 if (workload_type && 1387 smu10_is_raven1_refresh(hwmgr) && 1388 !hwmgr->gfxoff_state_changed_by_workload) { 1389 smu10_gfx_off_control(hwmgr, false); 1390 hwmgr->gfxoff_state_changed_by_workload = true; 1391 } 1392 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify, 1393 1 << workload_type, 1394 NULL); 1395 if (!result) 1396 hwmgr->power_profile_mode = input[size]; 1397 if (workload_type && hwmgr->gfxoff_state_changed_by_workload) { 1398 smu10_gfx_off_control(hwmgr, true); 1399 hwmgr->gfxoff_state_changed_by_workload = false; 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode) 1406 { 1407 return smum_send_msg_to_smc_with_parameter(hwmgr, 1408 PPSMC_MSG_DeviceDriverReset, 1409 mode, 1410 NULL); 1411 } 1412 1413 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, 1414 enum PP_OD_DPM_TABLE_COMMAND type, 1415 long *input, uint32_t size) 1416 { 1417 if (!hwmgr->od_enabled) { 1418 pr_err("Fine grain not support\n"); 1419 return -EINVAL; 1420 } 1421 1422 if (size != 2) { 1423 pr_err("Input parameter number not correct\n"); 1424 return -EINVAL; 1425 } 1426 1427 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 1428 if (input[0] == 0) 1429 smu10_set_hard_min_gfxclk_by_freq(hwmgr, input[1]); 1430 else if (input[0] == 1) 1431 smu10_set_soft_max_gfxclk_by_freq(hwmgr, input[1]); 1432 else 1433 return -EINVAL; 1434 } 1435 1436 return 0; 1437 } 1438 1439 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state) 1440 { 1441 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL); 1442 1443 return 0; 1444 } 1445 1446 static const struct pp_hwmgr_func smu10_hwmgr_funcs = { 1447 .backend_init = smu10_hwmgr_backend_init, 1448 .backend_fini = smu10_hwmgr_backend_fini, 1449 .apply_state_adjust_rules = smu10_apply_state_adjust_rules, 1450 .force_dpm_level = smu10_dpm_force_dpm_level, 1451 .get_power_state_size = smu10_get_power_state_size, 1452 .powerdown_uvd = NULL, 1453 .powergate_uvd = smu10_powergate_vcn, 1454 .powergate_vce = NULL, 1455 .get_mclk = smu10_dpm_get_mclk, 1456 .get_sclk = smu10_dpm_get_sclk, 1457 .patch_boot_state = smu10_dpm_patch_boot_state, 1458 .get_pp_table_entry = smu10_dpm_get_pp_table_entry, 1459 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries, 1460 .set_cpu_power_state = smu10_set_cpu_power_state, 1461 .store_cc6_data = smu10_store_cc6_data, 1462 .force_clock_level = smu10_force_clock_level, 1463 .print_clock_levels = smu10_print_clock_levels, 1464 .get_dal_power_level = smu10_get_dal_power_level, 1465 .get_performance_level = smu10_get_performance_level, 1466 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks, 1467 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency, 1468 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage, 1469 .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges, 1470 .get_max_high_clocks = smu10_get_max_high_clocks, 1471 .read_sensor = smu10_read_sensor, 1472 .set_active_display_count = smu10_set_active_display_count, 1473 .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk, 1474 .dynamic_state_management_enable = smu10_enable_dpm_tasks, 1475 .power_off_asic = smu10_power_off_asic, 1476 .asic_setup = smu10_setup_asic_task, 1477 .power_state_set = smu10_set_power_state_tasks, 1478 .dynamic_state_management_disable = smu10_disable_dpm_tasks, 1479 .powergate_mmhub = smu10_powergate_mmhub, 1480 .smus_notify_pwe = smu10_smus_notify_pwe, 1481 .display_clock_voltage_request = smu10_display_clock_voltage_request, 1482 .powergate_gfx = smu10_gfx_off_control, 1483 .powergate_sdma = smu10_powergate_sdma, 1484 .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq, 1485 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq, 1486 .set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq, 1487 .set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq, 1488 .get_power_profile_mode = smu10_get_power_profile_mode, 1489 .set_power_profile_mode = smu10_set_power_profile_mode, 1490 .asic_reset = smu10_asic_reset, 1491 .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol, 1492 .gfx_state_change = smu10_gfx_state_change, 1493 }; 1494 1495 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) 1496 { 1497 hwmgr->hwmgr_func = &smu10_hwmgr_funcs; 1498 hwmgr->pptable_func = &pptable_funcs; 1499 return 0; 1500 } 1501