1e098bc96SEvan Quan /* 2e098bc96SEvan Quan * Copyright 2016 Advanced Micro Devices, Inc. 3e098bc96SEvan Quan * 4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a 5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"), 6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation 7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the 9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions: 10e098bc96SEvan Quan * 11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in 12e098bc96SEvan Quan * all copies or substantial portions of the Software. 13e098bc96SEvan Quan * 14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE. 21e098bc96SEvan Quan * 22e098bc96SEvan Quan */ 23e098bc96SEvan Quan 24e098bc96SEvan Quan #ifndef PP_ATOMFWCTRL_H 25e098bc96SEvan Quan #define PP_ATOMFWCTRL_H 26e098bc96SEvan Quan 27e098bc96SEvan Quan #include "hwmgr.h" 28e098bc96SEvan Quan 29e098bc96SEvan Quan typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID; 30e098bc96SEvan Quan 31e098bc96SEvan Quan #define GetIndexIntoMasterCmdTable(FieldName) \ 320069a227SArnd Bergmann (offsetof(struct atom_master_list_of_command_functions_v2_1, FieldName) / sizeof(uint16_t)) 33e098bc96SEvan Quan #define GetIndexIntoMasterDataTable(FieldName) \ 340069a227SArnd Bergmann (offsetof(struct atom_master_list_of_data_tables_v2_1, FieldName) / sizeof(uint16_t)) 35e098bc96SEvan Quan 36e098bc96SEvan Quan #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32 37e098bc96SEvan Quan 38e098bc96SEvan Quan struct pp_atomfwctrl_voltage_table_entry { 39e098bc96SEvan Quan uint16_t value; 40e098bc96SEvan Quan uint32_t smio_low; 41e098bc96SEvan Quan }; 42e098bc96SEvan Quan 43e098bc96SEvan Quan struct pp_atomfwctrl_voltage_table { 44e098bc96SEvan Quan uint32_t count; 45e098bc96SEvan Quan uint32_t mask_low; 46e098bc96SEvan Quan uint32_t phase_delay; 47e098bc96SEvan Quan uint8_t psi0_enable; 48e098bc96SEvan Quan uint8_t psi1_enable; 49e098bc96SEvan Quan uint8_t max_vid_step; 50e098bc96SEvan Quan uint8_t telemetry_offset; 51e098bc96SEvan Quan uint8_t telemetry_slope; 52e098bc96SEvan Quan struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES]; 53e098bc96SEvan Quan }; 54e098bc96SEvan Quan 55e098bc96SEvan Quan struct pp_atomfwctrl_gpio_pin_assignment { 56e098bc96SEvan Quan uint16_t us_gpio_pin_aindex; 57e098bc96SEvan Quan uint8_t uc_gpio_pin_bit_shift; 58e098bc96SEvan Quan }; 59e098bc96SEvan Quan 60e098bc96SEvan Quan struct pp_atomfwctrl_clock_dividers_soc15 { 61e098bc96SEvan Quan uint32_t ulClock; /* the actual clock */ 62e098bc96SEvan Quan uint32_t ulDid; /* DFS divider */ 63e098bc96SEvan Quan uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */ 64e098bc96SEvan Quan uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */ 65e098bc96SEvan Quan uint16_t usPll_ss_slew_frac; 66e098bc96SEvan Quan uint8_t ucPll_ss_enable; 67e098bc96SEvan Quan uint8_t ucReserve; 68e098bc96SEvan Quan uint32_t ulReserve[2]; 69e098bc96SEvan Quan }; 70e098bc96SEvan Quan 71e098bc96SEvan Quan struct pp_atomfwctrl_avfs_parameters { 72e098bc96SEvan Quan uint32_t ulMaxVddc; 73e098bc96SEvan Quan uint32_t ulMinVddc; 74e098bc96SEvan Quan 75e098bc96SEvan Quan uint32_t ulMeanNsigmaAcontant0; 76e098bc96SEvan Quan uint32_t ulMeanNsigmaAcontant1; 77e098bc96SEvan Quan uint32_t ulMeanNsigmaAcontant2; 78e098bc96SEvan Quan uint16_t usMeanNsigmaDcTolSigma; 79e098bc96SEvan Quan uint16_t usMeanNsigmaPlatformMean; 80e098bc96SEvan Quan uint16_t usMeanNsigmaPlatformSigma; 81e098bc96SEvan Quan uint32_t ulGbVdroopTableCksoffA0; 82e098bc96SEvan Quan uint32_t ulGbVdroopTableCksoffA1; 83e098bc96SEvan Quan uint32_t ulGbVdroopTableCksoffA2; 84e098bc96SEvan Quan uint32_t ulGbVdroopTableCksonA0; 85e098bc96SEvan Quan uint32_t ulGbVdroopTableCksonA1; 86e098bc96SEvan Quan uint32_t ulGbVdroopTableCksonA2; 87e098bc96SEvan Quan 88e098bc96SEvan Quan uint32_t ulGbFuseTableCksoffM1; 89e098bc96SEvan Quan uint32_t ulGbFuseTableCksoffM2; 90e098bc96SEvan Quan uint32_t ulGbFuseTableCksoffB; 91e098bc96SEvan Quan 92e098bc96SEvan Quan uint32_t ulGbFuseTableCksonM1; 93e098bc96SEvan Quan uint32_t ulGbFuseTableCksonM2; 94e098bc96SEvan Quan uint32_t ulGbFuseTableCksonB; 95e098bc96SEvan Quan 96e098bc96SEvan Quan uint8_t ucEnableGbVdroopTableCkson; 97e098bc96SEvan Quan uint8_t ucEnableGbFuseTableCkson; 98e098bc96SEvan Quan uint16_t usPsmAgeComfactor; 99e098bc96SEvan Quan 100e098bc96SEvan Quan uint32_t ulDispclk2GfxclkM1; 101e098bc96SEvan Quan uint32_t ulDispclk2GfxclkM2; 102e098bc96SEvan Quan uint32_t ulDispclk2GfxclkB; 103e098bc96SEvan Quan uint32_t ulDcefclk2GfxclkM1; 104e098bc96SEvan Quan uint32_t ulDcefclk2GfxclkM2; 105e098bc96SEvan Quan uint32_t ulDcefclk2GfxclkB; 106e098bc96SEvan Quan uint32_t ulPixelclk2GfxclkM1; 107e098bc96SEvan Quan uint32_t ulPixelclk2GfxclkM2; 108e098bc96SEvan Quan uint32_t ulPixelclk2GfxclkB; 109e098bc96SEvan Quan uint32_t ulPhyclk2GfxclkM1; 110e098bc96SEvan Quan uint32_t ulPhyclk2GfxclkM2; 111e098bc96SEvan Quan uint32_t ulPhyclk2GfxclkB; 112e098bc96SEvan Quan uint32_t ulAcgGbVdroopTableA0; 113e098bc96SEvan Quan uint32_t ulAcgGbVdroopTableA1; 114e098bc96SEvan Quan uint32_t ulAcgGbVdroopTableA2; 115e098bc96SEvan Quan uint32_t ulAcgGbFuseTableM1; 116e098bc96SEvan Quan uint32_t ulAcgGbFuseTableM2; 117e098bc96SEvan Quan uint32_t ulAcgGbFuseTableB; 118e098bc96SEvan Quan uint32_t ucAcgEnableGbVdroopTable; 119e098bc96SEvan Quan uint32_t ucAcgEnableGbFuseTable; 120e098bc96SEvan Quan }; 121e098bc96SEvan Quan 122e098bc96SEvan Quan struct pp_atomfwctrl_gpio_parameters { 123e098bc96SEvan Quan uint8_t ucAcDcGpio; 124e098bc96SEvan Quan uint8_t ucAcDcPolarity; 125e098bc96SEvan Quan uint8_t ucVR0HotGpio; 126e098bc96SEvan Quan uint8_t ucVR0HotPolarity; 127e098bc96SEvan Quan uint8_t ucVR1HotGpio; 128e098bc96SEvan Quan uint8_t ucVR1HotPolarity; 129e098bc96SEvan Quan uint8_t ucFwCtfGpio; 130e098bc96SEvan Quan uint8_t ucFwCtfPolarity; 131e098bc96SEvan Quan }; 132e098bc96SEvan Quan 133e098bc96SEvan Quan struct pp_atomfwctrl_bios_boot_up_values { 134e098bc96SEvan Quan uint32_t ulRevision; 135e098bc96SEvan Quan uint32_t ulGfxClk; 136e098bc96SEvan Quan uint32_t ulUClk; 137e098bc96SEvan Quan uint32_t ulSocClk; 138e098bc96SEvan Quan uint32_t ulDCEFClk; 139e098bc96SEvan Quan uint32_t ulEClk; 140e098bc96SEvan Quan uint32_t ulVClk; 141e098bc96SEvan Quan uint32_t ulDClk; 142e098bc96SEvan Quan uint32_t ulFClk; 143e098bc96SEvan Quan uint16_t usVddc; 144e098bc96SEvan Quan uint16_t usVddci; 145e098bc96SEvan Quan uint16_t usMvddc; 146e098bc96SEvan Quan uint16_t usVddGfx; 147e098bc96SEvan Quan uint8_t ucCoolingID; 148e098bc96SEvan Quan }; 149e098bc96SEvan Quan 150*0abfc3fdSRan Sun struct pp_atomfwctrl_smc_dpm_parameters { 151e098bc96SEvan Quan uint8_t liquid1_i2c_address; 152e098bc96SEvan Quan uint8_t liquid2_i2c_address; 153e098bc96SEvan Quan uint8_t vr_i2c_address; 154e098bc96SEvan Quan uint8_t plx_i2c_address; 155e098bc96SEvan Quan uint8_t liquid_i2c_linescl; 156e098bc96SEvan Quan uint8_t liquid_i2c_linesda; 157e098bc96SEvan Quan uint8_t vr_i2c_linescl; 158e098bc96SEvan Quan uint8_t vr_i2c_linesda; 159e098bc96SEvan Quan uint8_t plx_i2c_linescl; 160e098bc96SEvan Quan uint8_t plx_i2c_linesda; 161e098bc96SEvan Quan uint8_t vrsensorpresent; 162e098bc96SEvan Quan uint8_t liquidsensorpresent; 163e098bc96SEvan Quan uint16_t maxvoltagestepgfx; 164e098bc96SEvan Quan uint16_t maxvoltagestepsoc; 165e098bc96SEvan Quan uint8_t vddgfxvrmapping; 166e098bc96SEvan Quan uint8_t vddsocvrmapping; 167e098bc96SEvan Quan uint8_t vddmem0vrmapping; 168e098bc96SEvan Quan uint8_t vddmem1vrmapping; 169e098bc96SEvan Quan uint8_t gfxulvphasesheddingmask; 170e098bc96SEvan Quan uint8_t soculvphasesheddingmask; 171e098bc96SEvan Quan 172e098bc96SEvan Quan uint16_t gfxmaxcurrent; 173e098bc96SEvan Quan uint8_t gfxoffset; 174e098bc96SEvan Quan uint8_t padding_telemetrygfx; 175e098bc96SEvan Quan uint16_t socmaxcurrent; 176e098bc96SEvan Quan uint8_t socoffset; 177e098bc96SEvan Quan uint8_t padding_telemetrysoc; 178e098bc96SEvan Quan uint16_t mem0maxcurrent; 179e098bc96SEvan Quan uint8_t mem0offset; 180e098bc96SEvan Quan uint8_t padding_telemetrymem0; 181e098bc96SEvan Quan uint16_t mem1maxcurrent; 182e098bc96SEvan Quan uint8_t mem1offset; 183e098bc96SEvan Quan uint8_t padding_telemetrymem1; 184e098bc96SEvan Quan 185e098bc96SEvan Quan uint8_t acdcgpio; 186e098bc96SEvan Quan uint8_t acdcpolarity; 187e098bc96SEvan Quan uint8_t vr0hotgpio; 188e098bc96SEvan Quan uint8_t vr0hotpolarity; 189e098bc96SEvan Quan uint8_t vr1hotgpio; 190e098bc96SEvan Quan uint8_t vr1hotpolarity; 191e098bc96SEvan Quan uint8_t padding1; 192e098bc96SEvan Quan uint8_t padding2; 193e098bc96SEvan Quan 194e098bc96SEvan Quan uint8_t ledpin0; 195e098bc96SEvan Quan uint8_t ledpin1; 196e098bc96SEvan Quan uint8_t ledpin2; 197e098bc96SEvan Quan 198e098bc96SEvan Quan uint8_t pllgfxclkspreadenabled; 199e098bc96SEvan Quan uint8_t pllgfxclkspreadpercent; 200e098bc96SEvan Quan uint16_t pllgfxclkspreadfreq; 201e098bc96SEvan Quan 202e098bc96SEvan Quan uint8_t uclkspreadenabled; 203e098bc96SEvan Quan uint8_t uclkspreadpercent; 204e098bc96SEvan Quan uint16_t uclkspreadfreq; 205e098bc96SEvan Quan 206e098bc96SEvan Quan uint8_t socclkspreadenabled; 207e098bc96SEvan Quan uint8_t socclkspreadpercent; 208e098bc96SEvan Quan uint16_t socclkspreadfreq; 209e098bc96SEvan Quan 210e098bc96SEvan Quan uint8_t acggfxclkspreadenabled; 211e098bc96SEvan Quan uint8_t acggfxclkspreadpercent; 212e098bc96SEvan Quan uint16_t acggfxclkspreadfreq; 213e098bc96SEvan Quan 214e098bc96SEvan Quan uint8_t Vr2_I2C_address; 215e098bc96SEvan Quan }; 216e098bc96SEvan Quan 217e098bc96SEvan Quan int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, 218e098bc96SEvan Quan uint32_t clock_type, uint32_t clock_value, 219e098bc96SEvan Quan struct pp_atomfwctrl_clock_dividers_soc15 *dividers); 220e098bc96SEvan Quan int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr); 221e098bc96SEvan Quan bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id, 222e098bc96SEvan Quan struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment); 223e098bc96SEvan Quan 224e098bc96SEvan Quan int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 225e098bc96SEvan Quan uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table); 226e098bc96SEvan Quan bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr, 227e098bc96SEvan Quan uint8_t voltage_type, uint8_t voltage_mode); 228e098bc96SEvan Quan 229e098bc96SEvan Quan int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, 230e098bc96SEvan Quan struct pp_atomfwctrl_avfs_parameters *param); 231e098bc96SEvan Quan int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, 232e098bc96SEvan Quan struct pp_atomfwctrl_gpio_parameters *param); 233e098bc96SEvan Quan 234e098bc96SEvan Quan int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, 235e098bc96SEvan Quan struct pp_atomfwctrl_bios_boot_up_values *boot_values); 236e098bc96SEvan Quan int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, 237e098bc96SEvan Quan struct pp_atomfwctrl_smc_dpm_parameters *param); 238e098bc96SEvan Quan int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, 239e098bc96SEvan Quan uint8_t clk_id, uint8_t syspll_id, 240e098bc96SEvan Quan uint32_t *frequency); 241e098bc96SEvan Quan 242e098bc96SEvan Quan #endif 243e098bc96SEvan Quan 244