1 /*
2  * Copyright 2015 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include "pp_debug.h"
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/gfp.h>
27 #include <linux/slab.h>
28 #include <linux/firmware.h>
29 #include "amd_shared.h"
30 #include "amd_powerplay.h"
31 #include "power_state.h"
32 #include "amdgpu.h"
33 #include "hwmgr.h"
34 
35 
36 static const struct amd_pm_funcs pp_dpm_funcs;
37 
38 static int amd_powerplay_create(struct amdgpu_device *adev)
39 {
40 	struct pp_hwmgr *hwmgr;
41 
42 	if (adev == NULL)
43 		return -EINVAL;
44 
45 	hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
46 	if (hwmgr == NULL)
47 		return -ENOMEM;
48 
49 	hwmgr->adev = adev;
50 	hwmgr->not_vf = !amdgpu_sriov_vf(adev);
51 	hwmgr->device = amdgpu_cgs_create_device(adev);
52 	mutex_init(&hwmgr->smu_lock);
53 	mutex_init(&hwmgr->msg_lock);
54 	hwmgr->chip_family = adev->family;
55 	hwmgr->chip_id = adev->asic_type;
56 	hwmgr->feature_mask = adev->pm.pp_feature;
57 	hwmgr->display_config = &adev->pm.pm_display_cfg;
58 	adev->powerplay.pp_handle = hwmgr;
59 	adev->powerplay.pp_funcs = &pp_dpm_funcs;
60 	return 0;
61 }
62 
63 
64 static void amd_powerplay_destroy(struct amdgpu_device *adev)
65 {
66 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
67 
68 	mutex_destroy(&hwmgr->msg_lock);
69 
70 	kfree(hwmgr->hardcode_pp_table);
71 	hwmgr->hardcode_pp_table = NULL;
72 
73 	kfree(hwmgr);
74 	hwmgr = NULL;
75 }
76 
77 static int pp_early_init(void *handle)
78 {
79 	int ret;
80 	struct amdgpu_device *adev = handle;
81 
82 	ret = amd_powerplay_create(adev);
83 
84 	if (ret != 0)
85 		return ret;
86 
87 	ret = hwmgr_early_init(adev->powerplay.pp_handle);
88 	if (ret)
89 		return -EINVAL;
90 
91 	return 0;
92 }
93 
94 static int pp_sw_init(void *handle)
95 {
96 	struct amdgpu_device *adev = handle;
97 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
98 	int ret = 0;
99 
100 	ret = hwmgr_sw_init(hwmgr);
101 
102 	pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully");
103 
104 	return ret;
105 }
106 
107 static int pp_sw_fini(void *handle)
108 {
109 	struct amdgpu_device *adev = handle;
110 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
111 
112 	hwmgr_sw_fini(hwmgr);
113 
114 	release_firmware(adev->pm.fw);
115 	adev->pm.fw = NULL;
116 
117 	return 0;
118 }
119 
120 static int pp_hw_init(void *handle)
121 {
122 	int ret = 0;
123 	struct amdgpu_device *adev = handle;
124 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
125 
126 	ret = hwmgr_hw_init(hwmgr);
127 
128 	if (ret)
129 		pr_err("powerplay hw init failed\n");
130 
131 	return ret;
132 }
133 
134 static int pp_hw_fini(void *handle)
135 {
136 	struct amdgpu_device *adev = handle;
137 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
138 
139 	hwmgr_hw_fini(hwmgr);
140 
141 	return 0;
142 }
143 
144 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
145 {
146 	int r = -EINVAL;
147 	void *cpu_ptr = NULL;
148 	uint64_t gpu_addr;
149 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
150 
151 	if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
152 						PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
153 						&adev->pm.smu_prv_buffer,
154 						&gpu_addr,
155 						&cpu_ptr)) {
156 		DRM_ERROR("amdgpu: failed to create smu prv buffer\n");
157 		return;
158 	}
159 
160 	if (hwmgr->hwmgr_func->notify_cac_buffer_info)
161 		r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
162 					lower_32_bits((unsigned long)cpu_ptr),
163 					upper_32_bits((unsigned long)cpu_ptr),
164 					lower_32_bits(gpu_addr),
165 					upper_32_bits(gpu_addr),
166 					adev->pm.smu_prv_buffer_size);
167 
168 	if (r) {
169 		amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
170 		adev->pm.smu_prv_buffer = NULL;
171 		DRM_ERROR("amdgpu: failed to notify SMU buffer address\n");
172 	}
173 }
174 
175 static int pp_late_init(void *handle)
176 {
177 	struct amdgpu_device *adev = handle;
178 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
179 
180 	if (hwmgr && hwmgr->pm_en) {
181 		mutex_lock(&hwmgr->smu_lock);
182 		hwmgr_handle_task(hwmgr,
183 					AMD_PP_TASK_COMPLETE_INIT, NULL);
184 		mutex_unlock(&hwmgr->smu_lock);
185 	}
186 	if (adev->pm.smu_prv_buffer_size != 0)
187 		pp_reserve_vram_for_smu(adev);
188 
189 	return 0;
190 }
191 
192 static void pp_late_fini(void *handle)
193 {
194 	struct amdgpu_device *adev = handle;
195 
196 	if (adev->pm.smu_prv_buffer)
197 		amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL);
198 	amd_powerplay_destroy(adev);
199 }
200 
201 
202 static bool pp_is_idle(void *handle)
203 {
204 	return false;
205 }
206 
207 static int pp_wait_for_idle(void *handle)
208 {
209 	return 0;
210 }
211 
212 static int pp_sw_reset(void *handle)
213 {
214 	return 0;
215 }
216 
217 static int pp_set_powergating_state(void *handle,
218 				    enum amd_powergating_state state)
219 {
220 	return 0;
221 }
222 
223 static int pp_suspend(void *handle)
224 {
225 	struct amdgpu_device *adev = handle;
226 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
227 
228 	return hwmgr_suspend(hwmgr);
229 }
230 
231 static int pp_resume(void *handle)
232 {
233 	struct amdgpu_device *adev = handle;
234 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
235 
236 	return hwmgr_resume(hwmgr);
237 }
238 
239 static int pp_set_clockgating_state(void *handle,
240 					  enum amd_clockgating_state state)
241 {
242 	return 0;
243 }
244 
245 static const struct amd_ip_funcs pp_ip_funcs = {
246 	.name = "powerplay",
247 	.early_init = pp_early_init,
248 	.late_init = pp_late_init,
249 	.sw_init = pp_sw_init,
250 	.sw_fini = pp_sw_fini,
251 	.hw_init = pp_hw_init,
252 	.hw_fini = pp_hw_fini,
253 	.late_fini = pp_late_fini,
254 	.suspend = pp_suspend,
255 	.resume = pp_resume,
256 	.is_idle = pp_is_idle,
257 	.wait_for_idle = pp_wait_for_idle,
258 	.soft_reset = pp_sw_reset,
259 	.set_clockgating_state = pp_set_clockgating_state,
260 	.set_powergating_state = pp_set_powergating_state,
261 };
262 
263 const struct amdgpu_ip_block_version pp_smu_ip_block =
264 {
265 	.type = AMD_IP_BLOCK_TYPE_SMC,
266 	.major = 1,
267 	.minor = 0,
268 	.rev = 0,
269 	.funcs = &pp_ip_funcs,
270 };
271 
272 /* This interface only be supported On Vi,
273  * because only smu7/8 can help to load gfx/sdma fw,
274  * smu need to be enabled before load other ip's fw.
275  * so call start smu to load smu7 fw and other ip's fw
276  */
277 static int pp_dpm_load_fw(void *handle)
278 {
279 	struct pp_hwmgr *hwmgr = handle;
280 
281 	if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
282 		return -EINVAL;
283 
284 	if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
285 		pr_err("fw load failed\n");
286 		return -EINVAL;
287 	}
288 
289 	return 0;
290 }
291 
292 static int pp_dpm_fw_loading_complete(void *handle)
293 {
294 	return 0;
295 }
296 
297 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
298 {
299 	struct pp_hwmgr *hwmgr = handle;
300 
301 	if (!hwmgr || !hwmgr->pm_en)
302 		return -EINVAL;
303 
304 	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
305 		pr_info_ratelimited("%s was not implemented.\n", __func__);
306 		return 0;
307 	}
308 
309 	return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
310 }
311 
312 static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
313 						enum amd_dpm_forced_level *level)
314 {
315 	uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
316 					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
317 					AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
318 					AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
319 
320 	if (!(hwmgr->dpm_level & profile_mode_mask)) {
321 		/* enter umd pstate, save current level, disable gfx cg*/
322 		if (*level & profile_mode_mask) {
323 			hwmgr->saved_dpm_level = hwmgr->dpm_level;
324 			hwmgr->en_umd_pstate = true;
325 			amdgpu_device_ip_set_powergating_state(hwmgr->adev,
326 					AMD_IP_BLOCK_TYPE_GFX,
327 					AMD_PG_STATE_UNGATE);
328 			amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
329 						AMD_IP_BLOCK_TYPE_GFX,
330 						AMD_CG_STATE_UNGATE);
331 		}
332 	} else {
333 		/* exit umd pstate, restore level, enable gfx cg*/
334 		if (!(*level & profile_mode_mask)) {
335 			if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
336 				*level = hwmgr->saved_dpm_level;
337 			hwmgr->en_umd_pstate = false;
338 			amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
339 					AMD_IP_BLOCK_TYPE_GFX,
340 					AMD_CG_STATE_GATE);
341 			amdgpu_device_ip_set_powergating_state(hwmgr->adev,
342 					AMD_IP_BLOCK_TYPE_GFX,
343 					AMD_PG_STATE_GATE);
344 		}
345 	}
346 }
347 
348 static int pp_dpm_force_performance_level(void *handle,
349 					enum amd_dpm_forced_level level)
350 {
351 	struct pp_hwmgr *hwmgr = handle;
352 
353 	if (!hwmgr || !hwmgr->pm_en)
354 		return -EINVAL;
355 
356 	if (level == hwmgr->dpm_level)
357 		return 0;
358 
359 	mutex_lock(&hwmgr->smu_lock);
360 	pp_dpm_en_umd_pstate(hwmgr, &level);
361 	hwmgr->request_dpm_level = level;
362 	hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
363 	mutex_unlock(&hwmgr->smu_lock);
364 
365 	return 0;
366 }
367 
368 static enum amd_dpm_forced_level pp_dpm_get_performance_level(
369 								void *handle)
370 {
371 	struct pp_hwmgr *hwmgr = handle;
372 	enum amd_dpm_forced_level level;
373 
374 	if (!hwmgr || !hwmgr->pm_en)
375 		return -EINVAL;
376 
377 	mutex_lock(&hwmgr->smu_lock);
378 	level = hwmgr->dpm_level;
379 	mutex_unlock(&hwmgr->smu_lock);
380 	return level;
381 }
382 
383 static uint32_t pp_dpm_get_sclk(void *handle, bool low)
384 {
385 	struct pp_hwmgr *hwmgr = handle;
386 	uint32_t clk = 0;
387 
388 	if (!hwmgr || !hwmgr->pm_en)
389 		return 0;
390 
391 	if (hwmgr->hwmgr_func->get_sclk == NULL) {
392 		pr_info_ratelimited("%s was not implemented.\n", __func__);
393 		return 0;
394 	}
395 	mutex_lock(&hwmgr->smu_lock);
396 	clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
397 	mutex_unlock(&hwmgr->smu_lock);
398 	return clk;
399 }
400 
401 static uint32_t pp_dpm_get_mclk(void *handle, bool low)
402 {
403 	struct pp_hwmgr *hwmgr = handle;
404 	uint32_t clk = 0;
405 
406 	if (!hwmgr || !hwmgr->pm_en)
407 		return 0;
408 
409 	if (hwmgr->hwmgr_func->get_mclk == NULL) {
410 		pr_info_ratelimited("%s was not implemented.\n", __func__);
411 		return 0;
412 	}
413 	mutex_lock(&hwmgr->smu_lock);
414 	clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
415 	mutex_unlock(&hwmgr->smu_lock);
416 	return clk;
417 }
418 
419 static void pp_dpm_powergate_vce(void *handle, bool gate)
420 {
421 	struct pp_hwmgr *hwmgr = handle;
422 
423 	if (!hwmgr || !hwmgr->pm_en)
424 		return;
425 
426 	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
427 		pr_info_ratelimited("%s was not implemented.\n", __func__);
428 		return;
429 	}
430 	mutex_lock(&hwmgr->smu_lock);
431 	hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
432 	mutex_unlock(&hwmgr->smu_lock);
433 }
434 
435 static void pp_dpm_powergate_uvd(void *handle, bool gate)
436 {
437 	struct pp_hwmgr *hwmgr = handle;
438 
439 	if (!hwmgr || !hwmgr->pm_en)
440 		return;
441 
442 	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
443 		pr_info_ratelimited("%s was not implemented.\n", __func__);
444 		return;
445 	}
446 	mutex_lock(&hwmgr->smu_lock);
447 	hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
448 	mutex_unlock(&hwmgr->smu_lock);
449 }
450 
451 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
452 		enum amd_pm_state_type *user_state)
453 {
454 	int ret = 0;
455 	struct pp_hwmgr *hwmgr = handle;
456 
457 	if (!hwmgr || !hwmgr->pm_en)
458 		return -EINVAL;
459 
460 	mutex_lock(&hwmgr->smu_lock);
461 	ret = hwmgr_handle_task(hwmgr, task_id, user_state);
462 	mutex_unlock(&hwmgr->smu_lock);
463 
464 	return ret;
465 }
466 
467 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
468 {
469 	struct pp_hwmgr *hwmgr = handle;
470 	struct pp_power_state *state;
471 	enum amd_pm_state_type pm_type;
472 
473 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
474 		return -EINVAL;
475 
476 	mutex_lock(&hwmgr->smu_lock);
477 
478 	state = hwmgr->current_ps;
479 
480 	switch (state->classification.ui_label) {
481 	case PP_StateUILabel_Battery:
482 		pm_type = POWER_STATE_TYPE_BATTERY;
483 		break;
484 	case PP_StateUILabel_Balanced:
485 		pm_type = POWER_STATE_TYPE_BALANCED;
486 		break;
487 	case PP_StateUILabel_Performance:
488 		pm_type = POWER_STATE_TYPE_PERFORMANCE;
489 		break;
490 	default:
491 		if (state->classification.flags & PP_StateClassificationFlag_Boot)
492 			pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
493 		else
494 			pm_type = POWER_STATE_TYPE_DEFAULT;
495 		break;
496 	}
497 	mutex_unlock(&hwmgr->smu_lock);
498 
499 	return pm_type;
500 }
501 
502 static void pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
503 {
504 	struct pp_hwmgr *hwmgr = handle;
505 
506 	if (!hwmgr || !hwmgr->pm_en)
507 		return;
508 
509 	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
510 		pr_info_ratelimited("%s was not implemented.\n", __func__);
511 		return;
512 	}
513 	mutex_lock(&hwmgr->smu_lock);
514 	hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
515 	mutex_unlock(&hwmgr->smu_lock);
516 }
517 
518 static uint32_t pp_dpm_get_fan_control_mode(void *handle)
519 {
520 	struct pp_hwmgr *hwmgr = handle;
521 	uint32_t mode = 0;
522 
523 	if (!hwmgr || !hwmgr->pm_en)
524 		return 0;
525 
526 	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
527 		pr_info_ratelimited("%s was not implemented.\n", __func__);
528 		return 0;
529 	}
530 	mutex_lock(&hwmgr->smu_lock);
531 	mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
532 	mutex_unlock(&hwmgr->smu_lock);
533 	return mode;
534 }
535 
536 static int pp_dpm_set_fan_speed_percent(void *handle, uint32_t percent)
537 {
538 	struct pp_hwmgr *hwmgr = handle;
539 	int ret = 0;
540 
541 	if (!hwmgr || !hwmgr->pm_en)
542 		return -EINVAL;
543 
544 	if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
545 		pr_info_ratelimited("%s was not implemented.\n", __func__);
546 		return 0;
547 	}
548 	mutex_lock(&hwmgr->smu_lock);
549 	ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
550 	mutex_unlock(&hwmgr->smu_lock);
551 	return ret;
552 }
553 
554 static int pp_dpm_get_fan_speed_percent(void *handle, uint32_t *speed)
555 {
556 	struct pp_hwmgr *hwmgr = handle;
557 	int ret = 0;
558 
559 	if (!hwmgr || !hwmgr->pm_en)
560 		return -EINVAL;
561 
562 	if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
563 		pr_info_ratelimited("%s was not implemented.\n", __func__);
564 		return 0;
565 	}
566 
567 	mutex_lock(&hwmgr->smu_lock);
568 	ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
569 	mutex_unlock(&hwmgr->smu_lock);
570 	return ret;
571 }
572 
573 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
574 {
575 	struct pp_hwmgr *hwmgr = handle;
576 	int ret = 0;
577 
578 	if (!hwmgr || !hwmgr->pm_en)
579 		return -EINVAL;
580 
581 	if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
582 		return -EINVAL;
583 
584 	mutex_lock(&hwmgr->smu_lock);
585 	ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
586 	mutex_unlock(&hwmgr->smu_lock);
587 	return ret;
588 }
589 
590 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
591 {
592 	struct pp_hwmgr *hwmgr = handle;
593 	int ret = 0;
594 
595 	if (!hwmgr || !hwmgr->pm_en)
596 		return -EINVAL;
597 
598 	if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
599 		pr_info_ratelimited("%s was not implemented.\n", __func__);
600 		return 0;
601 	}
602 	mutex_lock(&hwmgr->smu_lock);
603 	ret = hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
604 	mutex_unlock(&hwmgr->smu_lock);
605 	return ret;
606 }
607 
608 static int pp_dpm_get_pp_num_states(void *handle,
609 		struct pp_states_info *data)
610 {
611 	struct pp_hwmgr *hwmgr = handle;
612 	int i;
613 
614 	memset(data, 0, sizeof(*data));
615 
616 	if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
617 		return -EINVAL;
618 
619 	mutex_lock(&hwmgr->smu_lock);
620 
621 	data->nums = hwmgr->num_ps;
622 
623 	for (i = 0; i < hwmgr->num_ps; i++) {
624 		struct pp_power_state *state = (struct pp_power_state *)
625 				((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
626 		switch (state->classification.ui_label) {
627 		case PP_StateUILabel_Battery:
628 			data->states[i] = POWER_STATE_TYPE_BATTERY;
629 			break;
630 		case PP_StateUILabel_Balanced:
631 			data->states[i] = POWER_STATE_TYPE_BALANCED;
632 			break;
633 		case PP_StateUILabel_Performance:
634 			data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
635 			break;
636 		default:
637 			if (state->classification.flags & PP_StateClassificationFlag_Boot)
638 				data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
639 			else
640 				data->states[i] = POWER_STATE_TYPE_DEFAULT;
641 		}
642 	}
643 	mutex_unlock(&hwmgr->smu_lock);
644 	return 0;
645 }
646 
647 static int pp_dpm_get_pp_table(void *handle, char **table)
648 {
649 	struct pp_hwmgr *hwmgr = handle;
650 	int size = 0;
651 
652 	if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
653 		return -EINVAL;
654 
655 	mutex_lock(&hwmgr->smu_lock);
656 	*table = (char *)hwmgr->soft_pp_table;
657 	size = hwmgr->soft_pp_table_size;
658 	mutex_unlock(&hwmgr->smu_lock);
659 	return size;
660 }
661 
662 static int amd_powerplay_reset(void *handle)
663 {
664 	struct pp_hwmgr *hwmgr = handle;
665 	int ret;
666 
667 	ret = hwmgr_hw_fini(hwmgr);
668 	if (ret)
669 		return ret;
670 
671 	ret = hwmgr_hw_init(hwmgr);
672 	if (ret)
673 		return ret;
674 
675 	return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
676 }
677 
678 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
679 {
680 	struct pp_hwmgr *hwmgr = handle;
681 	int ret = -ENOMEM;
682 
683 	if (!hwmgr || !hwmgr->pm_en)
684 		return -EINVAL;
685 
686 	mutex_lock(&hwmgr->smu_lock);
687 	if (!hwmgr->hardcode_pp_table) {
688 		hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
689 						   hwmgr->soft_pp_table_size,
690 						   GFP_KERNEL);
691 		if (!hwmgr->hardcode_pp_table)
692 			goto err;
693 	}
694 
695 	memcpy(hwmgr->hardcode_pp_table, buf, size);
696 
697 	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
698 
699 	ret = amd_powerplay_reset(handle);
700 	if (ret)
701 		goto err;
702 
703 	if (hwmgr->hwmgr_func->avfs_control) {
704 		ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
705 		if (ret)
706 			goto err;
707 	}
708 	mutex_unlock(&hwmgr->smu_lock);
709 	return 0;
710 err:
711 	mutex_unlock(&hwmgr->smu_lock);
712 	return ret;
713 }
714 
715 static int pp_dpm_force_clock_level(void *handle,
716 		enum pp_clock_type type, uint32_t mask)
717 {
718 	struct pp_hwmgr *hwmgr = handle;
719 	int ret = 0;
720 
721 	if (!hwmgr || !hwmgr->pm_en)
722 		return -EINVAL;
723 
724 	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
725 		pr_info_ratelimited("%s was not implemented.\n", __func__);
726 		return 0;
727 	}
728 
729 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
730 		pr_debug("force clock level is for dpm manual mode only.\n");
731 		return -EINVAL;
732 	}
733 
734 	mutex_lock(&hwmgr->smu_lock);
735 	ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
736 	mutex_unlock(&hwmgr->smu_lock);
737 	return ret;
738 }
739 
740 static int pp_dpm_print_clock_levels(void *handle,
741 		enum pp_clock_type type, char *buf)
742 {
743 	struct pp_hwmgr *hwmgr = handle;
744 	int ret = 0;
745 
746 	if (!hwmgr || !hwmgr->pm_en)
747 		return -EINVAL;
748 
749 	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
750 		pr_info_ratelimited("%s was not implemented.\n", __func__);
751 		return 0;
752 	}
753 	mutex_lock(&hwmgr->smu_lock);
754 	ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
755 	mutex_unlock(&hwmgr->smu_lock);
756 	return ret;
757 }
758 
759 static int pp_dpm_get_sclk_od(void *handle)
760 {
761 	struct pp_hwmgr *hwmgr = handle;
762 	int ret = 0;
763 
764 	if (!hwmgr || !hwmgr->pm_en)
765 		return -EINVAL;
766 
767 	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
768 		pr_info_ratelimited("%s was not implemented.\n", __func__);
769 		return 0;
770 	}
771 	mutex_lock(&hwmgr->smu_lock);
772 	ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
773 	mutex_unlock(&hwmgr->smu_lock);
774 	return ret;
775 }
776 
777 static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
778 {
779 	struct pp_hwmgr *hwmgr = handle;
780 	int ret = 0;
781 
782 	if (!hwmgr || !hwmgr->pm_en)
783 		return -EINVAL;
784 
785 	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
786 		pr_info_ratelimited("%s was not implemented.\n", __func__);
787 		return 0;
788 	}
789 
790 	mutex_lock(&hwmgr->smu_lock);
791 	ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
792 	mutex_unlock(&hwmgr->smu_lock);
793 	return ret;
794 }
795 
796 static int pp_dpm_get_mclk_od(void *handle)
797 {
798 	struct pp_hwmgr *hwmgr = handle;
799 	int ret = 0;
800 
801 	if (!hwmgr || !hwmgr->pm_en)
802 		return -EINVAL;
803 
804 	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
805 		pr_info_ratelimited("%s was not implemented.\n", __func__);
806 		return 0;
807 	}
808 	mutex_lock(&hwmgr->smu_lock);
809 	ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
810 	mutex_unlock(&hwmgr->smu_lock);
811 	return ret;
812 }
813 
814 static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
815 {
816 	struct pp_hwmgr *hwmgr = handle;
817 	int ret = 0;
818 
819 	if (!hwmgr || !hwmgr->pm_en)
820 		return -EINVAL;
821 
822 	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
823 		pr_info_ratelimited("%s was not implemented.\n", __func__);
824 		return 0;
825 	}
826 	mutex_lock(&hwmgr->smu_lock);
827 	ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
828 	mutex_unlock(&hwmgr->smu_lock);
829 	return ret;
830 }
831 
832 static int pp_dpm_read_sensor(void *handle, int idx,
833 			      void *value, int *size)
834 {
835 	struct pp_hwmgr *hwmgr = handle;
836 	int ret = 0;
837 
838 	if (!hwmgr || !hwmgr->pm_en || !value)
839 		return -EINVAL;
840 
841 	switch (idx) {
842 	case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
843 		*((uint32_t *)value) = hwmgr->pstate_sclk;
844 		return 0;
845 	case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
846 		*((uint32_t *)value) = hwmgr->pstate_mclk;
847 		return 0;
848 	case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
849 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
850 		return 0;
851 	case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
852 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
853 		return 0;
854 	default:
855 		mutex_lock(&hwmgr->smu_lock);
856 		ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
857 		mutex_unlock(&hwmgr->smu_lock);
858 		return ret;
859 	}
860 }
861 
862 static struct amd_vce_state*
863 pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
864 {
865 	struct pp_hwmgr *hwmgr = handle;
866 
867 	if (!hwmgr || !hwmgr->pm_en)
868 		return NULL;
869 
870 	if (idx < hwmgr->num_vce_state_tables)
871 		return &hwmgr->vce_states[idx];
872 	return NULL;
873 }
874 
875 static int pp_get_power_profile_mode(void *handle, char *buf)
876 {
877 	struct pp_hwmgr *hwmgr = handle;
878 
879 	if (!hwmgr || !hwmgr->pm_en || !buf)
880 		return -EINVAL;
881 
882 	if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
883 		pr_info_ratelimited("%s was not implemented.\n", __func__);
884 		return snprintf(buf, PAGE_SIZE, "\n");
885 	}
886 
887 	return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
888 }
889 
890 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
891 {
892 	struct pp_hwmgr *hwmgr = handle;
893 	int ret = -EINVAL;
894 
895 	if (!hwmgr || !hwmgr->pm_en)
896 		return ret;
897 
898 	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
899 		pr_info_ratelimited("%s was not implemented.\n", __func__);
900 		return ret;
901 	}
902 
903 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
904 		pr_debug("power profile setting is for manual dpm mode only.\n");
905 		return ret;
906 	}
907 
908 	mutex_lock(&hwmgr->smu_lock);
909 	ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
910 	mutex_unlock(&hwmgr->smu_lock);
911 	return ret;
912 }
913 
914 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size)
915 {
916 	struct pp_hwmgr *hwmgr = handle;
917 
918 	if (!hwmgr || !hwmgr->pm_en)
919 		return -EINVAL;
920 
921 	if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL)
922 		return 0;
923 
924 	return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size);
925 }
926 
927 static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
928 {
929 	struct pp_hwmgr *hwmgr = handle;
930 
931 	if (!hwmgr || !hwmgr->pm_en)
932 		return -EINVAL;
933 
934 	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
935 		pr_info_ratelimited("%s was not implemented.\n", __func__);
936 		return 0;
937 	}
938 
939 	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
940 }
941 
942 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
943 {
944 	struct pp_hwmgr *hwmgr = handle;
945 
946 	if (!hwmgr)
947 		return -EINVAL;
948 
949 	if (!hwmgr->pm_en)
950 		return 0;
951 
952 	if (hwmgr->hwmgr_func->set_mp1_state)
953 		return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
954 
955 	return 0;
956 }
957 
958 static int pp_dpm_switch_power_profile(void *handle,
959 		enum PP_SMC_POWER_PROFILE type, bool en)
960 {
961 	struct pp_hwmgr *hwmgr = handle;
962 	long workload;
963 	uint32_t index;
964 
965 	if (!hwmgr || !hwmgr->pm_en)
966 		return -EINVAL;
967 
968 	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
969 		pr_info_ratelimited("%s was not implemented.\n", __func__);
970 		return -EINVAL;
971 	}
972 
973 	if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
974 		return -EINVAL;
975 
976 	mutex_lock(&hwmgr->smu_lock);
977 
978 	if (!en) {
979 		hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
980 		index = fls(hwmgr->workload_mask);
981 		index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
982 		workload = hwmgr->workload_setting[index];
983 	} else {
984 		hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
985 		index = fls(hwmgr->workload_mask);
986 		index = index <= Workload_Policy_Max ? index - 1 : 0;
987 		workload = hwmgr->workload_setting[index];
988 	}
989 
990 	if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
991 		hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
992 			if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) {
993 				mutex_unlock(&hwmgr->smu_lock);
994 				return -EINVAL;
995 			}
996 	}
997 
998 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
999 		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
1000 	mutex_unlock(&hwmgr->smu_lock);
1001 
1002 	return 0;
1003 }
1004 
1005 static int pp_set_power_limit(void *handle, uint32_t limit)
1006 {
1007 	struct pp_hwmgr *hwmgr = handle;
1008 	uint32_t max_power_limit;
1009 
1010 	if (!hwmgr || !hwmgr->pm_en)
1011 		return -EINVAL;
1012 
1013 	if (hwmgr->hwmgr_func->set_power_limit == NULL) {
1014 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1015 		return -EINVAL;
1016 	}
1017 
1018 	if (limit == 0)
1019 		limit = hwmgr->default_power_limit;
1020 
1021 	max_power_limit = hwmgr->default_power_limit;
1022 	if (hwmgr->od_enabled) {
1023 		max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1024 		max_power_limit /= 100;
1025 	}
1026 
1027 	if (limit > max_power_limit)
1028 		return -EINVAL;
1029 
1030 	mutex_lock(&hwmgr->smu_lock);
1031 	hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
1032 	hwmgr->power_limit = limit;
1033 	mutex_unlock(&hwmgr->smu_lock);
1034 	return 0;
1035 }
1036 
1037 static int pp_get_power_limit(void *handle, uint32_t *limit, bool default_limit)
1038 {
1039 	struct pp_hwmgr *hwmgr = handle;
1040 
1041 	if (!hwmgr || !hwmgr->pm_en ||!limit)
1042 		return -EINVAL;
1043 
1044 	mutex_lock(&hwmgr->smu_lock);
1045 
1046 	if (default_limit) {
1047 		*limit = hwmgr->default_power_limit;
1048 		if (hwmgr->od_enabled) {
1049 			*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1050 			*limit /= 100;
1051 		}
1052 	}
1053 	else
1054 		*limit = hwmgr->power_limit;
1055 
1056 	mutex_unlock(&hwmgr->smu_lock);
1057 
1058 	return 0;
1059 }
1060 
1061 static int pp_display_configuration_change(void *handle,
1062 	const struct amd_pp_display_configuration *display_config)
1063 {
1064 	struct pp_hwmgr *hwmgr = handle;
1065 
1066 	if (!hwmgr || !hwmgr->pm_en)
1067 		return -EINVAL;
1068 
1069 	mutex_lock(&hwmgr->smu_lock);
1070 	phm_store_dal_configuration_data(hwmgr, display_config);
1071 	mutex_unlock(&hwmgr->smu_lock);
1072 	return 0;
1073 }
1074 
1075 static int pp_get_display_power_level(void *handle,
1076 		struct amd_pp_simple_clock_info *output)
1077 {
1078 	struct pp_hwmgr *hwmgr = handle;
1079 	int ret = 0;
1080 
1081 	if (!hwmgr || !hwmgr->pm_en ||!output)
1082 		return -EINVAL;
1083 
1084 	mutex_lock(&hwmgr->smu_lock);
1085 	ret = phm_get_dal_power_level(hwmgr, output);
1086 	mutex_unlock(&hwmgr->smu_lock);
1087 	return ret;
1088 }
1089 
1090 static int pp_get_current_clocks(void *handle,
1091 		struct amd_pp_clock_info *clocks)
1092 {
1093 	struct amd_pp_simple_clock_info simple_clocks = { 0 };
1094 	struct pp_clock_info hw_clocks;
1095 	struct pp_hwmgr *hwmgr = handle;
1096 	int ret = 0;
1097 
1098 	if (!hwmgr || !hwmgr->pm_en)
1099 		return -EINVAL;
1100 
1101 	mutex_lock(&hwmgr->smu_lock);
1102 
1103 	phm_get_dal_power_level(hwmgr, &simple_clocks);
1104 
1105 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1106 					PHM_PlatformCaps_PowerContainment))
1107 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1108 					&hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1109 	else
1110 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1111 					&hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1112 
1113 	if (ret) {
1114 		pr_debug("Error in phm_get_clock_info \n");
1115 		mutex_unlock(&hwmgr->smu_lock);
1116 		return -EINVAL;
1117 	}
1118 
1119 	clocks->min_engine_clock = hw_clocks.min_eng_clk;
1120 	clocks->max_engine_clock = hw_clocks.max_eng_clk;
1121 	clocks->min_memory_clock = hw_clocks.min_mem_clk;
1122 	clocks->max_memory_clock = hw_clocks.max_mem_clk;
1123 	clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1124 	clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1125 
1126 	clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1127 	clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1128 
1129 	if (simple_clocks.level == 0)
1130 		clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1131 	else
1132 		clocks->max_clocks_state = simple_clocks.level;
1133 
1134 	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1135 		clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1136 		clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1137 	}
1138 	mutex_unlock(&hwmgr->smu_lock);
1139 	return 0;
1140 }
1141 
1142 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1143 {
1144 	struct pp_hwmgr *hwmgr = handle;
1145 	int ret = 0;
1146 
1147 	if (!hwmgr || !hwmgr->pm_en)
1148 		return -EINVAL;
1149 
1150 	if (clocks == NULL)
1151 		return -EINVAL;
1152 
1153 	mutex_lock(&hwmgr->smu_lock);
1154 	ret = phm_get_clock_by_type(hwmgr, type, clocks);
1155 	mutex_unlock(&hwmgr->smu_lock);
1156 	return ret;
1157 }
1158 
1159 static int pp_get_clock_by_type_with_latency(void *handle,
1160 		enum amd_pp_clock_type type,
1161 		struct pp_clock_levels_with_latency *clocks)
1162 {
1163 	struct pp_hwmgr *hwmgr = handle;
1164 	int ret = 0;
1165 
1166 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
1167 		return -EINVAL;
1168 
1169 	mutex_lock(&hwmgr->smu_lock);
1170 	ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1171 	mutex_unlock(&hwmgr->smu_lock);
1172 	return ret;
1173 }
1174 
1175 static int pp_get_clock_by_type_with_voltage(void *handle,
1176 		enum amd_pp_clock_type type,
1177 		struct pp_clock_levels_with_voltage *clocks)
1178 {
1179 	struct pp_hwmgr *hwmgr = handle;
1180 	int ret = 0;
1181 
1182 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
1183 		return -EINVAL;
1184 
1185 	mutex_lock(&hwmgr->smu_lock);
1186 
1187 	ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1188 
1189 	mutex_unlock(&hwmgr->smu_lock);
1190 	return ret;
1191 }
1192 
1193 static int pp_set_watermarks_for_clocks_ranges(void *handle,
1194 		void *clock_ranges)
1195 {
1196 	struct pp_hwmgr *hwmgr = handle;
1197 	int ret = 0;
1198 
1199 	if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
1200 		return -EINVAL;
1201 
1202 	mutex_lock(&hwmgr->smu_lock);
1203 	ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
1204 			clock_ranges);
1205 	mutex_unlock(&hwmgr->smu_lock);
1206 
1207 	return ret;
1208 }
1209 
1210 static int pp_display_clock_voltage_request(void *handle,
1211 		struct pp_display_clock_request *clock)
1212 {
1213 	struct pp_hwmgr *hwmgr = handle;
1214 	int ret = 0;
1215 
1216 	if (!hwmgr || !hwmgr->pm_en ||!clock)
1217 		return -EINVAL;
1218 
1219 	mutex_lock(&hwmgr->smu_lock);
1220 	ret = phm_display_clock_voltage_request(hwmgr, clock);
1221 	mutex_unlock(&hwmgr->smu_lock);
1222 
1223 	return ret;
1224 }
1225 
1226 static int pp_get_display_mode_validation_clocks(void *handle,
1227 		struct amd_pp_simple_clock_info *clocks)
1228 {
1229 	struct pp_hwmgr *hwmgr = handle;
1230 	int ret = 0;
1231 
1232 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
1233 		return -EINVAL;
1234 
1235 	clocks->level = PP_DAL_POWERLEVEL_7;
1236 
1237 	mutex_lock(&hwmgr->smu_lock);
1238 
1239 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1240 		ret = phm_get_max_high_clocks(hwmgr, clocks);
1241 
1242 	mutex_unlock(&hwmgr->smu_lock);
1243 	return ret;
1244 }
1245 
1246 static int pp_dpm_powergate_mmhub(void *handle)
1247 {
1248 	struct pp_hwmgr *hwmgr = handle;
1249 
1250 	if (!hwmgr || !hwmgr->pm_en)
1251 		return -EINVAL;
1252 
1253 	if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
1254 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1255 		return 0;
1256 	}
1257 
1258 	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
1259 }
1260 
1261 static int pp_dpm_powergate_gfx(void *handle, bool gate)
1262 {
1263 	struct pp_hwmgr *hwmgr = handle;
1264 
1265 	if (!hwmgr || !hwmgr->pm_en)
1266 		return 0;
1267 
1268 	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
1269 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1270 		return 0;
1271 	}
1272 
1273 	return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
1274 }
1275 
1276 static void pp_dpm_powergate_acp(void *handle, bool gate)
1277 {
1278 	struct pp_hwmgr *hwmgr = handle;
1279 
1280 	if (!hwmgr || !hwmgr->pm_en)
1281 		return;
1282 
1283 	if (hwmgr->hwmgr_func->powergate_acp == NULL) {
1284 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1285 		return;
1286 	}
1287 
1288 	hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
1289 }
1290 
1291 static void pp_dpm_powergate_sdma(void *handle, bool gate)
1292 {
1293 	struct pp_hwmgr *hwmgr = handle;
1294 
1295 	if (!hwmgr)
1296 		return;
1297 
1298 	if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
1299 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1300 		return;
1301 	}
1302 
1303 	hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
1304 }
1305 
1306 static int pp_set_powergating_by_smu(void *handle,
1307 				uint32_t block_type, bool gate)
1308 {
1309 	int ret = 0;
1310 
1311 	switch (block_type) {
1312 	case AMD_IP_BLOCK_TYPE_UVD:
1313 	case AMD_IP_BLOCK_TYPE_VCN:
1314 		pp_dpm_powergate_uvd(handle, gate);
1315 		break;
1316 	case AMD_IP_BLOCK_TYPE_VCE:
1317 		pp_dpm_powergate_vce(handle, gate);
1318 		break;
1319 	case AMD_IP_BLOCK_TYPE_GMC:
1320 		pp_dpm_powergate_mmhub(handle);
1321 		break;
1322 	case AMD_IP_BLOCK_TYPE_GFX:
1323 		ret = pp_dpm_powergate_gfx(handle, gate);
1324 		break;
1325 	case AMD_IP_BLOCK_TYPE_ACP:
1326 		pp_dpm_powergate_acp(handle, gate);
1327 		break;
1328 	case AMD_IP_BLOCK_TYPE_SDMA:
1329 		pp_dpm_powergate_sdma(handle, gate);
1330 		break;
1331 	default:
1332 		break;
1333 	}
1334 	return ret;
1335 }
1336 
1337 static int pp_notify_smu_enable_pwe(void *handle)
1338 {
1339 	struct pp_hwmgr *hwmgr = handle;
1340 
1341 	if (!hwmgr || !hwmgr->pm_en)
1342 		return -EINVAL;
1343 
1344 	if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
1345 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1346 		return -EINVAL;
1347 	}
1348 
1349 	mutex_lock(&hwmgr->smu_lock);
1350 	hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
1351 	mutex_unlock(&hwmgr->smu_lock);
1352 
1353 	return 0;
1354 }
1355 
1356 static int pp_enable_mgpu_fan_boost(void *handle)
1357 {
1358 	struct pp_hwmgr *hwmgr = handle;
1359 
1360 	if (!hwmgr)
1361 		return -EINVAL;
1362 
1363 	if (!hwmgr->pm_en ||
1364 	     hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
1365 		return 0;
1366 
1367 	mutex_lock(&hwmgr->smu_lock);
1368 	hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
1369 	mutex_unlock(&hwmgr->smu_lock);
1370 
1371 	return 0;
1372 }
1373 
1374 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
1375 {
1376 	struct pp_hwmgr *hwmgr = handle;
1377 
1378 	if (!hwmgr || !hwmgr->pm_en)
1379 		return -EINVAL;
1380 
1381 	if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
1382 		pr_debug("%s was not implemented.\n", __func__);
1383 		return -EINVAL;
1384 	}
1385 
1386 	mutex_lock(&hwmgr->smu_lock);
1387 	hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
1388 	mutex_unlock(&hwmgr->smu_lock);
1389 
1390 	return 0;
1391 }
1392 
1393 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)
1394 {
1395 	struct pp_hwmgr *hwmgr = handle;
1396 
1397 	if (!hwmgr || !hwmgr->pm_en)
1398 		return -EINVAL;
1399 
1400 	if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
1401 		pr_debug("%s was not implemented.\n", __func__);
1402 		return -EINVAL;
1403 	}
1404 
1405 	mutex_lock(&hwmgr->smu_lock);
1406 	hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
1407 	mutex_unlock(&hwmgr->smu_lock);
1408 
1409 	return 0;
1410 }
1411 
1412 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)
1413 {
1414 	struct pp_hwmgr *hwmgr = handle;
1415 
1416 	if (!hwmgr || !hwmgr->pm_en)
1417 		return -EINVAL;
1418 
1419 	if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
1420 		pr_debug("%s was not implemented.\n", __func__);
1421 		return -EINVAL;
1422 	}
1423 
1424 	mutex_lock(&hwmgr->smu_lock);
1425 	hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
1426 	mutex_unlock(&hwmgr->smu_lock);
1427 
1428 	return 0;
1429 }
1430 
1431 static int pp_set_active_display_count(void *handle, uint32_t count)
1432 {
1433 	struct pp_hwmgr *hwmgr = handle;
1434 	int ret = 0;
1435 
1436 	if (!hwmgr || !hwmgr->pm_en)
1437 		return -EINVAL;
1438 
1439 	mutex_lock(&hwmgr->smu_lock);
1440 	ret = phm_set_active_display_count(hwmgr, count);
1441 	mutex_unlock(&hwmgr->smu_lock);
1442 
1443 	return ret;
1444 }
1445 
1446 static int pp_get_asic_baco_capability(void *handle, bool *cap)
1447 {
1448 	struct pp_hwmgr *hwmgr = handle;
1449 
1450 	*cap = false;
1451 	if (!hwmgr)
1452 		return -EINVAL;
1453 
1454 	if (!(hwmgr->not_vf && amdgpu_dpm) ||
1455 		!hwmgr->hwmgr_func->get_asic_baco_capability)
1456 		return 0;
1457 
1458 	mutex_lock(&hwmgr->smu_lock);
1459 	hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
1460 	mutex_unlock(&hwmgr->smu_lock);
1461 
1462 	return 0;
1463 }
1464 
1465 static int pp_get_asic_baco_state(void *handle, int *state)
1466 {
1467 	struct pp_hwmgr *hwmgr = handle;
1468 
1469 	if (!hwmgr)
1470 		return -EINVAL;
1471 
1472 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1473 		return 0;
1474 
1475 	mutex_lock(&hwmgr->smu_lock);
1476 	hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
1477 	mutex_unlock(&hwmgr->smu_lock);
1478 
1479 	return 0;
1480 }
1481 
1482 static int pp_set_asic_baco_state(void *handle, int state)
1483 {
1484 	struct pp_hwmgr *hwmgr = handle;
1485 
1486 	if (!hwmgr)
1487 		return -EINVAL;
1488 
1489 	if (!(hwmgr->not_vf && amdgpu_dpm) ||
1490 		!hwmgr->hwmgr_func->set_asic_baco_state)
1491 		return 0;
1492 
1493 	mutex_lock(&hwmgr->smu_lock);
1494 	hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
1495 	mutex_unlock(&hwmgr->smu_lock);
1496 
1497 	return 0;
1498 }
1499 
1500 static int pp_get_ppfeature_status(void *handle, char *buf)
1501 {
1502 	struct pp_hwmgr *hwmgr = handle;
1503 	int ret = 0;
1504 
1505 	if (!hwmgr || !hwmgr->pm_en || !buf)
1506 		return -EINVAL;
1507 
1508 	if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
1509 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1510 		return -EINVAL;
1511 	}
1512 
1513 	mutex_lock(&hwmgr->smu_lock);
1514 	ret = hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
1515 	mutex_unlock(&hwmgr->smu_lock);
1516 
1517 	return ret;
1518 }
1519 
1520 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
1521 {
1522 	struct pp_hwmgr *hwmgr = handle;
1523 	int ret = 0;
1524 
1525 	if (!hwmgr || !hwmgr->pm_en)
1526 		return -EINVAL;
1527 
1528 	if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
1529 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1530 		return -EINVAL;
1531 	}
1532 
1533 	mutex_lock(&hwmgr->smu_lock);
1534 	ret = hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
1535 	mutex_unlock(&hwmgr->smu_lock);
1536 
1537 	return ret;
1538 }
1539 
1540 static int pp_asic_reset_mode_2(void *handle)
1541 {
1542 	struct pp_hwmgr *hwmgr = handle;
1543 		int ret = 0;
1544 
1545 	if (!hwmgr || !hwmgr->pm_en)
1546 		return -EINVAL;
1547 
1548 	if (hwmgr->hwmgr_func->asic_reset == NULL) {
1549 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1550 		return -EINVAL;
1551 	}
1552 
1553 	mutex_lock(&hwmgr->smu_lock);
1554 	ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
1555 	mutex_unlock(&hwmgr->smu_lock);
1556 
1557 	return ret;
1558 }
1559 
1560 static int pp_smu_i2c_bus_access(void *handle, bool acquire)
1561 {
1562 	struct pp_hwmgr *hwmgr = handle;
1563 	int ret = 0;
1564 
1565 	if (!hwmgr || !hwmgr->pm_en)
1566 		return -EINVAL;
1567 
1568 	if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
1569 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1570 		return -EINVAL;
1571 	}
1572 
1573 	mutex_lock(&hwmgr->smu_lock);
1574 	ret = hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
1575 	mutex_unlock(&hwmgr->smu_lock);
1576 
1577 	return ret;
1578 }
1579 
1580 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
1581 {
1582 	struct pp_hwmgr *hwmgr = handle;
1583 
1584 	if (!hwmgr)
1585 		return -EINVAL;
1586 
1587 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
1588 		return 0;
1589 
1590 	mutex_lock(&hwmgr->smu_lock);
1591 	hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
1592 	mutex_unlock(&hwmgr->smu_lock);
1593 
1594 	return 0;
1595 }
1596 
1597 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
1598 {
1599 	struct pp_hwmgr *hwmgr = handle;
1600 
1601 	if (!hwmgr)
1602 		return -EINVAL;
1603 
1604 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
1605 		return 0;
1606 
1607 	mutex_lock(&hwmgr->smu_lock);
1608 	hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
1609 	mutex_unlock(&hwmgr->smu_lock);
1610 
1611 	return 0;
1612 }
1613 
1614 static ssize_t pp_get_gpu_metrics(void *handle, void **table)
1615 {
1616 	struct pp_hwmgr *hwmgr = handle;
1617 	ssize_t size;
1618 
1619 	if (!hwmgr)
1620 		return -EINVAL;
1621 
1622 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics)
1623 		return -EOPNOTSUPP;
1624 
1625 	mutex_lock(&hwmgr->smu_lock);
1626 	size = hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table);
1627 	mutex_unlock(&hwmgr->smu_lock);
1628 
1629 	return size;
1630 }
1631 
1632 static int pp_gfx_state_change_set(void *handle, uint32_t state)
1633 {
1634 	struct pp_hwmgr *hwmgr = handle;
1635 
1636 	if (!hwmgr || !hwmgr->pm_en)
1637 		return -EINVAL;
1638 
1639 	if (hwmgr->hwmgr_func->gfx_state_change == NULL) {
1640 		pr_info_ratelimited("%s was not implemented.\n", __func__);
1641 		return -EINVAL;
1642 	}
1643 
1644 	mutex_lock(&hwmgr->smu_lock);
1645 	hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
1646 	mutex_unlock(&hwmgr->smu_lock);
1647 	return 0;
1648 }
1649 
1650 static const struct amd_pm_funcs pp_dpm_funcs = {
1651 	.load_firmware = pp_dpm_load_fw,
1652 	.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1653 	.force_performance_level = pp_dpm_force_performance_level,
1654 	.get_performance_level = pp_dpm_get_performance_level,
1655 	.get_current_power_state = pp_dpm_get_current_power_state,
1656 	.dispatch_tasks = pp_dpm_dispatch_tasks,
1657 	.set_fan_control_mode = pp_dpm_set_fan_control_mode,
1658 	.get_fan_control_mode = pp_dpm_get_fan_control_mode,
1659 	.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
1660 	.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
1661 	.get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1662 	.set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm,
1663 	.get_pp_num_states = pp_dpm_get_pp_num_states,
1664 	.get_pp_table = pp_dpm_get_pp_table,
1665 	.set_pp_table = pp_dpm_set_pp_table,
1666 	.force_clock_level = pp_dpm_force_clock_level,
1667 	.print_clock_levels = pp_dpm_print_clock_levels,
1668 	.get_sclk_od = pp_dpm_get_sclk_od,
1669 	.set_sclk_od = pp_dpm_set_sclk_od,
1670 	.get_mclk_od = pp_dpm_get_mclk_od,
1671 	.set_mclk_od = pp_dpm_set_mclk_od,
1672 	.read_sensor = pp_dpm_read_sensor,
1673 	.get_vce_clock_state = pp_dpm_get_vce_clock_state,
1674 	.switch_power_profile = pp_dpm_switch_power_profile,
1675 	.set_clockgating_by_smu = pp_set_clockgating_by_smu,
1676 	.set_powergating_by_smu = pp_set_powergating_by_smu,
1677 	.get_power_profile_mode = pp_get_power_profile_mode,
1678 	.set_power_profile_mode = pp_set_power_profile_mode,
1679 	.set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol,
1680 	.odn_edit_dpm_table = pp_odn_edit_dpm_table,
1681 	.set_mp1_state = pp_dpm_set_mp1_state,
1682 	.set_power_limit = pp_set_power_limit,
1683 	.get_power_limit = pp_get_power_limit,
1684 /* export to DC */
1685 	.get_sclk = pp_dpm_get_sclk,
1686 	.get_mclk = pp_dpm_get_mclk,
1687 	.display_configuration_change = pp_display_configuration_change,
1688 	.get_display_power_level = pp_get_display_power_level,
1689 	.get_current_clocks = pp_get_current_clocks,
1690 	.get_clock_by_type = pp_get_clock_by_type,
1691 	.get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
1692 	.get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
1693 	.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
1694 	.display_clock_voltage_request = pp_display_clock_voltage_request,
1695 	.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
1696 	.notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
1697 	.enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
1698 	.set_active_display_count = pp_set_active_display_count,
1699 	.set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
1700 	.set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
1701 	.set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
1702 	.get_asic_baco_capability = pp_get_asic_baco_capability,
1703 	.get_asic_baco_state = pp_get_asic_baco_state,
1704 	.set_asic_baco_state = pp_set_asic_baco_state,
1705 	.get_ppfeature_status = pp_get_ppfeature_status,
1706 	.set_ppfeature_status = pp_set_ppfeature_status,
1707 	.asic_reset_mode_2 = pp_asic_reset_mode_2,
1708 	.smu_i2c_bus_access = pp_smu_i2c_bus_access,
1709 	.set_df_cstate = pp_set_df_cstate,
1710 	.set_xgmi_pstate = pp_set_xgmi_pstate,
1711 	.get_gpu_metrics = pp_get_gpu_metrics,
1712 	.gfx_state_change_set = pp_gfx_state_change_set,
1713 };
1714