1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/gfp.h> 27 #include <linux/slab.h> 28 #include <linux/firmware.h> 29 #include "amd_shared.h" 30 #include "amd_powerplay.h" 31 #include "power_state.h" 32 #include "amdgpu.h" 33 #include "hwmgr.h" 34 #include "amdgpu_dpm_internal.h" 35 #include "amdgpu_display.h" 36 37 static const struct amd_pm_funcs pp_dpm_funcs; 38 39 static int amd_powerplay_create(struct amdgpu_device *adev) 40 { 41 struct pp_hwmgr *hwmgr; 42 43 if (adev == NULL) 44 return -EINVAL; 45 46 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL); 47 if (hwmgr == NULL) 48 return -ENOMEM; 49 50 hwmgr->adev = adev; 51 hwmgr->not_vf = !amdgpu_sriov_vf(adev); 52 hwmgr->device = amdgpu_cgs_create_device(adev); 53 mutex_init(&hwmgr->msg_lock); 54 hwmgr->chip_family = adev->family; 55 hwmgr->chip_id = adev->asic_type; 56 hwmgr->feature_mask = adev->pm.pp_feature; 57 hwmgr->display_config = &adev->pm.pm_display_cfg; 58 adev->powerplay.pp_handle = hwmgr; 59 adev->powerplay.pp_funcs = &pp_dpm_funcs; 60 return 0; 61 } 62 63 64 static void amd_powerplay_destroy(struct amdgpu_device *adev) 65 { 66 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 67 68 mutex_destroy(&hwmgr->msg_lock); 69 70 kfree(hwmgr->hardcode_pp_table); 71 hwmgr->hardcode_pp_table = NULL; 72 73 kfree(hwmgr); 74 hwmgr = NULL; 75 } 76 77 static int pp_early_init(void *handle) 78 { 79 int ret; 80 struct amdgpu_device *adev = handle; 81 82 ret = amd_powerplay_create(adev); 83 84 if (ret != 0) 85 return ret; 86 87 ret = hwmgr_early_init(adev->powerplay.pp_handle); 88 if (ret) 89 return -EINVAL; 90 91 return 0; 92 } 93 94 static int pp_sw_init(void *handle) 95 { 96 struct amdgpu_device *adev = handle; 97 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 98 int ret = 0; 99 100 ret = hwmgr_sw_init(hwmgr); 101 102 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully"); 103 104 return ret; 105 } 106 107 static int pp_sw_fini(void *handle) 108 { 109 struct amdgpu_device *adev = handle; 110 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 111 112 hwmgr_sw_fini(hwmgr); 113 114 release_firmware(adev->pm.fw); 115 adev->pm.fw = NULL; 116 117 return 0; 118 } 119 120 static int pp_hw_init(void *handle) 121 { 122 int ret = 0; 123 struct amdgpu_device *adev = handle; 124 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 125 126 ret = hwmgr_hw_init(hwmgr); 127 128 if (ret) 129 pr_err("powerplay hw init failed\n"); 130 131 return ret; 132 } 133 134 static int pp_hw_fini(void *handle) 135 { 136 struct amdgpu_device *adev = handle; 137 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 138 139 hwmgr_hw_fini(hwmgr); 140 141 return 0; 142 } 143 144 static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) 145 { 146 int r = -EINVAL; 147 void *cpu_ptr = NULL; 148 uint64_t gpu_addr; 149 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 150 151 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size, 152 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 153 &adev->pm.smu_prv_buffer, 154 &gpu_addr, 155 &cpu_ptr)) { 156 DRM_ERROR("amdgpu: failed to create smu prv buffer\n"); 157 return; 158 } 159 160 if (hwmgr->hwmgr_func->notify_cac_buffer_info) 161 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr, 162 lower_32_bits((unsigned long)cpu_ptr), 163 upper_32_bits((unsigned long)cpu_ptr), 164 lower_32_bits(gpu_addr), 165 upper_32_bits(gpu_addr), 166 adev->pm.smu_prv_buffer_size); 167 168 if (r) { 169 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 170 adev->pm.smu_prv_buffer = NULL; 171 DRM_ERROR("amdgpu: failed to notify SMU buffer address\n"); 172 } 173 } 174 175 static int pp_late_init(void *handle) 176 { 177 struct amdgpu_device *adev = handle; 178 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 179 180 if (hwmgr && hwmgr->pm_en) 181 hwmgr_handle_task(hwmgr, 182 AMD_PP_TASK_COMPLETE_INIT, NULL); 183 if (adev->pm.smu_prv_buffer_size != 0) 184 pp_reserve_vram_for_smu(adev); 185 186 return 0; 187 } 188 189 static void pp_late_fini(void *handle) 190 { 191 struct amdgpu_device *adev = handle; 192 193 if (adev->pm.smu_prv_buffer) 194 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); 195 amd_powerplay_destroy(adev); 196 } 197 198 199 static bool pp_is_idle(void *handle) 200 { 201 return false; 202 } 203 204 static int pp_wait_for_idle(void *handle) 205 { 206 return 0; 207 } 208 209 static int pp_sw_reset(void *handle) 210 { 211 return 0; 212 } 213 214 static int pp_set_powergating_state(void *handle, 215 enum amd_powergating_state state) 216 { 217 return 0; 218 } 219 220 static int pp_suspend(void *handle) 221 { 222 struct amdgpu_device *adev = handle; 223 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 224 225 return hwmgr_suspend(hwmgr); 226 } 227 228 static int pp_resume(void *handle) 229 { 230 struct amdgpu_device *adev = handle; 231 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; 232 233 return hwmgr_resume(hwmgr); 234 } 235 236 static int pp_set_clockgating_state(void *handle, 237 enum amd_clockgating_state state) 238 { 239 return 0; 240 } 241 242 static const struct amd_ip_funcs pp_ip_funcs = { 243 .name = "powerplay", 244 .early_init = pp_early_init, 245 .late_init = pp_late_init, 246 .sw_init = pp_sw_init, 247 .sw_fini = pp_sw_fini, 248 .hw_init = pp_hw_init, 249 .hw_fini = pp_hw_fini, 250 .late_fini = pp_late_fini, 251 .suspend = pp_suspend, 252 .resume = pp_resume, 253 .is_idle = pp_is_idle, 254 .wait_for_idle = pp_wait_for_idle, 255 .soft_reset = pp_sw_reset, 256 .set_clockgating_state = pp_set_clockgating_state, 257 .set_powergating_state = pp_set_powergating_state, 258 }; 259 260 const struct amdgpu_ip_block_version pp_smu_ip_block = 261 { 262 .type = AMD_IP_BLOCK_TYPE_SMC, 263 .major = 1, 264 .minor = 0, 265 .rev = 0, 266 .funcs = &pp_ip_funcs, 267 }; 268 269 /* This interface only be supported On Vi, 270 * because only smu7/8 can help to load gfx/sdma fw, 271 * smu need to be enabled before load other ip's fw. 272 * so call start smu to load smu7 fw and other ip's fw 273 */ 274 static int pp_dpm_load_fw(void *handle) 275 { 276 struct pp_hwmgr *hwmgr = handle; 277 278 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu) 279 return -EINVAL; 280 281 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) { 282 pr_err("fw load failed\n"); 283 return -EINVAL; 284 } 285 286 return 0; 287 } 288 289 static int pp_dpm_fw_loading_complete(void *handle) 290 { 291 return 0; 292 } 293 294 static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) 295 { 296 struct pp_hwmgr *hwmgr = handle; 297 298 if (!hwmgr || !hwmgr->pm_en) 299 return -EINVAL; 300 301 if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { 302 pr_info_ratelimited("%s was not implemented.\n", __func__); 303 return 0; 304 } 305 306 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id); 307 } 308 309 static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, 310 enum amd_dpm_forced_level *level) 311 { 312 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD | 313 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK | 314 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK | 315 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 316 317 if (!(hwmgr->dpm_level & profile_mode_mask)) { 318 /* enter umd pstate, save current level, disable gfx cg*/ 319 if (*level & profile_mode_mask) { 320 hwmgr->saved_dpm_level = hwmgr->dpm_level; 321 hwmgr->en_umd_pstate = true; 322 } 323 } else { 324 /* exit umd pstate, restore level, enable gfx cg*/ 325 if (!(*level & profile_mode_mask)) { 326 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT) 327 *level = hwmgr->saved_dpm_level; 328 hwmgr->en_umd_pstate = false; 329 } 330 } 331 } 332 333 static int pp_dpm_force_performance_level(void *handle, 334 enum amd_dpm_forced_level level) 335 { 336 struct pp_hwmgr *hwmgr = handle; 337 338 if (!hwmgr || !hwmgr->pm_en) 339 return -EINVAL; 340 341 if (level == hwmgr->dpm_level) 342 return 0; 343 344 pp_dpm_en_umd_pstate(hwmgr, &level); 345 hwmgr->request_dpm_level = level; 346 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 347 348 return 0; 349 } 350 351 static enum amd_dpm_forced_level pp_dpm_get_performance_level( 352 void *handle) 353 { 354 struct pp_hwmgr *hwmgr = handle; 355 356 if (!hwmgr || !hwmgr->pm_en) 357 return -EINVAL; 358 359 return hwmgr->dpm_level; 360 } 361 362 static uint32_t pp_dpm_get_sclk(void *handle, bool low) 363 { 364 struct pp_hwmgr *hwmgr = handle; 365 366 if (!hwmgr || !hwmgr->pm_en) 367 return 0; 368 369 if (hwmgr->hwmgr_func->get_sclk == NULL) { 370 pr_info_ratelimited("%s was not implemented.\n", __func__); 371 return 0; 372 } 373 return hwmgr->hwmgr_func->get_sclk(hwmgr, low); 374 } 375 376 static uint32_t pp_dpm_get_mclk(void *handle, bool low) 377 { 378 struct pp_hwmgr *hwmgr = handle; 379 380 if (!hwmgr || !hwmgr->pm_en) 381 return 0; 382 383 if (hwmgr->hwmgr_func->get_mclk == NULL) { 384 pr_info_ratelimited("%s was not implemented.\n", __func__); 385 return 0; 386 } 387 return hwmgr->hwmgr_func->get_mclk(hwmgr, low); 388 } 389 390 static void pp_dpm_powergate_vce(void *handle, bool gate) 391 { 392 struct pp_hwmgr *hwmgr = handle; 393 394 if (!hwmgr || !hwmgr->pm_en) 395 return; 396 397 if (hwmgr->hwmgr_func->powergate_vce == NULL) { 398 pr_info_ratelimited("%s was not implemented.\n", __func__); 399 return; 400 } 401 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); 402 } 403 404 static void pp_dpm_powergate_uvd(void *handle, bool gate) 405 { 406 struct pp_hwmgr *hwmgr = handle; 407 408 if (!hwmgr || !hwmgr->pm_en) 409 return; 410 411 if (hwmgr->hwmgr_func->powergate_uvd == NULL) { 412 pr_info_ratelimited("%s was not implemented.\n", __func__); 413 return; 414 } 415 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); 416 } 417 418 static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id, 419 enum amd_pm_state_type *user_state) 420 { 421 struct pp_hwmgr *hwmgr = handle; 422 423 if (!hwmgr || !hwmgr->pm_en) 424 return -EINVAL; 425 426 return hwmgr_handle_task(hwmgr, task_id, user_state); 427 } 428 429 static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) 430 { 431 struct pp_hwmgr *hwmgr = handle; 432 struct pp_power_state *state; 433 enum amd_pm_state_type pm_type; 434 435 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps) 436 return -EINVAL; 437 438 state = hwmgr->current_ps; 439 440 switch (state->classification.ui_label) { 441 case PP_StateUILabel_Battery: 442 pm_type = POWER_STATE_TYPE_BATTERY; 443 break; 444 case PP_StateUILabel_Balanced: 445 pm_type = POWER_STATE_TYPE_BALANCED; 446 break; 447 case PP_StateUILabel_Performance: 448 pm_type = POWER_STATE_TYPE_PERFORMANCE; 449 break; 450 default: 451 if (state->classification.flags & PP_StateClassificationFlag_Boot) 452 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT; 453 else 454 pm_type = POWER_STATE_TYPE_DEFAULT; 455 break; 456 } 457 458 return pm_type; 459 } 460 461 static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode) 462 { 463 struct pp_hwmgr *hwmgr = handle; 464 465 if (!hwmgr || !hwmgr->pm_en) 466 return -EOPNOTSUPP; 467 468 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) 469 return -EOPNOTSUPP; 470 471 if (mode == U32_MAX) 472 return -EINVAL; 473 474 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode); 475 476 return 0; 477 } 478 479 static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode) 480 { 481 struct pp_hwmgr *hwmgr = handle; 482 483 if (!hwmgr || !hwmgr->pm_en) 484 return -EOPNOTSUPP; 485 486 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) 487 return -EOPNOTSUPP; 488 489 if (!fan_mode) 490 return -EINVAL; 491 492 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr); 493 return 0; 494 } 495 496 static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed) 497 { 498 struct pp_hwmgr *hwmgr = handle; 499 500 if (!hwmgr || !hwmgr->pm_en) 501 return -EOPNOTSUPP; 502 503 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL) 504 return -EOPNOTSUPP; 505 506 if (speed == U32_MAX) 507 return -EINVAL; 508 509 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed); 510 } 511 512 static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed) 513 { 514 struct pp_hwmgr *hwmgr = handle; 515 516 if (!hwmgr || !hwmgr->pm_en) 517 return -EOPNOTSUPP; 518 519 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL) 520 return -EOPNOTSUPP; 521 522 if (!speed) 523 return -EINVAL; 524 525 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed); 526 } 527 528 static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm) 529 { 530 struct pp_hwmgr *hwmgr = handle; 531 532 if (!hwmgr || !hwmgr->pm_en) 533 return -EOPNOTSUPP; 534 535 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL) 536 return -EOPNOTSUPP; 537 538 if (!rpm) 539 return -EINVAL; 540 541 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm); 542 } 543 544 static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm) 545 { 546 struct pp_hwmgr *hwmgr = handle; 547 548 if (!hwmgr || !hwmgr->pm_en) 549 return -EOPNOTSUPP; 550 551 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) 552 return -EOPNOTSUPP; 553 554 if (rpm == U32_MAX) 555 return -EINVAL; 556 557 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm); 558 } 559 560 static int pp_dpm_get_pp_num_states(void *handle, 561 struct pp_states_info *data) 562 { 563 struct pp_hwmgr *hwmgr = handle; 564 int i; 565 566 memset(data, 0, sizeof(*data)); 567 568 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps) 569 return -EINVAL; 570 571 data->nums = hwmgr->num_ps; 572 573 for (i = 0; i < hwmgr->num_ps; i++) { 574 struct pp_power_state *state = (struct pp_power_state *) 575 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size); 576 switch (state->classification.ui_label) { 577 case PP_StateUILabel_Battery: 578 data->states[i] = POWER_STATE_TYPE_BATTERY; 579 break; 580 case PP_StateUILabel_Balanced: 581 data->states[i] = POWER_STATE_TYPE_BALANCED; 582 break; 583 case PP_StateUILabel_Performance: 584 data->states[i] = POWER_STATE_TYPE_PERFORMANCE; 585 break; 586 default: 587 if (state->classification.flags & PP_StateClassificationFlag_Boot) 588 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT; 589 else 590 data->states[i] = POWER_STATE_TYPE_DEFAULT; 591 } 592 } 593 return 0; 594 } 595 596 static int pp_dpm_get_pp_table(void *handle, char **table) 597 { 598 struct pp_hwmgr *hwmgr = handle; 599 600 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table) 601 return -EINVAL; 602 603 *table = (char *)hwmgr->soft_pp_table; 604 return hwmgr->soft_pp_table_size; 605 } 606 607 static int amd_powerplay_reset(void *handle) 608 { 609 struct pp_hwmgr *hwmgr = handle; 610 int ret; 611 612 ret = hwmgr_hw_fini(hwmgr); 613 if (ret) 614 return ret; 615 616 ret = hwmgr_hw_init(hwmgr); 617 if (ret) 618 return ret; 619 620 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL); 621 } 622 623 static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size) 624 { 625 struct pp_hwmgr *hwmgr = handle; 626 int ret = -ENOMEM; 627 628 if (!hwmgr || !hwmgr->pm_en) 629 return -EINVAL; 630 631 if (!hwmgr->hardcode_pp_table) { 632 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table, 633 hwmgr->soft_pp_table_size, 634 GFP_KERNEL); 635 if (!hwmgr->hardcode_pp_table) 636 return ret; 637 } 638 639 memcpy(hwmgr->hardcode_pp_table, buf, size); 640 641 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table; 642 643 ret = amd_powerplay_reset(handle); 644 if (ret) 645 return ret; 646 647 if (hwmgr->hwmgr_func->avfs_control) 648 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false); 649 650 return ret; 651 } 652 653 static int pp_dpm_force_clock_level(void *handle, 654 enum pp_clock_type type, uint32_t mask) 655 { 656 struct pp_hwmgr *hwmgr = handle; 657 658 if (!hwmgr || !hwmgr->pm_en) 659 return -EINVAL; 660 661 if (hwmgr->hwmgr_func->force_clock_level == NULL) { 662 pr_info_ratelimited("%s was not implemented.\n", __func__); 663 return 0; 664 } 665 666 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 667 pr_debug("force clock level is for dpm manual mode only.\n"); 668 return -EINVAL; 669 } 670 671 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask); 672 } 673 674 static int pp_dpm_print_clock_levels(void *handle, 675 enum pp_clock_type type, char *buf) 676 { 677 struct pp_hwmgr *hwmgr = handle; 678 679 if (!hwmgr || !hwmgr->pm_en) 680 return -EINVAL; 681 682 if (hwmgr->hwmgr_func->print_clock_levels == NULL) { 683 pr_info_ratelimited("%s was not implemented.\n", __func__); 684 return 0; 685 } 686 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); 687 } 688 689 static int pp_dpm_get_sclk_od(void *handle) 690 { 691 struct pp_hwmgr *hwmgr = handle; 692 693 if (!hwmgr || !hwmgr->pm_en) 694 return -EINVAL; 695 696 if (hwmgr->hwmgr_func->get_sclk_od == NULL) { 697 pr_info_ratelimited("%s was not implemented.\n", __func__); 698 return 0; 699 } 700 return hwmgr->hwmgr_func->get_sclk_od(hwmgr); 701 } 702 703 static int pp_dpm_set_sclk_od(void *handle, uint32_t value) 704 { 705 struct pp_hwmgr *hwmgr = handle; 706 707 if (!hwmgr || !hwmgr->pm_en) 708 return -EINVAL; 709 710 if (hwmgr->hwmgr_func->set_sclk_od == NULL) { 711 pr_info_ratelimited("%s was not implemented.\n", __func__); 712 return 0; 713 } 714 715 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value); 716 } 717 718 static int pp_dpm_get_mclk_od(void *handle) 719 { 720 struct pp_hwmgr *hwmgr = handle; 721 722 if (!hwmgr || !hwmgr->pm_en) 723 return -EINVAL; 724 725 if (hwmgr->hwmgr_func->get_mclk_od == NULL) { 726 pr_info_ratelimited("%s was not implemented.\n", __func__); 727 return 0; 728 } 729 return hwmgr->hwmgr_func->get_mclk_od(hwmgr); 730 } 731 732 static int pp_dpm_set_mclk_od(void *handle, uint32_t value) 733 { 734 struct pp_hwmgr *hwmgr = handle; 735 736 if (!hwmgr || !hwmgr->pm_en) 737 return -EINVAL; 738 739 if (hwmgr->hwmgr_func->set_mclk_od == NULL) { 740 pr_info_ratelimited("%s was not implemented.\n", __func__); 741 return 0; 742 } 743 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value); 744 } 745 746 static int pp_dpm_read_sensor(void *handle, int idx, 747 void *value, int *size) 748 { 749 struct pp_hwmgr *hwmgr = handle; 750 751 if (!hwmgr || !hwmgr->pm_en || !value) 752 return -EINVAL; 753 754 switch (idx) { 755 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK: 756 *((uint32_t *)value) = hwmgr->pstate_sclk; 757 return 0; 758 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK: 759 *((uint32_t *)value) = hwmgr->pstate_mclk; 760 return 0; 761 case AMDGPU_PP_SENSOR_MIN_FAN_RPM: 762 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM; 763 return 0; 764 case AMDGPU_PP_SENSOR_MAX_FAN_RPM: 765 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM; 766 return 0; 767 default: 768 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size); 769 } 770 } 771 772 static struct amd_vce_state* 773 pp_dpm_get_vce_clock_state(void *handle, unsigned idx) 774 { 775 struct pp_hwmgr *hwmgr = handle; 776 777 if (!hwmgr || !hwmgr->pm_en) 778 return NULL; 779 780 if (idx < hwmgr->num_vce_state_tables) 781 return &hwmgr->vce_states[idx]; 782 return NULL; 783 } 784 785 static int pp_get_power_profile_mode(void *handle, char *buf) 786 { 787 struct pp_hwmgr *hwmgr = handle; 788 789 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode) 790 return -EOPNOTSUPP; 791 if (!buf) 792 return -EINVAL; 793 794 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf); 795 } 796 797 static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size) 798 { 799 struct pp_hwmgr *hwmgr = handle; 800 801 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode) 802 return -EOPNOTSUPP; 803 804 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) { 805 pr_debug("power profile setting is for manual dpm mode only.\n"); 806 return -EINVAL; 807 } 808 809 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size); 810 } 811 812 static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size) 813 { 814 struct pp_hwmgr *hwmgr = handle; 815 816 if (!hwmgr || !hwmgr->pm_en) 817 return -EINVAL; 818 819 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL) 820 return 0; 821 822 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size); 823 } 824 825 static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size) 826 { 827 struct pp_hwmgr *hwmgr = handle; 828 829 if (!hwmgr || !hwmgr->pm_en) 830 return -EINVAL; 831 832 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) { 833 pr_info_ratelimited("%s was not implemented.\n", __func__); 834 return 0; 835 } 836 837 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size); 838 } 839 840 static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state) 841 { 842 struct pp_hwmgr *hwmgr = handle; 843 844 if (!hwmgr) 845 return -EINVAL; 846 847 if (!hwmgr->pm_en) 848 return 0; 849 850 if (hwmgr->hwmgr_func->set_mp1_state) 851 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state); 852 853 return 0; 854 } 855 856 static int pp_dpm_switch_power_profile(void *handle, 857 enum PP_SMC_POWER_PROFILE type, bool en) 858 { 859 struct pp_hwmgr *hwmgr = handle; 860 long workload; 861 uint32_t index; 862 863 if (!hwmgr || !hwmgr->pm_en) 864 return -EINVAL; 865 866 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) { 867 pr_info_ratelimited("%s was not implemented.\n", __func__); 868 return -EINVAL; 869 } 870 871 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM)) 872 return -EINVAL; 873 874 if (!en) { 875 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]); 876 index = fls(hwmgr->workload_mask); 877 index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0; 878 workload = hwmgr->workload_setting[index]; 879 } else { 880 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]); 881 index = fls(hwmgr->workload_mask); 882 index = index <= Workload_Policy_Max ? index - 1 : 0; 883 workload = hwmgr->workload_setting[index]; 884 } 885 886 if (type == PP_SMC_POWER_PROFILE_COMPUTE && 887 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) { 888 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en)) 889 return -EINVAL; 890 } 891 892 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) 893 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0); 894 895 return 0; 896 } 897 898 static int pp_set_power_limit(void *handle, uint32_t limit) 899 { 900 struct pp_hwmgr *hwmgr = handle; 901 uint32_t max_power_limit; 902 903 if (!hwmgr || !hwmgr->pm_en) 904 return -EINVAL; 905 906 if (hwmgr->hwmgr_func->set_power_limit == NULL) { 907 pr_info_ratelimited("%s was not implemented.\n", __func__); 908 return -EINVAL; 909 } 910 911 if (limit == 0) 912 limit = hwmgr->default_power_limit; 913 914 max_power_limit = hwmgr->default_power_limit; 915 if (hwmgr->od_enabled) { 916 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 917 max_power_limit /= 100; 918 } 919 920 if (limit > max_power_limit) 921 return -EINVAL; 922 923 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit); 924 hwmgr->power_limit = limit; 925 return 0; 926 } 927 928 static int pp_get_power_limit(void *handle, uint32_t *limit, 929 enum pp_power_limit_level pp_limit_level, 930 enum pp_power_type power_type) 931 { 932 struct pp_hwmgr *hwmgr = handle; 933 int ret = 0; 934 935 if (!hwmgr || !hwmgr->pm_en ||!limit) 936 return -EINVAL; 937 938 if (power_type != PP_PWR_TYPE_SUSTAINED) 939 return -EOPNOTSUPP; 940 941 switch (pp_limit_level) { 942 case PP_PWR_LIMIT_CURRENT: 943 *limit = hwmgr->power_limit; 944 break; 945 case PP_PWR_LIMIT_DEFAULT: 946 *limit = hwmgr->default_power_limit; 947 break; 948 case PP_PWR_LIMIT_MAX: 949 *limit = hwmgr->default_power_limit; 950 if (hwmgr->od_enabled) { 951 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit); 952 *limit /= 100; 953 } 954 break; 955 default: 956 ret = -EOPNOTSUPP; 957 break; 958 } 959 960 return ret; 961 } 962 963 static int pp_display_configuration_change(void *handle, 964 const struct amd_pp_display_configuration *display_config) 965 { 966 struct pp_hwmgr *hwmgr = handle; 967 968 if (!hwmgr || !hwmgr->pm_en) 969 return -EINVAL; 970 971 phm_store_dal_configuration_data(hwmgr, display_config); 972 return 0; 973 } 974 975 static int pp_get_display_power_level(void *handle, 976 struct amd_pp_simple_clock_info *output) 977 { 978 struct pp_hwmgr *hwmgr = handle; 979 980 if (!hwmgr || !hwmgr->pm_en ||!output) 981 return -EINVAL; 982 983 return phm_get_dal_power_level(hwmgr, output); 984 } 985 986 static int pp_get_current_clocks(void *handle, 987 struct amd_pp_clock_info *clocks) 988 { 989 struct amd_pp_simple_clock_info simple_clocks = { 0 }; 990 struct pp_clock_info hw_clocks; 991 struct pp_hwmgr *hwmgr = handle; 992 int ret = 0; 993 994 if (!hwmgr || !hwmgr->pm_en) 995 return -EINVAL; 996 997 phm_get_dal_power_level(hwmgr, &simple_clocks); 998 999 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1000 PHM_PlatformCaps_PowerContainment)) 1001 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1002 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment); 1003 else 1004 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware, 1005 &hw_clocks, PHM_PerformanceLevelDesignation_Activity); 1006 1007 if (ret) { 1008 pr_debug("Error in phm_get_clock_info \n"); 1009 return -EINVAL; 1010 } 1011 1012 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1013 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1014 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1015 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1016 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1017 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1018 1019 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1020 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1021 1022 if (simple_clocks.level == 0) 1023 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7; 1024 else 1025 clocks->max_clocks_state = simple_clocks.level; 1026 1027 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) { 1028 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1029 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1030 } 1031 return 0; 1032 } 1033 1034 static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) 1035 { 1036 struct pp_hwmgr *hwmgr = handle; 1037 1038 if (!hwmgr || !hwmgr->pm_en) 1039 return -EINVAL; 1040 1041 if (clocks == NULL) 1042 return -EINVAL; 1043 1044 return phm_get_clock_by_type(hwmgr, type, clocks); 1045 } 1046 1047 static int pp_get_clock_by_type_with_latency(void *handle, 1048 enum amd_pp_clock_type type, 1049 struct pp_clock_levels_with_latency *clocks) 1050 { 1051 struct pp_hwmgr *hwmgr = handle; 1052 1053 if (!hwmgr || !hwmgr->pm_en ||!clocks) 1054 return -EINVAL; 1055 1056 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks); 1057 } 1058 1059 static int pp_get_clock_by_type_with_voltage(void *handle, 1060 enum amd_pp_clock_type type, 1061 struct pp_clock_levels_with_voltage *clocks) 1062 { 1063 struct pp_hwmgr *hwmgr = handle; 1064 1065 if (!hwmgr || !hwmgr->pm_en ||!clocks) 1066 return -EINVAL; 1067 1068 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks); 1069 } 1070 1071 static int pp_set_watermarks_for_clocks_ranges(void *handle, 1072 void *clock_ranges) 1073 { 1074 struct pp_hwmgr *hwmgr = handle; 1075 1076 if (!hwmgr || !hwmgr->pm_en || !clock_ranges) 1077 return -EINVAL; 1078 1079 return phm_set_watermarks_for_clocks_ranges(hwmgr, 1080 clock_ranges); 1081 } 1082 1083 static int pp_display_clock_voltage_request(void *handle, 1084 struct pp_display_clock_request *clock) 1085 { 1086 struct pp_hwmgr *hwmgr = handle; 1087 1088 if (!hwmgr || !hwmgr->pm_en ||!clock) 1089 return -EINVAL; 1090 1091 return phm_display_clock_voltage_request(hwmgr, clock); 1092 } 1093 1094 static int pp_get_display_mode_validation_clocks(void *handle, 1095 struct amd_pp_simple_clock_info *clocks) 1096 { 1097 struct pp_hwmgr *hwmgr = handle; 1098 int ret = 0; 1099 1100 if (!hwmgr || !hwmgr->pm_en ||!clocks) 1101 return -EINVAL; 1102 1103 clocks->level = PP_DAL_POWERLEVEL_7; 1104 1105 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState)) 1106 ret = phm_get_max_high_clocks(hwmgr, clocks); 1107 1108 return ret; 1109 } 1110 1111 static int pp_dpm_powergate_mmhub(void *handle) 1112 { 1113 struct pp_hwmgr *hwmgr = handle; 1114 1115 if (!hwmgr || !hwmgr->pm_en) 1116 return -EINVAL; 1117 1118 if (hwmgr->hwmgr_func->powergate_mmhub == NULL) { 1119 pr_info_ratelimited("%s was not implemented.\n", __func__); 1120 return 0; 1121 } 1122 1123 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr); 1124 } 1125 1126 static int pp_dpm_powergate_gfx(void *handle, bool gate) 1127 { 1128 struct pp_hwmgr *hwmgr = handle; 1129 1130 if (!hwmgr || !hwmgr->pm_en) 1131 return 0; 1132 1133 if (hwmgr->hwmgr_func->powergate_gfx == NULL) { 1134 pr_info_ratelimited("%s was not implemented.\n", __func__); 1135 return 0; 1136 } 1137 1138 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate); 1139 } 1140 1141 static void pp_dpm_powergate_acp(void *handle, bool gate) 1142 { 1143 struct pp_hwmgr *hwmgr = handle; 1144 1145 if (!hwmgr || !hwmgr->pm_en) 1146 return; 1147 1148 if (hwmgr->hwmgr_func->powergate_acp == NULL) { 1149 pr_info_ratelimited("%s was not implemented.\n", __func__); 1150 return; 1151 } 1152 1153 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate); 1154 } 1155 1156 static void pp_dpm_powergate_sdma(void *handle, bool gate) 1157 { 1158 struct pp_hwmgr *hwmgr = handle; 1159 1160 if (!hwmgr) 1161 return; 1162 1163 if (hwmgr->hwmgr_func->powergate_sdma == NULL) { 1164 pr_info_ratelimited("%s was not implemented.\n", __func__); 1165 return; 1166 } 1167 1168 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate); 1169 } 1170 1171 static int pp_set_powergating_by_smu(void *handle, 1172 uint32_t block_type, bool gate) 1173 { 1174 int ret = 0; 1175 1176 switch (block_type) { 1177 case AMD_IP_BLOCK_TYPE_UVD: 1178 case AMD_IP_BLOCK_TYPE_VCN: 1179 pp_dpm_powergate_uvd(handle, gate); 1180 break; 1181 case AMD_IP_BLOCK_TYPE_VCE: 1182 pp_dpm_powergate_vce(handle, gate); 1183 break; 1184 case AMD_IP_BLOCK_TYPE_GMC: 1185 /* 1186 * For now, this is only used on PICASSO. 1187 * And only "gate" operation is supported. 1188 */ 1189 if (gate) 1190 pp_dpm_powergate_mmhub(handle); 1191 break; 1192 case AMD_IP_BLOCK_TYPE_GFX: 1193 ret = pp_dpm_powergate_gfx(handle, gate); 1194 break; 1195 case AMD_IP_BLOCK_TYPE_ACP: 1196 pp_dpm_powergate_acp(handle, gate); 1197 break; 1198 case AMD_IP_BLOCK_TYPE_SDMA: 1199 pp_dpm_powergate_sdma(handle, gate); 1200 break; 1201 default: 1202 break; 1203 } 1204 return ret; 1205 } 1206 1207 static int pp_notify_smu_enable_pwe(void *handle) 1208 { 1209 struct pp_hwmgr *hwmgr = handle; 1210 1211 if (!hwmgr || !hwmgr->pm_en) 1212 return -EINVAL; 1213 1214 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) { 1215 pr_info_ratelimited("%s was not implemented.\n", __func__); 1216 return -EINVAL; 1217 } 1218 1219 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr); 1220 1221 return 0; 1222 } 1223 1224 static int pp_enable_mgpu_fan_boost(void *handle) 1225 { 1226 struct pp_hwmgr *hwmgr = handle; 1227 1228 if (!hwmgr) 1229 return -EINVAL; 1230 1231 if (!hwmgr->pm_en || 1232 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) 1233 return 0; 1234 1235 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr); 1236 1237 return 0; 1238 } 1239 1240 static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock) 1241 { 1242 struct pp_hwmgr *hwmgr = handle; 1243 1244 if (!hwmgr || !hwmgr->pm_en) 1245 return -EINVAL; 1246 1247 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) { 1248 pr_debug("%s was not implemented.\n", __func__); 1249 return -EINVAL; 1250 } 1251 1252 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock); 1253 1254 return 0; 1255 } 1256 1257 static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock) 1258 { 1259 struct pp_hwmgr *hwmgr = handle; 1260 1261 if (!hwmgr || !hwmgr->pm_en) 1262 return -EINVAL; 1263 1264 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) { 1265 pr_debug("%s was not implemented.\n", __func__); 1266 return -EINVAL; 1267 } 1268 1269 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock); 1270 1271 return 0; 1272 } 1273 1274 static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock) 1275 { 1276 struct pp_hwmgr *hwmgr = handle; 1277 1278 if (!hwmgr || !hwmgr->pm_en) 1279 return -EINVAL; 1280 1281 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) { 1282 pr_debug("%s was not implemented.\n", __func__); 1283 return -EINVAL; 1284 } 1285 1286 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock); 1287 1288 return 0; 1289 } 1290 1291 static int pp_set_active_display_count(void *handle, uint32_t count) 1292 { 1293 struct pp_hwmgr *hwmgr = handle; 1294 1295 if (!hwmgr || !hwmgr->pm_en) 1296 return -EINVAL; 1297 1298 return phm_set_active_display_count(hwmgr, count); 1299 } 1300 1301 static int pp_get_asic_baco_capability(void *handle, bool *cap) 1302 { 1303 struct pp_hwmgr *hwmgr = handle; 1304 1305 *cap = false; 1306 if (!hwmgr) 1307 return -EINVAL; 1308 1309 if (!(hwmgr->not_vf && amdgpu_dpm) || 1310 !hwmgr->hwmgr_func->get_asic_baco_capability) 1311 return 0; 1312 1313 hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap); 1314 1315 return 0; 1316 } 1317 1318 static int pp_get_asic_baco_state(void *handle, int *state) 1319 { 1320 struct pp_hwmgr *hwmgr = handle; 1321 1322 if (!hwmgr) 1323 return -EINVAL; 1324 1325 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state) 1326 return 0; 1327 1328 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state); 1329 1330 return 0; 1331 } 1332 1333 static int pp_set_asic_baco_state(void *handle, int state) 1334 { 1335 struct pp_hwmgr *hwmgr = handle; 1336 1337 if (!hwmgr) 1338 return -EINVAL; 1339 1340 if (!(hwmgr->not_vf && amdgpu_dpm) || 1341 !hwmgr->hwmgr_func->set_asic_baco_state) 1342 return 0; 1343 1344 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state); 1345 1346 return 0; 1347 } 1348 1349 static int pp_get_ppfeature_status(void *handle, char *buf) 1350 { 1351 struct pp_hwmgr *hwmgr = handle; 1352 1353 if (!hwmgr || !hwmgr->pm_en || !buf) 1354 return -EINVAL; 1355 1356 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) { 1357 pr_info_ratelimited("%s was not implemented.\n", __func__); 1358 return -EINVAL; 1359 } 1360 1361 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf); 1362 } 1363 1364 static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks) 1365 { 1366 struct pp_hwmgr *hwmgr = handle; 1367 1368 if (!hwmgr || !hwmgr->pm_en) 1369 return -EINVAL; 1370 1371 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) { 1372 pr_info_ratelimited("%s was not implemented.\n", __func__); 1373 return -EINVAL; 1374 } 1375 1376 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks); 1377 } 1378 1379 static int pp_asic_reset_mode_2(void *handle) 1380 { 1381 struct pp_hwmgr *hwmgr = handle; 1382 1383 if (!hwmgr || !hwmgr->pm_en) 1384 return -EINVAL; 1385 1386 if (hwmgr->hwmgr_func->asic_reset == NULL) { 1387 pr_info_ratelimited("%s was not implemented.\n", __func__); 1388 return -EINVAL; 1389 } 1390 1391 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2); 1392 } 1393 1394 static int pp_smu_i2c_bus_access(void *handle, bool acquire) 1395 { 1396 struct pp_hwmgr *hwmgr = handle; 1397 1398 if (!hwmgr || !hwmgr->pm_en) 1399 return -EINVAL; 1400 1401 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) { 1402 pr_info_ratelimited("%s was not implemented.\n", __func__); 1403 return -EINVAL; 1404 } 1405 1406 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire); 1407 } 1408 1409 static int pp_set_df_cstate(void *handle, enum pp_df_cstate state) 1410 { 1411 struct pp_hwmgr *hwmgr = handle; 1412 1413 if (!hwmgr) 1414 return -EINVAL; 1415 1416 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate) 1417 return 0; 1418 1419 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state); 1420 1421 return 0; 1422 } 1423 1424 static int pp_set_xgmi_pstate(void *handle, uint32_t pstate) 1425 { 1426 struct pp_hwmgr *hwmgr = handle; 1427 1428 if (!hwmgr) 1429 return -EINVAL; 1430 1431 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate) 1432 return 0; 1433 1434 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate); 1435 1436 return 0; 1437 } 1438 1439 static ssize_t pp_get_gpu_metrics(void *handle, void **table) 1440 { 1441 struct pp_hwmgr *hwmgr = handle; 1442 1443 if (!hwmgr) 1444 return -EINVAL; 1445 1446 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics) 1447 return -EOPNOTSUPP; 1448 1449 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table); 1450 } 1451 1452 static int pp_gfx_state_change_set(void *handle, uint32_t state) 1453 { 1454 struct pp_hwmgr *hwmgr = handle; 1455 1456 if (!hwmgr || !hwmgr->pm_en) 1457 return -EINVAL; 1458 1459 if (hwmgr->hwmgr_func->gfx_state_change == NULL) { 1460 pr_info_ratelimited("%s was not implemented.\n", __func__); 1461 return -EINVAL; 1462 } 1463 1464 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state); 1465 return 0; 1466 } 1467 1468 static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size) 1469 { 1470 struct pp_hwmgr *hwmgr = handle; 1471 struct amdgpu_device *adev = hwmgr->adev; 1472 1473 if (!addr || !size) 1474 return -EINVAL; 1475 1476 *addr = NULL; 1477 *size = 0; 1478 if (adev->pm.smu_prv_buffer) { 1479 amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr); 1480 *size = adev->pm.smu_prv_buffer_size; 1481 } 1482 1483 return 0; 1484 } 1485 1486 static void pp_pm_compute_clocks(void *handle) 1487 { 1488 struct pp_hwmgr *hwmgr = handle; 1489 struct amdgpu_device *adev = hwmgr->adev; 1490 int i = 0; 1491 1492 if (adev->mode_info.num_crtc) 1493 amdgpu_display_bandwidth_update(adev); 1494 1495 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1496 struct amdgpu_ring *ring = adev->rings[i]; 1497 if (ring && ring->sched.ready) 1498 amdgpu_fence_wait_empty(ring); 1499 } 1500 1501 if (!amdgpu_device_has_dc_support(adev)) { 1502 amdgpu_dpm_get_active_displays(adev); 1503 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; 1504 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); 1505 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); 1506 /* we have issues with mclk switching with 1507 * refresh rates over 120 hz on the non-DC code. 1508 */ 1509 if (adev->pm.pm_display_cfg.vrefresh > 120) 1510 adev->pm.pm_display_cfg.min_vblank_time = 0; 1511 1512 pp_display_configuration_change(handle, 1513 &adev->pm.pm_display_cfg); 1514 } 1515 1516 pp_dpm_dispatch_tasks(handle, 1517 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 1518 NULL); 1519 } 1520 1521 static const struct amd_pm_funcs pp_dpm_funcs = { 1522 .load_firmware = pp_dpm_load_fw, 1523 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete, 1524 .force_performance_level = pp_dpm_force_performance_level, 1525 .get_performance_level = pp_dpm_get_performance_level, 1526 .get_current_power_state = pp_dpm_get_current_power_state, 1527 .dispatch_tasks = pp_dpm_dispatch_tasks, 1528 .set_fan_control_mode = pp_dpm_set_fan_control_mode, 1529 .get_fan_control_mode = pp_dpm_get_fan_control_mode, 1530 .set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm, 1531 .get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm, 1532 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm, 1533 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm, 1534 .get_pp_num_states = pp_dpm_get_pp_num_states, 1535 .get_pp_table = pp_dpm_get_pp_table, 1536 .set_pp_table = pp_dpm_set_pp_table, 1537 .force_clock_level = pp_dpm_force_clock_level, 1538 .print_clock_levels = pp_dpm_print_clock_levels, 1539 .get_sclk_od = pp_dpm_get_sclk_od, 1540 .set_sclk_od = pp_dpm_set_sclk_od, 1541 .get_mclk_od = pp_dpm_get_mclk_od, 1542 .set_mclk_od = pp_dpm_set_mclk_od, 1543 .read_sensor = pp_dpm_read_sensor, 1544 .get_vce_clock_state = pp_dpm_get_vce_clock_state, 1545 .switch_power_profile = pp_dpm_switch_power_profile, 1546 .set_clockgating_by_smu = pp_set_clockgating_by_smu, 1547 .set_powergating_by_smu = pp_set_powergating_by_smu, 1548 .get_power_profile_mode = pp_get_power_profile_mode, 1549 .set_power_profile_mode = pp_set_power_profile_mode, 1550 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol, 1551 .odn_edit_dpm_table = pp_odn_edit_dpm_table, 1552 .set_mp1_state = pp_dpm_set_mp1_state, 1553 .set_power_limit = pp_set_power_limit, 1554 .get_power_limit = pp_get_power_limit, 1555 /* export to DC */ 1556 .get_sclk = pp_dpm_get_sclk, 1557 .get_mclk = pp_dpm_get_mclk, 1558 .display_configuration_change = pp_display_configuration_change, 1559 .get_display_power_level = pp_get_display_power_level, 1560 .get_current_clocks = pp_get_current_clocks, 1561 .get_clock_by_type = pp_get_clock_by_type, 1562 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency, 1563 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage, 1564 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges, 1565 .display_clock_voltage_request = pp_display_clock_voltage_request, 1566 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks, 1567 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe, 1568 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost, 1569 .set_active_display_count = pp_set_active_display_count, 1570 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk, 1571 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq, 1572 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq, 1573 .get_asic_baco_capability = pp_get_asic_baco_capability, 1574 .get_asic_baco_state = pp_get_asic_baco_state, 1575 .set_asic_baco_state = pp_set_asic_baco_state, 1576 .get_ppfeature_status = pp_get_ppfeature_status, 1577 .set_ppfeature_status = pp_set_ppfeature_status, 1578 .asic_reset_mode_2 = pp_asic_reset_mode_2, 1579 .smu_i2c_bus_access = pp_smu_i2c_bus_access, 1580 .set_df_cstate = pp_set_df_cstate, 1581 .set_xgmi_pstate = pp_set_xgmi_pstate, 1582 .get_gpu_metrics = pp_get_gpu_metrics, 1583 .gfx_state_change_set = pp_gfx_state_change_set, 1584 .get_smu_prv_buf_details = pp_get_prv_buffer_details, 1585 .pm_compute_clocks = pp_pm_compute_clocks, 1586 }; 1587