1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "amdgpu_atombios.h" 31 #include "amd_pcie.h" 32 #include "sid.h" 33 #include "r600_dpm.h" 34 #include "si_dpm.h" 35 #include "atom.h" 36 #include "../include/pptable.h" 37 #include <linux/math64.h> 38 #include <linux/seq_file.h> 39 #include <linux/firmware.h> 40 #include <legacy_dpm.h> 41 42 #define MC_CG_ARB_FREQ_F0 0x0a 43 #define MC_CG_ARB_FREQ_F1 0x0b 44 #define MC_CG_ARB_FREQ_F2 0x0c 45 #define MC_CG_ARB_FREQ_F3 0x0d 46 47 #define SMC_RAM_END 0x20000 48 49 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 50 51 52 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 56 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 57 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 58 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 59 60 #define BIOS_SCRATCH_4 0x5cd 61 62 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); 63 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); 64 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); 65 MODULE_FIRMWARE("amdgpu/verde_smc.bin"); 66 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); 67 MODULE_FIRMWARE("amdgpu/oland_smc.bin"); 68 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); 69 MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); 70 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); 71 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); 72 73 static const struct amd_pm_funcs si_dpm_funcs; 74 75 union power_info { 76 struct _ATOM_POWERPLAY_INFO info; 77 struct _ATOM_POWERPLAY_INFO_V2 info_2; 78 struct _ATOM_POWERPLAY_INFO_V3 info_3; 79 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 80 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 81 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 82 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 83 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 84 }; 85 86 union fan_info { 87 struct _ATOM_PPLIB_FANTABLE fan; 88 struct _ATOM_PPLIB_FANTABLE2 fan2; 89 struct _ATOM_PPLIB_FANTABLE3 fan3; 90 }; 91 92 union pplib_clock_info { 93 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 94 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 95 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 96 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 97 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 98 }; 99 100 enum si_dpm_auto_throttle_src { 101 SI_DPM_AUTO_THROTTLE_SRC_THERMAL, 102 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL 103 }; 104 105 enum si_dpm_event_src { 106 SI_DPM_EVENT_SRC_ANALOG = 0, 107 SI_DPM_EVENT_SRC_EXTERNAL = 1, 108 SI_DPM_EVENT_SRC_DIGITAL = 2, 109 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 110 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 111 }; 112 113 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 114 { 115 R600_UTC_DFLT_00, 116 R600_UTC_DFLT_01, 117 R600_UTC_DFLT_02, 118 R600_UTC_DFLT_03, 119 R600_UTC_DFLT_04, 120 R600_UTC_DFLT_05, 121 R600_UTC_DFLT_06, 122 R600_UTC_DFLT_07, 123 R600_UTC_DFLT_08, 124 R600_UTC_DFLT_09, 125 R600_UTC_DFLT_10, 126 R600_UTC_DFLT_11, 127 R600_UTC_DFLT_12, 128 R600_UTC_DFLT_13, 129 R600_UTC_DFLT_14, 130 }; 131 132 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 133 { 134 R600_DTC_DFLT_00, 135 R600_DTC_DFLT_01, 136 R600_DTC_DFLT_02, 137 R600_DTC_DFLT_03, 138 R600_DTC_DFLT_04, 139 R600_DTC_DFLT_05, 140 R600_DTC_DFLT_06, 141 R600_DTC_DFLT_07, 142 R600_DTC_DFLT_08, 143 R600_DTC_DFLT_09, 144 R600_DTC_DFLT_10, 145 R600_DTC_DFLT_11, 146 R600_DTC_DFLT_12, 147 R600_DTC_DFLT_13, 148 R600_DTC_DFLT_14, 149 }; 150 151 static const struct si_cac_config_reg cac_weights_tahiti[] = 152 { 153 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 154 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 155 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 156 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 157 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 158 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 159 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 160 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 161 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 162 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 163 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 164 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 165 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 166 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 168 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 169 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 170 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 171 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 172 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 173 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 174 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 175 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 176 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 177 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 178 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 179 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 180 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 181 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 182 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 183 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 184 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 185 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 186 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 187 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 188 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 189 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 190 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 192 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 193 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 195 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 196 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 197 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 198 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 199 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 200 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 201 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 202 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 203 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 204 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 205 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 206 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 207 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 208 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 209 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 210 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 211 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 212 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 213 { 0xFFFFFFFF } 214 }; 215 216 static const struct si_cac_config_reg lcac_tahiti[] = 217 { 218 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 219 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 220 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 221 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 222 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 223 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 224 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 225 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 226 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 227 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 228 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 229 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 230 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 231 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 232 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 233 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 234 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 235 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 236 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 237 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 238 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 239 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 240 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 241 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 242 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 243 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 244 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 245 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 246 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 247 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 248 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 249 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 250 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 251 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 252 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 253 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 254 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 255 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 256 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 257 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 258 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 259 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 260 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 261 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 262 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 263 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 264 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 265 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 266 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 267 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 268 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 269 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 270 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 271 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 272 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 273 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 274 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 275 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 276 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 277 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 278 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 279 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 280 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 281 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 282 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 283 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 284 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 285 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 286 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 287 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 288 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 289 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 290 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 291 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 292 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 293 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 294 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 295 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 296 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 297 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 298 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 299 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 300 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 301 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 302 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 303 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 304 { 0xFFFFFFFF } 305 306 }; 307 308 static const struct si_cac_config_reg cac_override_tahiti[] = 309 { 310 { 0xFFFFFFFF } 311 }; 312 313 static const struct si_powertune_data powertune_data_tahiti = 314 { 315 ((1 << 16) | 27027), 316 6, 317 0, 318 4, 319 95, 320 { 321 0UL, 322 0UL, 323 4521550UL, 324 309631529UL, 325 -1270850L, 326 4513710L, 327 40 328 }, 329 595000000UL, 330 12, 331 { 332 0, 333 0, 334 0, 335 0, 336 0, 337 0, 338 0, 339 0 340 }, 341 true 342 }; 343 344 static const struct si_dte_data dte_data_tahiti = 345 { 346 { 1159409, 0, 0, 0, 0 }, 347 { 777, 0, 0, 0, 0 }, 348 2, 349 54000, 350 127000, 351 25, 352 2, 353 10, 354 13, 355 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 356 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 357 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 358 85, 359 false 360 }; 361 362 static const struct si_dte_data dte_data_tahiti_pro = 363 { 364 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 365 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 366 5, 367 45000, 368 100, 369 0xA, 370 1, 371 0, 372 0x10, 373 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 374 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 375 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 376 90, 377 true 378 }; 379 380 static const struct si_dte_data dte_data_new_zealand = 381 { 382 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 383 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 384 0x5, 385 0xAFC8, 386 0x69, 387 0x32, 388 1, 389 0, 390 0x10, 391 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 392 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 393 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 394 85, 395 true 396 }; 397 398 static const struct si_dte_data dte_data_aruba_pro = 399 { 400 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 401 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 402 5, 403 45000, 404 100, 405 0xA, 406 1, 407 0, 408 0x10, 409 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 410 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 411 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 412 90, 413 true 414 }; 415 416 static const struct si_dte_data dte_data_malta = 417 { 418 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 419 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 420 5, 421 45000, 422 100, 423 0xA, 424 1, 425 0, 426 0x10, 427 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 428 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 429 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 430 90, 431 true 432 }; 433 434 static const struct si_cac_config_reg cac_weights_pitcairn[] = 435 { 436 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 437 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 438 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 439 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 440 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 441 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 442 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 443 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 444 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 445 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 446 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 447 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 448 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 449 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 450 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 451 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 452 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 453 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 454 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 455 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 456 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 457 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 458 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 459 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 460 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 461 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 462 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 463 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 464 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 465 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 466 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 467 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 468 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 469 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 470 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 471 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 472 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 473 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 474 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 477 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 478 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 479 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 480 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 481 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 482 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 483 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 484 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 485 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 486 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 487 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 488 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 489 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 490 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 491 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 492 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 493 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 494 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 495 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 496 { 0xFFFFFFFF } 497 }; 498 499 static const struct si_cac_config_reg lcac_pitcairn[] = 500 { 501 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 502 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 503 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 504 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 505 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 506 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 507 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 508 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 509 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 510 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 511 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 512 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 513 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 514 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 515 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 516 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 517 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 518 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 519 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 520 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 521 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 522 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 523 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 524 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 525 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 526 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 527 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 528 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 529 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 530 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 531 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 532 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 533 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 534 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 535 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 536 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 537 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 538 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 539 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 540 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 541 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 542 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 543 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 544 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 545 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 546 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 547 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 548 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 549 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 550 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 551 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 552 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 553 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 554 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 555 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 556 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 557 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 558 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 559 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 560 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 561 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 562 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 563 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 564 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 565 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 566 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 567 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 568 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 569 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 570 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 571 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 572 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 573 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 574 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 575 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 576 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 577 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 578 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 579 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 580 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 581 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 582 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 583 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 584 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 585 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 586 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 587 { 0xFFFFFFFF } 588 }; 589 590 static const struct si_cac_config_reg cac_override_pitcairn[] = 591 { 592 { 0xFFFFFFFF } 593 }; 594 595 static const struct si_powertune_data powertune_data_pitcairn = 596 { 597 ((1 << 16) | 27027), 598 5, 599 0, 600 6, 601 100, 602 { 603 51600000UL, 604 1800000UL, 605 7194395UL, 606 309631529UL, 607 -1270850L, 608 4513710L, 609 100 610 }, 611 117830498UL, 612 12, 613 { 614 0, 615 0, 616 0, 617 0, 618 0, 619 0, 620 0, 621 0 622 }, 623 true 624 }; 625 626 static const struct si_dte_data dte_data_pitcairn = 627 { 628 { 0, 0, 0, 0, 0 }, 629 { 0, 0, 0, 0, 0 }, 630 0, 631 0, 632 0, 633 0, 634 0, 635 0, 636 0, 637 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 640 0, 641 false 642 }; 643 644 static const struct si_dte_data dte_data_curacao_xt = 645 { 646 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 647 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 648 5, 649 45000, 650 100, 651 0xA, 652 1, 653 0, 654 0x10, 655 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 656 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 657 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 658 90, 659 true 660 }; 661 662 static const struct si_dte_data dte_data_curacao_pro = 663 { 664 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 665 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 666 5, 667 45000, 668 100, 669 0xA, 670 1, 671 0, 672 0x10, 673 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 674 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 675 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 676 90, 677 true 678 }; 679 680 static const struct si_dte_data dte_data_neptune_xt = 681 { 682 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 683 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 684 5, 685 45000, 686 100, 687 0xA, 688 1, 689 0, 690 0x10, 691 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 692 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 693 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 694 90, 695 true 696 }; 697 698 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 699 { 700 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 701 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 702 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 703 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 704 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 706 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 707 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 708 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 709 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 710 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 711 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 712 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 713 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 714 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 715 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 716 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 717 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 718 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 719 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 720 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 721 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 722 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 723 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 724 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 725 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 726 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 727 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 729 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 730 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 731 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 732 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 733 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 734 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 735 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 736 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 737 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 738 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 739 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 740 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 741 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 742 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 743 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 744 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 746 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 747 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 748 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 749 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 750 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 751 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 752 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 753 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 755 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 757 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 758 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 760 { 0xFFFFFFFF } 761 }; 762 763 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 764 { 765 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 766 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 767 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 768 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 769 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 771 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 772 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 773 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 774 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 775 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 776 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 777 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 778 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 779 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 780 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 781 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 782 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 783 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 784 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 785 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 786 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 787 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 788 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 789 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 790 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 791 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 792 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 794 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 795 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 796 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 797 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 798 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 799 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 800 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 801 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 802 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 803 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 804 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 805 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 806 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 807 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 808 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 809 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 811 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 812 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 813 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 814 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 815 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 816 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 817 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 818 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 820 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 822 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 823 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 825 { 0xFFFFFFFF } 826 }; 827 828 static const struct si_cac_config_reg cac_weights_heathrow[] = 829 { 830 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 831 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 832 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 833 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 834 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 836 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 837 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 838 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 839 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 840 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 841 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 842 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 843 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 844 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 845 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 846 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 847 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 848 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 849 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 850 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 851 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 852 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 853 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 854 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 855 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 856 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 857 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 859 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 860 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 861 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 862 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 863 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 864 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 865 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 866 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 867 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 868 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 869 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 870 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 871 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 872 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 873 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 874 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 876 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 877 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 878 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 879 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 880 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 881 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 882 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 883 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 885 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 887 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 888 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 890 { 0xFFFFFFFF } 891 }; 892 893 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 894 { 895 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 896 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 897 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 898 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 899 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 901 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 902 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 903 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 904 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 905 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 906 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 907 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 908 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 909 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 910 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 911 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 912 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 913 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 914 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 915 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 916 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 917 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 918 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 919 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 920 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 921 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 922 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 924 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 925 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 926 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 927 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 928 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 929 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 930 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 931 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 932 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 933 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 934 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 935 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 936 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 937 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 938 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 939 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 940 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 941 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 942 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 943 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 944 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 945 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 946 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 947 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 948 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 949 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 950 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 951 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 952 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 953 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 954 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 955 { 0xFFFFFFFF } 956 }; 957 958 static const struct si_cac_config_reg cac_weights_cape_verde[] = 959 { 960 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 961 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 962 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 963 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 964 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 965 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 966 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 967 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 968 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 969 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 970 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 971 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 972 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 973 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 974 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 975 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 976 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 977 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 978 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 979 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 980 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 981 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 982 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 983 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 984 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 985 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 986 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 987 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 988 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 990 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 991 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 992 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 993 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 994 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 995 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 996 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 997 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 998 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 999 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1000 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1001 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1002 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1003 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1004 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1005 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1006 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1007 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1008 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1009 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1010 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1011 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1012 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1013 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1014 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1015 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1016 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1017 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1018 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1019 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1020 { 0xFFFFFFFF } 1021 }; 1022 1023 static const struct si_cac_config_reg lcac_cape_verde[] = 1024 { 1025 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1026 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1027 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1028 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1029 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1030 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1031 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1032 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1033 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1034 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1035 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1036 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1037 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1038 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1039 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1040 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1041 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1042 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1043 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1044 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1045 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1046 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1047 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1048 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1049 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1050 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1051 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1052 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1053 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1054 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1055 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1056 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1057 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1058 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1059 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1060 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1079 { 0xFFFFFFFF } 1080 }; 1081 1082 static const struct si_cac_config_reg cac_override_cape_verde[] = 1083 { 1084 { 0xFFFFFFFF } 1085 }; 1086 1087 static const struct si_powertune_data powertune_data_cape_verde = 1088 { 1089 ((1 << 16) | 0x6993), 1090 5, 1091 0, 1092 7, 1093 105, 1094 { 1095 0UL, 1096 0UL, 1097 7194395UL, 1098 309631529UL, 1099 -1270850L, 1100 4513710L, 1101 100 1102 }, 1103 117830498UL, 1104 12, 1105 { 1106 0, 1107 0, 1108 0, 1109 0, 1110 0, 1111 0, 1112 0, 1113 0 1114 }, 1115 true 1116 }; 1117 1118 static const struct si_dte_data dte_data_cape_verde = 1119 { 1120 { 0, 0, 0, 0, 0 }, 1121 { 0, 0, 0, 0, 0 }, 1122 0, 1123 0, 1124 0, 1125 0, 1126 0, 1127 0, 1128 0, 1129 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1132 0, 1133 false 1134 }; 1135 1136 static const struct si_dte_data dte_data_venus_xtx = 1137 { 1138 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1139 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1140 5, 1141 55000, 1142 0x69, 1143 0xA, 1144 1, 1145 0, 1146 0x3, 1147 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1148 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1149 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1150 90, 1151 true 1152 }; 1153 1154 static const struct si_dte_data dte_data_venus_xt = 1155 { 1156 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1157 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1158 5, 1159 55000, 1160 0x69, 1161 0xA, 1162 1, 1163 0, 1164 0x3, 1165 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1166 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1167 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1168 90, 1169 true 1170 }; 1171 1172 static const struct si_dte_data dte_data_venus_pro = 1173 { 1174 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1175 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1176 5, 1177 55000, 1178 0x69, 1179 0xA, 1180 1, 1181 0, 1182 0x3, 1183 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1184 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1185 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1186 90, 1187 true 1188 }; 1189 1190 static const struct si_cac_config_reg cac_weights_oland[] = 1191 { 1192 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1193 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1211 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1212 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1213 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1214 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1215 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1216 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1217 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1218 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1219 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1229 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1230 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1231 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xFFFFFFFF } 1253 }; 1254 1255 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1256 { 1257 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1276 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1277 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1278 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1279 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1280 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1281 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1282 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1283 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1284 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1294 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1295 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1296 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xFFFFFFFF } 1318 }; 1319 1320 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1321 { 1322 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1341 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1342 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1343 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1344 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1345 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1346 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1347 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1348 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1349 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1359 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1360 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1361 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xFFFFFFFF } 1383 }; 1384 1385 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1386 { 1387 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1406 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1407 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1408 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1409 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1410 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1411 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1412 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1413 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1414 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1424 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1425 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1426 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1447 { 0xFFFFFFFF } 1448 }; 1449 1450 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1451 { 1452 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1471 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1472 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1473 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1474 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1475 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1476 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1477 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1478 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1479 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1512 { 0xFFFFFFFF } 1513 }; 1514 1515 static const struct si_cac_config_reg lcac_oland[] = 1516 { 1517 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1522 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1523 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1524 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1525 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1526 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1527 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1528 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1529 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1530 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1531 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1532 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1533 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1534 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1535 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1536 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1537 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1538 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1539 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1540 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1541 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1542 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1543 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1544 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1545 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1546 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1547 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1548 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1549 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1550 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1551 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1552 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1553 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1554 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1555 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1556 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1557 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1558 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1559 { 0xFFFFFFFF } 1560 }; 1561 1562 static const struct si_cac_config_reg lcac_mars_pro[] = 1563 { 1564 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1565 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1566 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1567 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1568 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1569 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1570 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1571 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1572 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1573 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1574 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1575 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1576 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1577 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1578 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1579 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1580 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1581 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1582 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1583 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1584 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1585 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1586 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1587 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1588 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1606 { 0xFFFFFFFF } 1607 }; 1608 1609 static const struct si_cac_config_reg cac_override_oland[] = 1610 { 1611 { 0xFFFFFFFF } 1612 }; 1613 1614 static const struct si_powertune_data powertune_data_oland = 1615 { 1616 ((1 << 16) | 0x6993), 1617 5, 1618 0, 1619 7, 1620 105, 1621 { 1622 0UL, 1623 0UL, 1624 7194395UL, 1625 309631529UL, 1626 -1270850L, 1627 4513710L, 1628 100 1629 }, 1630 117830498UL, 1631 12, 1632 { 1633 0, 1634 0, 1635 0, 1636 0, 1637 0, 1638 0, 1639 0, 1640 0 1641 }, 1642 true 1643 }; 1644 1645 static const struct si_powertune_data powertune_data_mars_pro = 1646 { 1647 ((1 << 16) | 0x6993), 1648 5, 1649 0, 1650 7, 1651 105, 1652 { 1653 0UL, 1654 0UL, 1655 7194395UL, 1656 309631529UL, 1657 -1270850L, 1658 4513710L, 1659 100 1660 }, 1661 117830498UL, 1662 12, 1663 { 1664 0, 1665 0, 1666 0, 1667 0, 1668 0, 1669 0, 1670 0, 1671 0 1672 }, 1673 true 1674 }; 1675 1676 static const struct si_dte_data dte_data_oland = 1677 { 1678 { 0, 0, 0, 0, 0 }, 1679 { 0, 0, 0, 0, 0 }, 1680 0, 1681 0, 1682 0, 1683 0, 1684 0, 1685 0, 1686 0, 1687 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1690 0, 1691 false 1692 }; 1693 1694 static const struct si_dte_data dte_data_mars_pro = 1695 { 1696 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1697 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1698 5, 1699 55000, 1700 105, 1701 0xA, 1702 1, 1703 0, 1704 0x10, 1705 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1706 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1707 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1708 90, 1709 true 1710 }; 1711 1712 static const struct si_dte_data dte_data_sun_xt = 1713 { 1714 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1715 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1716 5, 1717 55000, 1718 105, 1719 0xA, 1720 1, 1721 0, 1722 0x10, 1723 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1724 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1725 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1726 90, 1727 true 1728 }; 1729 1730 1731 static const struct si_cac_config_reg cac_weights_hainan[] = 1732 { 1733 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1734 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1735 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1736 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1737 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1738 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1739 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1740 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1741 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1742 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1743 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1744 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1745 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1746 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1747 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1748 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1749 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1750 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1751 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1752 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1753 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1754 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1755 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1756 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1757 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1758 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1759 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1760 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1761 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1762 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1763 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1764 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1765 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1766 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1767 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1768 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1769 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1770 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1771 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1772 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1773 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1774 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1775 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1776 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1777 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1778 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1779 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1780 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1781 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1782 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1783 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1784 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1785 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1786 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1787 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1788 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1789 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1790 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1791 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1792 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1793 { 0xFFFFFFFF } 1794 }; 1795 1796 static const struct si_powertune_data powertune_data_hainan = 1797 { 1798 ((1 << 16) | 0x6993), 1799 5, 1800 0, 1801 9, 1802 105, 1803 { 1804 0UL, 1805 0UL, 1806 7194395UL, 1807 309631529UL, 1808 -1270850L, 1809 4513710L, 1810 100 1811 }, 1812 117830498UL, 1813 12, 1814 { 1815 0, 1816 0, 1817 0, 1818 0, 1819 0, 1820 0, 1821 0, 1822 0 1823 }, 1824 true 1825 }; 1826 1827 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); 1828 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); 1829 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); 1830 static struct si_ps *si_get_ps(struct amdgpu_ps *rps); 1831 1832 static int si_populate_voltage_value(struct amdgpu_device *adev, 1833 const struct atom_voltage_table *table, 1834 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1835 static int si_get_std_voltage_value(struct amdgpu_device *adev, 1836 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1837 u16 *std_voltage); 1838 static int si_write_smc_soft_register(struct amdgpu_device *adev, 1839 u16 reg_offset, u32 value); 1840 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 1841 struct rv7xx_pl *pl, 1842 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1843 static int si_calculate_sclk_params(struct amdgpu_device *adev, 1844 u32 engine_clock, 1845 SISLANDS_SMC_SCLK_VALUE *sclk); 1846 1847 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); 1848 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); 1849 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); 1850 1851 static struct si_power_info *si_get_pi(struct amdgpu_device *adev) 1852 { 1853 struct si_power_info *pi = adev->pm.dpm.priv; 1854 return pi; 1855 } 1856 1857 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1858 u16 v, s32 t, u32 ileakage, u32 *leakage) 1859 { 1860 s64 kt, kv, leakage_w, i_leakage, vddc; 1861 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1862 s64 tmp; 1863 1864 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1865 vddc = div64_s64(drm_int2fixp(v), 1000); 1866 temperature = div64_s64(drm_int2fixp(t), 1000); 1867 1868 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1869 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1870 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1871 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1872 t_ref = drm_int2fixp(coeff->t_ref); 1873 1874 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1875 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1876 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1877 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1878 1879 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1880 1881 *leakage = drm_fixp2int(leakage_w * 1000); 1882 } 1883 1884 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, 1885 const struct ni_leakage_coeffients *coeff, 1886 u16 v, 1887 s32 t, 1888 u32 i_leakage, 1889 u32 *leakage) 1890 { 1891 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1892 } 1893 1894 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1895 const u32 fixed_kt, u16 v, 1896 u32 ileakage, u32 *leakage) 1897 { 1898 s64 kt, kv, leakage_w, i_leakage, vddc; 1899 1900 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1901 vddc = div64_s64(drm_int2fixp(v), 1000); 1902 1903 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1904 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1905 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1906 1907 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1908 1909 *leakage = drm_fixp2int(leakage_w * 1000); 1910 } 1911 1912 static void si_calculate_leakage_for_v(struct amdgpu_device *adev, 1913 const struct ni_leakage_coeffients *coeff, 1914 const u32 fixed_kt, 1915 u16 v, 1916 u32 i_leakage, 1917 u32 *leakage) 1918 { 1919 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1920 } 1921 1922 1923 static void si_update_dte_from_pl2(struct amdgpu_device *adev, 1924 struct si_dte_data *dte_data) 1925 { 1926 u32 p_limit1 = adev->pm.dpm.tdp_limit; 1927 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; 1928 u32 k = dte_data->k; 1929 u32 t_max = dte_data->max_t; 1930 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1931 u32 t_0 = dte_data->t0; 1932 u32 i; 1933 1934 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1935 dte_data->tdep_count = 3; 1936 1937 for (i = 0; i < k; i++) { 1938 dte_data->r[i] = 1939 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1940 (p_limit2 * (u32)100); 1941 } 1942 1943 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1944 1945 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1946 dte_data->tdep_r[i] = dte_data->r[4]; 1947 } 1948 } else { 1949 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1950 } 1951 } 1952 1953 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) 1954 { 1955 struct rv7xx_power_info *pi = adev->pm.dpm.priv; 1956 1957 return pi; 1958 } 1959 1960 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) 1961 { 1962 struct ni_power_info *pi = adev->pm.dpm.priv; 1963 1964 return pi; 1965 } 1966 1967 static struct si_ps *si_get_ps(struct amdgpu_ps *aps) 1968 { 1969 struct si_ps *ps = aps->ps_priv; 1970 1971 return ps; 1972 } 1973 1974 static void si_initialize_powertune_defaults(struct amdgpu_device *adev) 1975 { 1976 struct ni_power_info *ni_pi = ni_get_pi(adev); 1977 struct si_power_info *si_pi = si_get_pi(adev); 1978 bool update_dte_from_pl2 = false; 1979 1980 if (adev->asic_type == CHIP_TAHITI) { 1981 si_pi->cac_weights = cac_weights_tahiti; 1982 si_pi->lcac_config = lcac_tahiti; 1983 si_pi->cac_override = cac_override_tahiti; 1984 si_pi->powertune_data = &powertune_data_tahiti; 1985 si_pi->dte_data = dte_data_tahiti; 1986 1987 switch (adev->pdev->device) { 1988 case 0x6798: 1989 si_pi->dte_data.enable_dte_by_default = true; 1990 break; 1991 case 0x6799: 1992 si_pi->dte_data = dte_data_new_zealand; 1993 break; 1994 case 0x6790: 1995 case 0x6791: 1996 case 0x6792: 1997 case 0x679E: 1998 si_pi->dte_data = dte_data_aruba_pro; 1999 update_dte_from_pl2 = true; 2000 break; 2001 case 0x679B: 2002 si_pi->dte_data = dte_data_malta; 2003 update_dte_from_pl2 = true; 2004 break; 2005 case 0x679A: 2006 si_pi->dte_data = dte_data_tahiti_pro; 2007 update_dte_from_pl2 = true; 2008 break; 2009 default: 2010 if (si_pi->dte_data.enable_dte_by_default == true) 2011 DRM_ERROR("DTE is not enabled!\n"); 2012 break; 2013 } 2014 } else if (adev->asic_type == CHIP_PITCAIRN) { 2015 si_pi->cac_weights = cac_weights_pitcairn; 2016 si_pi->lcac_config = lcac_pitcairn; 2017 si_pi->cac_override = cac_override_pitcairn; 2018 si_pi->powertune_data = &powertune_data_pitcairn; 2019 2020 switch (adev->pdev->device) { 2021 case 0x6810: 2022 case 0x6818: 2023 si_pi->dte_data = dte_data_curacao_xt; 2024 update_dte_from_pl2 = true; 2025 break; 2026 case 0x6819: 2027 case 0x6811: 2028 si_pi->dte_data = dte_data_curacao_pro; 2029 update_dte_from_pl2 = true; 2030 break; 2031 case 0x6800: 2032 case 0x6806: 2033 si_pi->dte_data = dte_data_neptune_xt; 2034 update_dte_from_pl2 = true; 2035 break; 2036 default: 2037 si_pi->dte_data = dte_data_pitcairn; 2038 break; 2039 } 2040 } else if (adev->asic_type == CHIP_VERDE) { 2041 si_pi->lcac_config = lcac_cape_verde; 2042 si_pi->cac_override = cac_override_cape_verde; 2043 si_pi->powertune_data = &powertune_data_cape_verde; 2044 2045 switch (adev->pdev->device) { 2046 case 0x683B: 2047 case 0x683F: 2048 case 0x6829: 2049 case 0x6835: 2050 si_pi->cac_weights = cac_weights_cape_verde_pro; 2051 si_pi->dte_data = dte_data_cape_verde; 2052 break; 2053 case 0x682C: 2054 si_pi->cac_weights = cac_weights_cape_verde_pro; 2055 si_pi->dte_data = dte_data_sun_xt; 2056 update_dte_from_pl2 = true; 2057 break; 2058 case 0x6825: 2059 case 0x6827: 2060 si_pi->cac_weights = cac_weights_heathrow; 2061 si_pi->dte_data = dte_data_cape_verde; 2062 break; 2063 case 0x6824: 2064 case 0x682D: 2065 si_pi->cac_weights = cac_weights_chelsea_xt; 2066 si_pi->dte_data = dte_data_cape_verde; 2067 break; 2068 case 0x682F: 2069 si_pi->cac_weights = cac_weights_chelsea_pro; 2070 si_pi->dte_data = dte_data_cape_verde; 2071 break; 2072 case 0x6820: 2073 si_pi->cac_weights = cac_weights_heathrow; 2074 si_pi->dte_data = dte_data_venus_xtx; 2075 break; 2076 case 0x6821: 2077 si_pi->cac_weights = cac_weights_heathrow; 2078 si_pi->dte_data = dte_data_venus_xt; 2079 break; 2080 case 0x6823: 2081 case 0x682B: 2082 case 0x6822: 2083 case 0x682A: 2084 si_pi->cac_weights = cac_weights_chelsea_pro; 2085 si_pi->dte_data = dte_data_venus_pro; 2086 break; 2087 default: 2088 si_pi->cac_weights = cac_weights_cape_verde; 2089 si_pi->dte_data = dte_data_cape_verde; 2090 break; 2091 } 2092 } else if (adev->asic_type == CHIP_OLAND) { 2093 si_pi->lcac_config = lcac_mars_pro; 2094 si_pi->cac_override = cac_override_oland; 2095 si_pi->powertune_data = &powertune_data_mars_pro; 2096 si_pi->dte_data = dte_data_mars_pro; 2097 2098 switch (adev->pdev->device) { 2099 case 0x6601: 2100 case 0x6621: 2101 case 0x6603: 2102 case 0x6605: 2103 si_pi->cac_weights = cac_weights_mars_pro; 2104 update_dte_from_pl2 = true; 2105 break; 2106 case 0x6600: 2107 case 0x6606: 2108 case 0x6620: 2109 case 0x6604: 2110 si_pi->cac_weights = cac_weights_mars_xt; 2111 update_dte_from_pl2 = true; 2112 break; 2113 case 0x6611: 2114 case 0x6613: 2115 case 0x6608: 2116 si_pi->cac_weights = cac_weights_oland_pro; 2117 update_dte_from_pl2 = true; 2118 break; 2119 case 0x6610: 2120 si_pi->cac_weights = cac_weights_oland_xt; 2121 update_dte_from_pl2 = true; 2122 break; 2123 default: 2124 si_pi->cac_weights = cac_weights_oland; 2125 si_pi->lcac_config = lcac_oland; 2126 si_pi->cac_override = cac_override_oland; 2127 si_pi->powertune_data = &powertune_data_oland; 2128 si_pi->dte_data = dte_data_oland; 2129 break; 2130 } 2131 } else if (adev->asic_type == CHIP_HAINAN) { 2132 si_pi->cac_weights = cac_weights_hainan; 2133 si_pi->lcac_config = lcac_oland; 2134 si_pi->cac_override = cac_override_oland; 2135 si_pi->powertune_data = &powertune_data_hainan; 2136 si_pi->dte_data = dte_data_sun_xt; 2137 update_dte_from_pl2 = true; 2138 } else { 2139 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2140 return; 2141 } 2142 2143 ni_pi->enable_power_containment = false; 2144 ni_pi->enable_cac = false; 2145 ni_pi->enable_sq_ramping = false; 2146 si_pi->enable_dte = false; 2147 2148 if (si_pi->powertune_data->enable_powertune_by_default) { 2149 ni_pi->enable_power_containment = true; 2150 ni_pi->enable_cac = true; 2151 if (si_pi->dte_data.enable_dte_by_default) { 2152 si_pi->enable_dte = true; 2153 if (update_dte_from_pl2) 2154 si_update_dte_from_pl2(adev, &si_pi->dte_data); 2155 2156 } 2157 ni_pi->enable_sq_ramping = true; 2158 } 2159 2160 ni_pi->driver_calculate_cac_leakage = true; 2161 ni_pi->cac_configuration_required = true; 2162 2163 if (ni_pi->cac_configuration_required) { 2164 ni_pi->support_cac_long_term_average = true; 2165 si_pi->dyn_powertune_data.l2_lta_window_size = 2166 si_pi->powertune_data->l2_lta_window_size_default; 2167 si_pi->dyn_powertune_data.lts_truncate = 2168 si_pi->powertune_data->lts_truncate_default; 2169 } else { 2170 ni_pi->support_cac_long_term_average = false; 2171 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2172 si_pi->dyn_powertune_data.lts_truncate = 0; 2173 } 2174 2175 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2176 } 2177 2178 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) 2179 { 2180 return 1; 2181 } 2182 2183 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) 2184 { 2185 u32 xclk; 2186 u32 wintime; 2187 u32 cac_window; 2188 u32 cac_window_size; 2189 2190 xclk = amdgpu_asic_get_xclk(adev); 2191 2192 if (xclk == 0) 2193 return 0; 2194 2195 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2196 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2197 2198 wintime = (cac_window_size * 100) / xclk; 2199 2200 return wintime; 2201 } 2202 2203 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2204 { 2205 return power_in_watts; 2206 } 2207 2208 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, 2209 bool adjust_polarity, 2210 u32 tdp_adjustment, 2211 u32 *tdp_limit, 2212 u32 *near_tdp_limit) 2213 { 2214 u32 adjustment_delta, max_tdp_limit; 2215 2216 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) 2217 return -EINVAL; 2218 2219 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; 2220 2221 if (adjust_polarity) { 2222 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2223 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); 2224 } else { 2225 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2226 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; 2227 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) 2228 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2229 else 2230 *near_tdp_limit = 0; 2231 } 2232 2233 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2234 return -EINVAL; 2235 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2236 return -EINVAL; 2237 2238 return 0; 2239 } 2240 2241 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 2242 struct amdgpu_ps *amdgpu_state) 2243 { 2244 struct ni_power_info *ni_pi = ni_get_pi(adev); 2245 struct si_power_info *si_pi = si_get_pi(adev); 2246 2247 if (ni_pi->enable_power_containment) { 2248 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2249 PP_SIslands_PAPMParameters *papm_parm; 2250 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; 2251 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2252 u32 tdp_limit; 2253 u32 near_tdp_limit; 2254 int ret; 2255 2256 if (scaling_factor == 0) 2257 return -EINVAL; 2258 2259 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2260 2261 ret = si_calculate_adjusted_tdp_limits(adev, 2262 false, /* ??? */ 2263 adev->pm.dpm.tdp_adjustment, 2264 &tdp_limit, 2265 &near_tdp_limit); 2266 if (ret) 2267 return ret; 2268 2269 smc_table->dpm2Params.TDPLimit = 2270 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2271 smc_table->dpm2Params.NearTDPLimit = 2272 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2273 smc_table->dpm2Params.SafePowerLimit = 2274 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2275 2276 ret = amdgpu_si_copy_bytes_to_smc(adev, 2277 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2278 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2279 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2280 sizeof(u32) * 3, 2281 si_pi->sram_end); 2282 if (ret) 2283 return ret; 2284 2285 if (si_pi->enable_ppm) { 2286 papm_parm = &si_pi->papm_parm; 2287 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2288 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2289 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2290 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2291 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2292 papm_parm->PlatformPowerLimit = 0xffffffff; 2293 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2294 2295 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2296 (u8 *)papm_parm, 2297 sizeof(PP_SIslands_PAPMParameters), 2298 si_pi->sram_end); 2299 if (ret) 2300 return ret; 2301 } 2302 } 2303 return 0; 2304 } 2305 2306 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 2307 struct amdgpu_ps *amdgpu_state) 2308 { 2309 struct ni_power_info *ni_pi = ni_get_pi(adev); 2310 struct si_power_info *si_pi = si_get_pi(adev); 2311 2312 if (ni_pi->enable_power_containment) { 2313 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2314 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2315 int ret; 2316 2317 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2318 2319 smc_table->dpm2Params.NearTDPLimit = 2320 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2321 smc_table->dpm2Params.SafePowerLimit = 2322 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2323 2324 ret = amdgpu_si_copy_bytes_to_smc(adev, 2325 (si_pi->state_table_start + 2326 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2327 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2328 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2329 sizeof(u32) * 2, 2330 si_pi->sram_end); 2331 if (ret) 2332 return ret; 2333 } 2334 2335 return 0; 2336 } 2337 2338 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, 2339 const u16 prev_std_vddc, 2340 const u16 curr_std_vddc) 2341 { 2342 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2343 u64 prev_vddc = (u64)prev_std_vddc; 2344 u64 curr_vddc = (u64)curr_std_vddc; 2345 u64 pwr_efficiency_ratio, n, d; 2346 2347 if ((prev_vddc == 0) || (curr_vddc == 0)) 2348 return 0; 2349 2350 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2351 d = prev_vddc * prev_vddc; 2352 pwr_efficiency_ratio = div64_u64(n, d); 2353 2354 if (pwr_efficiency_ratio > (u64)0xFFFF) 2355 return 0; 2356 2357 return (u16)pwr_efficiency_ratio; 2358 } 2359 2360 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, 2361 struct amdgpu_ps *amdgpu_state) 2362 { 2363 struct si_power_info *si_pi = si_get_pi(adev); 2364 2365 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2366 amdgpu_state->vclk && amdgpu_state->dclk) 2367 return true; 2368 2369 return false; 2370 } 2371 2372 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) 2373 { 2374 struct evergreen_power_info *pi = adev->pm.dpm.priv; 2375 2376 return pi; 2377 } 2378 2379 static int si_populate_power_containment_values(struct amdgpu_device *adev, 2380 struct amdgpu_ps *amdgpu_state, 2381 SISLANDS_SMC_SWSTATE *smc_state) 2382 { 2383 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 2384 struct ni_power_info *ni_pi = ni_get_pi(adev); 2385 struct si_ps *state = si_get_ps(amdgpu_state); 2386 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2387 u32 prev_sclk; 2388 u32 max_sclk; 2389 u32 min_sclk; 2390 u16 prev_std_vddc; 2391 u16 curr_std_vddc; 2392 int i; 2393 u16 pwr_efficiency_ratio; 2394 u8 max_ps_percent; 2395 bool disable_uvd_power_tune; 2396 int ret; 2397 2398 if (ni_pi->enable_power_containment == false) 2399 return 0; 2400 2401 if (state->performance_level_count == 0) 2402 return -EINVAL; 2403 2404 if (smc_state->levelCount != state->performance_level_count) 2405 return -EINVAL; 2406 2407 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); 2408 2409 smc_state->levels[0].dpm2.MaxPS = 0; 2410 smc_state->levels[0].dpm2.NearTDPDec = 0; 2411 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2412 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2413 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2414 2415 for (i = 1; i < state->performance_level_count; i++) { 2416 prev_sclk = state->performance_levels[i-1].sclk; 2417 max_sclk = state->performance_levels[i].sclk; 2418 if (i == 1) 2419 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2420 else 2421 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2422 2423 if (prev_sclk > max_sclk) 2424 return -EINVAL; 2425 2426 if ((max_ps_percent == 0) || 2427 (prev_sclk == max_sclk) || 2428 disable_uvd_power_tune) 2429 min_sclk = max_sclk; 2430 else if (i == 1) 2431 min_sclk = prev_sclk; 2432 else 2433 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2434 2435 if (min_sclk < state->performance_levels[0].sclk) 2436 min_sclk = state->performance_levels[0].sclk; 2437 2438 if (min_sclk == 0) 2439 return -EINVAL; 2440 2441 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2442 state->performance_levels[i-1].vddc, &vddc); 2443 if (ret) 2444 return ret; 2445 2446 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); 2447 if (ret) 2448 return ret; 2449 2450 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2451 state->performance_levels[i].vddc, &vddc); 2452 if (ret) 2453 return ret; 2454 2455 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); 2456 if (ret) 2457 return ret; 2458 2459 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, 2460 prev_std_vddc, curr_std_vddc); 2461 2462 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2463 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2464 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2465 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2466 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2467 } 2468 2469 return 0; 2470 } 2471 2472 static int si_populate_sq_ramping_values(struct amdgpu_device *adev, 2473 struct amdgpu_ps *amdgpu_state, 2474 SISLANDS_SMC_SWSTATE *smc_state) 2475 { 2476 struct ni_power_info *ni_pi = ni_get_pi(adev); 2477 struct si_ps *state = si_get_ps(amdgpu_state); 2478 u32 sq_power_throttle, sq_power_throttle2; 2479 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2480 int i; 2481 2482 if (state->performance_level_count == 0) 2483 return -EINVAL; 2484 2485 if (smc_state->levelCount != state->performance_level_count) 2486 return -EINVAL; 2487 2488 if (adev->pm.dpm.sq_ramping_threshold == 0) 2489 return -EINVAL; 2490 2491 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2492 enable_sq_ramping = false; 2493 2494 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2495 enable_sq_ramping = false; 2496 2497 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2498 enable_sq_ramping = false; 2499 2500 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2501 enable_sq_ramping = false; 2502 2503 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2504 enable_sq_ramping = false; 2505 2506 for (i = 0; i < state->performance_level_count; i++) { 2507 sq_power_throttle = 0; 2508 sq_power_throttle2 = 0; 2509 2510 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && 2511 enable_sq_ramping) { 2512 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2513 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2514 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2515 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2516 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2517 } else { 2518 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2519 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2520 } 2521 2522 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2523 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2524 } 2525 2526 return 0; 2527 } 2528 2529 static int si_enable_power_containment(struct amdgpu_device *adev, 2530 struct amdgpu_ps *amdgpu_new_state, 2531 bool enable) 2532 { 2533 struct ni_power_info *ni_pi = ni_get_pi(adev); 2534 PPSMC_Result smc_result; 2535 int ret = 0; 2536 2537 if (ni_pi->enable_power_containment) { 2538 if (enable) { 2539 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2540 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2541 if (smc_result != PPSMC_Result_OK) { 2542 ret = -EINVAL; 2543 ni_pi->pc_enabled = false; 2544 } else { 2545 ni_pi->pc_enabled = true; 2546 } 2547 } 2548 } else { 2549 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2550 if (smc_result != PPSMC_Result_OK) 2551 ret = -EINVAL; 2552 ni_pi->pc_enabled = false; 2553 } 2554 } 2555 2556 return ret; 2557 } 2558 2559 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 2560 { 2561 struct si_power_info *si_pi = si_get_pi(adev); 2562 int ret = 0; 2563 struct si_dte_data *dte_data = &si_pi->dte_data; 2564 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2565 u32 table_size; 2566 u8 tdep_count; 2567 u32 i; 2568 2569 if (dte_data == NULL) 2570 si_pi->enable_dte = false; 2571 2572 if (si_pi->enable_dte == false) 2573 return 0; 2574 2575 if (dte_data->k <= 0) 2576 return -EINVAL; 2577 2578 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2579 if (dte_tables == NULL) { 2580 si_pi->enable_dte = false; 2581 return -ENOMEM; 2582 } 2583 2584 table_size = dte_data->k; 2585 2586 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2587 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2588 2589 tdep_count = dte_data->tdep_count; 2590 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2591 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2592 2593 dte_tables->K = cpu_to_be32(table_size); 2594 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2595 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2596 dte_tables->WindowSize = dte_data->window_size; 2597 dte_tables->temp_select = dte_data->temp_select; 2598 dte_tables->DTE_mode = dte_data->dte_mode; 2599 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2600 2601 if (tdep_count > 0) 2602 table_size--; 2603 2604 for (i = 0; i < table_size; i++) { 2605 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2606 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2607 } 2608 2609 dte_tables->Tdep_count = tdep_count; 2610 2611 for (i = 0; i < (u32)tdep_count; i++) { 2612 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2613 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2614 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2615 } 2616 2617 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2618 (u8 *)dte_tables, 2619 sizeof(Smc_SIslands_DTE_Configuration), 2620 si_pi->sram_end); 2621 kfree(dte_tables); 2622 2623 return ret; 2624 } 2625 2626 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, 2627 u16 *max, u16 *min) 2628 { 2629 struct si_power_info *si_pi = si_get_pi(adev); 2630 struct amdgpu_cac_leakage_table *table = 2631 &adev->pm.dpm.dyn_state.cac_leakage_table; 2632 u32 i; 2633 u32 v0_loadline; 2634 2635 if (table == NULL) 2636 return -EINVAL; 2637 2638 *max = 0; 2639 *min = 0xFFFF; 2640 2641 for (i = 0; i < table->count; i++) { 2642 if (table->entries[i].vddc > *max) 2643 *max = table->entries[i].vddc; 2644 if (table->entries[i].vddc < *min) 2645 *min = table->entries[i].vddc; 2646 } 2647 2648 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2649 return -EINVAL; 2650 2651 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2652 2653 if (v0_loadline > 0xFFFFUL) 2654 return -EINVAL; 2655 2656 *min = (u16)v0_loadline; 2657 2658 if ((*min > *max) || (*max == 0) || (*min == 0)) 2659 return -EINVAL; 2660 2661 return 0; 2662 } 2663 2664 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2665 { 2666 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2667 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2668 } 2669 2670 static int si_init_dte_leakage_table(struct amdgpu_device *adev, 2671 PP_SIslands_CacConfig *cac_tables, 2672 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2673 u16 t0, u16 t_step) 2674 { 2675 struct si_power_info *si_pi = si_get_pi(adev); 2676 u32 leakage; 2677 unsigned int i, j; 2678 s32 t; 2679 u32 smc_leakage; 2680 u32 scaling_factor; 2681 u16 voltage; 2682 2683 scaling_factor = si_get_smc_power_scaling_factor(adev); 2684 2685 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2686 t = (1000 * (i * t_step + t0)); 2687 2688 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2689 voltage = vddc_max - (vddc_step * j); 2690 2691 si_calculate_leakage_for_v_and_t(adev, 2692 &si_pi->powertune_data->leakage_coefficients, 2693 voltage, 2694 t, 2695 si_pi->dyn_powertune_data.cac_leakage, 2696 &leakage); 2697 2698 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2699 2700 if (smc_leakage > 0xFFFF) 2701 smc_leakage = 0xFFFF; 2702 2703 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2704 cpu_to_be16((u16)smc_leakage); 2705 } 2706 } 2707 return 0; 2708 } 2709 2710 static int si_init_simplified_leakage_table(struct amdgpu_device *adev, 2711 PP_SIslands_CacConfig *cac_tables, 2712 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2713 { 2714 struct si_power_info *si_pi = si_get_pi(adev); 2715 u32 leakage; 2716 unsigned int i, j; 2717 u32 smc_leakage; 2718 u32 scaling_factor; 2719 u16 voltage; 2720 2721 scaling_factor = si_get_smc_power_scaling_factor(adev); 2722 2723 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2724 voltage = vddc_max - (vddc_step * j); 2725 2726 si_calculate_leakage_for_v(adev, 2727 &si_pi->powertune_data->leakage_coefficients, 2728 si_pi->powertune_data->fixed_kt, 2729 voltage, 2730 si_pi->dyn_powertune_data.cac_leakage, 2731 &leakage); 2732 2733 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2734 2735 if (smc_leakage > 0xFFFF) 2736 smc_leakage = 0xFFFF; 2737 2738 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2739 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2740 cpu_to_be16((u16)smc_leakage); 2741 } 2742 return 0; 2743 } 2744 2745 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 2746 { 2747 struct ni_power_info *ni_pi = ni_get_pi(adev); 2748 struct si_power_info *si_pi = si_get_pi(adev); 2749 PP_SIslands_CacConfig *cac_tables = NULL; 2750 u16 vddc_max, vddc_min, vddc_step; 2751 u16 t0, t_step; 2752 u32 load_line_slope, reg; 2753 int ret = 0; 2754 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; 2755 2756 if (ni_pi->enable_cac == false) 2757 return 0; 2758 2759 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2760 if (!cac_tables) 2761 return -ENOMEM; 2762 2763 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2764 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2765 WREG32(CG_CAC_CTRL, reg); 2766 2767 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; 2768 si_pi->dyn_powertune_data.dc_pwr_value = 2769 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2770 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); 2771 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2772 2773 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2774 2775 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); 2776 if (ret) 2777 goto done_free; 2778 2779 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2780 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2781 t_step = 4; 2782 t0 = 60; 2783 2784 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2785 ret = si_init_dte_leakage_table(adev, cac_tables, 2786 vddc_max, vddc_min, vddc_step, 2787 t0, t_step); 2788 else 2789 ret = si_init_simplified_leakage_table(adev, cac_tables, 2790 vddc_max, vddc_min, vddc_step); 2791 if (ret) 2792 goto done_free; 2793 2794 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2795 2796 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2797 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2798 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2799 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2800 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2801 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2802 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2803 cac_tables->calculation_repeats = cpu_to_be32(2); 2804 cac_tables->dc_cac = cpu_to_be32(0); 2805 cac_tables->log2_PG_LKG_SCALE = 12; 2806 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2807 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2808 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2809 2810 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2811 (u8 *)cac_tables, 2812 sizeof(PP_SIslands_CacConfig), 2813 si_pi->sram_end); 2814 2815 if (ret) 2816 goto done_free; 2817 2818 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2819 2820 done_free: 2821 if (ret) { 2822 ni_pi->enable_cac = false; 2823 ni_pi->enable_power_containment = false; 2824 } 2825 2826 kfree(cac_tables); 2827 2828 return ret; 2829 } 2830 2831 static int si_program_cac_config_registers(struct amdgpu_device *adev, 2832 const struct si_cac_config_reg *cac_config_regs) 2833 { 2834 const struct si_cac_config_reg *config_regs = cac_config_regs; 2835 u32 data = 0, offset; 2836 2837 if (!config_regs) 2838 return -EINVAL; 2839 2840 while (config_regs->offset != 0xFFFFFFFF) { 2841 switch (config_regs->type) { 2842 case SISLANDS_CACCONFIG_CGIND: 2843 offset = SMC_CG_IND_START + config_regs->offset; 2844 if (offset < SMC_CG_IND_END) 2845 data = RREG32_SMC(offset); 2846 break; 2847 default: 2848 data = RREG32(config_regs->offset); 2849 break; 2850 } 2851 2852 data &= ~config_regs->mask; 2853 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2854 2855 switch (config_regs->type) { 2856 case SISLANDS_CACCONFIG_CGIND: 2857 offset = SMC_CG_IND_START + config_regs->offset; 2858 if (offset < SMC_CG_IND_END) 2859 WREG32_SMC(offset, data); 2860 break; 2861 default: 2862 WREG32(config_regs->offset, data); 2863 break; 2864 } 2865 config_regs++; 2866 } 2867 return 0; 2868 } 2869 2870 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) 2871 { 2872 struct ni_power_info *ni_pi = ni_get_pi(adev); 2873 struct si_power_info *si_pi = si_get_pi(adev); 2874 int ret; 2875 2876 if ((ni_pi->enable_cac == false) || 2877 (ni_pi->cac_configuration_required == false)) 2878 return 0; 2879 2880 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); 2881 if (ret) 2882 return ret; 2883 ret = si_program_cac_config_registers(adev, si_pi->cac_override); 2884 if (ret) 2885 return ret; 2886 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); 2887 if (ret) 2888 return ret; 2889 2890 return 0; 2891 } 2892 2893 static int si_enable_smc_cac(struct amdgpu_device *adev, 2894 struct amdgpu_ps *amdgpu_new_state, 2895 bool enable) 2896 { 2897 struct ni_power_info *ni_pi = ni_get_pi(adev); 2898 struct si_power_info *si_pi = si_get_pi(adev); 2899 PPSMC_Result smc_result; 2900 int ret = 0; 2901 2902 if (ni_pi->enable_cac) { 2903 if (enable) { 2904 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2905 if (ni_pi->support_cac_long_term_average) { 2906 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2907 if (smc_result != PPSMC_Result_OK) 2908 ni_pi->support_cac_long_term_average = false; 2909 } 2910 2911 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2912 if (smc_result != PPSMC_Result_OK) { 2913 ret = -EINVAL; 2914 ni_pi->cac_enabled = false; 2915 } else { 2916 ni_pi->cac_enabled = true; 2917 } 2918 2919 if (si_pi->enable_dte) { 2920 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2921 if (smc_result != PPSMC_Result_OK) 2922 ret = -EINVAL; 2923 } 2924 } 2925 } else if (ni_pi->cac_enabled) { 2926 if (si_pi->enable_dte) 2927 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2928 2929 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2930 2931 ni_pi->cac_enabled = false; 2932 2933 if (ni_pi->support_cac_long_term_average) 2934 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2935 } 2936 } 2937 return ret; 2938 } 2939 2940 static int si_init_smc_spll_table(struct amdgpu_device *adev) 2941 { 2942 struct ni_power_info *ni_pi = ni_get_pi(adev); 2943 struct si_power_info *si_pi = si_get_pi(adev); 2944 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2945 SISLANDS_SMC_SCLK_VALUE sclk_params; 2946 u32 fb_div, p_div; 2947 u32 clk_s, clk_v; 2948 u32 sclk = 0; 2949 int ret = 0; 2950 u32 tmp; 2951 int i; 2952 2953 if (si_pi->spll_table_start == 0) 2954 return -EINVAL; 2955 2956 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2957 if (spll_table == NULL) 2958 return -ENOMEM; 2959 2960 for (i = 0; i < 256; i++) { 2961 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); 2962 if (ret) 2963 break; 2964 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2965 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2966 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2967 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2968 2969 fb_div &= ~0x00001FFF; 2970 fb_div >>= 1; 2971 clk_v >>= 6; 2972 2973 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2974 ret = -EINVAL; 2975 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2976 ret = -EINVAL; 2977 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2978 ret = -EINVAL; 2979 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2980 ret = -EINVAL; 2981 2982 if (ret) 2983 break; 2984 2985 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2986 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2987 spll_table->freq[i] = cpu_to_be32(tmp); 2988 2989 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2990 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2991 spll_table->ss[i] = cpu_to_be32(tmp); 2992 2993 sclk += 512; 2994 } 2995 2996 2997 if (!ret) 2998 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 2999 (u8 *)spll_table, 3000 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3001 si_pi->sram_end); 3002 3003 if (ret) 3004 ni_pi->enable_power_containment = false; 3005 3006 kfree(spll_table); 3007 3008 return ret; 3009 } 3010 3011 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, 3012 u16 vce_voltage) 3013 { 3014 u16 highest_leakage = 0; 3015 struct si_power_info *si_pi = si_get_pi(adev); 3016 int i; 3017 3018 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 3019 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 3020 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 3021 } 3022 3023 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 3024 return highest_leakage; 3025 3026 return vce_voltage; 3027 } 3028 3029 static int si_get_vce_clock_voltage(struct amdgpu_device *adev, 3030 u32 evclk, u32 ecclk, u16 *voltage) 3031 { 3032 u32 i; 3033 int ret = -EINVAL; 3034 struct amdgpu_vce_clock_voltage_dependency_table *table = 3035 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3036 3037 if (((evclk == 0) && (ecclk == 0)) || 3038 (table && (table->count == 0))) { 3039 *voltage = 0; 3040 return 0; 3041 } 3042 3043 for (i = 0; i < table->count; i++) { 3044 if ((evclk <= table->entries[i].evclk) && 3045 (ecclk <= table->entries[i].ecclk)) { 3046 *voltage = table->entries[i].v; 3047 ret = 0; 3048 break; 3049 } 3050 } 3051 3052 /* if no match return the highest voltage */ 3053 if (ret) 3054 *voltage = table->entries[table->count - 1].v; 3055 3056 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); 3057 3058 return ret; 3059 } 3060 3061 static bool si_dpm_vblank_too_short(void *handle) 3062 { 3063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3064 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); 3065 /* we never hit the non-gddr5 limit so disable it */ 3066 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3067 3068 if (vblank_time < switch_limit) 3069 return true; 3070 else 3071 return false; 3072 3073 } 3074 3075 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, 3076 u32 arb_freq_src, u32 arb_freq_dest) 3077 { 3078 u32 mc_arb_dram_timing; 3079 u32 mc_arb_dram_timing2; 3080 u32 burst_time; 3081 u32 mc_cg_config; 3082 3083 switch (arb_freq_src) { 3084 case MC_CG_ARB_FREQ_F0: 3085 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 3086 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3087 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 3088 break; 3089 case MC_CG_ARB_FREQ_F1: 3090 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 3091 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3092 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 3093 break; 3094 case MC_CG_ARB_FREQ_F2: 3095 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 3096 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3097 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 3098 break; 3099 case MC_CG_ARB_FREQ_F3: 3100 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 3101 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3102 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 3103 break; 3104 default: 3105 return -EINVAL; 3106 } 3107 3108 switch (arb_freq_dest) { 3109 case MC_CG_ARB_FREQ_F0: 3110 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 3111 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3112 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 3113 break; 3114 case MC_CG_ARB_FREQ_F1: 3115 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 3116 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3117 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 3118 break; 3119 case MC_CG_ARB_FREQ_F2: 3120 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 3121 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 3122 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 3123 break; 3124 case MC_CG_ARB_FREQ_F3: 3125 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 3126 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 3127 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 3128 break; 3129 default: 3130 return -EINVAL; 3131 } 3132 3133 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 3134 WREG32(MC_CG_CONFIG, mc_cg_config); 3135 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 3136 3137 return 0; 3138 } 3139 3140 static void ni_update_current_ps(struct amdgpu_device *adev, 3141 struct amdgpu_ps *rps) 3142 { 3143 struct si_ps *new_ps = si_get_ps(rps); 3144 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3145 struct ni_power_info *ni_pi = ni_get_pi(adev); 3146 3147 eg_pi->current_rps = *rps; 3148 ni_pi->current_ps = *new_ps; 3149 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3150 adev->pm.dpm.current_ps = &eg_pi->current_rps; 3151 } 3152 3153 static void ni_update_requested_ps(struct amdgpu_device *adev, 3154 struct amdgpu_ps *rps) 3155 { 3156 struct si_ps *new_ps = si_get_ps(rps); 3157 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3158 struct ni_power_info *ni_pi = ni_get_pi(adev); 3159 3160 eg_pi->requested_rps = *rps; 3161 ni_pi->requested_ps = *new_ps; 3162 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3163 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; 3164 } 3165 3166 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, 3167 struct amdgpu_ps *new_ps, 3168 struct amdgpu_ps *old_ps) 3169 { 3170 struct si_ps *new_state = si_get_ps(new_ps); 3171 struct si_ps *current_state = si_get_ps(old_ps); 3172 3173 if ((new_ps->vclk == old_ps->vclk) && 3174 (new_ps->dclk == old_ps->dclk)) 3175 return; 3176 3177 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3178 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3179 return; 3180 3181 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3182 } 3183 3184 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, 3185 struct amdgpu_ps *new_ps, 3186 struct amdgpu_ps *old_ps) 3187 { 3188 struct si_ps *new_state = si_get_ps(new_ps); 3189 struct si_ps *current_state = si_get_ps(old_ps); 3190 3191 if ((new_ps->vclk == old_ps->vclk) && 3192 (new_ps->dclk == old_ps->dclk)) 3193 return; 3194 3195 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3196 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3197 return; 3198 3199 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3200 } 3201 3202 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 3203 { 3204 unsigned int i; 3205 3206 for (i = 0; i < table->count; i++) 3207 if (voltage <= table->entries[i].value) 3208 return table->entries[i].value; 3209 3210 return table->entries[table->count - 1].value; 3211 } 3212 3213 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, 3214 u32 max_clock, u32 requested_clock) 3215 { 3216 unsigned int i; 3217 3218 if ((clocks == NULL) || (clocks->count == 0)) 3219 return (requested_clock < max_clock) ? requested_clock : max_clock; 3220 3221 for (i = 0; i < clocks->count; i++) { 3222 if (clocks->values[i] >= requested_clock) 3223 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 3224 } 3225 3226 return (clocks->values[clocks->count - 1] < max_clock) ? 3227 clocks->values[clocks->count - 1] : max_clock; 3228 } 3229 3230 static u32 btc_get_valid_mclk(struct amdgpu_device *adev, 3231 u32 max_mclk, u32 requested_mclk) 3232 { 3233 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, 3234 max_mclk, requested_mclk); 3235 } 3236 3237 static u32 btc_get_valid_sclk(struct amdgpu_device *adev, 3238 u32 max_sclk, u32 requested_sclk) 3239 { 3240 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, 3241 max_sclk, requested_sclk); 3242 } 3243 3244 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, 3245 u32 *max_clock) 3246 { 3247 u32 i, clock = 0; 3248 3249 if ((table == NULL) || (table->count == 0)) { 3250 *max_clock = clock; 3251 return; 3252 } 3253 3254 for (i = 0; i < table->count; i++) { 3255 if (clock < table->entries[i].clk) 3256 clock = table->entries[i].clk; 3257 } 3258 *max_clock = clock; 3259 } 3260 3261 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, 3262 u32 clock, u16 max_voltage, u16 *voltage) 3263 { 3264 u32 i; 3265 3266 if ((table == NULL) || (table->count == 0)) 3267 return; 3268 3269 for (i= 0; i < table->count; i++) { 3270 if (clock <= table->entries[i].clk) { 3271 if (*voltage < table->entries[i].v) 3272 *voltage = (u16)((table->entries[i].v < max_voltage) ? 3273 table->entries[i].v : max_voltage); 3274 return; 3275 } 3276 } 3277 3278 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 3279 } 3280 3281 static void btc_adjust_clock_combinations(struct amdgpu_device *adev, 3282 const struct amdgpu_clock_and_voltage_limits *max_limits, 3283 struct rv7xx_pl *pl) 3284 { 3285 3286 if ((pl->mclk == 0) || (pl->sclk == 0)) 3287 return; 3288 3289 if (pl->mclk == pl->sclk) 3290 return; 3291 3292 if (pl->mclk > pl->sclk) { 3293 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) 3294 pl->sclk = btc_get_valid_sclk(adev, 3295 max_limits->sclk, 3296 (pl->mclk + 3297 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 3298 adev->pm.dpm.dyn_state.mclk_sclk_ratio); 3299 } else { 3300 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) 3301 pl->mclk = btc_get_valid_mclk(adev, 3302 max_limits->mclk, 3303 pl->sclk - 3304 adev->pm.dpm.dyn_state.sclk_mclk_delta); 3305 } 3306 } 3307 3308 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, 3309 u16 max_vddc, u16 max_vddci, 3310 u16 *vddc, u16 *vddci) 3311 { 3312 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3313 u16 new_voltage; 3314 3315 if ((0 == *vddc) || (0 == *vddci)) 3316 return; 3317 3318 if (*vddc > *vddci) { 3319 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3320 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 3321 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3322 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 3323 } 3324 } else { 3325 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3326 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 3327 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3328 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 3329 } 3330 } 3331 } 3332 3333 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3334 u32 *p, u32 *u) 3335 { 3336 u32 b_c = 0; 3337 u32 i_c; 3338 u32 tmp; 3339 3340 i_c = (i * r_c) / 100; 3341 tmp = i_c >> p_b; 3342 3343 while (tmp) { 3344 b_c++; 3345 tmp >>= 1; 3346 } 3347 3348 *u = (b_c + 1) / 2; 3349 *p = i_c / (1 << (2 * (*u))); 3350 } 3351 3352 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 3353 { 3354 u32 k, a, ah, al; 3355 u32 t1; 3356 3357 if ((fl == 0) || (fh == 0) || (fl > fh)) 3358 return -EINVAL; 3359 3360 k = (100 * fh) / fl; 3361 t1 = (t * (k - 100)); 3362 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 3363 a = (a + 5) / 10; 3364 ah = ((a * t) + 5000) / 10000; 3365 al = a - ah; 3366 3367 *th = t - ah; 3368 *tl = t + al; 3369 3370 return 0; 3371 } 3372 3373 static bool r600_is_uvd_state(u32 class, u32 class2) 3374 { 3375 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3376 return true; 3377 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 3378 return true; 3379 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 3380 return true; 3381 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 3382 return true; 3383 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 3384 return true; 3385 return false; 3386 } 3387 3388 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) 3389 { 3390 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); 3391 } 3392 3393 static void rv770_get_max_vddc(struct amdgpu_device *adev) 3394 { 3395 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3396 u16 vddc; 3397 3398 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) 3399 pi->max_vddc = 0; 3400 else 3401 pi->max_vddc = vddc; 3402 } 3403 3404 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) 3405 { 3406 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3407 struct amdgpu_atom_ss ss; 3408 3409 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3410 ASIC_INTERNAL_ENGINE_SS, 0); 3411 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3412 ASIC_INTERNAL_MEMORY_SS, 0); 3413 3414 if (pi->sclk_ss || pi->mclk_ss) 3415 pi->dynamic_ss = true; 3416 else 3417 pi->dynamic_ss = false; 3418 } 3419 3420 3421 static void si_apply_state_adjust_rules(struct amdgpu_device *adev, 3422 struct amdgpu_ps *rps) 3423 { 3424 struct si_ps *ps = si_get_ps(rps); 3425 struct amdgpu_clock_and_voltage_limits *max_limits; 3426 bool disable_mclk_switching = false; 3427 bool disable_sclk_switching = false; 3428 u32 mclk, sclk; 3429 u16 vddc, vddci, min_vce_voltage = 0; 3430 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3431 u32 max_sclk = 0, max_mclk = 0; 3432 int i; 3433 3434 if (adev->asic_type == CHIP_HAINAN) { 3435 if ((adev->pdev->revision == 0x81) || 3436 (adev->pdev->revision == 0xC3) || 3437 (adev->pdev->device == 0x6664) || 3438 (adev->pdev->device == 0x6665) || 3439 (adev->pdev->device == 0x6667)) { 3440 max_sclk = 75000; 3441 } 3442 if ((adev->pdev->revision == 0xC3) || 3443 (adev->pdev->device == 0x6665)) { 3444 max_sclk = 60000; 3445 max_mclk = 80000; 3446 } 3447 } else if (adev->asic_type == CHIP_OLAND) { 3448 if ((adev->pdev->revision == 0xC7) || 3449 (adev->pdev->revision == 0x80) || 3450 (adev->pdev->revision == 0x81) || 3451 (adev->pdev->revision == 0x83) || 3452 (adev->pdev->revision == 0x87) || 3453 (adev->pdev->device == 0x6604) || 3454 (adev->pdev->device == 0x6605)) { 3455 max_sclk = 75000; 3456 } 3457 } 3458 3459 if (rps->vce_active) { 3460 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3461 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 3462 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, 3463 &min_vce_voltage); 3464 } else { 3465 rps->evclk = 0; 3466 rps->ecclk = 0; 3467 } 3468 3469 if ((adev->pm.dpm.new_active_crtc_count > 1) || 3470 si_dpm_vblank_too_short(adev)) 3471 disable_mclk_switching = true; 3472 3473 if (rps->vclk || rps->dclk) { 3474 disable_mclk_switching = true; 3475 disable_sclk_switching = true; 3476 } 3477 3478 if (adev->pm.ac_power) 3479 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3480 else 3481 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3482 3483 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3484 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3485 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3486 } 3487 if (adev->pm.ac_power == false) { 3488 for (i = 0; i < ps->performance_level_count; i++) { 3489 if (ps->performance_levels[i].mclk > max_limits->mclk) 3490 ps->performance_levels[i].mclk = max_limits->mclk; 3491 if (ps->performance_levels[i].sclk > max_limits->sclk) 3492 ps->performance_levels[i].sclk = max_limits->sclk; 3493 if (ps->performance_levels[i].vddc > max_limits->vddc) 3494 ps->performance_levels[i].vddc = max_limits->vddc; 3495 if (ps->performance_levels[i].vddci > max_limits->vddci) 3496 ps->performance_levels[i].vddci = max_limits->vddci; 3497 } 3498 } 3499 3500 /* limit clocks to max supported clocks based on voltage dependency tables */ 3501 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3502 &max_sclk_vddc); 3503 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3504 &max_mclk_vddci); 3505 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3506 &max_mclk_vddc); 3507 3508 for (i = 0; i < ps->performance_level_count; i++) { 3509 if (max_sclk_vddc) { 3510 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3511 ps->performance_levels[i].sclk = max_sclk_vddc; 3512 } 3513 if (max_mclk_vddci) { 3514 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3515 ps->performance_levels[i].mclk = max_mclk_vddci; 3516 } 3517 if (max_mclk_vddc) { 3518 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3519 ps->performance_levels[i].mclk = max_mclk_vddc; 3520 } 3521 if (max_mclk) { 3522 if (ps->performance_levels[i].mclk > max_mclk) 3523 ps->performance_levels[i].mclk = max_mclk; 3524 } 3525 if (max_sclk) { 3526 if (ps->performance_levels[i].sclk > max_sclk) 3527 ps->performance_levels[i].sclk = max_sclk; 3528 } 3529 } 3530 3531 /* XXX validate the min clocks required for display */ 3532 3533 if (disable_mclk_switching) { 3534 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3535 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3536 } else { 3537 mclk = ps->performance_levels[0].mclk; 3538 vddci = ps->performance_levels[0].vddci; 3539 } 3540 3541 if (disable_sclk_switching) { 3542 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3543 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3544 } else { 3545 sclk = ps->performance_levels[0].sclk; 3546 vddc = ps->performance_levels[0].vddc; 3547 } 3548 3549 if (rps->vce_active) { 3550 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 3551 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 3552 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) 3553 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; 3554 } 3555 3556 /* adjusted low state */ 3557 ps->performance_levels[0].sclk = sclk; 3558 ps->performance_levels[0].mclk = mclk; 3559 ps->performance_levels[0].vddc = vddc; 3560 ps->performance_levels[0].vddci = vddci; 3561 3562 if (disable_sclk_switching) { 3563 sclk = ps->performance_levels[0].sclk; 3564 for (i = 1; i < ps->performance_level_count; i++) { 3565 if (sclk < ps->performance_levels[i].sclk) 3566 sclk = ps->performance_levels[i].sclk; 3567 } 3568 for (i = 0; i < ps->performance_level_count; i++) { 3569 ps->performance_levels[i].sclk = sclk; 3570 ps->performance_levels[i].vddc = vddc; 3571 } 3572 } else { 3573 for (i = 1; i < ps->performance_level_count; i++) { 3574 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3575 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3576 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3577 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3578 } 3579 } 3580 3581 if (disable_mclk_switching) { 3582 mclk = ps->performance_levels[0].mclk; 3583 for (i = 1; i < ps->performance_level_count; i++) { 3584 if (mclk < ps->performance_levels[i].mclk) 3585 mclk = ps->performance_levels[i].mclk; 3586 } 3587 for (i = 0; i < ps->performance_level_count; i++) { 3588 ps->performance_levels[i].mclk = mclk; 3589 ps->performance_levels[i].vddci = vddci; 3590 } 3591 } else { 3592 for (i = 1; i < ps->performance_level_count; i++) { 3593 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3594 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3595 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3596 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3597 } 3598 } 3599 3600 for (i = 0; i < ps->performance_level_count; i++) 3601 btc_adjust_clock_combinations(adev, max_limits, 3602 &ps->performance_levels[i]); 3603 3604 for (i = 0; i < ps->performance_level_count; i++) { 3605 if (ps->performance_levels[i].vddc < min_vce_voltage) 3606 ps->performance_levels[i].vddc = min_vce_voltage; 3607 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3608 ps->performance_levels[i].sclk, 3609 max_limits->vddc, &ps->performance_levels[i].vddc); 3610 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3611 ps->performance_levels[i].mclk, 3612 max_limits->vddci, &ps->performance_levels[i].vddci); 3613 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3614 ps->performance_levels[i].mclk, 3615 max_limits->vddc, &ps->performance_levels[i].vddc); 3616 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3617 adev->clock.current_dispclk, 3618 max_limits->vddc, &ps->performance_levels[i].vddc); 3619 } 3620 3621 for (i = 0; i < ps->performance_level_count; i++) { 3622 btc_apply_voltage_delta_rules(adev, 3623 max_limits->vddc, max_limits->vddci, 3624 &ps->performance_levels[i].vddc, 3625 &ps->performance_levels[i].vddci); 3626 } 3627 3628 ps->dc_compatible = true; 3629 for (i = 0; i < ps->performance_level_count; i++) { 3630 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3631 ps->dc_compatible = false; 3632 } 3633 } 3634 3635 #if 0 3636 static int si_read_smc_soft_register(struct amdgpu_device *adev, 3637 u16 reg_offset, u32 *value) 3638 { 3639 struct si_power_info *si_pi = si_get_pi(adev); 3640 3641 return amdgpu_si_read_smc_sram_dword(adev, 3642 si_pi->soft_regs_start + reg_offset, value, 3643 si_pi->sram_end); 3644 } 3645 #endif 3646 3647 static int si_write_smc_soft_register(struct amdgpu_device *adev, 3648 u16 reg_offset, u32 value) 3649 { 3650 struct si_power_info *si_pi = si_get_pi(adev); 3651 3652 return amdgpu_si_write_smc_sram_dword(adev, 3653 si_pi->soft_regs_start + reg_offset, 3654 value, si_pi->sram_end); 3655 } 3656 3657 static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3658 { 3659 bool ret = false; 3660 u32 tmp, width, row, column, bank, density; 3661 bool is_memory_gddr5, is_special; 3662 3663 tmp = RREG32(MC_SEQ_MISC0); 3664 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3665 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3666 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3667 3668 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3669 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3670 3671 tmp = RREG32(MC_ARB_RAMCFG); 3672 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3673 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3674 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3675 3676 density = (1 << (row + column - 20 + bank)) * width; 3677 3678 if ((adev->pdev->device == 0x6819) && 3679 is_memory_gddr5 && is_special && (density == 0x400)) 3680 ret = true; 3681 3682 return ret; 3683 } 3684 3685 static void si_get_leakage_vddc(struct amdgpu_device *adev) 3686 { 3687 struct si_power_info *si_pi = si_get_pi(adev); 3688 u16 vddc, count = 0; 3689 int i, ret; 3690 3691 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3692 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3693 3694 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3695 si_pi->leakage_voltage.entries[count].voltage = vddc; 3696 si_pi->leakage_voltage.entries[count].leakage_index = 3697 SISLANDS_LEAKAGE_INDEX0 + i; 3698 count++; 3699 } 3700 } 3701 si_pi->leakage_voltage.count = count; 3702 } 3703 3704 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, 3705 u32 index, u16 *leakage_voltage) 3706 { 3707 struct si_power_info *si_pi = si_get_pi(adev); 3708 int i; 3709 3710 if (leakage_voltage == NULL) 3711 return -EINVAL; 3712 3713 if ((index & 0xff00) != 0xff00) 3714 return -EINVAL; 3715 3716 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3717 return -EINVAL; 3718 3719 if (index < SISLANDS_LEAKAGE_INDEX0) 3720 return -EINVAL; 3721 3722 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3723 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3724 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3725 return 0; 3726 } 3727 } 3728 return -EAGAIN; 3729 } 3730 3731 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) 3732 { 3733 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3734 bool want_thermal_protection; 3735 enum si_dpm_event_src dpm_event_src; 3736 3737 switch (sources) { 3738 case 0: 3739 default: 3740 want_thermal_protection = false; 3741 break; 3742 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL): 3743 want_thermal_protection = true; 3744 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL; 3745 break; 3746 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3747 want_thermal_protection = true; 3748 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL; 3749 break; 3750 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3751 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3752 want_thermal_protection = true; 3753 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3754 break; 3755 } 3756 3757 if (want_thermal_protection) { 3758 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3759 if (pi->thermal_protection) 3760 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3761 } else { 3762 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3763 } 3764 } 3765 3766 static void si_enable_auto_throttle_source(struct amdgpu_device *adev, 3767 enum si_dpm_auto_throttle_src source, 3768 bool enable) 3769 { 3770 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3771 3772 if (enable) { 3773 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3774 pi->active_auto_throttle_sources |= 1 << source; 3775 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3776 } 3777 } else { 3778 if (pi->active_auto_throttle_sources & (1 << source)) { 3779 pi->active_auto_throttle_sources &= ~(1 << source); 3780 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3781 } 3782 } 3783 } 3784 3785 static void si_start_dpm(struct amdgpu_device *adev) 3786 { 3787 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3788 } 3789 3790 static void si_stop_dpm(struct amdgpu_device *adev) 3791 { 3792 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3793 } 3794 3795 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) 3796 { 3797 if (enable) 3798 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3799 else 3800 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3801 3802 } 3803 3804 #if 0 3805 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 3806 u32 thermal_level) 3807 { 3808 PPSMC_Result ret; 3809 3810 if (thermal_level == 0) { 3811 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3812 if (ret == PPSMC_Result_OK) 3813 return 0; 3814 else 3815 return -EINVAL; 3816 } 3817 return 0; 3818 } 3819 3820 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 3821 { 3822 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3823 } 3824 #endif 3825 3826 #if 0 3827 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power) 3828 { 3829 if (ac_power) 3830 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3831 0 : -EINVAL; 3832 3833 return 0; 3834 } 3835 #endif 3836 3837 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 3838 PPSMC_Msg msg, u32 parameter) 3839 { 3840 WREG32(SMC_SCRATCH0, parameter); 3841 return amdgpu_si_send_msg_to_smc(adev, msg); 3842 } 3843 3844 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3845 { 3846 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3847 return -EINVAL; 3848 3849 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3850 0 : -EINVAL; 3851 } 3852 3853 static int si_dpm_force_performance_level(void *handle, 3854 enum amd_dpm_forced_level level) 3855 { 3856 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3857 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3858 struct si_ps *ps = si_get_ps(rps); 3859 u32 levels = ps->performance_level_count; 3860 3861 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 3862 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3863 return -EINVAL; 3864 3865 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3866 return -EINVAL; 3867 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 3868 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3869 return -EINVAL; 3870 3871 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3872 return -EINVAL; 3873 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 3874 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3875 return -EINVAL; 3876 3877 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3878 return -EINVAL; 3879 } 3880 3881 adev->pm.dpm.forced_level = level; 3882 3883 return 0; 3884 } 3885 3886 #if 0 3887 static int si_set_boot_state(struct amdgpu_device *adev) 3888 { 3889 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3890 0 : -EINVAL; 3891 } 3892 #endif 3893 3894 static int si_set_powergating_by_smu(void *handle, 3895 uint32_t block_type, 3896 bool gate) 3897 { 3898 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3899 3900 switch (block_type) { 3901 case AMD_IP_BLOCK_TYPE_UVD: 3902 if (!gate) { 3903 adev->pm.dpm.uvd_active = true; 3904 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; 3905 } else { 3906 adev->pm.dpm.uvd_active = false; 3907 } 3908 3909 amdgpu_legacy_dpm_compute_clocks(handle); 3910 break; 3911 case AMD_IP_BLOCK_TYPE_VCE: 3912 if (!gate) { 3913 adev->pm.dpm.vce_active = true; 3914 /* XXX select vce level based on ring/task */ 3915 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 3916 } else { 3917 adev->pm.dpm.vce_active = false; 3918 } 3919 3920 amdgpu_legacy_dpm_compute_clocks(handle); 3921 break; 3922 default: 3923 break; 3924 } 3925 return 0; 3926 } 3927 3928 static int si_set_sw_state(struct amdgpu_device *adev) 3929 { 3930 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3931 0 : -EINVAL; 3932 } 3933 3934 static int si_halt_smc(struct amdgpu_device *adev) 3935 { 3936 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3937 return -EINVAL; 3938 3939 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3940 0 : -EINVAL; 3941 } 3942 3943 static int si_resume_smc(struct amdgpu_device *adev) 3944 { 3945 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3946 return -EINVAL; 3947 3948 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3949 0 : -EINVAL; 3950 } 3951 3952 static void si_dpm_start_smc(struct amdgpu_device *adev) 3953 { 3954 amdgpu_si_program_jump_on_start(adev); 3955 amdgpu_si_start_smc(adev); 3956 amdgpu_si_smc_clock(adev, true); 3957 } 3958 3959 static void si_dpm_stop_smc(struct amdgpu_device *adev) 3960 { 3961 amdgpu_si_reset_smc(adev); 3962 amdgpu_si_smc_clock(adev, false); 3963 } 3964 3965 static int si_process_firmware_header(struct amdgpu_device *adev) 3966 { 3967 struct si_power_info *si_pi = si_get_pi(adev); 3968 u32 tmp; 3969 int ret; 3970 3971 ret = amdgpu_si_read_smc_sram_dword(adev, 3972 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3973 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3974 &tmp, si_pi->sram_end); 3975 if (ret) 3976 return ret; 3977 3978 si_pi->state_table_start = tmp; 3979 3980 ret = amdgpu_si_read_smc_sram_dword(adev, 3981 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3982 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3983 &tmp, si_pi->sram_end); 3984 if (ret) 3985 return ret; 3986 3987 si_pi->soft_regs_start = tmp; 3988 3989 ret = amdgpu_si_read_smc_sram_dword(adev, 3990 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3991 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3992 &tmp, si_pi->sram_end); 3993 if (ret) 3994 return ret; 3995 3996 si_pi->mc_reg_table_start = tmp; 3997 3998 ret = amdgpu_si_read_smc_sram_dword(adev, 3999 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4000 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 4001 &tmp, si_pi->sram_end); 4002 if (ret) 4003 return ret; 4004 4005 si_pi->fan_table_start = tmp; 4006 4007 ret = amdgpu_si_read_smc_sram_dword(adev, 4008 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4009 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4010 &tmp, si_pi->sram_end); 4011 if (ret) 4012 return ret; 4013 4014 si_pi->arb_table_start = tmp; 4015 4016 ret = amdgpu_si_read_smc_sram_dword(adev, 4017 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4018 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4019 &tmp, si_pi->sram_end); 4020 if (ret) 4021 return ret; 4022 4023 si_pi->cac_table_start = tmp; 4024 4025 ret = amdgpu_si_read_smc_sram_dword(adev, 4026 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4027 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4028 &tmp, si_pi->sram_end); 4029 if (ret) 4030 return ret; 4031 4032 si_pi->dte_table_start = tmp; 4033 4034 ret = amdgpu_si_read_smc_sram_dword(adev, 4035 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4036 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4037 &tmp, si_pi->sram_end); 4038 if (ret) 4039 return ret; 4040 4041 si_pi->spll_table_start = tmp; 4042 4043 ret = amdgpu_si_read_smc_sram_dword(adev, 4044 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4045 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4046 &tmp, si_pi->sram_end); 4047 if (ret) 4048 return ret; 4049 4050 si_pi->papm_cfg_table_start = tmp; 4051 4052 return ret; 4053 } 4054 4055 static void si_read_clock_registers(struct amdgpu_device *adev) 4056 { 4057 struct si_power_info *si_pi = si_get_pi(adev); 4058 4059 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 4060 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 4061 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 4062 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 4063 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 4064 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 4065 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 4066 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 4067 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 4068 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 4069 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 4070 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 4071 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 4072 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 4073 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 4074 } 4075 4076 static void si_enable_thermal_protection(struct amdgpu_device *adev, 4077 bool enable) 4078 { 4079 if (enable) 4080 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 4081 else 4082 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 4083 } 4084 4085 static void si_enable_acpi_power_management(struct amdgpu_device *adev) 4086 { 4087 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 4088 } 4089 4090 #if 0 4091 static int si_enter_ulp_state(struct amdgpu_device *adev) 4092 { 4093 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 4094 4095 udelay(25000); 4096 4097 return 0; 4098 } 4099 4100 static int si_exit_ulp_state(struct amdgpu_device *adev) 4101 { 4102 int i; 4103 4104 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 4105 4106 udelay(7000); 4107 4108 for (i = 0; i < adev->usec_timeout; i++) { 4109 if (RREG32(SMC_RESP_0) == 1) 4110 break; 4111 udelay(1000); 4112 } 4113 4114 return 0; 4115 } 4116 #endif 4117 4118 static int si_notify_smc_display_change(struct amdgpu_device *adev, 4119 bool has_display) 4120 { 4121 PPSMC_Msg msg = has_display ? 4122 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4123 4124 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4125 0 : -EINVAL; 4126 } 4127 4128 static void si_program_response_times(struct amdgpu_device *adev) 4129 { 4130 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 4131 u32 vddc_dly, acpi_dly, vbi_dly; 4132 u32 reference_clock; 4133 4134 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 4135 4136 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; 4137 4138 if (voltage_response_time == 0) 4139 voltage_response_time = 1000; 4140 4141 acpi_delay_time = 15000; 4142 vbi_time_out = 100000; 4143 4144 reference_clock = amdgpu_asic_get_xclk(adev); 4145 4146 vddc_dly = (voltage_response_time * reference_clock) / 100; 4147 acpi_dly = (acpi_delay_time * reference_clock) / 100; 4148 vbi_dly = (vbi_time_out * reference_clock) / 100; 4149 4150 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 4151 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 4152 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 4153 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 4154 } 4155 4156 static void si_program_ds_registers(struct amdgpu_device *adev) 4157 { 4158 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4159 u32 tmp; 4160 4161 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ 4162 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) 4163 tmp = 0x10; 4164 else 4165 tmp = 0x1; 4166 4167 if (eg_pi->sclk_deep_sleep) { 4168 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 4169 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 4170 ~AUTOSCALE_ON_SS_CLEAR); 4171 } 4172 } 4173 4174 static void si_program_display_gap(struct amdgpu_device *adev) 4175 { 4176 u32 tmp, pipe; 4177 int i; 4178 4179 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 4180 if (adev->pm.dpm.new_active_crtc_count > 0) 4181 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 4182 else 4183 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 4184 4185 if (adev->pm.dpm.new_active_crtc_count > 1) 4186 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 4187 else 4188 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 4189 4190 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 4191 4192 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 4193 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 4194 4195 if ((adev->pm.dpm.new_active_crtc_count > 0) && 4196 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 4197 /* find the first active crtc */ 4198 for (i = 0; i < adev->mode_info.num_crtc; i++) { 4199 if (adev->pm.dpm.new_active_crtcs & (1 << i)) 4200 break; 4201 } 4202 if (i == adev->mode_info.num_crtc) 4203 pipe = 0; 4204 else 4205 pipe = i; 4206 4207 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 4208 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 4209 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 4210 } 4211 4212 /* Setting this to false forces the performance state to low if the crtcs are disabled. 4213 * This can be a problem on PowerXpress systems or if you want to use the card 4214 * for offscreen rendering or compute if there are no crtcs enabled. 4215 */ 4216 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0); 4217 } 4218 4219 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) 4220 { 4221 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4222 4223 if (enable) { 4224 if (pi->sclk_ss) 4225 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 4226 } else { 4227 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 4228 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 4229 } 4230 } 4231 4232 static void si_setup_bsp(struct amdgpu_device *adev) 4233 { 4234 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4235 u32 xclk = amdgpu_asic_get_xclk(adev); 4236 4237 r600_calculate_u_and_p(pi->asi, 4238 xclk, 4239 16, 4240 &pi->bsp, 4241 &pi->bsu); 4242 4243 r600_calculate_u_and_p(pi->pasi, 4244 xclk, 4245 16, 4246 &pi->pbsp, 4247 &pi->pbsu); 4248 4249 4250 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 4251 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 4252 4253 WREG32(CG_BSP, pi->dsp); 4254 } 4255 4256 static void si_program_git(struct amdgpu_device *adev) 4257 { 4258 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 4259 } 4260 4261 static void si_program_tp(struct amdgpu_device *adev) 4262 { 4263 int i; 4264 enum r600_td td = R600_TD_DFLT; 4265 4266 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 4267 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 4268 4269 if (td == R600_TD_AUTO) 4270 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 4271 else 4272 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 4273 4274 if (td == R600_TD_UP) 4275 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 4276 4277 if (td == R600_TD_DOWN) 4278 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 4279 } 4280 4281 static void si_program_tpp(struct amdgpu_device *adev) 4282 { 4283 WREG32(CG_TPC, R600_TPC_DFLT); 4284 } 4285 4286 static void si_program_sstp(struct amdgpu_device *adev) 4287 { 4288 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 4289 } 4290 4291 static void si_enable_display_gap(struct amdgpu_device *adev) 4292 { 4293 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 4294 4295 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 4296 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 4297 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 4298 4299 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 4300 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 4301 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 4302 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 4303 } 4304 4305 static void si_program_vc(struct amdgpu_device *adev) 4306 { 4307 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4308 4309 WREG32(CG_FTV, pi->vrc); 4310 } 4311 4312 static void si_clear_vc(struct amdgpu_device *adev) 4313 { 4314 WREG32(CG_FTV, 0); 4315 } 4316 4317 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 4318 { 4319 u8 mc_para_index; 4320 4321 if (memory_clock < 10000) 4322 mc_para_index = 0; 4323 else if (memory_clock >= 80000) 4324 mc_para_index = 0x0f; 4325 else 4326 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4327 return mc_para_index; 4328 } 4329 4330 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 4331 { 4332 u8 mc_para_index; 4333 4334 if (strobe_mode) { 4335 if (memory_clock < 12500) 4336 mc_para_index = 0x00; 4337 else if (memory_clock > 47500) 4338 mc_para_index = 0x0f; 4339 else 4340 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4341 } else { 4342 if (memory_clock < 65000) 4343 mc_para_index = 0x00; 4344 else if (memory_clock > 135000) 4345 mc_para_index = 0x0f; 4346 else 4347 mc_para_index = (u8)((memory_clock - 60000) / 5000); 4348 } 4349 return mc_para_index; 4350 } 4351 4352 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) 4353 { 4354 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4355 bool strobe_mode = false; 4356 u8 result = 0; 4357 4358 if (mclk <= pi->mclk_strobe_mode_threshold) 4359 strobe_mode = true; 4360 4361 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4362 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4363 else 4364 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4365 4366 if (strobe_mode) 4367 result |= SISLANDS_SMC_STROBE_ENABLE; 4368 4369 return result; 4370 } 4371 4372 static int si_upload_firmware(struct amdgpu_device *adev) 4373 { 4374 struct si_power_info *si_pi = si_get_pi(adev); 4375 4376 amdgpu_si_reset_smc(adev); 4377 amdgpu_si_smc_clock(adev, false); 4378 4379 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4380 } 4381 4382 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4383 const struct atom_voltage_table *table, 4384 const struct amdgpu_phase_shedding_limits_table *limits) 4385 { 4386 u32 data, num_bits, num_levels; 4387 4388 if ((table == NULL) || (limits == NULL)) 4389 return false; 4390 4391 data = table->mask_low; 4392 4393 num_bits = hweight32(data); 4394 4395 if (num_bits == 0) 4396 return false; 4397 4398 num_levels = (1 << num_bits); 4399 4400 if (table->count != num_levels) 4401 return false; 4402 4403 if (limits->count != (num_levels - 1)) 4404 return false; 4405 4406 return true; 4407 } 4408 4409 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, 4410 u32 max_voltage_steps, 4411 struct atom_voltage_table *voltage_table) 4412 { 4413 unsigned int i, diff; 4414 4415 if (voltage_table->count <= max_voltage_steps) 4416 return; 4417 4418 diff = voltage_table->count - max_voltage_steps; 4419 4420 for (i= 0; i < max_voltage_steps; i++) 4421 voltage_table->entries[i] = voltage_table->entries[i + diff]; 4422 4423 voltage_table->count = max_voltage_steps; 4424 } 4425 4426 static int si_get_svi2_voltage_table(struct amdgpu_device *adev, 4427 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, 4428 struct atom_voltage_table *voltage_table) 4429 { 4430 u32 i; 4431 4432 if (voltage_dependency_table == NULL) 4433 return -EINVAL; 4434 4435 voltage_table->mask_low = 0; 4436 voltage_table->phase_delay = 0; 4437 4438 voltage_table->count = voltage_dependency_table->count; 4439 for (i = 0; i < voltage_table->count; i++) { 4440 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4441 voltage_table->entries[i].smio_low = 0; 4442 } 4443 4444 return 0; 4445 } 4446 4447 static int si_construct_voltage_tables(struct amdgpu_device *adev) 4448 { 4449 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4450 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4451 struct si_power_info *si_pi = si_get_pi(adev); 4452 int ret; 4453 4454 if (pi->voltage_control) { 4455 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4456 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4457 if (ret) 4458 return ret; 4459 4460 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4461 si_trim_voltage_table_to_fit_state_table(adev, 4462 SISLANDS_MAX_NO_VREG_STEPS, 4463 &eg_pi->vddc_voltage_table); 4464 } else if (si_pi->voltage_control_svi2) { 4465 ret = si_get_svi2_voltage_table(adev, 4466 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4467 &eg_pi->vddc_voltage_table); 4468 if (ret) 4469 return ret; 4470 } else { 4471 return -EINVAL; 4472 } 4473 4474 if (eg_pi->vddci_control) { 4475 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, 4476 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4477 if (ret) 4478 return ret; 4479 4480 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4481 si_trim_voltage_table_to_fit_state_table(adev, 4482 SISLANDS_MAX_NO_VREG_STEPS, 4483 &eg_pi->vddci_voltage_table); 4484 } 4485 if (si_pi->vddci_control_svi2) { 4486 ret = si_get_svi2_voltage_table(adev, 4487 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4488 &eg_pi->vddci_voltage_table); 4489 if (ret) 4490 return ret; 4491 } 4492 4493 if (pi->mvdd_control) { 4494 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, 4495 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4496 4497 if (ret) { 4498 pi->mvdd_control = false; 4499 return ret; 4500 } 4501 4502 if (si_pi->mvdd_voltage_table.count == 0) { 4503 pi->mvdd_control = false; 4504 return -EINVAL; 4505 } 4506 4507 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4508 si_trim_voltage_table_to_fit_state_table(adev, 4509 SISLANDS_MAX_NO_VREG_STEPS, 4510 &si_pi->mvdd_voltage_table); 4511 } 4512 4513 if (si_pi->vddc_phase_shed_control) { 4514 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4515 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4516 if (ret) 4517 si_pi->vddc_phase_shed_control = false; 4518 4519 if ((si_pi->vddc_phase_shed_table.count == 0) || 4520 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4521 si_pi->vddc_phase_shed_control = false; 4522 } 4523 4524 return 0; 4525 } 4526 4527 static void si_populate_smc_voltage_table(struct amdgpu_device *adev, 4528 const struct atom_voltage_table *voltage_table, 4529 SISLANDS_SMC_STATETABLE *table) 4530 { 4531 unsigned int i; 4532 4533 for (i = 0; i < voltage_table->count; i++) 4534 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4535 } 4536 4537 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, 4538 SISLANDS_SMC_STATETABLE *table) 4539 { 4540 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4541 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4542 struct si_power_info *si_pi = si_get_pi(adev); 4543 u8 i; 4544 4545 if (si_pi->voltage_control_svi2) { 4546 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4547 si_pi->svc_gpio_id); 4548 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4549 si_pi->svd_gpio_id); 4550 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4551 2); 4552 } else { 4553 if (eg_pi->vddc_voltage_table.count) { 4554 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); 4555 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4556 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4557 4558 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4559 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4560 table->maxVDDCIndexInPPTable = i; 4561 break; 4562 } 4563 } 4564 } 4565 4566 if (eg_pi->vddci_voltage_table.count) { 4567 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); 4568 4569 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4570 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4571 } 4572 4573 4574 if (si_pi->mvdd_voltage_table.count) { 4575 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); 4576 4577 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4578 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4579 } 4580 4581 if (si_pi->vddc_phase_shed_control) { 4582 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, 4583 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4584 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4585 4586 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4587 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4588 4589 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4590 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4591 } else { 4592 si_pi->vddc_phase_shed_control = false; 4593 } 4594 } 4595 } 4596 4597 return 0; 4598 } 4599 4600 static int si_populate_voltage_value(struct amdgpu_device *adev, 4601 const struct atom_voltage_table *table, 4602 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4603 { 4604 unsigned int i; 4605 4606 for (i = 0; i < table->count; i++) { 4607 if (value <= table->entries[i].value) { 4608 voltage->index = (u8)i; 4609 voltage->value = cpu_to_be16(table->entries[i].value); 4610 break; 4611 } 4612 } 4613 4614 if (i >= table->count) 4615 return -EINVAL; 4616 4617 return 0; 4618 } 4619 4620 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, 4621 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4622 { 4623 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4624 struct si_power_info *si_pi = si_get_pi(adev); 4625 4626 if (pi->mvdd_control) { 4627 if (mclk <= pi->mvdd_split_frequency) 4628 voltage->index = 0; 4629 else 4630 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4631 4632 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4633 } 4634 return 0; 4635 } 4636 4637 static int si_get_std_voltage_value(struct amdgpu_device *adev, 4638 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4639 u16 *std_voltage) 4640 { 4641 u16 v_index; 4642 bool voltage_found = false; 4643 *std_voltage = be16_to_cpu(voltage->value); 4644 4645 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4646 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4647 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4648 return -EINVAL; 4649 4650 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4651 if (be16_to_cpu(voltage->value) == 4652 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4653 voltage_found = true; 4654 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4655 *std_voltage = 4656 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4657 else 4658 *std_voltage = 4659 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4660 break; 4661 } 4662 } 4663 4664 if (!voltage_found) { 4665 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4666 if (be16_to_cpu(voltage->value) <= 4667 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4668 voltage_found = true; 4669 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4670 *std_voltage = 4671 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4672 else 4673 *std_voltage = 4674 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4675 break; 4676 } 4677 } 4678 } 4679 } else { 4680 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4681 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4682 } 4683 } 4684 4685 return 0; 4686 } 4687 4688 static int si_populate_std_voltage_value(struct amdgpu_device *adev, 4689 u16 value, u8 index, 4690 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4691 { 4692 voltage->index = index; 4693 voltage->value = cpu_to_be16(value); 4694 4695 return 0; 4696 } 4697 4698 static int si_populate_phase_shedding_value(struct amdgpu_device *adev, 4699 const struct amdgpu_phase_shedding_limits_table *limits, 4700 u16 voltage, u32 sclk, u32 mclk, 4701 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4702 { 4703 unsigned int i; 4704 4705 for (i = 0; i < limits->count; i++) { 4706 if ((voltage <= limits->entries[i].voltage) && 4707 (sclk <= limits->entries[i].sclk) && 4708 (mclk <= limits->entries[i].mclk)) 4709 break; 4710 } 4711 4712 smc_voltage->phase_settings = (u8)i; 4713 4714 return 0; 4715 } 4716 4717 static int si_init_arb_table_index(struct amdgpu_device *adev) 4718 { 4719 struct si_power_info *si_pi = si_get_pi(adev); 4720 u32 tmp; 4721 int ret; 4722 4723 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4724 &tmp, si_pi->sram_end); 4725 if (ret) 4726 return ret; 4727 4728 tmp &= 0x00FFFFFF; 4729 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4730 4731 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4732 tmp, si_pi->sram_end); 4733 } 4734 4735 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4736 { 4737 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4738 } 4739 4740 static int si_reset_to_default(struct amdgpu_device *adev) 4741 { 4742 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4743 0 : -EINVAL; 4744 } 4745 4746 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 4747 { 4748 struct si_power_info *si_pi = si_get_pi(adev); 4749 u32 tmp; 4750 int ret; 4751 4752 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4753 &tmp, si_pi->sram_end); 4754 if (ret) 4755 return ret; 4756 4757 tmp = (tmp >> 24) & 0xff; 4758 4759 if (tmp == MC_CG_ARB_FREQ_F0) 4760 return 0; 4761 4762 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); 4763 } 4764 4765 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, 4766 u32 engine_clock) 4767 { 4768 u32 dram_rows; 4769 u32 dram_refresh_rate; 4770 u32 mc_arb_rfsh_rate; 4771 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4772 4773 if (tmp >= 4) 4774 dram_rows = 16384; 4775 else 4776 dram_rows = 1 << (tmp + 10); 4777 4778 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4779 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4780 4781 return mc_arb_rfsh_rate; 4782 } 4783 4784 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, 4785 struct rv7xx_pl *pl, 4786 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4787 { 4788 u32 dram_timing; 4789 u32 dram_timing2; 4790 u32 burst_time; 4791 4792 arb_regs->mc_arb_rfsh_rate = 4793 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); 4794 4795 amdgpu_atombios_set_engine_dram_timings(adev, 4796 pl->sclk, 4797 pl->mclk); 4798 4799 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4800 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4801 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4802 4803 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4804 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4805 arb_regs->mc_arb_burst_time = (u8)burst_time; 4806 4807 return 0; 4808 } 4809 4810 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 4811 struct amdgpu_ps *amdgpu_state, 4812 unsigned int first_arb_set) 4813 { 4814 struct si_power_info *si_pi = si_get_pi(adev); 4815 struct si_ps *state = si_get_ps(amdgpu_state); 4816 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4817 int i, ret = 0; 4818 4819 for (i = 0; i < state->performance_level_count; i++) { 4820 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4821 if (ret) 4822 break; 4823 ret = amdgpu_si_copy_bytes_to_smc(adev, 4824 si_pi->arb_table_start + 4825 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4826 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4827 (u8 *)&arb_regs, 4828 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4829 si_pi->sram_end); 4830 if (ret) 4831 break; 4832 } 4833 4834 return ret; 4835 } 4836 4837 static int si_program_memory_timing_parameters(struct amdgpu_device *adev, 4838 struct amdgpu_ps *amdgpu_new_state) 4839 { 4840 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, 4841 SISLANDS_DRIVER_STATE_ARB_INDEX); 4842 } 4843 4844 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, 4845 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4846 { 4847 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4848 struct si_power_info *si_pi = si_get_pi(adev); 4849 4850 if (pi->mvdd_control) 4851 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, 4852 si_pi->mvdd_bootup_value, voltage); 4853 4854 return 0; 4855 } 4856 4857 static int si_populate_smc_initial_state(struct amdgpu_device *adev, 4858 struct amdgpu_ps *amdgpu_initial_state, 4859 SISLANDS_SMC_STATETABLE *table) 4860 { 4861 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); 4862 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4863 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4864 struct si_power_info *si_pi = si_get_pi(adev); 4865 u32 reg; 4866 int ret; 4867 4868 table->initialState.level.mclk.vDLL_CNTL = 4869 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4870 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4871 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4872 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4873 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4874 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4875 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4876 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4877 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4878 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4879 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4880 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4881 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4882 table->initialState.level.mclk.vMPLL_SS = 4883 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4884 table->initialState.level.mclk.vMPLL_SS2 = 4885 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4886 4887 table->initialState.level.mclk.mclk_value = 4888 cpu_to_be32(initial_state->performance_levels[0].mclk); 4889 4890 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4891 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4892 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4893 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4894 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4895 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4896 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4897 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4898 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4899 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4900 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4901 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4902 4903 table->initialState.level.sclk.sclk_value = 4904 cpu_to_be32(initial_state->performance_levels[0].sclk); 4905 4906 table->initialState.level.arbRefreshState = 4907 SISLANDS_INITIAL_STATE_ARB_INDEX; 4908 4909 table->initialState.level.ACIndex = 0; 4910 4911 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 4912 initial_state->performance_levels[0].vddc, 4913 &table->initialState.level.vddc); 4914 4915 if (!ret) { 4916 u16 std_vddc; 4917 4918 ret = si_get_std_voltage_value(adev, 4919 &table->initialState.level.vddc, 4920 &std_vddc); 4921 if (!ret) 4922 si_populate_std_voltage_value(adev, std_vddc, 4923 table->initialState.level.vddc.index, 4924 &table->initialState.level.std_vddc); 4925 } 4926 4927 if (eg_pi->vddci_control) 4928 si_populate_voltage_value(adev, 4929 &eg_pi->vddci_voltage_table, 4930 initial_state->performance_levels[0].vddci, 4931 &table->initialState.level.vddci); 4932 4933 if (si_pi->vddc_phase_shed_control) 4934 si_populate_phase_shedding_value(adev, 4935 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 4936 initial_state->performance_levels[0].vddc, 4937 initial_state->performance_levels[0].sclk, 4938 initial_state->performance_levels[0].mclk, 4939 &table->initialState.level.vddc); 4940 4941 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); 4942 4943 reg = CG_R(0xffff) | CG_L(0); 4944 table->initialState.level.aT = cpu_to_be32(reg); 4945 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4946 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4947 4948 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4949 table->initialState.level.strobeMode = 4950 si_get_strobe_mode_settings(adev, 4951 initial_state->performance_levels[0].mclk); 4952 4953 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4954 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4955 else 4956 table->initialState.level.mcFlags = 0; 4957 } 4958 4959 table->initialState.levelCount = 1; 4960 4961 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4962 4963 table->initialState.level.dpm2.MaxPS = 0; 4964 table->initialState.level.dpm2.NearTDPDec = 0; 4965 table->initialState.level.dpm2.AboveSafeInc = 0; 4966 table->initialState.level.dpm2.BelowSafeInc = 0; 4967 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4968 4969 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4970 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 4971 4972 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4973 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 4974 4975 return 0; 4976 } 4977 4978 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, 4979 u32 sys_mask, 4980 enum si_pcie_gen asic_gen, 4981 enum si_pcie_gen default_gen) 4982 { 4983 switch (asic_gen) { 4984 case SI_PCIE_GEN1: 4985 return SI_PCIE_GEN1; 4986 case SI_PCIE_GEN2: 4987 return SI_PCIE_GEN2; 4988 case SI_PCIE_GEN3: 4989 return SI_PCIE_GEN3; 4990 default: 4991 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) && 4992 (default_gen == SI_PCIE_GEN3)) 4993 return SI_PCIE_GEN3; 4994 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) && 4995 (default_gen == SI_PCIE_GEN2)) 4996 return SI_PCIE_GEN2; 4997 else 4998 return SI_PCIE_GEN1; 4999 } 5000 return SI_PCIE_GEN1; 5001 } 5002 5003 static int si_populate_smc_acpi_state(struct amdgpu_device *adev, 5004 SISLANDS_SMC_STATETABLE *table) 5005 { 5006 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5007 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5008 struct si_power_info *si_pi = si_get_pi(adev); 5009 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5010 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5011 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5012 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5013 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5014 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5015 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5016 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5017 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5018 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5019 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5020 u32 reg; 5021 int ret; 5022 5023 table->ACPIState = table->initialState; 5024 5025 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 5026 5027 if (pi->acpi_vddc) { 5028 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5029 pi->acpi_vddc, &table->ACPIState.level.vddc); 5030 if (!ret) { 5031 u16 std_vddc; 5032 5033 ret = si_get_std_voltage_value(adev, 5034 &table->ACPIState.level.vddc, &std_vddc); 5035 if (!ret) 5036 si_populate_std_voltage_value(adev, std_vddc, 5037 table->ACPIState.level.vddc.index, 5038 &table->ACPIState.level.std_vddc); 5039 } 5040 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 5041 5042 if (si_pi->vddc_phase_shed_control) { 5043 si_populate_phase_shedding_value(adev, 5044 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5045 pi->acpi_vddc, 5046 0, 5047 0, 5048 &table->ACPIState.level.vddc); 5049 } 5050 } else { 5051 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5052 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 5053 if (!ret) { 5054 u16 std_vddc; 5055 5056 ret = si_get_std_voltage_value(adev, 5057 &table->ACPIState.level.vddc, &std_vddc); 5058 5059 if (!ret) 5060 si_populate_std_voltage_value(adev, std_vddc, 5061 table->ACPIState.level.vddc.index, 5062 &table->ACPIState.level.std_vddc); 5063 } 5064 table->ACPIState.level.gen2PCIE = 5065 (u8)si_gen_pcie_gen_support(adev, 5066 si_pi->sys_pcie_mask, 5067 si_pi->boot_pcie_gen, 5068 SI_PCIE_GEN1); 5069 5070 if (si_pi->vddc_phase_shed_control) 5071 si_populate_phase_shedding_value(adev, 5072 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5073 pi->min_vddc_in_table, 5074 0, 5075 0, 5076 &table->ACPIState.level.vddc); 5077 } 5078 5079 if (pi->acpi_vddc) { 5080 if (eg_pi->acpi_vddci) 5081 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5082 eg_pi->acpi_vddci, 5083 &table->ACPIState.level.vddci); 5084 } 5085 5086 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 5087 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5088 5089 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 5090 5091 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 5092 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 5093 5094 table->ACPIState.level.mclk.vDLL_CNTL = 5095 cpu_to_be32(dll_cntl); 5096 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 5097 cpu_to_be32(mclk_pwrmgt_cntl); 5098 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 5099 cpu_to_be32(mpll_ad_func_cntl); 5100 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 5101 cpu_to_be32(mpll_dq_func_cntl); 5102 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 5103 cpu_to_be32(mpll_func_cntl); 5104 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 5105 cpu_to_be32(mpll_func_cntl_1); 5106 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 5107 cpu_to_be32(mpll_func_cntl_2); 5108 table->ACPIState.level.mclk.vMPLL_SS = 5109 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 5110 table->ACPIState.level.mclk.vMPLL_SS2 = 5111 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 5112 5113 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 5114 cpu_to_be32(spll_func_cntl); 5115 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 5116 cpu_to_be32(spll_func_cntl_2); 5117 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 5118 cpu_to_be32(spll_func_cntl_3); 5119 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 5120 cpu_to_be32(spll_func_cntl_4); 5121 5122 table->ACPIState.level.mclk.mclk_value = 0; 5123 table->ACPIState.level.sclk.sclk_value = 0; 5124 5125 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); 5126 5127 if (eg_pi->dynamic_ac_timing) 5128 table->ACPIState.level.ACIndex = 0; 5129 5130 table->ACPIState.level.dpm2.MaxPS = 0; 5131 table->ACPIState.level.dpm2.NearTDPDec = 0; 5132 table->ACPIState.level.dpm2.AboveSafeInc = 0; 5133 table->ACPIState.level.dpm2.BelowSafeInc = 0; 5134 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 5135 5136 reg = MIN_POWER_MASK | MAX_POWER_MASK; 5137 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 5138 5139 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 5140 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5141 5142 return 0; 5143 } 5144 5145 static int si_populate_ulv_state(struct amdgpu_device *adev, 5146 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 5147 { 5148 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5149 struct si_power_info *si_pi = si_get_pi(adev); 5150 struct si_ulv_param *ulv = &si_pi->ulv; 5151 u32 sclk_in_sr = 1350; /* ??? */ 5152 int ret; 5153 5154 ret = si_convert_power_level_to_smc(adev, &ulv->pl, 5155 &state->level); 5156 if (!ret) { 5157 if (eg_pi->sclk_deep_sleep) { 5158 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5159 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5160 else 5161 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5162 } 5163 if (ulv->one_pcie_lane_in_ulv) 5164 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 5165 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 5166 state->level.ACIndex = 1; 5167 state->level.std_vddc = state->level.vddc; 5168 state->levelCount = 1; 5169 5170 state->flags |= PPSMC_SWSTATE_FLAG_DC; 5171 } 5172 5173 return ret; 5174 } 5175 5176 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 5177 { 5178 struct si_power_info *si_pi = si_get_pi(adev); 5179 struct si_ulv_param *ulv = &si_pi->ulv; 5180 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 5181 int ret; 5182 5183 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, 5184 &arb_regs); 5185 if (ret) 5186 return ret; 5187 5188 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5189 ulv->volt_change_delay); 5190 5191 ret = amdgpu_si_copy_bytes_to_smc(adev, 5192 si_pi->arb_table_start + 5193 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5194 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5195 (u8 *)&arb_regs, 5196 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5197 si_pi->sram_end); 5198 5199 return ret; 5200 } 5201 5202 static void si_get_mvdd_configuration(struct amdgpu_device *adev) 5203 { 5204 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5205 5206 pi->mvdd_split_frequency = 30000; 5207 } 5208 5209 static int si_init_smc_table(struct amdgpu_device *adev) 5210 { 5211 struct si_power_info *si_pi = si_get_pi(adev); 5212 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; 5213 const struct si_ulv_param *ulv = &si_pi->ulv; 5214 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 5215 int ret; 5216 u32 lane_width; 5217 u32 vr_hot_gpio; 5218 5219 si_populate_smc_voltage_tables(adev, table); 5220 5221 switch (adev->pm.int_thermal_type) { 5222 case THERMAL_TYPE_SI: 5223 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 5224 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 5225 break; 5226 case THERMAL_TYPE_NONE: 5227 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 5228 break; 5229 default: 5230 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 5231 break; 5232 } 5233 5234 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 5235 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 5236 5237 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 5238 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) 5239 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 5240 } 5241 5242 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5243 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5244 5245 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5246 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5247 5248 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5249 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 5250 5251 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 5252 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 5253 vr_hot_gpio = adev->pm.dpm.backbias_response_time; 5254 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 5255 vr_hot_gpio); 5256 } 5257 5258 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); 5259 if (ret) 5260 return ret; 5261 5262 ret = si_populate_smc_acpi_state(adev, table); 5263 if (ret) 5264 return ret; 5265 5266 table->driverState.flags = table->initialState.flags; 5267 table->driverState.levelCount = table->initialState.levelCount; 5268 table->driverState.levels[0] = table->initialState.level; 5269 5270 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, 5271 SISLANDS_INITIAL_STATE_ARB_INDEX); 5272 if (ret) 5273 return ret; 5274 5275 if (ulv->supported && ulv->pl.vddc) { 5276 ret = si_populate_ulv_state(adev, &table->ULVState); 5277 if (ret) 5278 return ret; 5279 5280 ret = si_program_ulv_memory_timing_parameters(adev); 5281 if (ret) 5282 return ret; 5283 5284 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 5285 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 5286 5287 lane_width = amdgpu_get_pcie_lanes(adev); 5288 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5289 } else { 5290 table->ULVState = table->initialState; 5291 } 5292 5293 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5294 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5295 si_pi->sram_end); 5296 } 5297 5298 static int si_calculate_sclk_params(struct amdgpu_device *adev, 5299 u32 engine_clock, 5300 SISLANDS_SMC_SCLK_VALUE *sclk) 5301 { 5302 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5303 struct si_power_info *si_pi = si_get_pi(adev); 5304 struct atom_clock_dividers dividers; 5305 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5306 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5307 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5308 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5309 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 5310 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 5311 u64 tmp; 5312 u32 reference_clock = adev->clock.spll.reference_freq; 5313 u32 reference_divider; 5314 u32 fbdiv; 5315 int ret; 5316 5317 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 5318 engine_clock, false, ÷rs); 5319 if (ret) 5320 return ret; 5321 5322 reference_divider = 1 + dividers.ref_div; 5323 5324 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5325 do_div(tmp, reference_clock); 5326 fbdiv = (u32) tmp; 5327 5328 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 5329 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 5330 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 5331 5332 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 5333 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 5334 5335 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 5336 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 5337 spll_func_cntl_3 |= SPLL_DITHEN; 5338 5339 if (pi->sclk_ss) { 5340 struct amdgpu_atom_ss ss; 5341 u32 vco_freq = engine_clock * dividers.post_div; 5342 5343 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5344 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 5345 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 5346 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 5347 5348 cg_spll_spread_spectrum &= ~CLK_S_MASK; 5349 cg_spll_spread_spectrum |= CLK_S(clk_s); 5350 cg_spll_spread_spectrum |= SSEN; 5351 5352 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 5353 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 5354 } 5355 } 5356 5357 sclk->sclk_value = engine_clock; 5358 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 5359 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 5360 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 5361 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 5362 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 5363 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 5364 5365 return 0; 5366 } 5367 5368 static int si_populate_sclk_value(struct amdgpu_device *adev, 5369 u32 engine_clock, 5370 SISLANDS_SMC_SCLK_VALUE *sclk) 5371 { 5372 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 5373 int ret; 5374 5375 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); 5376 if (!ret) { 5377 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 5378 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 5379 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 5380 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 5381 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 5382 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 5383 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 5384 } 5385 5386 return ret; 5387 } 5388 5389 static int si_populate_mclk_value(struct amdgpu_device *adev, 5390 u32 engine_clock, 5391 u32 memory_clock, 5392 SISLANDS_SMC_MCLK_VALUE *mclk, 5393 bool strobe_mode, 5394 bool dll_state_on) 5395 { 5396 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5397 struct si_power_info *si_pi = si_get_pi(adev); 5398 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5399 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5400 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5401 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5402 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5403 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5404 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5405 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 5406 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 5407 struct atom_mpll_param mpll_param; 5408 int ret; 5409 5410 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); 5411 if (ret) 5412 return ret; 5413 5414 mpll_func_cntl &= ~BWCTRL_MASK; 5415 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 5416 5417 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 5418 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 5419 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 5420 5421 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5422 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5423 5424 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5425 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5426 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5427 YCLK_POST_DIV(mpll_param.post_div); 5428 } 5429 5430 if (pi->mclk_ss) { 5431 struct amdgpu_atom_ss ss; 5432 u32 freq_nom; 5433 u32 tmp; 5434 u32 reference_clock = adev->clock.mpll.reference_freq; 5435 5436 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5437 freq_nom = memory_clock * 4; 5438 else 5439 freq_nom = memory_clock * 2; 5440 5441 tmp = freq_nom / reference_clock; 5442 tmp = tmp * tmp; 5443 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5444 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 5445 u32 clks = reference_clock * 5 / ss.rate; 5446 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 5447 5448 mpll_ss1 &= ~CLKV_MASK; 5449 mpll_ss1 |= CLKV(clkv); 5450 5451 mpll_ss2 &= ~CLKS_MASK; 5452 mpll_ss2 |= CLKS(clks); 5453 } 5454 } 5455 5456 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5457 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5458 5459 if (dll_state_on) 5460 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5461 else 5462 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5463 5464 mclk->mclk_value = cpu_to_be32(memory_clock); 5465 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5466 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5467 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5468 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5469 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5470 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5471 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5472 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5473 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5474 5475 return 0; 5476 } 5477 5478 static void si_populate_smc_sp(struct amdgpu_device *adev, 5479 struct amdgpu_ps *amdgpu_state, 5480 SISLANDS_SMC_SWSTATE *smc_state) 5481 { 5482 struct si_ps *ps = si_get_ps(amdgpu_state); 5483 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5484 int i; 5485 5486 for (i = 0; i < ps->performance_level_count - 1; i++) 5487 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5488 5489 smc_state->levels[ps->performance_level_count - 1].bSP = 5490 cpu_to_be32(pi->psp); 5491 } 5492 5493 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 5494 struct rv7xx_pl *pl, 5495 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5496 { 5497 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5498 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5499 struct si_power_info *si_pi = si_get_pi(adev); 5500 int ret; 5501 bool dll_state_on; 5502 u16 std_vddc; 5503 bool gmc_pg = false; 5504 5505 if (eg_pi->pcie_performance_request && 5506 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) 5507 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5508 else 5509 level->gen2PCIE = (u8)pl->pcie_gen; 5510 5511 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); 5512 if (ret) 5513 return ret; 5514 5515 level->mcFlags = 0; 5516 5517 if (pi->mclk_stutter_mode_threshold && 5518 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5519 !eg_pi->uvd_enabled && 5520 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 5521 (adev->pm.dpm.new_active_crtc_count <= 2)) { 5522 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5523 5524 if (gmc_pg) 5525 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 5526 } 5527 5528 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5529 if (pl->mclk > pi->mclk_edc_enable_threshold) 5530 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5531 5532 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5533 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5534 5535 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); 5536 5537 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5538 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5539 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5540 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5541 else 5542 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5543 } else { 5544 dll_state_on = false; 5545 } 5546 } else { 5547 level->strobeMode = si_get_strobe_mode_settings(adev, 5548 pl->mclk); 5549 5550 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5551 } 5552 5553 ret = si_populate_mclk_value(adev, 5554 pl->sclk, 5555 pl->mclk, 5556 &level->mclk, 5557 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5558 if (ret) 5559 return ret; 5560 5561 ret = si_populate_voltage_value(adev, 5562 &eg_pi->vddc_voltage_table, 5563 pl->vddc, &level->vddc); 5564 if (ret) 5565 return ret; 5566 5567 5568 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); 5569 if (ret) 5570 return ret; 5571 5572 ret = si_populate_std_voltage_value(adev, std_vddc, 5573 level->vddc.index, &level->std_vddc); 5574 if (ret) 5575 return ret; 5576 5577 if (eg_pi->vddci_control) { 5578 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5579 pl->vddci, &level->vddci); 5580 if (ret) 5581 return ret; 5582 } 5583 5584 if (si_pi->vddc_phase_shed_control) { 5585 ret = si_populate_phase_shedding_value(adev, 5586 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5587 pl->vddc, 5588 pl->sclk, 5589 pl->mclk, 5590 &level->vddc); 5591 if (ret) 5592 return ret; 5593 } 5594 5595 level->MaxPoweredUpCU = si_pi->max_cu; 5596 5597 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); 5598 5599 return ret; 5600 } 5601 5602 static int si_populate_smc_t(struct amdgpu_device *adev, 5603 struct amdgpu_ps *amdgpu_state, 5604 SISLANDS_SMC_SWSTATE *smc_state) 5605 { 5606 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5607 struct si_ps *state = si_get_ps(amdgpu_state); 5608 u32 a_t; 5609 u32 t_l, t_h; 5610 u32 high_bsp; 5611 int i, ret; 5612 5613 if (state->performance_level_count >= 9) 5614 return -EINVAL; 5615 5616 if (state->performance_level_count < 2) { 5617 a_t = CG_R(0xffff) | CG_L(0); 5618 smc_state->levels[0].aT = cpu_to_be32(a_t); 5619 return 0; 5620 } 5621 5622 smc_state->levels[0].aT = cpu_to_be32(0); 5623 5624 for (i = 0; i <= state->performance_level_count - 2; i++) { 5625 ret = r600_calculate_at( 5626 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5627 100 * R600_AH_DFLT, 5628 state->performance_levels[i + 1].sclk, 5629 state->performance_levels[i].sclk, 5630 &t_l, 5631 &t_h); 5632 5633 if (ret) { 5634 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5635 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5636 } 5637 5638 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5639 a_t |= CG_R(t_l * pi->bsp / 20000); 5640 smc_state->levels[i].aT = cpu_to_be32(a_t); 5641 5642 high_bsp = (i == state->performance_level_count - 2) ? 5643 pi->pbsp : pi->bsp; 5644 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5645 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5646 } 5647 5648 return 0; 5649 } 5650 5651 static int si_disable_ulv(struct amdgpu_device *adev) 5652 { 5653 struct si_power_info *si_pi = si_get_pi(adev); 5654 struct si_ulv_param *ulv = &si_pi->ulv; 5655 5656 if (ulv->supported) 5657 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5658 0 : -EINVAL; 5659 5660 return 0; 5661 } 5662 5663 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, 5664 struct amdgpu_ps *amdgpu_state) 5665 { 5666 const struct si_power_info *si_pi = si_get_pi(adev); 5667 const struct si_ulv_param *ulv = &si_pi->ulv; 5668 const struct si_ps *state = si_get_ps(amdgpu_state); 5669 int i; 5670 5671 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5672 return false; 5673 5674 /* XXX validate against display requirements! */ 5675 5676 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5677 if (adev->clock.current_dispclk <= 5678 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5679 if (ulv->pl.vddc < 5680 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5681 return false; 5682 } 5683 } 5684 5685 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) 5686 return false; 5687 5688 return true; 5689 } 5690 5691 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, 5692 struct amdgpu_ps *amdgpu_new_state) 5693 { 5694 const struct si_power_info *si_pi = si_get_pi(adev); 5695 const struct si_ulv_param *ulv = &si_pi->ulv; 5696 5697 if (ulv->supported) { 5698 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5699 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5700 0 : -EINVAL; 5701 } 5702 return 0; 5703 } 5704 5705 static int si_convert_power_state_to_smc(struct amdgpu_device *adev, 5706 struct amdgpu_ps *amdgpu_state, 5707 SISLANDS_SMC_SWSTATE *smc_state) 5708 { 5709 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5710 struct ni_power_info *ni_pi = ni_get_pi(adev); 5711 struct si_power_info *si_pi = si_get_pi(adev); 5712 struct si_ps *state = si_get_ps(amdgpu_state); 5713 int i, ret; 5714 u32 threshold; 5715 u32 sclk_in_sr = 1350; /* ??? */ 5716 5717 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5718 return -EINVAL; 5719 5720 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5721 5722 if (amdgpu_state->vclk && amdgpu_state->dclk) { 5723 eg_pi->uvd_enabled = true; 5724 if (eg_pi->smu_uvd_hs) 5725 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5726 } else { 5727 eg_pi->uvd_enabled = false; 5728 } 5729 5730 if (state->dc_compatible) 5731 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5732 5733 smc_state->levelCount = 0; 5734 for (i = 0; i < state->performance_level_count; i++) { 5735 if (eg_pi->sclk_deep_sleep) { 5736 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5737 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5738 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5739 else 5740 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5741 } 5742 } 5743 5744 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], 5745 &smc_state->levels[i]); 5746 smc_state->levels[i].arbRefreshState = 5747 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5748 5749 if (ret) 5750 return ret; 5751 5752 if (ni_pi->enable_power_containment) 5753 smc_state->levels[i].displayWatermark = 5754 (state->performance_levels[i].sclk < threshold) ? 5755 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5756 else 5757 smc_state->levels[i].displayWatermark = (i < 2) ? 5758 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5759 5760 if (eg_pi->dynamic_ac_timing) 5761 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5762 else 5763 smc_state->levels[i].ACIndex = 0; 5764 5765 smc_state->levelCount++; 5766 } 5767 5768 si_write_smc_soft_register(adev, 5769 SI_SMC_SOFT_REGISTER_watermark_threshold, 5770 threshold / 512); 5771 5772 si_populate_smc_sp(adev, amdgpu_state, smc_state); 5773 5774 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); 5775 if (ret) 5776 ni_pi->enable_power_containment = false; 5777 5778 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); 5779 if (ret) 5780 ni_pi->enable_sq_ramping = false; 5781 5782 return si_populate_smc_t(adev, amdgpu_state, smc_state); 5783 } 5784 5785 static int si_upload_sw_state(struct amdgpu_device *adev, 5786 struct amdgpu_ps *amdgpu_new_state) 5787 { 5788 struct si_power_info *si_pi = si_get_pi(adev); 5789 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 5790 int ret; 5791 u32 address = si_pi->state_table_start + 5792 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5793 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5794 size_t state_size = struct_size(smc_state, levels, 5795 new_state->performance_level_count); 5796 memset(smc_state, 0, state_size); 5797 5798 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); 5799 if (ret) 5800 return ret; 5801 5802 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5803 state_size, si_pi->sram_end); 5804 } 5805 5806 static int si_upload_ulv_state(struct amdgpu_device *adev) 5807 { 5808 struct si_power_info *si_pi = si_get_pi(adev); 5809 struct si_ulv_param *ulv = &si_pi->ulv; 5810 int ret = 0; 5811 5812 if (ulv->supported && ulv->pl.vddc) { 5813 u32 address = si_pi->state_table_start + 5814 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5815 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5816 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5817 5818 memset(smc_state, 0, state_size); 5819 5820 ret = si_populate_ulv_state(adev, smc_state); 5821 if (!ret) 5822 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5823 state_size, si_pi->sram_end); 5824 } 5825 5826 return ret; 5827 } 5828 5829 static int si_upload_smc_data(struct amdgpu_device *adev) 5830 { 5831 struct amdgpu_crtc *amdgpu_crtc = NULL; 5832 int i; 5833 5834 if (adev->pm.dpm.new_active_crtc_count == 0) 5835 return 0; 5836 5837 for (i = 0; i < adev->mode_info.num_crtc; i++) { 5838 if (adev->pm.dpm.new_active_crtcs & (1 << i)) { 5839 amdgpu_crtc = adev->mode_info.crtcs[i]; 5840 break; 5841 } 5842 } 5843 5844 if (amdgpu_crtc == NULL) 5845 return 0; 5846 5847 if (amdgpu_crtc->line_time <= 0) 5848 return 0; 5849 5850 if (si_write_smc_soft_register(adev, 5851 SI_SMC_SOFT_REGISTER_crtc_index, 5852 amdgpu_crtc->crtc_id) != PPSMC_Result_OK) 5853 return 0; 5854 5855 if (si_write_smc_soft_register(adev, 5856 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5857 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5858 return 0; 5859 5860 if (si_write_smc_soft_register(adev, 5861 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5862 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK) 5863 return 0; 5864 5865 return 0; 5866 } 5867 5868 static int si_set_mc_special_registers(struct amdgpu_device *adev, 5869 struct si_mc_reg_table *table) 5870 { 5871 u8 i, j, k; 5872 u32 temp_reg; 5873 5874 for (i = 0, j = table->last; i < table->last; i++) { 5875 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5876 return -EINVAL; 5877 switch (table->mc_reg_address[i].s1) { 5878 case MC_SEQ_MISC1: 5879 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5880 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; 5881 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; 5882 for (k = 0; k < table->num_entries; k++) 5883 table->mc_reg_table_entry[k].mc_data[j] = 5884 ((temp_reg & 0xffff0000)) | 5885 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5886 j++; 5887 5888 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5889 return -EINVAL; 5890 temp_reg = RREG32(MC_PMG_CMD_MRS); 5891 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; 5892 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; 5893 for (k = 0; k < table->num_entries; k++) { 5894 table->mc_reg_table_entry[k].mc_data[j] = 5895 (temp_reg & 0xffff0000) | 5896 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5897 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5898 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5899 } 5900 j++; 5901 5902 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5903 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5904 return -EINVAL; 5905 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5906 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; 5907 for (k = 0; k < table->num_entries; k++) 5908 table->mc_reg_table_entry[k].mc_data[j] = 5909 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5910 j++; 5911 } 5912 break; 5913 case MC_SEQ_RESERVE_M: 5914 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5915 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; 5916 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; 5917 for(k = 0; k < table->num_entries; k++) 5918 table->mc_reg_table_entry[k].mc_data[j] = 5919 (temp_reg & 0xffff0000) | 5920 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5921 j++; 5922 break; 5923 default: 5924 break; 5925 } 5926 } 5927 5928 table->last = j; 5929 5930 return 0; 5931 } 5932 5933 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5934 { 5935 bool result = true; 5936 switch (in_reg) { 5937 case MC_SEQ_RAS_TIMING: 5938 *out_reg = MC_SEQ_RAS_TIMING_LP; 5939 break; 5940 case MC_SEQ_CAS_TIMING: 5941 *out_reg = MC_SEQ_CAS_TIMING_LP; 5942 break; 5943 case MC_SEQ_MISC_TIMING: 5944 *out_reg = MC_SEQ_MISC_TIMING_LP; 5945 break; 5946 case MC_SEQ_MISC_TIMING2: 5947 *out_reg = MC_SEQ_MISC_TIMING2_LP; 5948 break; 5949 case MC_SEQ_RD_CTL_D0: 5950 *out_reg = MC_SEQ_RD_CTL_D0_LP; 5951 break; 5952 case MC_SEQ_RD_CTL_D1: 5953 *out_reg = MC_SEQ_RD_CTL_D1_LP; 5954 break; 5955 case MC_SEQ_WR_CTL_D0: 5956 *out_reg = MC_SEQ_WR_CTL_D0_LP; 5957 break; 5958 case MC_SEQ_WR_CTL_D1: 5959 *out_reg = MC_SEQ_WR_CTL_D1_LP; 5960 break; 5961 case MC_PMG_CMD_EMRS: 5962 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; 5963 break; 5964 case MC_PMG_CMD_MRS: 5965 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; 5966 break; 5967 case MC_PMG_CMD_MRS1: 5968 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; 5969 break; 5970 case MC_SEQ_PMG_TIMING: 5971 *out_reg = MC_SEQ_PMG_TIMING_LP; 5972 break; 5973 case MC_PMG_CMD_MRS2: 5974 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; 5975 break; 5976 case MC_SEQ_WR_CTL_2: 5977 *out_reg = MC_SEQ_WR_CTL_2_LP; 5978 break; 5979 default: 5980 result = false; 5981 break; 5982 } 5983 5984 return result; 5985 } 5986 5987 static void si_set_valid_flag(struct si_mc_reg_table *table) 5988 { 5989 u8 i, j; 5990 5991 for (i = 0; i < table->last; i++) { 5992 for (j = 1; j < table->num_entries; j++) { 5993 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5994 table->valid_flag |= 1 << i; 5995 break; 5996 } 5997 } 5998 } 5999 } 6000 6001 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 6002 { 6003 u32 i; 6004 u16 address; 6005 6006 for (i = 0; i < table->last; i++) 6007 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 6008 address : table->mc_reg_address[i].s1; 6009 6010 } 6011 6012 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 6013 struct si_mc_reg_table *si_table) 6014 { 6015 u8 i, j; 6016 6017 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6018 return -EINVAL; 6019 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 6020 return -EINVAL; 6021 6022 for (i = 0; i < table->last; i++) 6023 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 6024 si_table->last = table->last; 6025 6026 for (i = 0; i < table->num_entries; i++) { 6027 si_table->mc_reg_table_entry[i].mclk_max = 6028 table->mc_reg_table_entry[i].mclk_max; 6029 for (j = 0; j < table->last; j++) { 6030 si_table->mc_reg_table_entry[i].mc_data[j] = 6031 table->mc_reg_table_entry[i].mc_data[j]; 6032 } 6033 } 6034 si_table->num_entries = table->num_entries; 6035 6036 return 0; 6037 } 6038 6039 static int si_initialize_mc_reg_table(struct amdgpu_device *adev) 6040 { 6041 struct si_power_info *si_pi = si_get_pi(adev); 6042 struct atom_mc_reg_table *table; 6043 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 6044 u8 module_index = rv770_get_memory_module_index(adev); 6045 int ret; 6046 6047 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 6048 if (!table) 6049 return -ENOMEM; 6050 6051 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 6052 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 6053 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 6054 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 6055 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 6056 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 6057 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 6058 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 6059 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 6060 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 6061 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 6062 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 6063 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 6064 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 6065 6066 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); 6067 if (ret) 6068 goto init_mc_done; 6069 6070 ret = si_copy_vbios_mc_reg_table(table, si_table); 6071 if (ret) 6072 goto init_mc_done; 6073 6074 si_set_s0_mc_reg_index(si_table); 6075 6076 ret = si_set_mc_special_registers(adev, si_table); 6077 if (ret) 6078 goto init_mc_done; 6079 6080 si_set_valid_flag(si_table); 6081 6082 init_mc_done: 6083 kfree(table); 6084 6085 return ret; 6086 6087 } 6088 6089 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, 6090 SMC_SIslands_MCRegisters *mc_reg_table) 6091 { 6092 struct si_power_info *si_pi = si_get_pi(adev); 6093 u32 i, j; 6094 6095 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 6096 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 6097 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6098 break; 6099 mc_reg_table->address[i].s0 = 6100 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 6101 mc_reg_table->address[i].s1 = 6102 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 6103 i++; 6104 } 6105 } 6106 mc_reg_table->last = (u8)i; 6107 } 6108 6109 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 6110 SMC_SIslands_MCRegisterSet *data, 6111 u32 num_entries, u32 valid_flag) 6112 { 6113 u32 i, j; 6114 6115 for(i = 0, j = 0; j < num_entries; j++) { 6116 if (valid_flag & (1 << j)) { 6117 data->value[i] = cpu_to_be32(entry->mc_data[j]); 6118 i++; 6119 } 6120 } 6121 } 6122 6123 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, 6124 struct rv7xx_pl *pl, 6125 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 6126 { 6127 struct si_power_info *si_pi = si_get_pi(adev); 6128 u32 i = 0; 6129 6130 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 6131 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 6132 break; 6133 } 6134 6135 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 6136 --i; 6137 6138 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 6139 mc_reg_table_data, si_pi->mc_reg_table.last, 6140 si_pi->mc_reg_table.valid_flag); 6141 } 6142 6143 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, 6144 struct amdgpu_ps *amdgpu_state, 6145 SMC_SIslands_MCRegisters *mc_reg_table) 6146 { 6147 struct si_ps *state = si_get_ps(amdgpu_state); 6148 int i; 6149 6150 for (i = 0; i < state->performance_level_count; i++) { 6151 si_convert_mc_reg_table_entry_to_smc(adev, 6152 &state->performance_levels[i], 6153 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 6154 } 6155 } 6156 6157 static int si_populate_mc_reg_table(struct amdgpu_device *adev, 6158 struct amdgpu_ps *amdgpu_boot_state) 6159 { 6160 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); 6161 struct si_power_info *si_pi = si_get_pi(adev); 6162 struct si_ulv_param *ulv = &si_pi->ulv; 6163 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6164 6165 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6166 6167 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); 6168 6169 si_populate_mc_reg_addresses(adev, smc_mc_reg_table); 6170 6171 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], 6172 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 6173 6174 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6175 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 6176 si_pi->mc_reg_table.last, 6177 si_pi->mc_reg_table.valid_flag); 6178 6179 if (ulv->supported && ulv->pl.vddc != 0) 6180 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, 6181 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 6182 else 6183 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6184 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 6185 si_pi->mc_reg_table.last, 6186 si_pi->mc_reg_table.valid_flag); 6187 6188 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6189 6190 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6191 (u8 *)smc_mc_reg_table, 6192 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6193 } 6194 6195 static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6196 struct amdgpu_ps *amdgpu_new_state) 6197 { 6198 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 6199 struct si_power_info *si_pi = si_get_pi(adev); 6200 u32 address = si_pi->mc_reg_table_start + 6201 offsetof(SMC_SIslands_MCRegisters, 6202 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 6203 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6204 6205 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6206 6207 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6208 6209 return amdgpu_si_copy_bytes_to_smc(adev, address, 6210 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6211 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6212 si_pi->sram_end); 6213 } 6214 6215 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6216 { 6217 if (enable) 6218 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 6219 else 6220 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 6221 } 6222 6223 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, 6224 struct amdgpu_ps *amdgpu_state) 6225 { 6226 struct si_ps *state = si_get_ps(amdgpu_state); 6227 int i; 6228 u16 pcie_speed, max_speed = 0; 6229 6230 for (i = 0; i < state->performance_level_count; i++) { 6231 pcie_speed = state->performance_levels[i].pcie_gen; 6232 if (max_speed < pcie_speed) 6233 max_speed = pcie_speed; 6234 } 6235 return max_speed; 6236 } 6237 6238 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) 6239 { 6240 u32 speed_cntl; 6241 6242 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 6243 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 6244 6245 return (u16)speed_cntl; 6246 } 6247 6248 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, 6249 struct amdgpu_ps *amdgpu_new_state, 6250 struct amdgpu_ps *amdgpu_current_state) 6251 { 6252 struct si_power_info *si_pi = si_get_pi(adev); 6253 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6254 enum si_pcie_gen current_link_speed; 6255 6256 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) 6257 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); 6258 else 6259 current_link_speed = si_pi->force_pcie_gen; 6260 6261 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 6262 si_pi->pspp_notify_required = false; 6263 if (target_link_speed > current_link_speed) { 6264 switch (target_link_speed) { 6265 #if defined(CONFIG_ACPI) 6266 case SI_PCIE_GEN3: 6267 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 6268 break; 6269 si_pi->force_pcie_gen = SI_PCIE_GEN2; 6270 if (current_link_speed == SI_PCIE_GEN2) 6271 break; 6272 fallthrough; 6273 case SI_PCIE_GEN2: 6274 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 6275 break; 6276 fallthrough; 6277 #endif 6278 default: 6279 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); 6280 break; 6281 } 6282 } else { 6283 if (target_link_speed < current_link_speed) 6284 si_pi->pspp_notify_required = true; 6285 } 6286 } 6287 6288 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, 6289 struct amdgpu_ps *amdgpu_new_state, 6290 struct amdgpu_ps *amdgpu_current_state) 6291 { 6292 struct si_power_info *si_pi = si_get_pi(adev); 6293 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6294 u8 request; 6295 6296 if (si_pi->pspp_notify_required) { 6297 if (target_link_speed == SI_PCIE_GEN3) 6298 request = PCIE_PERF_REQ_PECI_GEN3; 6299 else if (target_link_speed == SI_PCIE_GEN2) 6300 request = PCIE_PERF_REQ_PECI_GEN2; 6301 else 6302 request = PCIE_PERF_REQ_PECI_GEN1; 6303 6304 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 6305 (si_get_current_pcie_speed(adev) > 0)) 6306 return; 6307 6308 #if defined(CONFIG_ACPI) 6309 amdgpu_acpi_pcie_performance_request(adev, request, false); 6310 #endif 6311 } 6312 } 6313 6314 #if 0 6315 static int si_ds_request(struct amdgpu_device *adev, 6316 bool ds_status_on, u32 count_write) 6317 { 6318 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6319 6320 if (eg_pi->sclk_deep_sleep) { 6321 if (ds_status_on) 6322 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6323 PPSMC_Result_OK) ? 6324 0 : -EINVAL; 6325 else 6326 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6327 PPSMC_Result_OK) ? 0 : -EINVAL; 6328 } 6329 return 0; 6330 } 6331 #endif 6332 6333 static void si_set_max_cu_value(struct amdgpu_device *adev) 6334 { 6335 struct si_power_info *si_pi = si_get_pi(adev); 6336 6337 if (adev->asic_type == CHIP_VERDE) { 6338 switch (adev->pdev->device) { 6339 case 0x6820: 6340 case 0x6825: 6341 case 0x6821: 6342 case 0x6823: 6343 case 0x6827: 6344 si_pi->max_cu = 10; 6345 break; 6346 case 0x682D: 6347 case 0x6824: 6348 case 0x682F: 6349 case 0x6826: 6350 si_pi->max_cu = 8; 6351 break; 6352 case 0x6828: 6353 case 0x6830: 6354 case 0x6831: 6355 case 0x6838: 6356 case 0x6839: 6357 case 0x683D: 6358 si_pi->max_cu = 10; 6359 break; 6360 case 0x683B: 6361 case 0x683F: 6362 case 0x6829: 6363 si_pi->max_cu = 8; 6364 break; 6365 default: 6366 si_pi->max_cu = 0; 6367 break; 6368 } 6369 } else { 6370 si_pi->max_cu = 0; 6371 } 6372 } 6373 6374 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, 6375 struct amdgpu_clock_voltage_dependency_table *table) 6376 { 6377 u32 i; 6378 int j; 6379 u16 leakage_voltage; 6380 6381 if (table) { 6382 for (i = 0; i < table->count; i++) { 6383 switch (si_get_leakage_voltage_from_leakage_index(adev, 6384 table->entries[i].v, 6385 &leakage_voltage)) { 6386 case 0: 6387 table->entries[i].v = leakage_voltage; 6388 break; 6389 case -EAGAIN: 6390 return -EINVAL; 6391 case -EINVAL: 6392 default: 6393 break; 6394 } 6395 } 6396 6397 for (j = (table->count - 2); j >= 0; j--) { 6398 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 6399 table->entries[j].v : table->entries[j + 1].v; 6400 } 6401 } 6402 return 0; 6403 } 6404 6405 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) 6406 { 6407 int ret = 0; 6408 6409 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6410 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 6411 if (ret) 6412 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); 6413 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6414 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 6415 if (ret) 6416 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); 6417 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6418 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 6419 if (ret) 6420 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); 6421 return ret; 6422 } 6423 6424 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, 6425 struct amdgpu_ps *amdgpu_new_state, 6426 struct amdgpu_ps *amdgpu_current_state) 6427 { 6428 u32 lane_width; 6429 u32 new_lane_width = 6430 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6431 u32 current_lane_width = 6432 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6433 6434 if (new_lane_width != current_lane_width) { 6435 amdgpu_set_pcie_lanes(adev, new_lane_width); 6436 lane_width = amdgpu_get_pcie_lanes(adev); 6437 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6438 } 6439 } 6440 6441 static void si_dpm_setup_asic(struct amdgpu_device *adev) 6442 { 6443 si_read_clock_registers(adev); 6444 si_enable_acpi_power_management(adev); 6445 } 6446 6447 static int si_thermal_enable_alert(struct amdgpu_device *adev, 6448 bool enable) 6449 { 6450 u32 thermal_int = RREG32(CG_THERMAL_INT); 6451 6452 if (enable) { 6453 PPSMC_Result result; 6454 6455 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 6456 WREG32(CG_THERMAL_INT, thermal_int); 6457 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6458 if (result != PPSMC_Result_OK) { 6459 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6460 return -EINVAL; 6461 } 6462 } else { 6463 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 6464 WREG32(CG_THERMAL_INT, thermal_int); 6465 } 6466 6467 return 0; 6468 } 6469 6470 static int si_thermal_set_temperature_range(struct amdgpu_device *adev, 6471 int min_temp, int max_temp) 6472 { 6473 int low_temp = 0 * 1000; 6474 int high_temp = 255 * 1000; 6475 6476 if (low_temp < min_temp) 6477 low_temp = min_temp; 6478 if (high_temp > max_temp) 6479 high_temp = max_temp; 6480 if (high_temp < low_temp) { 6481 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6482 return -EINVAL; 6483 } 6484 6485 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 6486 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 6487 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 6488 6489 adev->pm.dpm.thermal.min_temp = low_temp; 6490 adev->pm.dpm.thermal.max_temp = high_temp; 6491 6492 return 0; 6493 } 6494 6495 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) 6496 { 6497 struct si_power_info *si_pi = si_get_pi(adev); 6498 u32 tmp; 6499 6500 if (si_pi->fan_ctrl_is_in_default_mode) { 6501 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 6502 si_pi->fan_ctrl_default_mode = tmp; 6503 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 6504 si_pi->t_min = tmp; 6505 si_pi->fan_ctrl_is_in_default_mode = false; 6506 } 6507 6508 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6509 tmp |= TMIN(0); 6510 WREG32(CG_FDO_CTRL2, tmp); 6511 6512 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6513 tmp |= FDO_PWM_MODE(mode); 6514 WREG32(CG_FDO_CTRL2, tmp); 6515 } 6516 6517 static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 6518 { 6519 struct si_power_info *si_pi = si_get_pi(adev); 6520 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6521 u32 duty100; 6522 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6523 u16 fdo_min, slope1, slope2; 6524 u32 reference_clock, tmp; 6525 int ret; 6526 u64 tmp64; 6527 6528 if (!si_pi->fan_table_start) { 6529 adev->pm.dpm.fan.ucode_fan_control = false; 6530 return 0; 6531 } 6532 6533 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6534 6535 if (duty100 == 0) { 6536 adev->pm.dpm.fan.ucode_fan_control = false; 6537 return 0; 6538 } 6539 6540 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; 6541 do_div(tmp64, 10000); 6542 fdo_min = (u16)tmp64; 6543 6544 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; 6545 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; 6546 6547 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; 6548 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; 6549 6550 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6551 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6552 6553 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); 6554 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); 6555 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); 6556 fan_table.slope1 = cpu_to_be16(slope1); 6557 fan_table.slope2 = cpu_to_be16(slope2); 6558 fan_table.fdo_min = cpu_to_be16(fdo_min); 6559 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); 6560 fan_table.hys_up = cpu_to_be16(1); 6561 fan_table.hys_slope = cpu_to_be16(1); 6562 fan_table.temp_resp_lim = cpu_to_be16(5); 6563 reference_clock = amdgpu_asic_get_xclk(adev); 6564 6565 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * 6566 reference_clock) / 1600); 6567 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6568 6569 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6570 fan_table.temp_src = (uint8_t)tmp; 6571 6572 ret = amdgpu_si_copy_bytes_to_smc(adev, 6573 si_pi->fan_table_start, 6574 (u8 *)(&fan_table), 6575 sizeof(fan_table), 6576 si_pi->sram_end); 6577 6578 if (ret) { 6579 DRM_ERROR("Failed to load fan table to the SMC."); 6580 adev->pm.dpm.fan.ucode_fan_control = false; 6581 } 6582 6583 return ret; 6584 } 6585 6586 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 6587 { 6588 struct si_power_info *si_pi = si_get_pi(adev); 6589 PPSMC_Result ret; 6590 6591 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6592 if (ret == PPSMC_Result_OK) { 6593 si_pi->fan_is_controlled_by_smc = true; 6594 return 0; 6595 } else { 6596 return -EINVAL; 6597 } 6598 } 6599 6600 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 6601 { 6602 struct si_power_info *si_pi = si_get_pi(adev); 6603 PPSMC_Result ret; 6604 6605 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6606 6607 if (ret == PPSMC_Result_OK) { 6608 si_pi->fan_is_controlled_by_smc = false; 6609 return 0; 6610 } else { 6611 return -EINVAL; 6612 } 6613 } 6614 6615 static int si_dpm_get_fan_speed_pwm(void *handle, 6616 u32 *speed) 6617 { 6618 u32 duty, duty100; 6619 u64 tmp64; 6620 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6621 6622 if (!speed) 6623 return -EINVAL; 6624 6625 if (adev->pm.no_fan) 6626 return -ENOENT; 6627 6628 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6629 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6630 6631 if (duty100 == 0) 6632 return -EINVAL; 6633 6634 tmp64 = (u64)duty * 255; 6635 do_div(tmp64, duty100); 6636 *speed = MIN((u32)tmp64, 255); 6637 6638 return 0; 6639 } 6640 6641 static int si_dpm_set_fan_speed_pwm(void *handle, 6642 u32 speed) 6643 { 6644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6645 struct si_power_info *si_pi = si_get_pi(adev); 6646 u32 tmp; 6647 u32 duty, duty100; 6648 u64 tmp64; 6649 6650 if (adev->pm.no_fan) 6651 return -ENOENT; 6652 6653 if (si_pi->fan_is_controlled_by_smc) 6654 return -EINVAL; 6655 6656 if (speed > 255) 6657 return -EINVAL; 6658 6659 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6660 6661 if (duty100 == 0) 6662 return -EINVAL; 6663 6664 tmp64 = (u64)speed * duty100; 6665 do_div(tmp64, 255); 6666 duty = (u32)tmp64; 6667 6668 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6669 tmp |= FDO_STATIC_DUTY(duty); 6670 WREG32(CG_FDO_CTRL0, tmp); 6671 6672 return 0; 6673 } 6674 6675 static int si_dpm_set_fan_control_mode(void *handle, u32 mode) 6676 { 6677 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6678 6679 if (mode == U32_MAX) 6680 return -EINVAL; 6681 6682 if (mode) { 6683 /* stop auto-manage */ 6684 if (adev->pm.dpm.fan.ucode_fan_control) 6685 si_fan_ctrl_stop_smc_fan_control(adev); 6686 si_fan_ctrl_set_static_mode(adev, mode); 6687 } else { 6688 /* restart auto-manage */ 6689 if (adev->pm.dpm.fan.ucode_fan_control) 6690 si_thermal_start_smc_fan_control(adev); 6691 else 6692 si_fan_ctrl_set_default_mode(adev); 6693 } 6694 6695 return 0; 6696 } 6697 6698 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) 6699 { 6700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6701 struct si_power_info *si_pi = si_get_pi(adev); 6702 u32 tmp; 6703 6704 if (!fan_mode) 6705 return -EINVAL; 6706 6707 if (si_pi->fan_is_controlled_by_smc) 6708 return 0; 6709 6710 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6711 *fan_mode = (tmp >> FDO_PWM_MODE_SHIFT); 6712 6713 return 0; 6714 } 6715 6716 #if 0 6717 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, 6718 u32 *speed) 6719 { 6720 u32 tach_period; 6721 u32 xclk = amdgpu_asic_get_xclk(adev); 6722 6723 if (adev->pm.no_fan) 6724 return -ENOENT; 6725 6726 if (adev->pm.fan_pulses_per_revolution == 0) 6727 return -ENOENT; 6728 6729 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6730 if (tach_period == 0) 6731 return -ENOENT; 6732 6733 *speed = 60 * xclk * 10000 / tach_period; 6734 6735 return 0; 6736 } 6737 6738 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, 6739 u32 speed) 6740 { 6741 u32 tach_period, tmp; 6742 u32 xclk = amdgpu_asic_get_xclk(adev); 6743 6744 if (adev->pm.no_fan) 6745 return -ENOENT; 6746 6747 if (adev->pm.fan_pulses_per_revolution == 0) 6748 return -ENOENT; 6749 6750 if ((speed < adev->pm.fan_min_rpm) || 6751 (speed > adev->pm.fan_max_rpm)) 6752 return -EINVAL; 6753 6754 if (adev->pm.dpm.fan.ucode_fan_control) 6755 si_fan_ctrl_stop_smc_fan_control(adev); 6756 6757 tach_period = 60 * xclk * 10000 / (8 * speed); 6758 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6759 tmp |= TARGET_PERIOD(tach_period); 6760 WREG32(CG_TACH_CTRL, tmp); 6761 6762 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); 6763 6764 return 0; 6765 } 6766 #endif 6767 6768 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) 6769 { 6770 struct si_power_info *si_pi = si_get_pi(adev); 6771 u32 tmp; 6772 6773 if (!si_pi->fan_ctrl_is_in_default_mode) { 6774 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6775 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6776 WREG32(CG_FDO_CTRL2, tmp); 6777 6778 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6779 tmp |= TMIN(si_pi->t_min); 6780 WREG32(CG_FDO_CTRL2, tmp); 6781 si_pi->fan_ctrl_is_in_default_mode = true; 6782 } 6783 } 6784 6785 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) 6786 { 6787 if (adev->pm.dpm.fan.ucode_fan_control) { 6788 si_fan_ctrl_start_smc_fan_control(adev); 6789 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); 6790 } 6791 } 6792 6793 static void si_thermal_initialize(struct amdgpu_device *adev) 6794 { 6795 u32 tmp; 6796 6797 if (adev->pm.fan_pulses_per_revolution) { 6798 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6799 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1); 6800 WREG32(CG_TACH_CTRL, tmp); 6801 } 6802 6803 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6804 tmp |= TACH_PWM_RESP_RATE(0x28); 6805 WREG32(CG_FDO_CTRL2, tmp); 6806 } 6807 6808 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) 6809 { 6810 int ret; 6811 6812 si_thermal_initialize(adev); 6813 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6814 if (ret) 6815 return ret; 6816 ret = si_thermal_enable_alert(adev, true); 6817 if (ret) 6818 return ret; 6819 if (adev->pm.dpm.fan.ucode_fan_control) { 6820 ret = si_halt_smc(adev); 6821 if (ret) 6822 return ret; 6823 ret = si_thermal_setup_fan_table(adev); 6824 if (ret) 6825 return ret; 6826 ret = si_resume_smc(adev); 6827 if (ret) 6828 return ret; 6829 si_thermal_start_smc_fan_control(adev); 6830 } 6831 6832 return 0; 6833 } 6834 6835 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) 6836 { 6837 if (!adev->pm.no_fan) { 6838 si_fan_ctrl_set_default_mode(adev); 6839 si_fan_ctrl_stop_smc_fan_control(adev); 6840 } 6841 } 6842 6843 static int si_dpm_enable(struct amdgpu_device *adev) 6844 { 6845 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6846 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6847 struct si_power_info *si_pi = si_get_pi(adev); 6848 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6849 int ret; 6850 6851 if (amdgpu_si_is_smc_running(adev)) 6852 return -EINVAL; 6853 if (pi->voltage_control || si_pi->voltage_control_svi2) 6854 si_enable_voltage_control(adev, true); 6855 if (pi->mvdd_control) 6856 si_get_mvdd_configuration(adev); 6857 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6858 ret = si_construct_voltage_tables(adev); 6859 if (ret) { 6860 DRM_ERROR("si_construct_voltage_tables failed\n"); 6861 return ret; 6862 } 6863 } 6864 if (eg_pi->dynamic_ac_timing) { 6865 ret = si_initialize_mc_reg_table(adev); 6866 if (ret) 6867 eg_pi->dynamic_ac_timing = false; 6868 } 6869 if (pi->dynamic_ss) 6870 si_enable_spread_spectrum(adev, true); 6871 if (pi->thermal_protection) 6872 si_enable_thermal_protection(adev, true); 6873 si_setup_bsp(adev); 6874 si_program_git(adev); 6875 si_program_tp(adev); 6876 si_program_tpp(adev); 6877 si_program_sstp(adev); 6878 si_enable_display_gap(adev); 6879 si_program_vc(adev); 6880 ret = si_upload_firmware(adev); 6881 if (ret) { 6882 DRM_ERROR("si_upload_firmware failed\n"); 6883 return ret; 6884 } 6885 ret = si_process_firmware_header(adev); 6886 if (ret) { 6887 DRM_ERROR("si_process_firmware_header failed\n"); 6888 return ret; 6889 } 6890 ret = si_initial_switch_from_arb_f0_to_f1(adev); 6891 if (ret) { 6892 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6893 return ret; 6894 } 6895 ret = si_init_smc_table(adev); 6896 if (ret) { 6897 DRM_ERROR("si_init_smc_table failed\n"); 6898 return ret; 6899 } 6900 ret = si_init_smc_spll_table(adev); 6901 if (ret) { 6902 DRM_ERROR("si_init_smc_spll_table failed\n"); 6903 return ret; 6904 } 6905 ret = si_init_arb_table_index(adev); 6906 if (ret) { 6907 DRM_ERROR("si_init_arb_table_index failed\n"); 6908 return ret; 6909 } 6910 if (eg_pi->dynamic_ac_timing) { 6911 ret = si_populate_mc_reg_table(adev, boot_ps); 6912 if (ret) { 6913 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6914 return ret; 6915 } 6916 } 6917 ret = si_initialize_smc_cac_tables(adev); 6918 if (ret) { 6919 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6920 return ret; 6921 } 6922 ret = si_initialize_hardware_cac_manager(adev); 6923 if (ret) { 6924 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6925 return ret; 6926 } 6927 ret = si_initialize_smc_dte_tables(adev); 6928 if (ret) { 6929 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6930 return ret; 6931 } 6932 ret = si_populate_smc_tdp_limits(adev, boot_ps); 6933 if (ret) { 6934 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6935 return ret; 6936 } 6937 ret = si_populate_smc_tdp_limits_2(adev, boot_ps); 6938 if (ret) { 6939 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6940 return ret; 6941 } 6942 si_program_response_times(adev); 6943 si_program_ds_registers(adev); 6944 si_dpm_start_smc(adev); 6945 ret = si_notify_smc_display_change(adev, false); 6946 if (ret) { 6947 DRM_ERROR("si_notify_smc_display_change failed\n"); 6948 return ret; 6949 } 6950 si_enable_sclk_control(adev, true); 6951 si_start_dpm(adev); 6952 6953 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6954 si_thermal_start_thermal_controller(adev); 6955 6956 ni_update_current_ps(adev, boot_ps); 6957 6958 return 0; 6959 } 6960 6961 static int si_set_temperature_range(struct amdgpu_device *adev) 6962 { 6963 int ret; 6964 6965 ret = si_thermal_enable_alert(adev, false); 6966 if (ret) 6967 return ret; 6968 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6969 if (ret) 6970 return ret; 6971 ret = si_thermal_enable_alert(adev, true); 6972 if (ret) 6973 return ret; 6974 6975 return ret; 6976 } 6977 6978 static void si_dpm_disable(struct amdgpu_device *adev) 6979 { 6980 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6981 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6982 6983 if (!amdgpu_si_is_smc_running(adev)) 6984 return; 6985 si_thermal_stop_thermal_controller(adev); 6986 si_disable_ulv(adev); 6987 si_clear_vc(adev); 6988 if (pi->thermal_protection) 6989 si_enable_thermal_protection(adev, false); 6990 si_enable_power_containment(adev, boot_ps, false); 6991 si_enable_smc_cac(adev, boot_ps, false); 6992 si_enable_spread_spectrum(adev, false); 6993 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6994 si_stop_dpm(adev); 6995 si_reset_to_default(adev); 6996 si_dpm_stop_smc(adev); 6997 si_force_switch_to_arb_f0(adev); 6998 6999 ni_update_current_ps(adev, boot_ps); 7000 } 7001 7002 static int si_dpm_pre_set_power_state(void *handle) 7003 { 7004 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7005 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7006 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 7007 struct amdgpu_ps *new_ps = &requested_ps; 7008 7009 ni_update_requested_ps(adev, new_ps); 7010 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); 7011 7012 return 0; 7013 } 7014 7015 static int si_power_control_set_level(struct amdgpu_device *adev) 7016 { 7017 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; 7018 int ret; 7019 7020 ret = si_restrict_performance_levels_before_switch(adev); 7021 if (ret) 7022 return ret; 7023 ret = si_halt_smc(adev); 7024 if (ret) 7025 return ret; 7026 ret = si_populate_smc_tdp_limits(adev, new_ps); 7027 if (ret) 7028 return ret; 7029 ret = si_populate_smc_tdp_limits_2(adev, new_ps); 7030 if (ret) 7031 return ret; 7032 ret = si_resume_smc(adev); 7033 if (ret) 7034 return ret; 7035 return si_set_sw_state(adev); 7036 } 7037 7038 static void si_set_vce_clock(struct amdgpu_device *adev, 7039 struct amdgpu_ps *new_rps, 7040 struct amdgpu_ps *old_rps) 7041 { 7042 if ((old_rps->evclk != new_rps->evclk) || 7043 (old_rps->ecclk != new_rps->ecclk)) { 7044 /* Turn the clocks on when encoding, off otherwise */ 7045 if (new_rps->evclk || new_rps->ecclk) { 7046 /* Place holder for future VCE1.0 porting to amdgpu 7047 vce_v1_0_enable_mgcg(adev, false, false);*/ 7048 } else { 7049 /* Place holder for future VCE1.0 porting to amdgpu 7050 vce_v1_0_enable_mgcg(adev, true, false); 7051 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/ 7052 } 7053 } 7054 } 7055 7056 static int si_dpm_set_power_state(void *handle) 7057 { 7058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7059 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7060 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7061 struct amdgpu_ps *old_ps = &eg_pi->current_rps; 7062 int ret; 7063 7064 ret = si_disable_ulv(adev); 7065 if (ret) { 7066 DRM_ERROR("si_disable_ulv failed\n"); 7067 return ret; 7068 } 7069 ret = si_restrict_performance_levels_before_switch(adev); 7070 if (ret) { 7071 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 7072 return ret; 7073 } 7074 if (eg_pi->pcie_performance_request) 7075 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); 7076 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); 7077 ret = si_enable_power_containment(adev, new_ps, false); 7078 if (ret) { 7079 DRM_ERROR("si_enable_power_containment failed\n"); 7080 return ret; 7081 } 7082 ret = si_enable_smc_cac(adev, new_ps, false); 7083 if (ret) { 7084 DRM_ERROR("si_enable_smc_cac failed\n"); 7085 return ret; 7086 } 7087 ret = si_halt_smc(adev); 7088 if (ret) { 7089 DRM_ERROR("si_halt_smc failed\n"); 7090 return ret; 7091 } 7092 ret = si_upload_sw_state(adev, new_ps); 7093 if (ret) { 7094 DRM_ERROR("si_upload_sw_state failed\n"); 7095 return ret; 7096 } 7097 ret = si_upload_smc_data(adev); 7098 if (ret) { 7099 DRM_ERROR("si_upload_smc_data failed\n"); 7100 return ret; 7101 } 7102 ret = si_upload_ulv_state(adev); 7103 if (ret) { 7104 DRM_ERROR("si_upload_ulv_state failed\n"); 7105 return ret; 7106 } 7107 if (eg_pi->dynamic_ac_timing) { 7108 ret = si_upload_mc_reg_table(adev, new_ps); 7109 if (ret) { 7110 DRM_ERROR("si_upload_mc_reg_table failed\n"); 7111 return ret; 7112 } 7113 } 7114 ret = si_program_memory_timing_parameters(adev, new_ps); 7115 if (ret) { 7116 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 7117 return ret; 7118 } 7119 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); 7120 7121 ret = si_resume_smc(adev); 7122 if (ret) { 7123 DRM_ERROR("si_resume_smc failed\n"); 7124 return ret; 7125 } 7126 ret = si_set_sw_state(adev); 7127 if (ret) { 7128 DRM_ERROR("si_set_sw_state failed\n"); 7129 return ret; 7130 } 7131 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); 7132 si_set_vce_clock(adev, new_ps, old_ps); 7133 if (eg_pi->pcie_performance_request) 7134 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); 7135 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); 7136 if (ret) { 7137 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 7138 return ret; 7139 } 7140 ret = si_enable_smc_cac(adev, new_ps, true); 7141 if (ret) { 7142 DRM_ERROR("si_enable_smc_cac failed\n"); 7143 return ret; 7144 } 7145 ret = si_enable_power_containment(adev, new_ps, true); 7146 if (ret) { 7147 DRM_ERROR("si_enable_power_containment failed\n"); 7148 return ret; 7149 } 7150 7151 ret = si_power_control_set_level(adev); 7152 if (ret) { 7153 DRM_ERROR("si_power_control_set_level failed\n"); 7154 return ret; 7155 } 7156 7157 return 0; 7158 } 7159 7160 static void si_dpm_post_set_power_state(void *handle) 7161 { 7162 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7163 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7164 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7165 7166 ni_update_current_ps(adev, new_ps); 7167 } 7168 7169 #if 0 7170 void si_dpm_reset_asic(struct amdgpu_device *adev) 7171 { 7172 si_restrict_performance_levels_before_switch(adev); 7173 si_disable_ulv(adev); 7174 si_set_boot_state(adev); 7175 } 7176 #endif 7177 7178 static void si_dpm_display_configuration_changed(void *handle) 7179 { 7180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7181 7182 si_program_display_gap(adev); 7183 } 7184 7185 7186 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, 7187 struct amdgpu_ps *rps, 7188 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 7189 u8 table_rev) 7190 { 7191 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 7192 rps->class = le16_to_cpu(non_clock_info->usClassification); 7193 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 7194 7195 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 7196 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 7197 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 7198 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 7199 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 7200 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 7201 } else { 7202 rps->vclk = 0; 7203 rps->dclk = 0; 7204 } 7205 7206 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 7207 adev->pm.dpm.boot_ps = rps; 7208 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 7209 adev->pm.dpm.uvd_ps = rps; 7210 } 7211 7212 static void si_parse_pplib_clock_info(struct amdgpu_device *adev, 7213 struct amdgpu_ps *rps, int index, 7214 union pplib_clock_info *clock_info) 7215 { 7216 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7217 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7218 struct si_power_info *si_pi = si_get_pi(adev); 7219 struct si_ps *ps = si_get_ps(rps); 7220 u16 leakage_voltage; 7221 struct rv7xx_pl *pl = &ps->performance_levels[index]; 7222 int ret; 7223 7224 ps->performance_level_count = index + 1; 7225 7226 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7227 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 7228 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7229 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 7230 7231 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7232 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7233 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7234 pl->pcie_gen = si_gen_pcie_gen_support(adev, 7235 si_pi->sys_pcie_mask, 7236 si_pi->boot_pcie_gen, 7237 clock_info->si.ucPCIEGen); 7238 7239 /* patch up vddc if necessary */ 7240 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7241 &leakage_voltage); 7242 if (ret == 0) 7243 pl->vddc = leakage_voltage; 7244 7245 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 7246 pi->acpi_vddc = pl->vddc; 7247 eg_pi->acpi_vddci = pl->vddci; 7248 si_pi->acpi_pcie_gen = pl->pcie_gen; 7249 } 7250 7251 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 7252 index == 0) { 7253 /* XXX disable for A0 tahiti */ 7254 si_pi->ulv.supported = false; 7255 si_pi->ulv.pl = *pl; 7256 si_pi->ulv.one_pcie_lane_in_ulv = false; 7257 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 7258 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 7259 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 7260 } 7261 7262 if (pi->min_vddc_in_table > pl->vddc) 7263 pi->min_vddc_in_table = pl->vddc; 7264 7265 if (pi->max_vddc_in_table < pl->vddc) 7266 pi->max_vddc_in_table = pl->vddc; 7267 7268 /* patch up boot state */ 7269 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 7270 u16 vddc, vddci, mvdd; 7271 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); 7272 pl->mclk = adev->clock.default_mclk; 7273 pl->sclk = adev->clock.default_sclk; 7274 pl->vddc = vddc; 7275 pl->vddci = vddci; 7276 si_pi->mvdd_bootup_value = mvdd; 7277 } 7278 7279 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 7280 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 7281 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 7282 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 7283 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 7284 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 7285 } 7286 } 7287 7288 union pplib_power_state { 7289 struct _ATOM_PPLIB_STATE v1; 7290 struct _ATOM_PPLIB_STATE_V2 v2; 7291 }; 7292 7293 static int si_parse_power_table(struct amdgpu_device *adev) 7294 { 7295 struct amdgpu_mode_info *mode_info = &adev->mode_info; 7296 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 7297 union pplib_power_state *power_state; 7298 int i, j, k, non_clock_array_index, clock_array_index; 7299 union pplib_clock_info *clock_info; 7300 struct _StateArray *state_array; 7301 struct _ClockInfoArray *clock_info_array; 7302 struct _NonClockInfoArray *non_clock_info_array; 7303 union power_info *power_info; 7304 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 7305 u16 data_offset; 7306 u8 frev, crev; 7307 u8 *power_state_offset; 7308 struct si_ps *ps; 7309 7310 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 7311 &frev, &crev, &data_offset)) 7312 return -EINVAL; 7313 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 7314 7315 amdgpu_add_thermal_controller(adev); 7316 7317 state_array = (struct _StateArray *) 7318 (mode_info->atom_context->bios + data_offset + 7319 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 7320 clock_info_array = (struct _ClockInfoArray *) 7321 (mode_info->atom_context->bios + data_offset + 7322 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 7323 non_clock_info_array = (struct _NonClockInfoArray *) 7324 (mode_info->atom_context->bios + data_offset + 7325 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 7326 7327 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 7328 sizeof(struct amdgpu_ps), 7329 GFP_KERNEL); 7330 if (!adev->pm.dpm.ps) 7331 return -ENOMEM; 7332 power_state_offset = (u8 *)state_array->states; 7333 for (i = 0; i < state_array->ucNumEntries; i++) { 7334 u8 *idx; 7335 power_state = (union pplib_power_state *)power_state_offset; 7336 non_clock_array_index = power_state->v2.nonClockInfoIndex; 7337 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 7338 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 7339 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL); 7340 if (ps == NULL) { 7341 kfree(adev->pm.dpm.ps); 7342 return -ENOMEM; 7343 } 7344 adev->pm.dpm.ps[i].ps_priv = ps; 7345 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 7346 non_clock_info, 7347 non_clock_info_array->ucEntrySize); 7348 k = 0; 7349 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 7350 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 7351 clock_array_index = idx[j]; 7352 if (clock_array_index >= clock_info_array->ucNumEntries) 7353 continue; 7354 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 7355 break; 7356 clock_info = (union pplib_clock_info *) 7357 ((u8 *)&clock_info_array->clockInfo[0] + 7358 (clock_array_index * clock_info_array->ucEntrySize)); 7359 si_parse_pplib_clock_info(adev, 7360 &adev->pm.dpm.ps[i], k, 7361 clock_info); 7362 k++; 7363 } 7364 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 7365 } 7366 adev->pm.dpm.num_ps = state_array->ucNumEntries; 7367 7368 /* fill in the vce power states */ 7369 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7370 u32 sclk, mclk; 7371 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7372 clock_info = (union pplib_clock_info *) 7373 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 7374 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7375 sclk |= clock_info->si.ucEngineClockHigh << 16; 7376 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7377 mclk |= clock_info->si.ucMemoryClockHigh << 16; 7378 adev->pm.dpm.vce_states[i].sclk = sclk; 7379 adev->pm.dpm.vce_states[i].mclk = mclk; 7380 } 7381 7382 return 0; 7383 } 7384 7385 static int si_dpm_init(struct amdgpu_device *adev) 7386 { 7387 struct rv7xx_power_info *pi; 7388 struct evergreen_power_info *eg_pi; 7389 struct ni_power_info *ni_pi; 7390 struct si_power_info *si_pi; 7391 struct atom_clock_dividers dividers; 7392 int ret; 7393 7394 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 7395 if (si_pi == NULL) 7396 return -ENOMEM; 7397 adev->pm.dpm.priv = si_pi; 7398 ni_pi = &si_pi->ni; 7399 eg_pi = &ni_pi->eg; 7400 pi = &eg_pi->rv7xx; 7401 7402 si_pi->sys_pcie_mask = 7403 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; 7404 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 7405 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7406 7407 si_set_max_cu_value(adev); 7408 7409 rv770_get_max_vddc(adev); 7410 si_get_leakage_vddc(adev); 7411 si_patch_dependency_tables_based_on_leakage(adev); 7412 7413 pi->acpi_vddc = 0; 7414 eg_pi->acpi_vddci = 0; 7415 pi->min_vddc_in_table = 0; 7416 pi->max_vddc_in_table = 0; 7417 7418 ret = amdgpu_get_platform_caps(adev); 7419 if (ret) 7420 return ret; 7421 7422 ret = amdgpu_parse_extended_power_table(adev); 7423 if (ret) 7424 return ret; 7425 7426 ret = si_parse_power_table(adev); 7427 if (ret) 7428 return ret; 7429 7430 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7431 kcalloc(4, 7432 sizeof(struct amdgpu_clock_voltage_dependency_entry), 7433 GFP_KERNEL); 7434 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 7435 amdgpu_free_extended_power_table(adev); 7436 return -ENOMEM; 7437 } 7438 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7439 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7440 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7441 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7442 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7443 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7444 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7445 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7446 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7447 7448 if (adev->pm.dpm.voltage_response_time == 0) 7449 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7450 if (adev->pm.dpm.backbias_response_time == 0) 7451 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7452 7453 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 7454 0, false, ÷rs); 7455 if (ret) 7456 pi->ref_div = dividers.ref_div + 1; 7457 else 7458 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7459 7460 eg_pi->smu_uvd_hs = false; 7461 7462 pi->mclk_strobe_mode_threshold = 40000; 7463 if (si_is_special_1gb_platform(adev)) 7464 pi->mclk_stutter_mode_threshold = 0; 7465 else 7466 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7467 pi->mclk_edc_enable_threshold = 40000; 7468 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7469 7470 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7471 7472 pi->voltage_control = 7473 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7474 VOLTAGE_OBJ_GPIO_LUT); 7475 if (!pi->voltage_control) { 7476 si_pi->voltage_control_svi2 = 7477 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7478 VOLTAGE_OBJ_SVID2); 7479 if (si_pi->voltage_control_svi2) 7480 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7481 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7482 } 7483 7484 pi->mvdd_control = 7485 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7486 VOLTAGE_OBJ_GPIO_LUT); 7487 7488 eg_pi->vddci_control = 7489 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7490 VOLTAGE_OBJ_GPIO_LUT); 7491 if (!eg_pi->vddci_control) 7492 si_pi->vddci_control_svi2 = 7493 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7494 VOLTAGE_OBJ_SVID2); 7495 7496 si_pi->vddc_phase_shed_control = 7497 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7498 VOLTAGE_OBJ_PHASE_LUT); 7499 7500 rv770_get_engine_memory_ss(adev); 7501 7502 pi->asi = RV770_ASI_DFLT; 7503 pi->pasi = CYPRESS_HASI_DFLT; 7504 pi->vrc = SISLANDS_VRC_DFLT; 7505 7506 pi->gfx_clock_gating = true; 7507 7508 eg_pi->sclk_deep_sleep = true; 7509 si_pi->sclk_deep_sleep_above_low = false; 7510 7511 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7512 pi->thermal_protection = true; 7513 else 7514 pi->thermal_protection = false; 7515 7516 eg_pi->dynamic_ac_timing = true; 7517 7518 eg_pi->light_sleep = true; 7519 #if defined(CONFIG_ACPI) 7520 eg_pi->pcie_performance_request = 7521 amdgpu_acpi_is_pcie_performance_request_supported(adev); 7522 #else 7523 eg_pi->pcie_performance_request = false; 7524 #endif 7525 7526 si_pi->sram_end = SMC_RAM_END; 7527 7528 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7529 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7530 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7531 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7532 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7533 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7534 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7535 7536 si_initialize_powertune_defaults(adev); 7537 7538 /* make sure dc limits are valid */ 7539 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7540 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7541 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7542 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7543 7544 si_pi->fan_ctrl_is_in_default_mode = true; 7545 7546 return 0; 7547 } 7548 7549 static void si_dpm_fini(struct amdgpu_device *adev) 7550 { 7551 int i; 7552 7553 if (adev->pm.dpm.ps) 7554 for (i = 0; i < adev->pm.dpm.num_ps; i++) 7555 kfree(adev->pm.dpm.ps[i].ps_priv); 7556 kfree(adev->pm.dpm.ps); 7557 kfree(adev->pm.dpm.priv); 7558 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7559 amdgpu_free_extended_power_table(adev); 7560 } 7561 7562 static void si_dpm_debugfs_print_current_performance_level(void *handle, 7563 struct seq_file *m) 7564 { 7565 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7566 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7567 struct amdgpu_ps *rps = &eg_pi->current_rps; 7568 struct si_ps *ps = si_get_ps(rps); 7569 struct rv7xx_pl *pl; 7570 u32 current_index = 7571 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7572 CURRENT_STATE_INDEX_SHIFT; 7573 7574 if (current_index >= ps->performance_level_count) { 7575 seq_printf(m, "invalid dpm profile %d\n", current_index); 7576 } else { 7577 pl = &ps->performance_levels[current_index]; 7578 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7579 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7580 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7581 } 7582 } 7583 7584 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, 7585 struct amdgpu_irq_src *source, 7586 unsigned type, 7587 enum amdgpu_interrupt_state state) 7588 { 7589 u32 cg_thermal_int; 7590 7591 switch (type) { 7592 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 7593 switch (state) { 7594 case AMDGPU_IRQ_STATE_DISABLE: 7595 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7596 cg_thermal_int |= THERM_INT_MASK_HIGH; 7597 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7598 break; 7599 case AMDGPU_IRQ_STATE_ENABLE: 7600 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7601 cg_thermal_int &= ~THERM_INT_MASK_HIGH; 7602 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7603 break; 7604 default: 7605 break; 7606 } 7607 break; 7608 7609 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 7610 switch (state) { 7611 case AMDGPU_IRQ_STATE_DISABLE: 7612 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7613 cg_thermal_int |= THERM_INT_MASK_LOW; 7614 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7615 break; 7616 case AMDGPU_IRQ_STATE_ENABLE: 7617 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); 7618 cg_thermal_int &= ~THERM_INT_MASK_LOW; 7619 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); 7620 break; 7621 default: 7622 break; 7623 } 7624 break; 7625 7626 default: 7627 break; 7628 } 7629 return 0; 7630 } 7631 7632 static int si_dpm_process_interrupt(struct amdgpu_device *adev, 7633 struct amdgpu_irq_src *source, 7634 struct amdgpu_iv_entry *entry) 7635 { 7636 bool queue_thermal = false; 7637 7638 if (entry == NULL) 7639 return -EINVAL; 7640 7641 switch (entry->src_id) { 7642 case 230: /* thermal low to high */ 7643 DRM_DEBUG("IH: thermal low to high\n"); 7644 adev->pm.dpm.thermal.high_to_low = false; 7645 queue_thermal = true; 7646 break; 7647 case 231: /* thermal high to low */ 7648 DRM_DEBUG("IH: thermal high to low\n"); 7649 adev->pm.dpm.thermal.high_to_low = true; 7650 queue_thermal = true; 7651 break; 7652 default: 7653 break; 7654 } 7655 7656 if (queue_thermal) 7657 schedule_work(&adev->pm.dpm.thermal.work); 7658 7659 return 0; 7660 } 7661 7662 static int si_dpm_late_init(void *handle) 7663 { 7664 int ret; 7665 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7666 7667 if (!adev->pm.dpm_enabled) 7668 return 0; 7669 7670 ret = si_set_temperature_range(adev); 7671 if (ret) 7672 return ret; 7673 #if 0 //TODO ? 7674 si_dpm_powergate_uvd(adev, true); 7675 #endif 7676 return 0; 7677 } 7678 7679 /** 7680 * si_dpm_init_microcode - load ucode images from disk 7681 * 7682 * @adev: amdgpu_device pointer 7683 * 7684 * Use the firmware interface to load the ucode images into 7685 * the driver (not loaded into hw). 7686 * Returns 0 on success, error on failure. 7687 */ 7688 static int si_dpm_init_microcode(struct amdgpu_device *adev) 7689 { 7690 const char *chip_name; 7691 char fw_name[30]; 7692 int err; 7693 7694 DRM_DEBUG("\n"); 7695 switch (adev->asic_type) { 7696 case CHIP_TAHITI: 7697 chip_name = "tahiti"; 7698 break; 7699 case CHIP_PITCAIRN: 7700 if ((adev->pdev->revision == 0x81) && 7701 ((adev->pdev->device == 0x6810) || 7702 (adev->pdev->device == 0x6811))) 7703 chip_name = "pitcairn_k"; 7704 else 7705 chip_name = "pitcairn"; 7706 break; 7707 case CHIP_VERDE: 7708 if (((adev->pdev->device == 0x6820) && 7709 ((adev->pdev->revision == 0x81) || 7710 (adev->pdev->revision == 0x83))) || 7711 ((adev->pdev->device == 0x6821) && 7712 ((adev->pdev->revision == 0x83) || 7713 (adev->pdev->revision == 0x87))) || 7714 ((adev->pdev->revision == 0x87) && 7715 ((adev->pdev->device == 0x6823) || 7716 (adev->pdev->device == 0x682b)))) 7717 chip_name = "verde_k"; 7718 else 7719 chip_name = "verde"; 7720 break; 7721 case CHIP_OLAND: 7722 if (((adev->pdev->revision == 0x81) && 7723 ((adev->pdev->device == 0x6600) || 7724 (adev->pdev->device == 0x6604) || 7725 (adev->pdev->device == 0x6605) || 7726 (adev->pdev->device == 0x6610))) || 7727 ((adev->pdev->revision == 0x83) && 7728 (adev->pdev->device == 0x6610))) 7729 chip_name = "oland_k"; 7730 else 7731 chip_name = "oland"; 7732 break; 7733 case CHIP_HAINAN: 7734 if (((adev->pdev->revision == 0x81) && 7735 (adev->pdev->device == 0x6660)) || 7736 ((adev->pdev->revision == 0x83) && 7737 ((adev->pdev->device == 0x6660) || 7738 (adev->pdev->device == 0x6663) || 7739 (adev->pdev->device == 0x6665) || 7740 (adev->pdev->device == 0x6667)))) 7741 chip_name = "hainan_k"; 7742 else if ((adev->pdev->revision == 0xc3) && 7743 (adev->pdev->device == 0x6665)) 7744 chip_name = "banks_k_2"; 7745 else 7746 chip_name = "hainan"; 7747 break; 7748 default: BUG(); 7749 } 7750 7751 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); 7752 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); 7753 if (err) 7754 goto out; 7755 err = amdgpu_ucode_validate(adev->pm.fw); 7756 7757 out: 7758 if (err) { 7759 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n", 7760 err, fw_name); 7761 release_firmware(adev->pm.fw); 7762 adev->pm.fw = NULL; 7763 } 7764 return err; 7765 7766 } 7767 7768 static int si_dpm_sw_init(void *handle) 7769 { 7770 int ret; 7771 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7772 7773 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); 7774 if (ret) 7775 return ret; 7776 7777 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); 7778 if (ret) 7779 return ret; 7780 7781 /* default to balanced state */ 7782 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 7783 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 7784 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 7785 adev->pm.default_sclk = adev->clock.default_sclk; 7786 adev->pm.default_mclk = adev->clock.default_mclk; 7787 adev->pm.current_sclk = adev->clock.default_sclk; 7788 adev->pm.current_mclk = adev->clock.default_mclk; 7789 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 7790 7791 if (amdgpu_dpm == 0) 7792 return 0; 7793 7794 ret = si_dpm_init_microcode(adev); 7795 if (ret) 7796 return ret; 7797 7798 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7799 ret = si_dpm_init(adev); 7800 if (ret) 7801 goto dpm_failed; 7802 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7803 if (amdgpu_dpm == 1) 7804 amdgpu_pm_print_power_states(adev); 7805 DRM_INFO("amdgpu: dpm initialized\n"); 7806 7807 return 0; 7808 7809 dpm_failed: 7810 si_dpm_fini(adev); 7811 DRM_ERROR("amdgpu: dpm initialization failed\n"); 7812 return ret; 7813 } 7814 7815 static int si_dpm_sw_fini(void *handle) 7816 { 7817 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7818 7819 flush_work(&adev->pm.dpm.thermal.work); 7820 7821 si_dpm_fini(adev); 7822 7823 return 0; 7824 } 7825 7826 static int si_dpm_hw_init(void *handle) 7827 { 7828 int ret; 7829 7830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7831 7832 if (!amdgpu_dpm) 7833 return 0; 7834 7835 si_dpm_setup_asic(adev); 7836 ret = si_dpm_enable(adev); 7837 if (ret) 7838 adev->pm.dpm_enabled = false; 7839 else 7840 adev->pm.dpm_enabled = true; 7841 amdgpu_legacy_dpm_compute_clocks(adev); 7842 return ret; 7843 } 7844 7845 static int si_dpm_hw_fini(void *handle) 7846 { 7847 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7848 7849 if (adev->pm.dpm_enabled) 7850 si_dpm_disable(adev); 7851 7852 return 0; 7853 } 7854 7855 static int si_dpm_suspend(void *handle) 7856 { 7857 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7858 7859 if (adev->pm.dpm_enabled) { 7860 /* disable dpm */ 7861 si_dpm_disable(adev); 7862 /* reset the power state */ 7863 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7864 } 7865 return 0; 7866 } 7867 7868 static int si_dpm_resume(void *handle) 7869 { 7870 int ret; 7871 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7872 7873 if (adev->pm.dpm_enabled) { 7874 /* asic init will reset to the boot state */ 7875 si_dpm_setup_asic(adev); 7876 ret = si_dpm_enable(adev); 7877 if (ret) 7878 adev->pm.dpm_enabled = false; 7879 else 7880 adev->pm.dpm_enabled = true; 7881 if (adev->pm.dpm_enabled) 7882 amdgpu_legacy_dpm_compute_clocks(adev); 7883 } 7884 return 0; 7885 } 7886 7887 static bool si_dpm_is_idle(void *handle) 7888 { 7889 /* XXX */ 7890 return true; 7891 } 7892 7893 static int si_dpm_wait_for_idle(void *handle) 7894 { 7895 /* XXX */ 7896 return 0; 7897 } 7898 7899 static int si_dpm_soft_reset(void *handle) 7900 { 7901 return 0; 7902 } 7903 7904 static int si_dpm_set_clockgating_state(void *handle, 7905 enum amd_clockgating_state state) 7906 { 7907 return 0; 7908 } 7909 7910 static int si_dpm_set_powergating_state(void *handle, 7911 enum amd_powergating_state state) 7912 { 7913 return 0; 7914 } 7915 7916 /* get temperature in millidegrees */ 7917 static int si_dpm_get_temp(void *handle) 7918 { 7919 u32 temp; 7920 int actual_temp = 0; 7921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7922 7923 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 7924 CTF_TEMP_SHIFT; 7925 7926 if (temp & 0x200) 7927 actual_temp = 255; 7928 else 7929 actual_temp = temp & 0x1ff; 7930 7931 actual_temp = (actual_temp * 1000); 7932 7933 return actual_temp; 7934 } 7935 7936 static u32 si_dpm_get_sclk(void *handle, bool low) 7937 { 7938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7939 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7940 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7941 7942 if (low) 7943 return requested_state->performance_levels[0].sclk; 7944 else 7945 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7946 } 7947 7948 static u32 si_dpm_get_mclk(void *handle, bool low) 7949 { 7950 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7951 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7952 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7953 7954 if (low) 7955 return requested_state->performance_levels[0].mclk; 7956 else 7957 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7958 } 7959 7960 static void si_dpm_print_power_state(void *handle, 7961 void *current_ps) 7962 { 7963 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7964 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 7965 struct si_ps *ps = si_get_ps(rps); 7966 struct rv7xx_pl *pl; 7967 int i; 7968 7969 amdgpu_dpm_print_class_info(rps->class, rps->class2); 7970 amdgpu_dpm_print_cap_info(rps->caps); 7971 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7972 for (i = 0; i < ps->performance_level_count; i++) { 7973 pl = &ps->performance_levels[i]; 7974 if (adev->asic_type >= CHIP_TAHITI) 7975 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7976 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7977 else 7978 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n", 7979 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); 7980 } 7981 amdgpu_dpm_print_ps_status(adev, rps); 7982 } 7983 7984 static int si_dpm_early_init(void *handle) 7985 { 7986 7987 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7988 7989 adev->powerplay.pp_funcs = &si_dpm_funcs; 7990 adev->powerplay.pp_handle = adev; 7991 si_dpm_set_irq_funcs(adev); 7992 return 0; 7993 } 7994 7995 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, 7996 const struct rv7xx_pl *si_cpl2) 7997 { 7998 return ((si_cpl1->mclk == si_cpl2->mclk) && 7999 (si_cpl1->sclk == si_cpl2->sclk) && 8000 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && 8001 (si_cpl1->vddc == si_cpl2->vddc) && 8002 (si_cpl1->vddci == si_cpl2->vddci)); 8003 } 8004 8005 static int si_check_state_equal(void *handle, 8006 void *current_ps, 8007 void *request_ps, 8008 bool *equal) 8009 { 8010 struct si_ps *si_cps; 8011 struct si_ps *si_rps; 8012 int i; 8013 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 8014 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 8015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8016 8017 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 8018 return -EINVAL; 8019 8020 si_cps = si_get_ps((struct amdgpu_ps *)cps); 8021 si_rps = si_get_ps((struct amdgpu_ps *)rps); 8022 8023 if (si_cps == NULL) { 8024 printk("si_cps is NULL\n"); 8025 *equal = false; 8026 return 0; 8027 } 8028 8029 if (si_cps->performance_level_count != si_rps->performance_level_count) { 8030 *equal = false; 8031 return 0; 8032 } 8033 8034 for (i = 0; i < si_cps->performance_level_count; i++) { 8035 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), 8036 &(si_rps->performance_levels[i]))) { 8037 *equal = false; 8038 return 0; 8039 } 8040 } 8041 8042 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 8043 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 8044 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 8045 8046 return 0; 8047 } 8048 8049 static int si_dpm_read_sensor(void *handle, int idx, 8050 void *value, int *size) 8051 { 8052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8053 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8054 struct amdgpu_ps *rps = &eg_pi->current_rps; 8055 struct si_ps *ps = si_get_ps(rps); 8056 uint32_t sclk, mclk; 8057 u32 pl_index = 8058 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 8059 CURRENT_STATE_INDEX_SHIFT; 8060 8061 /* size must be at least 4 bytes for all sensors */ 8062 if (*size < 4) 8063 return -EINVAL; 8064 8065 switch (idx) { 8066 case AMDGPU_PP_SENSOR_GFX_SCLK: 8067 if (pl_index < ps->performance_level_count) { 8068 sclk = ps->performance_levels[pl_index].sclk; 8069 *((uint32_t *)value) = sclk; 8070 *size = 4; 8071 return 0; 8072 } 8073 return -EINVAL; 8074 case AMDGPU_PP_SENSOR_GFX_MCLK: 8075 if (pl_index < ps->performance_level_count) { 8076 mclk = ps->performance_levels[pl_index].mclk; 8077 *((uint32_t *)value) = mclk; 8078 *size = 4; 8079 return 0; 8080 } 8081 return -EINVAL; 8082 case AMDGPU_PP_SENSOR_GPU_TEMP: 8083 *((uint32_t *)value) = si_dpm_get_temp(adev); 8084 *size = 4; 8085 return 0; 8086 default: 8087 return -EOPNOTSUPP; 8088 } 8089 } 8090 8091 static const struct amd_ip_funcs si_dpm_ip_funcs = { 8092 .name = "si_dpm", 8093 .early_init = si_dpm_early_init, 8094 .late_init = si_dpm_late_init, 8095 .sw_init = si_dpm_sw_init, 8096 .sw_fini = si_dpm_sw_fini, 8097 .hw_init = si_dpm_hw_init, 8098 .hw_fini = si_dpm_hw_fini, 8099 .suspend = si_dpm_suspend, 8100 .resume = si_dpm_resume, 8101 .is_idle = si_dpm_is_idle, 8102 .wait_for_idle = si_dpm_wait_for_idle, 8103 .soft_reset = si_dpm_soft_reset, 8104 .set_clockgating_state = si_dpm_set_clockgating_state, 8105 .set_powergating_state = si_dpm_set_powergating_state, 8106 }; 8107 8108 const struct amdgpu_ip_block_version si_smu_ip_block = 8109 { 8110 .type = AMD_IP_BLOCK_TYPE_SMC, 8111 .major = 6, 8112 .minor = 0, 8113 .rev = 0, 8114 .funcs = &si_dpm_ip_funcs, 8115 }; 8116 8117 static const struct amd_pm_funcs si_dpm_funcs = { 8118 .pre_set_power_state = &si_dpm_pre_set_power_state, 8119 .set_power_state = &si_dpm_set_power_state, 8120 .post_set_power_state = &si_dpm_post_set_power_state, 8121 .display_configuration_changed = &si_dpm_display_configuration_changed, 8122 .get_sclk = &si_dpm_get_sclk, 8123 .get_mclk = &si_dpm_get_mclk, 8124 .print_power_state = &si_dpm_print_power_state, 8125 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8126 .force_performance_level = &si_dpm_force_performance_level, 8127 .set_powergating_by_smu = &si_set_powergating_by_smu, 8128 .vblank_too_short = &si_dpm_vblank_too_short, 8129 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8130 .get_fan_control_mode = &si_dpm_get_fan_control_mode, 8131 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm, 8132 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm, 8133 .check_state_equal = &si_check_state_equal, 8134 .get_vce_clock_state = amdgpu_get_vce_clock_state, 8135 .read_sensor = &si_dpm_read_sensor, 8136 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 8137 }; 8138 8139 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { 8140 .set = si_dpm_set_interrupt_state, 8141 .process = si_dpm_process_interrupt, 8142 }; 8143 8144 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) 8145 { 8146 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 8147 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8148 } 8149 8150