1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "cikd.h" 27 #include "atom.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_dpm.h" 30 #include "kv_dpm.h" 31 #include "gfx_v7_0.h" 32 #include <linux/seq_file.h> 33 34 #include "smu/smu_7_0_0_d.h" 35 #include "smu/smu_7_0_0_sh_mask.h" 36 37 #include "gca/gfx_7_2_d.h" 38 #include "gca/gfx_7_2_sh_mask.h" 39 #include "legacy_dpm.h" 40 41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 42 #define KV_MINIMUM_ENGINE_CLOCK 800 43 #define SMC_RAM_END 0x40000 44 45 static const struct amd_pm_funcs kv_dpm_funcs; 46 47 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev); 48 static int kv_enable_nb_dpm(struct amdgpu_device *adev, 49 bool enable); 50 static void kv_init_graphics_levels(struct amdgpu_device *adev); 51 static int kv_calculate_ds_divider(struct amdgpu_device *adev); 52 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev); 53 static int kv_calculate_dpm_settings(struct amdgpu_device *adev); 54 static void kv_enable_new_levels(struct amdgpu_device *adev); 55 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, 56 struct amdgpu_ps *new_rps); 57 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level); 58 static int kv_set_enabled_levels(struct amdgpu_device *adev); 59 static int kv_force_dpm_highest(struct amdgpu_device *adev); 60 static int kv_force_dpm_lowest(struct amdgpu_device *adev); 61 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, 62 struct amdgpu_ps *new_rps, 63 struct amdgpu_ps *old_rps); 64 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, 65 int min_temp, int max_temp); 66 static int kv_init_fps_limits(struct amdgpu_device *adev); 67 68 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate); 69 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate); 70 71 72 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, 73 struct sumo_vid_mapping_table *vid_mapping_table, 74 u32 vid_2bit) 75 { 76 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table = 77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 78 u32 i; 79 80 if (vddc_sclk_table && vddc_sclk_table->count) { 81 if (vid_2bit < vddc_sclk_table->count) 82 return vddc_sclk_table->entries[vid_2bit].v; 83 else 84 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v; 85 } else { 86 for (i = 0; i < vid_mapping_table->num_entries; i++) { 87 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) 88 return vid_mapping_table->entries[i].vid_7bit; 89 } 90 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; 91 } 92 } 93 94 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, 95 struct sumo_vid_mapping_table *vid_mapping_table, 96 u32 vid_7bit) 97 { 98 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table = 99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 100 u32 i; 101 102 if (vddc_sclk_table && vddc_sclk_table->count) { 103 for (i = 0; i < vddc_sclk_table->count; i++) { 104 if (vddc_sclk_table->entries[i].v == vid_7bit) 105 return i; 106 } 107 return vddc_sclk_table->count - 1; 108 } else { 109 for (i = 0; i < vid_mapping_table->num_entries; i++) { 110 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) 111 return vid_mapping_table->entries[i].vid_2bit; 112 } 113 114 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; 115 } 116 } 117 118 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) 119 { 120 /* This bit selects who handles display phy powergating. 121 * Clear the bit to let atom handle it. 122 * Set it to let the driver handle it. 123 * For now we just let atom handle it. 124 */ 125 #if 0 126 u32 v = RREG32(mmDOUT_SCRATCH3); 127 128 if (enable) 129 v |= 0x4; 130 else 131 v &= 0xFFFFFFFB; 132 133 WREG32(mmDOUT_SCRATCH3, v); 134 #endif 135 } 136 137 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, 138 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, 139 ATOM_AVAILABLE_SCLK_LIST *table) 140 { 141 u32 i; 142 u32 n = 0; 143 u32 prev_sclk = 0; 144 145 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { 146 if (table[i].ulSupportedSCLK > prev_sclk) { 147 sclk_voltage_mapping_table->entries[n].sclk_frequency = 148 table[i].ulSupportedSCLK; 149 sclk_voltage_mapping_table->entries[n].vid_2bit = 150 table[i].usVoltageIndex; 151 prev_sclk = table[i].ulSupportedSCLK; 152 n++; 153 } 154 } 155 156 sclk_voltage_mapping_table->num_max_dpm_entries = n; 157 } 158 159 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, 160 struct sumo_vid_mapping_table *vid_mapping_table, 161 ATOM_AVAILABLE_SCLK_LIST *table) 162 { 163 u32 i, j; 164 165 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { 166 if (table[i].ulSupportedSCLK != 0) { 167 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = 168 table[i].usVoltageID; 169 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = 170 table[i].usVoltageIndex; 171 } 172 } 173 174 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { 175 if (vid_mapping_table->entries[i].vid_7bit == 0) { 176 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { 177 if (vid_mapping_table->entries[j].vid_7bit != 0) { 178 vid_mapping_table->entries[i] = 179 vid_mapping_table->entries[j]; 180 vid_mapping_table->entries[j].vid_7bit = 0; 181 break; 182 } 183 } 184 185 if (j == SUMO_MAX_NUMBER_VOLTAGES) 186 break; 187 } 188 } 189 190 vid_mapping_table->num_entries = i; 191 } 192 193 #if 0 194 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = 195 { 196 { 0, 4, 1 }, 197 { 1, 4, 1 }, 198 { 2, 5, 1 }, 199 { 3, 4, 2 }, 200 { 4, 1, 1 }, 201 { 5, 5, 2 }, 202 { 6, 6, 1 }, 203 { 7, 9, 2 }, 204 { 0xffffffff } 205 }; 206 207 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = 208 { 209 { 0, 4, 1 }, 210 { 0xffffffff } 211 }; 212 213 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = 214 { 215 { 0, 4, 1 }, 216 { 0xffffffff } 217 }; 218 219 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = 220 { 221 { 0, 4, 1 }, 222 { 0xffffffff } 223 }; 224 225 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = 226 { 227 { 0, 4, 1 }, 228 { 0xffffffff } 229 }; 230 231 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = 232 { 233 { 0, 4, 1 }, 234 { 1, 4, 1 }, 235 { 2, 5, 1 }, 236 { 3, 4, 1 }, 237 { 4, 1, 1 }, 238 { 5, 5, 1 }, 239 { 6, 6, 1 }, 240 { 7, 9, 1 }, 241 { 8, 4, 1 }, 242 { 9, 2, 1 }, 243 { 10, 3, 1 }, 244 { 11, 6, 1 }, 245 { 12, 8, 2 }, 246 { 13, 1, 1 }, 247 { 14, 2, 1 }, 248 { 15, 3, 1 }, 249 { 16, 1, 1 }, 250 { 17, 4, 1 }, 251 { 18, 3, 1 }, 252 { 19, 1, 1 }, 253 { 20, 8, 1 }, 254 { 21, 5, 1 }, 255 { 22, 1, 1 }, 256 { 23, 1, 1 }, 257 { 24, 4, 1 }, 258 { 27, 6, 1 }, 259 { 28, 1, 1 }, 260 { 0xffffffff } 261 }; 262 263 static const struct kv_lcac_config_reg sx0_cac_config_reg[] = 264 { 265 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 266 }; 267 268 static const struct kv_lcac_config_reg mc0_cac_config_reg[] = 269 { 270 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 271 }; 272 273 static const struct kv_lcac_config_reg mc1_cac_config_reg[] = 274 { 275 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 276 }; 277 278 static const struct kv_lcac_config_reg mc2_cac_config_reg[] = 279 { 280 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 281 }; 282 283 static const struct kv_lcac_config_reg mc3_cac_config_reg[] = 284 { 285 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 286 }; 287 288 static const struct kv_lcac_config_reg cpl_cac_config_reg[] = 289 { 290 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 291 }; 292 #endif 293 294 static const struct kv_pt_config_reg didt_config_kv[] = 295 { 296 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 297 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 298 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 299 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 300 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 301 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 302 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 303 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 304 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 305 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 306 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 307 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 308 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 309 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 310 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 311 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 312 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 313 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 314 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 315 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 316 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 317 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 318 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 319 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 320 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 321 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 322 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 323 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 324 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 325 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 326 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 327 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 328 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 329 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 330 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 331 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 332 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 333 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 334 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 335 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 336 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 337 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 338 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 339 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 340 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 341 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 342 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 343 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 344 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 345 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 346 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 347 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 348 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 349 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 350 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 351 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 352 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 353 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 354 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 355 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 356 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 357 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 358 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 359 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 360 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 361 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 362 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 363 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 364 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 365 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 366 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 367 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 368 { 0xFFFFFFFF } 369 }; 370 371 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps) 372 { 373 struct kv_ps *ps = rps->ps_priv; 374 375 return ps; 376 } 377 378 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) 379 { 380 struct kv_power_info *pi = adev->pm.dpm.priv; 381 382 return pi; 383 } 384 385 #if 0 386 static void kv_program_local_cac_table(struct amdgpu_device *adev, 387 const struct kv_lcac_config_values *local_cac_table, 388 const struct kv_lcac_config_reg *local_cac_reg) 389 { 390 u32 i, count, data; 391 const struct kv_lcac_config_values *values = local_cac_table; 392 393 while (values->block_id != 0xffffffff) { 394 count = values->signal_id; 395 for (i = 0; i < count; i++) { 396 data = ((values->block_id << local_cac_reg->block_shift) & 397 local_cac_reg->block_mask); 398 data |= ((i << local_cac_reg->signal_shift) & 399 local_cac_reg->signal_mask); 400 data |= ((values->t << local_cac_reg->t_shift) & 401 local_cac_reg->t_mask); 402 data |= ((1 << local_cac_reg->enable_shift) & 403 local_cac_reg->enable_mask); 404 WREG32_SMC(local_cac_reg->cntl, data); 405 } 406 values++; 407 } 408 } 409 #endif 410 411 static int kv_program_pt_config_registers(struct amdgpu_device *adev, 412 const struct kv_pt_config_reg *cac_config_regs) 413 { 414 const struct kv_pt_config_reg *config_regs = cac_config_regs; 415 u32 data; 416 u32 cache = 0; 417 418 if (config_regs == NULL) 419 return -EINVAL; 420 421 while (config_regs->offset != 0xFFFFFFFF) { 422 if (config_regs->type == KV_CONFIGREG_CACHE) { 423 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 424 } else { 425 switch (config_regs->type) { 426 case KV_CONFIGREG_SMC_IND: 427 data = RREG32_SMC(config_regs->offset); 428 break; 429 case KV_CONFIGREG_DIDT_IND: 430 data = RREG32_DIDT(config_regs->offset); 431 break; 432 default: 433 data = RREG32(config_regs->offset); 434 break; 435 } 436 437 data &= ~config_regs->mask; 438 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 439 data |= cache; 440 cache = 0; 441 442 switch (config_regs->type) { 443 case KV_CONFIGREG_SMC_IND: 444 WREG32_SMC(config_regs->offset, data); 445 break; 446 case KV_CONFIGREG_DIDT_IND: 447 WREG32_DIDT(config_regs->offset, data); 448 break; 449 default: 450 WREG32(config_regs->offset, data); 451 break; 452 } 453 } 454 config_regs++; 455 } 456 457 return 0; 458 } 459 460 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) 461 { 462 struct kv_power_info *pi = kv_get_pi(adev); 463 u32 data; 464 465 if (pi->caps_sq_ramping) { 466 data = RREG32_DIDT(ixDIDT_SQ_CTRL0); 467 if (enable) 468 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; 469 else 470 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; 471 WREG32_DIDT(ixDIDT_SQ_CTRL0, data); 472 } 473 474 if (pi->caps_db_ramping) { 475 data = RREG32_DIDT(ixDIDT_DB_CTRL0); 476 if (enable) 477 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; 478 else 479 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; 480 WREG32_DIDT(ixDIDT_DB_CTRL0, data); 481 } 482 483 if (pi->caps_td_ramping) { 484 data = RREG32_DIDT(ixDIDT_TD_CTRL0); 485 if (enable) 486 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; 487 else 488 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; 489 WREG32_DIDT(ixDIDT_TD_CTRL0, data); 490 } 491 492 if (pi->caps_tcp_ramping) { 493 data = RREG32_DIDT(ixDIDT_TCP_CTRL0); 494 if (enable) 495 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; 496 else 497 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; 498 WREG32_DIDT(ixDIDT_TCP_CTRL0, data); 499 } 500 } 501 502 static int kv_enable_didt(struct amdgpu_device *adev, bool enable) 503 { 504 struct kv_power_info *pi = kv_get_pi(adev); 505 int ret; 506 507 if (pi->caps_sq_ramping || 508 pi->caps_db_ramping || 509 pi->caps_td_ramping || 510 pi->caps_tcp_ramping) { 511 amdgpu_gfx_rlc_enter_safe_mode(adev); 512 513 if (enable) { 514 ret = kv_program_pt_config_registers(adev, didt_config_kv); 515 if (ret) { 516 amdgpu_gfx_rlc_exit_safe_mode(adev); 517 return ret; 518 } 519 } 520 521 kv_do_enable_didt(adev, enable); 522 523 amdgpu_gfx_rlc_exit_safe_mode(adev); 524 } 525 526 return 0; 527 } 528 529 #if 0 530 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev) 531 { 532 struct kv_power_info *pi = kv_get_pi(adev); 533 534 if (pi->caps_cac) { 535 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0); 536 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0); 537 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg); 538 539 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0); 540 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0); 541 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); 542 543 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0); 544 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0); 545 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); 546 547 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0); 548 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0); 549 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); 550 551 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0); 552 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0); 553 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); 554 555 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0); 556 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0); 557 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); 558 } 559 } 560 #endif 561 562 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) 563 { 564 struct kv_power_info *pi = kv_get_pi(adev); 565 int ret = 0; 566 567 if (pi->caps_cac) { 568 if (enable) { 569 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); 570 if (ret) 571 pi->cac_enabled = false; 572 else 573 pi->cac_enabled = true; 574 } else if (pi->cac_enabled) { 575 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); 576 pi->cac_enabled = false; 577 } 578 } 579 580 return ret; 581 } 582 583 static int kv_process_firmware_header(struct amdgpu_device *adev) 584 { 585 struct kv_power_info *pi = kv_get_pi(adev); 586 u32 tmp; 587 int ret; 588 589 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + 590 offsetof(SMU7_Firmware_Header, DpmTable), 591 &tmp, pi->sram_end); 592 593 if (ret == 0) 594 pi->dpm_table_start = tmp; 595 596 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + 597 offsetof(SMU7_Firmware_Header, SoftRegisters), 598 &tmp, pi->sram_end); 599 600 if (ret == 0) 601 pi->soft_regs_start = tmp; 602 603 return ret; 604 } 605 606 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) 607 { 608 struct kv_power_info *pi = kv_get_pi(adev); 609 int ret; 610 611 pi->graphics_voltage_change_enable = 1; 612 613 ret = amdgpu_kv_copy_bytes_to_smc(adev, 614 pi->dpm_table_start + 615 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), 616 &pi->graphics_voltage_change_enable, 617 sizeof(u8), pi->sram_end); 618 619 return ret; 620 } 621 622 static int kv_set_dpm_interval(struct amdgpu_device *adev) 623 { 624 struct kv_power_info *pi = kv_get_pi(adev); 625 int ret; 626 627 pi->graphics_interval = 1; 628 629 ret = amdgpu_kv_copy_bytes_to_smc(adev, 630 pi->dpm_table_start + 631 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), 632 &pi->graphics_interval, 633 sizeof(u8), pi->sram_end); 634 635 return ret; 636 } 637 638 static int kv_set_dpm_boot_state(struct amdgpu_device *adev) 639 { 640 struct kv_power_info *pi = kv_get_pi(adev); 641 int ret; 642 643 ret = amdgpu_kv_copy_bytes_to_smc(adev, 644 pi->dpm_table_start + 645 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), 646 &pi->graphics_boot_level, 647 sizeof(u8), pi->sram_end); 648 649 return ret; 650 } 651 652 static void kv_program_vc(struct amdgpu_device *adev) 653 { 654 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100); 655 } 656 657 static void kv_clear_vc(struct amdgpu_device *adev) 658 { 659 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); 660 } 661 662 static int kv_set_divider_value(struct amdgpu_device *adev, 663 u32 index, u32 sclk) 664 { 665 struct kv_power_info *pi = kv_get_pi(adev); 666 struct atom_clock_dividers dividers; 667 int ret; 668 669 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 670 sclk, false, ÷rs); 671 if (ret) 672 return ret; 673 674 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; 675 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); 676 677 return 0; 678 } 679 680 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, 681 u16 voltage) 682 { 683 return 6200 - (voltage * 25); 684 } 685 686 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, 687 u32 vid_2bit) 688 { 689 struct kv_power_info *pi = kv_get_pi(adev); 690 u32 vid_8bit = kv_convert_vid2_to_vid7(adev, 691 &pi->sys_info.vid_mapping_table, 692 vid_2bit); 693 694 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); 695 } 696 697 698 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) 699 { 700 struct kv_power_info *pi = kv_get_pi(adev); 701 702 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; 703 pi->graphics_level[index].MinVddNb = 704 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); 705 706 return 0; 707 } 708 709 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) 710 { 711 struct kv_power_info *pi = kv_get_pi(adev); 712 713 pi->graphics_level[index].AT = cpu_to_be16((u16)at); 714 715 return 0; 716 } 717 718 static void kv_dpm_power_level_enable(struct amdgpu_device *adev, 719 u32 index, bool enable) 720 { 721 struct kv_power_info *pi = kv_get_pi(adev); 722 723 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; 724 } 725 726 static void kv_start_dpm(struct amdgpu_device *adev) 727 { 728 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); 729 730 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK; 731 WREG32_SMC(ixGENERAL_PWRMGT, tmp); 732 733 amdgpu_kv_smc_dpm_enable(adev, true); 734 } 735 736 static void kv_stop_dpm(struct amdgpu_device *adev) 737 { 738 amdgpu_kv_smc_dpm_enable(adev, false); 739 } 740 741 static void kv_start_am(struct amdgpu_device *adev) 742 { 743 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); 744 745 sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | 746 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); 747 sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK; 748 749 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 750 } 751 752 static void kv_reset_am(struct amdgpu_device *adev) 753 { 754 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); 755 756 sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | 757 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); 758 759 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 760 } 761 762 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) 763 { 764 return amdgpu_kv_notify_message_to_smu(adev, freeze ? 765 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); 766 } 767 768 static int kv_force_lowest_valid(struct amdgpu_device *adev) 769 { 770 return kv_force_dpm_lowest(adev); 771 } 772 773 static int kv_unforce_levels(struct amdgpu_device *adev) 774 { 775 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 776 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); 777 else 778 return kv_set_enabled_levels(adev); 779 } 780 781 static int kv_update_sclk_t(struct amdgpu_device *adev) 782 { 783 struct kv_power_info *pi = kv_get_pi(adev); 784 u32 low_sclk_interrupt_t = 0; 785 int ret = 0; 786 787 if (pi->caps_sclk_throttle_low_notification) { 788 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 789 790 ret = amdgpu_kv_copy_bytes_to_smc(adev, 791 pi->dpm_table_start + 792 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), 793 (u8 *)&low_sclk_interrupt_t, 794 sizeof(u32), pi->sram_end); 795 } 796 return ret; 797 } 798 799 static int kv_program_bootup_state(struct amdgpu_device *adev) 800 { 801 struct kv_power_info *pi = kv_get_pi(adev); 802 u32 i; 803 struct amdgpu_clock_voltage_dependency_table *table = 804 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 805 806 if (table && table->count) { 807 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 808 if (table->entries[i].clk == pi->boot_pl.sclk) 809 break; 810 } 811 812 pi->graphics_boot_level = (u8)i; 813 kv_dpm_power_level_enable(adev, i, true); 814 } else { 815 struct sumo_sclk_voltage_mapping_table *table = 816 &pi->sys_info.sclk_voltage_mapping_table; 817 818 if (table->num_max_dpm_entries == 0) 819 return -EINVAL; 820 821 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 822 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) 823 break; 824 } 825 826 pi->graphics_boot_level = (u8)i; 827 kv_dpm_power_level_enable(adev, i, true); 828 } 829 return 0; 830 } 831 832 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) 833 { 834 struct kv_power_info *pi = kv_get_pi(adev); 835 int ret; 836 837 pi->graphics_therm_throttle_enable = 1; 838 839 ret = amdgpu_kv_copy_bytes_to_smc(adev, 840 pi->dpm_table_start + 841 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), 842 &pi->graphics_therm_throttle_enable, 843 sizeof(u8), pi->sram_end); 844 845 return ret; 846 } 847 848 static int kv_upload_dpm_settings(struct amdgpu_device *adev) 849 { 850 struct kv_power_info *pi = kv_get_pi(adev); 851 int ret; 852 853 ret = amdgpu_kv_copy_bytes_to_smc(adev, 854 pi->dpm_table_start + 855 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), 856 (u8 *)&pi->graphics_level, 857 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, 858 pi->sram_end); 859 860 if (ret) 861 return ret; 862 863 ret = amdgpu_kv_copy_bytes_to_smc(adev, 864 pi->dpm_table_start + 865 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), 866 &pi->graphics_dpm_level_count, 867 sizeof(u8), pi->sram_end); 868 869 return ret; 870 } 871 872 static u32 kv_get_clock_difference(u32 a, u32 b) 873 { 874 return (a >= b) ? a - b : b - a; 875 } 876 877 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) 878 { 879 struct kv_power_info *pi = kv_get_pi(adev); 880 u32 value; 881 882 if (pi->caps_enable_dfs_bypass) { 883 if (kv_get_clock_difference(clk, 40000) < 200) 884 value = 3; 885 else if (kv_get_clock_difference(clk, 30000) < 200) 886 value = 2; 887 else if (kv_get_clock_difference(clk, 20000) < 200) 888 value = 7; 889 else if (kv_get_clock_difference(clk, 15000) < 200) 890 value = 6; 891 else if (kv_get_clock_difference(clk, 10000) < 200) 892 value = 8; 893 else 894 value = 0; 895 } else { 896 value = 0; 897 } 898 899 return value; 900 } 901 902 static int kv_populate_uvd_table(struct amdgpu_device *adev) 903 { 904 struct kv_power_info *pi = kv_get_pi(adev); 905 struct amdgpu_uvd_clock_voltage_dependency_table *table = 906 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 907 struct atom_clock_dividers dividers; 908 int ret; 909 u32 i; 910 911 if (table == NULL || table->count == 0) 912 return 0; 913 914 pi->uvd_level_count = 0; 915 for (i = 0; i < table->count; i++) { 916 if (pi->high_voltage_t && 917 (pi->high_voltage_t < table->entries[i].v)) 918 break; 919 920 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); 921 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); 922 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); 923 924 pi->uvd_level[i].VClkBypassCntl = 925 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); 926 pi->uvd_level[i].DClkBypassCntl = 927 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); 928 929 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 930 table->entries[i].vclk, false, ÷rs); 931 if (ret) 932 return ret; 933 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; 934 935 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 936 table->entries[i].dclk, false, ÷rs); 937 if (ret) 938 return ret; 939 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; 940 941 pi->uvd_level_count++; 942 } 943 944 ret = amdgpu_kv_copy_bytes_to_smc(adev, 945 pi->dpm_table_start + 946 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), 947 (u8 *)&pi->uvd_level_count, 948 sizeof(u8), pi->sram_end); 949 if (ret) 950 return ret; 951 952 pi->uvd_interval = 1; 953 954 ret = amdgpu_kv_copy_bytes_to_smc(adev, 955 pi->dpm_table_start + 956 offsetof(SMU7_Fusion_DpmTable, UVDInterval), 957 &pi->uvd_interval, 958 sizeof(u8), pi->sram_end); 959 if (ret) 960 return ret; 961 962 ret = amdgpu_kv_copy_bytes_to_smc(adev, 963 pi->dpm_table_start + 964 offsetof(SMU7_Fusion_DpmTable, UvdLevel), 965 (u8 *)&pi->uvd_level, 966 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, 967 pi->sram_end); 968 969 return ret; 970 971 } 972 973 static int kv_populate_vce_table(struct amdgpu_device *adev) 974 { 975 struct kv_power_info *pi = kv_get_pi(adev); 976 int ret; 977 u32 i; 978 struct amdgpu_vce_clock_voltage_dependency_table *table = 979 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 980 struct atom_clock_dividers dividers; 981 982 if (table == NULL || table->count == 0) 983 return 0; 984 985 pi->vce_level_count = 0; 986 for (i = 0; i < table->count; i++) { 987 if (pi->high_voltage_t && 988 pi->high_voltage_t < table->entries[i].v) 989 break; 990 991 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); 992 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 993 994 pi->vce_level[i].ClkBypassCntl = 995 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); 996 997 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 998 table->entries[i].evclk, false, ÷rs); 999 if (ret) 1000 return ret; 1001 pi->vce_level[i].Divider = (u8)dividers.post_div; 1002 1003 pi->vce_level_count++; 1004 } 1005 1006 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1007 pi->dpm_table_start + 1008 offsetof(SMU7_Fusion_DpmTable, VceLevelCount), 1009 (u8 *)&pi->vce_level_count, 1010 sizeof(u8), 1011 pi->sram_end); 1012 if (ret) 1013 return ret; 1014 1015 pi->vce_interval = 1; 1016 1017 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1018 pi->dpm_table_start + 1019 offsetof(SMU7_Fusion_DpmTable, VCEInterval), 1020 (u8 *)&pi->vce_interval, 1021 sizeof(u8), 1022 pi->sram_end); 1023 if (ret) 1024 return ret; 1025 1026 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1027 pi->dpm_table_start + 1028 offsetof(SMU7_Fusion_DpmTable, VceLevel), 1029 (u8 *)&pi->vce_level, 1030 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, 1031 pi->sram_end); 1032 1033 return ret; 1034 } 1035 1036 static int kv_populate_samu_table(struct amdgpu_device *adev) 1037 { 1038 struct kv_power_info *pi = kv_get_pi(adev); 1039 struct amdgpu_clock_voltage_dependency_table *table = 1040 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1041 struct atom_clock_dividers dividers; 1042 int ret; 1043 u32 i; 1044 1045 if (table == NULL || table->count == 0) 1046 return 0; 1047 1048 pi->samu_level_count = 0; 1049 for (i = 0; i < table->count; i++) { 1050 if (pi->high_voltage_t && 1051 pi->high_voltage_t < table->entries[i].v) 1052 break; 1053 1054 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1055 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1056 1057 pi->samu_level[i].ClkBypassCntl = 1058 (u8)kv_get_clk_bypass(adev, table->entries[i].clk); 1059 1060 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 1061 table->entries[i].clk, false, ÷rs); 1062 if (ret) 1063 return ret; 1064 pi->samu_level[i].Divider = (u8)dividers.post_div; 1065 1066 pi->samu_level_count++; 1067 } 1068 1069 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1070 pi->dpm_table_start + 1071 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), 1072 (u8 *)&pi->samu_level_count, 1073 sizeof(u8), 1074 pi->sram_end); 1075 if (ret) 1076 return ret; 1077 1078 pi->samu_interval = 1; 1079 1080 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1081 pi->dpm_table_start + 1082 offsetof(SMU7_Fusion_DpmTable, SAMUInterval), 1083 (u8 *)&pi->samu_interval, 1084 sizeof(u8), 1085 pi->sram_end); 1086 if (ret) 1087 return ret; 1088 1089 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1090 pi->dpm_table_start + 1091 offsetof(SMU7_Fusion_DpmTable, SamuLevel), 1092 (u8 *)&pi->samu_level, 1093 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, 1094 pi->sram_end); 1095 if (ret) 1096 return ret; 1097 1098 return ret; 1099 } 1100 1101 1102 static int kv_populate_acp_table(struct amdgpu_device *adev) 1103 { 1104 struct kv_power_info *pi = kv_get_pi(adev); 1105 struct amdgpu_clock_voltage_dependency_table *table = 1106 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1107 struct atom_clock_dividers dividers; 1108 int ret; 1109 u32 i; 1110 1111 if (table == NULL || table->count == 0) 1112 return 0; 1113 1114 pi->acp_level_count = 0; 1115 for (i = 0; i < table->count; i++) { 1116 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1117 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1118 1119 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 1120 table->entries[i].clk, false, ÷rs); 1121 if (ret) 1122 return ret; 1123 pi->acp_level[i].Divider = (u8)dividers.post_div; 1124 1125 pi->acp_level_count++; 1126 } 1127 1128 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1129 pi->dpm_table_start + 1130 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), 1131 (u8 *)&pi->acp_level_count, 1132 sizeof(u8), 1133 pi->sram_end); 1134 if (ret) 1135 return ret; 1136 1137 pi->acp_interval = 1; 1138 1139 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1140 pi->dpm_table_start + 1141 offsetof(SMU7_Fusion_DpmTable, ACPInterval), 1142 (u8 *)&pi->acp_interval, 1143 sizeof(u8), 1144 pi->sram_end); 1145 if (ret) 1146 return ret; 1147 1148 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1149 pi->dpm_table_start + 1150 offsetof(SMU7_Fusion_DpmTable, AcpLevel), 1151 (u8 *)&pi->acp_level, 1152 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, 1153 pi->sram_end); 1154 if (ret) 1155 return ret; 1156 1157 return ret; 1158 } 1159 1160 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) 1161 { 1162 struct kv_power_info *pi = kv_get_pi(adev); 1163 u32 i; 1164 struct amdgpu_clock_voltage_dependency_table *table = 1165 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1166 1167 if (table && table->count) { 1168 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1169 if (pi->caps_enable_dfs_bypass) { 1170 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) 1171 pi->graphics_level[i].ClkBypassCntl = 3; 1172 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) 1173 pi->graphics_level[i].ClkBypassCntl = 2; 1174 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) 1175 pi->graphics_level[i].ClkBypassCntl = 7; 1176 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) 1177 pi->graphics_level[i].ClkBypassCntl = 6; 1178 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) 1179 pi->graphics_level[i].ClkBypassCntl = 8; 1180 else 1181 pi->graphics_level[i].ClkBypassCntl = 0; 1182 } else { 1183 pi->graphics_level[i].ClkBypassCntl = 0; 1184 } 1185 } 1186 } else { 1187 struct sumo_sclk_voltage_mapping_table *table = 1188 &pi->sys_info.sclk_voltage_mapping_table; 1189 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1190 if (pi->caps_enable_dfs_bypass) { 1191 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) 1192 pi->graphics_level[i].ClkBypassCntl = 3; 1193 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) 1194 pi->graphics_level[i].ClkBypassCntl = 2; 1195 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) 1196 pi->graphics_level[i].ClkBypassCntl = 7; 1197 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) 1198 pi->graphics_level[i].ClkBypassCntl = 6; 1199 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) 1200 pi->graphics_level[i].ClkBypassCntl = 8; 1201 else 1202 pi->graphics_level[i].ClkBypassCntl = 0; 1203 } else { 1204 pi->graphics_level[i].ClkBypassCntl = 0; 1205 } 1206 } 1207 } 1208 } 1209 1210 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) 1211 { 1212 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1213 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); 1214 } 1215 1216 static void kv_reset_acp_boot_level(struct amdgpu_device *adev) 1217 { 1218 struct kv_power_info *pi = kv_get_pi(adev); 1219 1220 pi->acp_boot_level = 0xff; 1221 } 1222 1223 static void kv_update_current_ps(struct amdgpu_device *adev, 1224 struct amdgpu_ps *rps) 1225 { 1226 struct kv_ps *new_ps = kv_get_ps(rps); 1227 struct kv_power_info *pi = kv_get_pi(adev); 1228 1229 pi->current_rps = *rps; 1230 pi->current_ps = *new_ps; 1231 pi->current_rps.ps_priv = &pi->current_ps; 1232 adev->pm.dpm.current_ps = &pi->current_rps; 1233 } 1234 1235 static void kv_update_requested_ps(struct amdgpu_device *adev, 1236 struct amdgpu_ps *rps) 1237 { 1238 struct kv_ps *new_ps = kv_get_ps(rps); 1239 struct kv_power_info *pi = kv_get_pi(adev); 1240 1241 pi->requested_rps = *rps; 1242 pi->requested_ps = *new_ps; 1243 pi->requested_rps.ps_priv = &pi->requested_ps; 1244 adev->pm.dpm.requested_ps = &pi->requested_rps; 1245 } 1246 1247 static void kv_dpm_enable_bapm(void *handle, bool enable) 1248 { 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 struct kv_power_info *pi = kv_get_pi(adev); 1251 int ret; 1252 1253 if (pi->bapm_enable) { 1254 ret = amdgpu_kv_smc_bapm_enable(adev, enable); 1255 if (ret) 1256 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1257 } 1258 } 1259 1260 static bool kv_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor) 1261 { 1262 switch (sensor) { 1263 case THERMAL_TYPE_KV: 1264 return true; 1265 case THERMAL_TYPE_NONE: 1266 case THERMAL_TYPE_EXTERNAL: 1267 case THERMAL_TYPE_EXTERNAL_GPIO: 1268 default: 1269 return false; 1270 } 1271 } 1272 1273 static int kv_dpm_enable(struct amdgpu_device *adev) 1274 { 1275 struct kv_power_info *pi = kv_get_pi(adev); 1276 int ret; 1277 1278 ret = kv_process_firmware_header(adev); 1279 if (ret) { 1280 DRM_ERROR("kv_process_firmware_header failed\n"); 1281 return ret; 1282 } 1283 kv_init_fps_limits(adev); 1284 kv_init_graphics_levels(adev); 1285 ret = kv_program_bootup_state(adev); 1286 if (ret) { 1287 DRM_ERROR("kv_program_bootup_state failed\n"); 1288 return ret; 1289 } 1290 kv_calculate_dfs_bypass_settings(adev); 1291 ret = kv_upload_dpm_settings(adev); 1292 if (ret) { 1293 DRM_ERROR("kv_upload_dpm_settings failed\n"); 1294 return ret; 1295 } 1296 ret = kv_populate_uvd_table(adev); 1297 if (ret) { 1298 DRM_ERROR("kv_populate_uvd_table failed\n"); 1299 return ret; 1300 } 1301 ret = kv_populate_vce_table(adev); 1302 if (ret) { 1303 DRM_ERROR("kv_populate_vce_table failed\n"); 1304 return ret; 1305 } 1306 ret = kv_populate_samu_table(adev); 1307 if (ret) { 1308 DRM_ERROR("kv_populate_samu_table failed\n"); 1309 return ret; 1310 } 1311 ret = kv_populate_acp_table(adev); 1312 if (ret) { 1313 DRM_ERROR("kv_populate_acp_table failed\n"); 1314 return ret; 1315 } 1316 kv_program_vc(adev); 1317 #if 0 1318 kv_initialize_hardware_cac_manager(adev); 1319 #endif 1320 kv_start_am(adev); 1321 if (pi->enable_auto_thermal_throttling) { 1322 ret = kv_enable_auto_thermal_throttling(adev); 1323 if (ret) { 1324 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); 1325 return ret; 1326 } 1327 } 1328 ret = kv_enable_dpm_voltage_scaling(adev); 1329 if (ret) { 1330 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); 1331 return ret; 1332 } 1333 ret = kv_set_dpm_interval(adev); 1334 if (ret) { 1335 DRM_ERROR("kv_set_dpm_interval failed\n"); 1336 return ret; 1337 } 1338 ret = kv_set_dpm_boot_state(adev); 1339 if (ret) { 1340 DRM_ERROR("kv_set_dpm_boot_state failed\n"); 1341 return ret; 1342 } 1343 ret = kv_enable_ulv(adev, true); 1344 if (ret) { 1345 DRM_ERROR("kv_enable_ulv failed\n"); 1346 return ret; 1347 } 1348 kv_start_dpm(adev); 1349 ret = kv_enable_didt(adev, true); 1350 if (ret) { 1351 DRM_ERROR("kv_enable_didt failed\n"); 1352 return ret; 1353 } 1354 ret = kv_enable_smc_cac(adev, true); 1355 if (ret) { 1356 DRM_ERROR("kv_enable_smc_cac failed\n"); 1357 return ret; 1358 } 1359 1360 kv_reset_acp_boot_level(adev); 1361 1362 ret = amdgpu_kv_smc_bapm_enable(adev, false); 1363 if (ret) { 1364 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1365 return ret; 1366 } 1367 1368 if (adev->irq.installed && 1369 kv_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { 1370 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); 1371 if (ret) { 1372 DRM_ERROR("kv_set_thermal_temperature_range failed\n"); 1373 return ret; 1374 } 1375 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, 1376 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); 1377 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, 1378 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); 1379 } 1380 1381 return ret; 1382 } 1383 1384 static void kv_dpm_disable(struct amdgpu_device *adev) 1385 { 1386 struct kv_power_info *pi = kv_get_pi(adev); 1387 1388 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, 1389 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); 1390 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, 1391 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); 1392 1393 amdgpu_kv_smc_bapm_enable(adev, false); 1394 1395 if (adev->asic_type == CHIP_MULLINS) 1396 kv_enable_nb_dpm(adev, false); 1397 1398 /* powerup blocks */ 1399 kv_dpm_powergate_acp(adev, false); 1400 kv_dpm_powergate_samu(adev, false); 1401 if (pi->caps_vce_pg) /* power on the VCE block */ 1402 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1403 if (pi->caps_uvd_pg) /* power on the UVD block */ 1404 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1405 1406 kv_enable_smc_cac(adev, false); 1407 kv_enable_didt(adev, false); 1408 kv_clear_vc(adev); 1409 kv_stop_dpm(adev); 1410 kv_enable_ulv(adev, false); 1411 kv_reset_am(adev); 1412 1413 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); 1414 } 1415 1416 #if 0 1417 static int kv_write_smc_soft_register(struct amdgpu_device *adev, 1418 u16 reg_offset, u32 value) 1419 { 1420 struct kv_power_info *pi = kv_get_pi(adev); 1421 1422 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, 1423 (u8 *)&value, sizeof(u16), pi->sram_end); 1424 } 1425 1426 static int kv_read_smc_soft_register(struct amdgpu_device *adev, 1427 u16 reg_offset, u32 *value) 1428 { 1429 struct kv_power_info *pi = kv_get_pi(adev); 1430 1431 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset, 1432 value, pi->sram_end); 1433 } 1434 #endif 1435 1436 static void kv_init_sclk_t(struct amdgpu_device *adev) 1437 { 1438 struct kv_power_info *pi = kv_get_pi(adev); 1439 1440 pi->low_sclk_interrupt_t = 0; 1441 } 1442 1443 static int kv_init_fps_limits(struct amdgpu_device *adev) 1444 { 1445 struct kv_power_info *pi = kv_get_pi(adev); 1446 int ret = 0; 1447 1448 if (pi->caps_fps) { 1449 u16 tmp; 1450 1451 tmp = 45; 1452 pi->fps_high_t = cpu_to_be16(tmp); 1453 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1454 pi->dpm_table_start + 1455 offsetof(SMU7_Fusion_DpmTable, FpsHighT), 1456 (u8 *)&pi->fps_high_t, 1457 sizeof(u16), pi->sram_end); 1458 1459 tmp = 30; 1460 pi->fps_low_t = cpu_to_be16(tmp); 1461 1462 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1463 pi->dpm_table_start + 1464 offsetof(SMU7_Fusion_DpmTable, FpsLowT), 1465 (u8 *)&pi->fps_low_t, 1466 sizeof(u16), pi->sram_end); 1467 1468 } 1469 return ret; 1470 } 1471 1472 static void kv_init_powergate_state(struct amdgpu_device *adev) 1473 { 1474 struct kv_power_info *pi = kv_get_pi(adev); 1475 1476 pi->uvd_power_gated = false; 1477 pi->vce_power_gated = false; 1478 pi->samu_power_gated = false; 1479 pi->acp_power_gated = false; 1480 1481 } 1482 1483 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) 1484 { 1485 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1486 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); 1487 } 1488 1489 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) 1490 { 1491 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1492 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); 1493 } 1494 1495 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) 1496 { 1497 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1498 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); 1499 } 1500 1501 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) 1502 { 1503 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1504 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); 1505 } 1506 1507 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) 1508 { 1509 struct kv_power_info *pi = kv_get_pi(adev); 1510 struct amdgpu_uvd_clock_voltage_dependency_table *table = 1511 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1512 int ret; 1513 u32 mask; 1514 1515 if (!gate) { 1516 if (table->count) 1517 pi->uvd_boot_level = table->count - 1; 1518 else 1519 pi->uvd_boot_level = 0; 1520 1521 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { 1522 mask = 1 << pi->uvd_boot_level; 1523 } else { 1524 mask = 0x1f; 1525 } 1526 1527 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1528 pi->dpm_table_start + 1529 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), 1530 (uint8_t *)&pi->uvd_boot_level, 1531 sizeof(u8), pi->sram_end); 1532 if (ret) 1533 return ret; 1534 1535 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1536 PPSMC_MSG_UVDDPM_SetEnabledMask, 1537 mask); 1538 } 1539 1540 return kv_enable_uvd_dpm(adev, !gate); 1541 } 1542 1543 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) 1544 { 1545 u8 i; 1546 struct amdgpu_vce_clock_voltage_dependency_table *table = 1547 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1548 1549 for (i = 0; i < table->count; i++) { 1550 if (table->entries[i].evclk >= evclk) 1551 break; 1552 } 1553 1554 return i; 1555 } 1556 1557 static int kv_update_vce_dpm(struct amdgpu_device *adev, 1558 struct amdgpu_ps *amdgpu_new_state, 1559 struct amdgpu_ps *amdgpu_current_state) 1560 { 1561 struct kv_power_info *pi = kv_get_pi(adev); 1562 struct amdgpu_vce_clock_voltage_dependency_table *table = 1563 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1564 int ret; 1565 1566 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { 1567 if (pi->caps_stable_p_state) 1568 pi->vce_boot_level = table->count - 1; 1569 else 1570 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); 1571 1572 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1573 pi->dpm_table_start + 1574 offsetof(SMU7_Fusion_DpmTable, VceBootLevel), 1575 (u8 *)&pi->vce_boot_level, 1576 sizeof(u8), 1577 pi->sram_end); 1578 if (ret) 1579 return ret; 1580 1581 if (pi->caps_stable_p_state) 1582 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1583 PPSMC_MSG_VCEDPM_SetEnabledMask, 1584 (1 << pi->vce_boot_level)); 1585 kv_enable_vce_dpm(adev, true); 1586 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { 1587 kv_enable_vce_dpm(adev, false); 1588 } 1589 1590 return 0; 1591 } 1592 1593 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) 1594 { 1595 struct kv_power_info *pi = kv_get_pi(adev); 1596 struct amdgpu_clock_voltage_dependency_table *table = 1597 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1598 int ret; 1599 1600 if (!gate) { 1601 if (pi->caps_stable_p_state) 1602 pi->samu_boot_level = table->count - 1; 1603 else 1604 pi->samu_boot_level = 0; 1605 1606 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1607 pi->dpm_table_start + 1608 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), 1609 (u8 *)&pi->samu_boot_level, 1610 sizeof(u8), 1611 pi->sram_end); 1612 if (ret) 1613 return ret; 1614 1615 if (pi->caps_stable_p_state) 1616 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1617 PPSMC_MSG_SAMUDPM_SetEnabledMask, 1618 (1 << pi->samu_boot_level)); 1619 } 1620 1621 return kv_enable_samu_dpm(adev, !gate); 1622 } 1623 1624 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) 1625 { 1626 u8 i; 1627 struct amdgpu_clock_voltage_dependency_table *table = 1628 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1629 1630 for (i = 0; i < table->count; i++) { 1631 if (table->entries[i].clk >= 0) /* XXX */ 1632 break; 1633 } 1634 1635 if (i >= table->count) 1636 i = table->count - 1; 1637 1638 return i; 1639 } 1640 1641 static void kv_update_acp_boot_level(struct amdgpu_device *adev) 1642 { 1643 struct kv_power_info *pi = kv_get_pi(adev); 1644 u8 acp_boot_level; 1645 1646 if (!pi->caps_stable_p_state) { 1647 acp_boot_level = kv_get_acp_boot_level(adev); 1648 if (acp_boot_level != pi->acp_boot_level) { 1649 pi->acp_boot_level = acp_boot_level; 1650 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1651 PPSMC_MSG_ACPDPM_SetEnabledMask, 1652 (1 << pi->acp_boot_level)); 1653 } 1654 } 1655 } 1656 1657 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) 1658 { 1659 struct kv_power_info *pi = kv_get_pi(adev); 1660 struct amdgpu_clock_voltage_dependency_table *table = 1661 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1662 int ret; 1663 1664 if (!gate) { 1665 if (pi->caps_stable_p_state) 1666 pi->acp_boot_level = table->count - 1; 1667 else 1668 pi->acp_boot_level = kv_get_acp_boot_level(adev); 1669 1670 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1671 pi->dpm_table_start + 1672 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), 1673 (u8 *)&pi->acp_boot_level, 1674 sizeof(u8), 1675 pi->sram_end); 1676 if (ret) 1677 return ret; 1678 1679 if (pi->caps_stable_p_state) 1680 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1681 PPSMC_MSG_ACPDPM_SetEnabledMask, 1682 (1 << pi->acp_boot_level)); 1683 } 1684 1685 return kv_enable_acp_dpm(adev, !gate); 1686 } 1687 1688 static void kv_dpm_powergate_uvd(void *handle, bool gate) 1689 { 1690 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1691 struct kv_power_info *pi = kv_get_pi(adev); 1692 1693 pi->uvd_power_gated = gate; 1694 1695 if (gate) { 1696 /* stop the UVD block */ 1697 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1698 AMD_PG_STATE_GATE); 1699 kv_update_uvd_dpm(adev, gate); 1700 if (pi->caps_uvd_pg) 1701 /* power off the UVD block */ 1702 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); 1703 } else { 1704 if (pi->caps_uvd_pg) 1705 /* power on the UVD block */ 1706 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1707 /* re-init the UVD block */ 1708 kv_update_uvd_dpm(adev, gate); 1709 1710 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1711 AMD_PG_STATE_UNGATE); 1712 } 1713 } 1714 1715 static void kv_dpm_powergate_vce(void *handle, bool gate) 1716 { 1717 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1718 struct kv_power_info *pi = kv_get_pi(adev); 1719 1720 pi->vce_power_gated = gate; 1721 1722 if (gate) { 1723 /* stop the VCE block */ 1724 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1725 AMD_PG_STATE_GATE); 1726 kv_enable_vce_dpm(adev, false); 1727 if (pi->caps_vce_pg) /* power off the VCE block */ 1728 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); 1729 } else { 1730 if (pi->caps_vce_pg) /* power on the VCE block */ 1731 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1732 kv_enable_vce_dpm(adev, true); 1733 /* re-init the VCE block */ 1734 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1735 AMD_PG_STATE_UNGATE); 1736 } 1737 } 1738 1739 1740 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) 1741 { 1742 struct kv_power_info *pi = kv_get_pi(adev); 1743 1744 if (pi->samu_power_gated == gate) 1745 return; 1746 1747 pi->samu_power_gated = gate; 1748 1749 if (gate) { 1750 kv_update_samu_dpm(adev, true); 1751 if (pi->caps_samu_pg) 1752 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); 1753 } else { 1754 if (pi->caps_samu_pg) 1755 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); 1756 kv_update_samu_dpm(adev, false); 1757 } 1758 } 1759 1760 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) 1761 { 1762 struct kv_power_info *pi = kv_get_pi(adev); 1763 1764 if (pi->acp_power_gated == gate) 1765 return; 1766 1767 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 1768 return; 1769 1770 pi->acp_power_gated = gate; 1771 1772 if (gate) { 1773 kv_update_acp_dpm(adev, true); 1774 if (pi->caps_acp_pg) 1775 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); 1776 } else { 1777 if (pi->caps_acp_pg) 1778 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); 1779 kv_update_acp_dpm(adev, false); 1780 } 1781 } 1782 1783 static void kv_set_valid_clock_range(struct amdgpu_device *adev, 1784 struct amdgpu_ps *new_rps) 1785 { 1786 struct kv_ps *new_ps = kv_get_ps(new_rps); 1787 struct kv_power_info *pi = kv_get_pi(adev); 1788 u32 i; 1789 struct amdgpu_clock_voltage_dependency_table *table = 1790 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1791 1792 if (table && table->count) { 1793 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1794 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || 1795 (i == (pi->graphics_dpm_level_count - 1))) { 1796 pi->lowest_valid = i; 1797 break; 1798 } 1799 } 1800 1801 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1802 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) 1803 break; 1804 } 1805 pi->highest_valid = i; 1806 1807 if (pi->lowest_valid > pi->highest_valid) { 1808 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > 1809 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) 1810 pi->highest_valid = pi->lowest_valid; 1811 else 1812 pi->lowest_valid = pi->highest_valid; 1813 } 1814 } else { 1815 struct sumo_sclk_voltage_mapping_table *table = 1816 &pi->sys_info.sclk_voltage_mapping_table; 1817 1818 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { 1819 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || 1820 i == (int)(pi->graphics_dpm_level_count - 1)) { 1821 pi->lowest_valid = i; 1822 break; 1823 } 1824 } 1825 1826 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1827 if (table->entries[i].sclk_frequency <= 1828 new_ps->levels[new_ps->num_levels - 1].sclk) 1829 break; 1830 } 1831 pi->highest_valid = i; 1832 1833 if (pi->lowest_valid > pi->highest_valid) { 1834 if ((new_ps->levels[0].sclk - 1835 table->entries[pi->highest_valid].sclk_frequency) > 1836 (table->entries[pi->lowest_valid].sclk_frequency - 1837 new_ps->levels[new_ps->num_levels -1].sclk)) 1838 pi->highest_valid = pi->lowest_valid; 1839 else 1840 pi->lowest_valid = pi->highest_valid; 1841 } 1842 } 1843 } 1844 1845 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, 1846 struct amdgpu_ps *new_rps) 1847 { 1848 struct kv_ps *new_ps = kv_get_ps(new_rps); 1849 struct kv_power_info *pi = kv_get_pi(adev); 1850 int ret = 0; 1851 u8 clk_bypass_cntl; 1852 1853 if (pi->caps_enable_dfs_bypass) { 1854 clk_bypass_cntl = new_ps->need_dfs_bypass ? 1855 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; 1856 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1857 (pi->dpm_table_start + 1858 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + 1859 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + 1860 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), 1861 &clk_bypass_cntl, 1862 sizeof(u8), pi->sram_end); 1863 } 1864 1865 return ret; 1866 } 1867 1868 static int kv_enable_nb_dpm(struct amdgpu_device *adev, 1869 bool enable) 1870 { 1871 struct kv_power_info *pi = kv_get_pi(adev); 1872 int ret = 0; 1873 1874 if (enable) { 1875 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { 1876 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); 1877 if (ret == 0) 1878 pi->nb_dpm_enabled = true; 1879 } 1880 } else { 1881 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { 1882 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); 1883 if (ret == 0) 1884 pi->nb_dpm_enabled = false; 1885 } 1886 } 1887 1888 return ret; 1889 } 1890 1891 static int kv_dpm_force_performance_level(void *handle, 1892 enum amd_dpm_forced_level level) 1893 { 1894 int ret; 1895 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1896 1897 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 1898 ret = kv_force_dpm_highest(adev); 1899 if (ret) 1900 return ret; 1901 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 1902 ret = kv_force_dpm_lowest(adev); 1903 if (ret) 1904 return ret; 1905 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 1906 ret = kv_unforce_levels(adev); 1907 if (ret) 1908 return ret; 1909 } 1910 1911 adev->pm.dpm.forced_level = level; 1912 1913 return 0; 1914 } 1915 1916 static int kv_dpm_pre_set_power_state(void *handle) 1917 { 1918 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1919 struct kv_power_info *pi = kv_get_pi(adev); 1920 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 1921 struct amdgpu_ps *new_ps = &requested_ps; 1922 1923 kv_update_requested_ps(adev, new_ps); 1924 1925 kv_apply_state_adjust_rules(adev, 1926 &pi->requested_rps, 1927 &pi->current_rps); 1928 1929 return 0; 1930 } 1931 1932 static int kv_dpm_set_power_state(void *handle) 1933 { 1934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1935 struct kv_power_info *pi = kv_get_pi(adev); 1936 struct amdgpu_ps *new_ps = &pi->requested_rps; 1937 struct amdgpu_ps *old_ps = &pi->current_rps; 1938 int ret; 1939 1940 if (pi->bapm_enable) { 1941 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power); 1942 if (ret) { 1943 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1944 return ret; 1945 } 1946 } 1947 1948 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 1949 if (pi->enable_dpm) { 1950 kv_set_valid_clock_range(adev, new_ps); 1951 kv_update_dfs_bypass_settings(adev, new_ps); 1952 ret = kv_calculate_ds_divider(adev); 1953 if (ret) { 1954 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1955 return ret; 1956 } 1957 kv_calculate_nbps_level_settings(adev); 1958 kv_calculate_dpm_settings(adev); 1959 kv_force_lowest_valid(adev); 1960 kv_enable_new_levels(adev); 1961 kv_upload_dpm_settings(adev); 1962 kv_program_nbps_index_settings(adev, new_ps); 1963 kv_unforce_levels(adev); 1964 kv_set_enabled_levels(adev); 1965 kv_force_lowest_valid(adev); 1966 kv_unforce_levels(adev); 1967 1968 ret = kv_update_vce_dpm(adev, new_ps, old_ps); 1969 if (ret) { 1970 DRM_ERROR("kv_update_vce_dpm failed\n"); 1971 return ret; 1972 } 1973 kv_update_sclk_t(adev); 1974 if (adev->asic_type == CHIP_MULLINS) 1975 kv_enable_nb_dpm(adev, true); 1976 } 1977 } else { 1978 if (pi->enable_dpm) { 1979 kv_set_valid_clock_range(adev, new_ps); 1980 kv_update_dfs_bypass_settings(adev, new_ps); 1981 ret = kv_calculate_ds_divider(adev); 1982 if (ret) { 1983 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1984 return ret; 1985 } 1986 kv_calculate_nbps_level_settings(adev); 1987 kv_calculate_dpm_settings(adev); 1988 kv_freeze_sclk_dpm(adev, true); 1989 kv_upload_dpm_settings(adev); 1990 kv_program_nbps_index_settings(adev, new_ps); 1991 kv_freeze_sclk_dpm(adev, false); 1992 kv_set_enabled_levels(adev); 1993 ret = kv_update_vce_dpm(adev, new_ps, old_ps); 1994 if (ret) { 1995 DRM_ERROR("kv_update_vce_dpm failed\n"); 1996 return ret; 1997 } 1998 kv_update_acp_boot_level(adev); 1999 kv_update_sclk_t(adev); 2000 kv_enable_nb_dpm(adev, true); 2001 } 2002 } 2003 2004 return 0; 2005 } 2006 2007 static void kv_dpm_post_set_power_state(void *handle) 2008 { 2009 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2010 struct kv_power_info *pi = kv_get_pi(adev); 2011 struct amdgpu_ps *new_ps = &pi->requested_rps; 2012 2013 kv_update_current_ps(adev, new_ps); 2014 } 2015 2016 static void kv_dpm_setup_asic(struct amdgpu_device *adev) 2017 { 2018 sumo_take_smu_control(adev, true); 2019 kv_init_powergate_state(adev); 2020 kv_init_sclk_t(adev); 2021 } 2022 2023 #if 0 2024 static void kv_dpm_reset_asic(struct amdgpu_device *adev) 2025 { 2026 struct kv_power_info *pi = kv_get_pi(adev); 2027 2028 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 2029 kv_force_lowest_valid(adev); 2030 kv_init_graphics_levels(adev); 2031 kv_program_bootup_state(adev); 2032 kv_upload_dpm_settings(adev); 2033 kv_force_lowest_valid(adev); 2034 kv_unforce_levels(adev); 2035 } else { 2036 kv_init_graphics_levels(adev); 2037 kv_program_bootup_state(adev); 2038 kv_freeze_sclk_dpm(adev, true); 2039 kv_upload_dpm_settings(adev); 2040 kv_freeze_sclk_dpm(adev, false); 2041 kv_set_enabled_level(adev, pi->graphics_boot_level); 2042 } 2043 } 2044 #endif 2045 2046 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, 2047 struct amdgpu_clock_and_voltage_limits *table) 2048 { 2049 struct kv_power_info *pi = kv_get_pi(adev); 2050 2051 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { 2052 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; 2053 table->sclk = 2054 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; 2055 table->vddc = 2056 kv_convert_2bit_index_to_voltage(adev, 2057 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); 2058 } 2059 2060 table->mclk = pi->sys_info.nbp_memory_clock[0]; 2061 } 2062 2063 static void kv_patch_voltage_values(struct amdgpu_device *adev) 2064 { 2065 int i; 2066 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table = 2067 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 2068 struct amdgpu_vce_clock_voltage_dependency_table *vce_table = 2069 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2070 struct amdgpu_clock_voltage_dependency_table *samu_table = 2071 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 2072 struct amdgpu_clock_voltage_dependency_table *acp_table = 2073 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 2074 2075 if (uvd_table->count) { 2076 for (i = 0; i < uvd_table->count; i++) 2077 uvd_table->entries[i].v = 2078 kv_convert_8bit_index_to_voltage(adev, 2079 uvd_table->entries[i].v); 2080 } 2081 2082 if (vce_table->count) { 2083 for (i = 0; i < vce_table->count; i++) 2084 vce_table->entries[i].v = 2085 kv_convert_8bit_index_to_voltage(adev, 2086 vce_table->entries[i].v); 2087 } 2088 2089 if (samu_table->count) { 2090 for (i = 0; i < samu_table->count; i++) 2091 samu_table->entries[i].v = 2092 kv_convert_8bit_index_to_voltage(adev, 2093 samu_table->entries[i].v); 2094 } 2095 2096 if (acp_table->count) { 2097 for (i = 0; i < acp_table->count; i++) 2098 acp_table->entries[i].v = 2099 kv_convert_8bit_index_to_voltage(adev, 2100 acp_table->entries[i].v); 2101 } 2102 2103 } 2104 2105 static void kv_construct_boot_state(struct amdgpu_device *adev) 2106 { 2107 struct kv_power_info *pi = kv_get_pi(adev); 2108 2109 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; 2110 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; 2111 pi->boot_pl.ds_divider_index = 0; 2112 pi->boot_pl.ss_divider_index = 0; 2113 pi->boot_pl.allow_gnb_slow = 1; 2114 pi->boot_pl.force_nbp_state = 0; 2115 pi->boot_pl.display_wm = 0; 2116 pi->boot_pl.vce_wm = 0; 2117 } 2118 2119 static int kv_force_dpm_highest(struct amdgpu_device *adev) 2120 { 2121 int ret; 2122 u32 enable_mask, i; 2123 2124 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); 2125 if (ret) 2126 return ret; 2127 2128 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) { 2129 if (enable_mask & (1 << i)) 2130 break; 2131 } 2132 2133 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 2134 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); 2135 else 2136 return kv_set_enabled_level(adev, i); 2137 } 2138 2139 static int kv_force_dpm_lowest(struct amdgpu_device *adev) 2140 { 2141 int ret; 2142 u32 enable_mask, i; 2143 2144 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); 2145 if (ret) 2146 return ret; 2147 2148 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2149 if (enable_mask & (1 << i)) 2150 break; 2151 } 2152 2153 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 2154 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); 2155 else 2156 return kv_set_enabled_level(adev, i); 2157 } 2158 2159 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, 2160 u32 sclk, u32 min_sclk_in_sr) 2161 { 2162 struct kv_power_info *pi = kv_get_pi(adev); 2163 u32 i; 2164 u32 temp; 2165 u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK); 2166 2167 if (sclk < min) 2168 return 0; 2169 2170 if (!pi->caps_sclk_ds) 2171 return 0; 2172 2173 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { 2174 temp = sclk >> i; 2175 if (temp >= min) 2176 break; 2177 } 2178 2179 return (u8)i; 2180 } 2181 2182 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) 2183 { 2184 struct kv_power_info *pi = kv_get_pi(adev); 2185 struct amdgpu_clock_voltage_dependency_table *table = 2186 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2187 int i; 2188 2189 if (table && table->count) { 2190 for (i = table->count - 1; i >= 0; i--) { 2191 if (pi->high_voltage_t && 2192 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= 2193 pi->high_voltage_t)) { 2194 *limit = i; 2195 return 0; 2196 } 2197 } 2198 } else { 2199 struct sumo_sclk_voltage_mapping_table *table = 2200 &pi->sys_info.sclk_voltage_mapping_table; 2201 2202 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { 2203 if (pi->high_voltage_t && 2204 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= 2205 pi->high_voltage_t)) { 2206 *limit = i; 2207 return 0; 2208 } 2209 } 2210 } 2211 2212 *limit = 0; 2213 return 0; 2214 } 2215 2216 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, 2217 struct amdgpu_ps *new_rps, 2218 struct amdgpu_ps *old_rps) 2219 { 2220 struct kv_ps *ps = kv_get_ps(new_rps); 2221 struct kv_power_info *pi = kv_get_pi(adev); 2222 u32 min_sclk = 10000; /* ??? */ 2223 u32 sclk, mclk = 0; 2224 int i, limit; 2225 bool force_high; 2226 struct amdgpu_clock_voltage_dependency_table *table = 2227 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2228 u32 stable_p_state_sclk = 0; 2229 struct amdgpu_clock_and_voltage_limits *max_limits = 2230 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2231 2232 if (new_rps->vce_active) { 2233 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 2234 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 2235 } else { 2236 new_rps->evclk = 0; 2237 new_rps->ecclk = 0; 2238 } 2239 2240 mclk = max_limits->mclk; 2241 sclk = min_sclk; 2242 2243 if (pi->caps_stable_p_state) { 2244 stable_p_state_sclk = (max_limits->sclk * 75) / 100; 2245 2246 for (i = table->count - 1; i >= 0; i--) { 2247 if (stable_p_state_sclk >= table->entries[i].clk) { 2248 stable_p_state_sclk = table->entries[i].clk; 2249 break; 2250 } 2251 } 2252 2253 if (i > 0) 2254 stable_p_state_sclk = table->entries[0].clk; 2255 2256 sclk = stable_p_state_sclk; 2257 } 2258 2259 if (new_rps->vce_active) { 2260 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 2261 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 2262 } 2263 2264 ps->need_dfs_bypass = true; 2265 2266 for (i = 0; i < ps->num_levels; i++) { 2267 if (ps->levels[i].sclk < sclk) 2268 ps->levels[i].sclk = sclk; 2269 } 2270 2271 if (table && table->count) { 2272 for (i = 0; i < ps->num_levels; i++) { 2273 if (pi->high_voltage_t && 2274 (pi->high_voltage_t < 2275 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { 2276 kv_get_high_voltage_limit(adev, &limit); 2277 ps->levels[i].sclk = table->entries[limit].clk; 2278 } 2279 } 2280 } else { 2281 struct sumo_sclk_voltage_mapping_table *table = 2282 &pi->sys_info.sclk_voltage_mapping_table; 2283 2284 for (i = 0; i < ps->num_levels; i++) { 2285 if (pi->high_voltage_t && 2286 (pi->high_voltage_t < 2287 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { 2288 kv_get_high_voltage_limit(adev, &limit); 2289 ps->levels[i].sclk = table->entries[limit].sclk_frequency; 2290 } 2291 } 2292 } 2293 2294 if (pi->caps_stable_p_state) { 2295 for (i = 0; i < ps->num_levels; i++) { 2296 ps->levels[i].sclk = stable_p_state_sclk; 2297 } 2298 } 2299 2300 pi->video_start = new_rps->dclk || new_rps->vclk || 2301 new_rps->evclk || new_rps->ecclk; 2302 2303 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2304 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 2305 pi->battery_state = true; 2306 else 2307 pi->battery_state = false; 2308 2309 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 2310 ps->dpm0_pg_nb_ps_lo = 0x1; 2311 ps->dpm0_pg_nb_ps_hi = 0x0; 2312 ps->dpmx_nb_ps_lo = 0x1; 2313 ps->dpmx_nb_ps_hi = 0x0; 2314 } else { 2315 ps->dpm0_pg_nb_ps_lo = 0x3; 2316 ps->dpm0_pg_nb_ps_hi = 0x0; 2317 ps->dpmx_nb_ps_lo = 0x3; 2318 ps->dpmx_nb_ps_hi = 0x0; 2319 2320 if (pi->sys_info.nb_dpm_enable) { 2321 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || 2322 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || 2323 pi->disable_nb_ps3_in_battery; 2324 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; 2325 ps->dpm0_pg_nb_ps_hi = 0x2; 2326 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; 2327 ps->dpmx_nb_ps_hi = 0x2; 2328 } 2329 } 2330 } 2331 2332 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, 2333 u32 index, bool enable) 2334 { 2335 struct kv_power_info *pi = kv_get_pi(adev); 2336 2337 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; 2338 } 2339 2340 static int kv_calculate_ds_divider(struct amdgpu_device *adev) 2341 { 2342 struct kv_power_info *pi = kv_get_pi(adev); 2343 u32 sclk_in_sr = 10000; /* ??? */ 2344 u32 i; 2345 2346 if (pi->lowest_valid > pi->highest_valid) 2347 return -EINVAL; 2348 2349 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2350 pi->graphics_level[i].DeepSleepDivId = 2351 kv_get_sleep_divider_id_from_clock(adev, 2352 be32_to_cpu(pi->graphics_level[i].SclkFrequency), 2353 sclk_in_sr); 2354 } 2355 return 0; 2356 } 2357 2358 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) 2359 { 2360 struct kv_power_info *pi = kv_get_pi(adev); 2361 u32 i; 2362 bool force_high; 2363 struct amdgpu_clock_and_voltage_limits *max_limits = 2364 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2365 u32 mclk = max_limits->mclk; 2366 2367 if (pi->lowest_valid > pi->highest_valid) 2368 return -EINVAL; 2369 2370 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 2371 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2372 pi->graphics_level[i].GnbSlow = 1; 2373 pi->graphics_level[i].ForceNbPs1 = 0; 2374 pi->graphics_level[i].UpH = 0; 2375 } 2376 2377 if (!pi->sys_info.nb_dpm_enable) 2378 return 0; 2379 2380 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || 2381 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); 2382 2383 if (force_high) { 2384 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2385 pi->graphics_level[i].GnbSlow = 0; 2386 } else { 2387 if (pi->battery_state) 2388 pi->graphics_level[0].ForceNbPs1 = 1; 2389 2390 pi->graphics_level[1].GnbSlow = 0; 2391 pi->graphics_level[2].GnbSlow = 0; 2392 pi->graphics_level[3].GnbSlow = 0; 2393 pi->graphics_level[4].GnbSlow = 0; 2394 } 2395 } else { 2396 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2397 pi->graphics_level[i].GnbSlow = 1; 2398 pi->graphics_level[i].ForceNbPs1 = 0; 2399 pi->graphics_level[i].UpH = 0; 2400 } 2401 2402 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { 2403 pi->graphics_level[pi->lowest_valid].UpH = 0x28; 2404 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; 2405 if (pi->lowest_valid != pi->highest_valid) 2406 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; 2407 } 2408 } 2409 return 0; 2410 } 2411 2412 static int kv_calculate_dpm_settings(struct amdgpu_device *adev) 2413 { 2414 struct kv_power_info *pi = kv_get_pi(adev); 2415 u32 i; 2416 2417 if (pi->lowest_valid > pi->highest_valid) 2418 return -EINVAL; 2419 2420 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2421 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; 2422 2423 return 0; 2424 } 2425 2426 static void kv_init_graphics_levels(struct amdgpu_device *adev) 2427 { 2428 struct kv_power_info *pi = kv_get_pi(adev); 2429 u32 i; 2430 struct amdgpu_clock_voltage_dependency_table *table = 2431 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2432 2433 if (table && table->count) { 2434 u32 vid_2bit; 2435 2436 pi->graphics_dpm_level_count = 0; 2437 for (i = 0; i < table->count; i++) { 2438 if (pi->high_voltage_t && 2439 (pi->high_voltage_t < 2440 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) 2441 break; 2442 2443 kv_set_divider_value(adev, i, table->entries[i].clk); 2444 vid_2bit = kv_convert_vid7_to_vid2(adev, 2445 &pi->sys_info.vid_mapping_table, 2446 table->entries[i].v); 2447 kv_set_vid(adev, i, vid_2bit); 2448 kv_set_at(adev, i, pi->at[i]); 2449 kv_dpm_power_level_enabled_for_throttle(adev, i, true); 2450 pi->graphics_dpm_level_count++; 2451 } 2452 } else { 2453 struct sumo_sclk_voltage_mapping_table *table = 2454 &pi->sys_info.sclk_voltage_mapping_table; 2455 2456 pi->graphics_dpm_level_count = 0; 2457 for (i = 0; i < table->num_max_dpm_entries; i++) { 2458 if (pi->high_voltage_t && 2459 pi->high_voltage_t < 2460 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) 2461 break; 2462 2463 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); 2464 kv_set_vid(adev, i, table->entries[i].vid_2bit); 2465 kv_set_at(adev, i, pi->at[i]); 2466 kv_dpm_power_level_enabled_for_throttle(adev, i, true); 2467 pi->graphics_dpm_level_count++; 2468 } 2469 } 2470 2471 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 2472 kv_dpm_power_level_enable(adev, i, false); 2473 } 2474 2475 static void kv_enable_new_levels(struct amdgpu_device *adev) 2476 { 2477 struct kv_power_info *pi = kv_get_pi(adev); 2478 u32 i; 2479 2480 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2481 if (i >= pi->lowest_valid && i <= pi->highest_valid) 2482 kv_dpm_power_level_enable(adev, i, true); 2483 } 2484 } 2485 2486 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) 2487 { 2488 u32 new_mask = (1 << level); 2489 2490 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, 2491 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2492 new_mask); 2493 } 2494 2495 static int kv_set_enabled_levels(struct amdgpu_device *adev) 2496 { 2497 struct kv_power_info *pi = kv_get_pi(adev); 2498 u32 i, new_mask = 0; 2499 2500 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2501 new_mask |= (1 << i); 2502 2503 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, 2504 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2505 new_mask); 2506 } 2507 2508 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, 2509 struct amdgpu_ps *new_rps) 2510 { 2511 struct kv_ps *new_ps = kv_get_ps(new_rps); 2512 struct kv_power_info *pi = kv_get_pi(adev); 2513 u32 nbdpmconfig1; 2514 2515 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 2516 return; 2517 2518 if (pi->sys_info.nb_dpm_enable) { 2519 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); 2520 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK | 2521 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK | 2522 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK | 2523 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK); 2524 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) | 2525 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) | 2526 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) | 2527 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT); 2528 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1); 2529 } 2530 } 2531 2532 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, 2533 int min_temp, int max_temp) 2534 { 2535 int low_temp = 0 * 1000; 2536 int high_temp = 255 * 1000; 2537 u32 tmp; 2538 2539 if (low_temp < min_temp) 2540 low_temp = min_temp; 2541 if (high_temp > max_temp) 2542 high_temp = max_temp; 2543 if (high_temp < low_temp) { 2544 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 2545 return -EINVAL; 2546 } 2547 2548 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 2549 tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK | 2550 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK); 2551 tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) | 2552 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT); 2553 WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp); 2554 2555 adev->pm.dpm.thermal.min_temp = low_temp; 2556 adev->pm.dpm.thermal.max_temp = high_temp; 2557 2558 return 0; 2559 } 2560 2561 union igp_info { 2562 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 2563 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 2564 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; 2565 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 2566 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 2567 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 2568 }; 2569 2570 static int kv_parse_sys_info_table(struct amdgpu_device *adev) 2571 { 2572 struct kv_power_info *pi = kv_get_pi(adev); 2573 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2574 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 2575 union igp_info *igp_info; 2576 u8 frev, crev; 2577 u16 data_offset; 2578 int i; 2579 2580 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 2581 &frev, &crev, &data_offset)) { 2582 igp_info = (union igp_info *)(mode_info->atom_context->bios + 2583 data_offset); 2584 2585 if (crev != 8) { 2586 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 2587 return -EINVAL; 2588 } 2589 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); 2590 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); 2591 pi->sys_info.bootup_nb_voltage_index = 2592 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); 2593 if (igp_info->info_8.ucHtcTmpLmt == 0) 2594 pi->sys_info.htc_tmp_lmt = 203; 2595 else 2596 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; 2597 if (igp_info->info_8.ucHtcHystLmt == 0) 2598 pi->sys_info.htc_hyst_lmt = 5; 2599 else 2600 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; 2601 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { 2602 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); 2603 } 2604 2605 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) 2606 pi->sys_info.nb_dpm_enable = true; 2607 else 2608 pi->sys_info.nb_dpm_enable = false; 2609 2610 for (i = 0; i < KV_NUM_NBPSTATES; i++) { 2611 pi->sys_info.nbp_memory_clock[i] = 2612 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); 2613 pi->sys_info.nbp_n_clock[i] = 2614 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); 2615 } 2616 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & 2617 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) 2618 pi->caps_enable_dfs_bypass = true; 2619 2620 sumo_construct_sclk_voltage_mapping_table(adev, 2621 &pi->sys_info.sclk_voltage_mapping_table, 2622 igp_info->info_8.sAvail_SCLK); 2623 2624 sumo_construct_vid_mapping_table(adev, 2625 &pi->sys_info.vid_mapping_table, 2626 igp_info->info_8.sAvail_SCLK); 2627 2628 kv_construct_max_power_limits_table(adev, 2629 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 2630 } 2631 return 0; 2632 } 2633 2634 union power_info { 2635 struct _ATOM_POWERPLAY_INFO info; 2636 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2637 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2638 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2639 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2640 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2641 }; 2642 2643 union pplib_clock_info { 2644 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2645 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2646 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2647 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2648 }; 2649 2650 union pplib_power_state { 2651 struct _ATOM_PPLIB_STATE v1; 2652 struct _ATOM_PPLIB_STATE_V2 v2; 2653 }; 2654 2655 static void kv_patch_boot_state(struct amdgpu_device *adev, 2656 struct kv_ps *ps) 2657 { 2658 struct kv_power_info *pi = kv_get_pi(adev); 2659 2660 ps->num_levels = 1; 2661 ps->levels[0] = pi->boot_pl; 2662 } 2663 2664 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, 2665 struct amdgpu_ps *rps, 2666 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 2667 u8 table_rev) 2668 { 2669 struct kv_ps *ps = kv_get_ps(rps); 2670 2671 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2672 rps->class = le16_to_cpu(non_clock_info->usClassification); 2673 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 2674 2675 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 2676 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 2677 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 2678 } else { 2679 rps->vclk = 0; 2680 rps->dclk = 0; 2681 } 2682 2683 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2684 adev->pm.dpm.boot_ps = rps; 2685 kv_patch_boot_state(adev, ps); 2686 } 2687 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 2688 adev->pm.dpm.uvd_ps = rps; 2689 } 2690 2691 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, 2692 struct amdgpu_ps *rps, int index, 2693 union pplib_clock_info *clock_info) 2694 { 2695 struct kv_power_info *pi = kv_get_pi(adev); 2696 struct kv_ps *ps = kv_get_ps(rps); 2697 struct kv_pl *pl = &ps->levels[index]; 2698 u32 sclk; 2699 2700 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2701 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2702 pl->sclk = sclk; 2703 pl->vddc_index = clock_info->sumo.vddcIndex; 2704 2705 ps->num_levels = index + 1; 2706 2707 if (pi->caps_sclk_ds) { 2708 pl->ds_divider_index = 5; 2709 pl->ss_divider_index = 5; 2710 } 2711 } 2712 2713 static int kv_parse_power_table(struct amdgpu_device *adev) 2714 { 2715 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2716 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2717 union pplib_power_state *power_state; 2718 int i, j, k, non_clock_array_index, clock_array_index; 2719 union pplib_clock_info *clock_info; 2720 struct _StateArray *state_array; 2721 struct _ClockInfoArray *clock_info_array; 2722 struct _NonClockInfoArray *non_clock_info_array; 2723 union power_info *power_info; 2724 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2725 u16 data_offset; 2726 u8 frev, crev; 2727 u8 *power_state_offset; 2728 struct kv_ps *ps; 2729 2730 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 2731 &frev, &crev, &data_offset)) 2732 return -EINVAL; 2733 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2734 2735 amdgpu_add_thermal_controller(adev); 2736 2737 state_array = (struct _StateArray *) 2738 (mode_info->atom_context->bios + data_offset + 2739 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2740 clock_info_array = (struct _ClockInfoArray *) 2741 (mode_info->atom_context->bios + data_offset + 2742 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2743 non_clock_info_array = (struct _NonClockInfoArray *) 2744 (mode_info->atom_context->bios + data_offset + 2745 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2746 2747 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 2748 sizeof(struct amdgpu_ps), 2749 GFP_KERNEL); 2750 if (!adev->pm.dpm.ps) 2751 return -ENOMEM; 2752 power_state_offset = (u8 *)state_array->states; 2753 for (i = 0; i < state_array->ucNumEntries; i++) { 2754 u8 *idx; 2755 power_state = (union pplib_power_state *)power_state_offset; 2756 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2757 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2758 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2759 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); 2760 if (ps == NULL) { 2761 kfree(adev->pm.dpm.ps); 2762 return -ENOMEM; 2763 } 2764 adev->pm.dpm.ps[i].ps_priv = ps; 2765 k = 0; 2766 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 2767 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2768 clock_array_index = idx[j]; 2769 if (clock_array_index >= clock_info_array->ucNumEntries) 2770 continue; 2771 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) 2772 break; 2773 clock_info = (union pplib_clock_info *) 2774 ((u8 *)&clock_info_array->clockInfo[0] + 2775 (clock_array_index * clock_info_array->ucEntrySize)); 2776 kv_parse_pplib_clock_info(adev, 2777 &adev->pm.dpm.ps[i], k, 2778 clock_info); 2779 k++; 2780 } 2781 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 2782 non_clock_info, 2783 non_clock_info_array->ucEntrySize); 2784 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2785 } 2786 adev->pm.dpm.num_ps = state_array->ucNumEntries; 2787 2788 /* fill in the vce power states */ 2789 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 2790 u32 sclk; 2791 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 2792 clock_info = (union pplib_clock_info *) 2793 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2794 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2795 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2796 adev->pm.dpm.vce_states[i].sclk = sclk; 2797 adev->pm.dpm.vce_states[i].mclk = 0; 2798 } 2799 2800 return 0; 2801 } 2802 2803 static int kv_dpm_init(struct amdgpu_device *adev) 2804 { 2805 struct kv_power_info *pi; 2806 int ret, i; 2807 2808 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); 2809 if (pi == NULL) 2810 return -ENOMEM; 2811 adev->pm.dpm.priv = pi; 2812 2813 ret = amdgpu_get_platform_caps(adev); 2814 if (ret) 2815 return ret; 2816 2817 ret = amdgpu_parse_extended_power_table(adev); 2818 if (ret) 2819 return ret; 2820 2821 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 2822 pi->at[i] = TRINITY_AT_DFLT; 2823 2824 pi->sram_end = SMC_RAM_END; 2825 2826 pi->enable_nb_dpm = true; 2827 2828 pi->caps_power_containment = true; 2829 pi->caps_cac = true; 2830 pi->enable_didt = false; 2831 if (pi->enable_didt) { 2832 pi->caps_sq_ramping = true; 2833 pi->caps_db_ramping = true; 2834 pi->caps_td_ramping = true; 2835 pi->caps_tcp_ramping = true; 2836 } 2837 2838 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 2839 pi->caps_sclk_ds = true; 2840 else 2841 pi->caps_sclk_ds = false; 2842 2843 pi->enable_auto_thermal_throttling = true; 2844 pi->disable_nb_ps3_in_battery = false; 2845 if (amdgpu_bapm == 0) 2846 pi->bapm_enable = false; 2847 else 2848 pi->bapm_enable = true; 2849 pi->voltage_drop_t = 0; 2850 pi->caps_sclk_throttle_low_notification = false; 2851 pi->caps_fps = false; /* true? */ 2852 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; 2853 pi->caps_uvd_dpm = true; 2854 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; 2855 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; 2856 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; 2857 pi->caps_stable_p_state = false; 2858 2859 ret = kv_parse_sys_info_table(adev); 2860 if (ret) 2861 return ret; 2862 2863 kv_patch_voltage_values(adev); 2864 kv_construct_boot_state(adev); 2865 2866 ret = kv_parse_power_table(adev); 2867 if (ret) 2868 return ret; 2869 2870 pi->enable_dpm = true; 2871 2872 return 0; 2873 } 2874 2875 static void 2876 kv_dpm_debugfs_print_current_performance_level(void *handle, 2877 struct seq_file *m) 2878 { 2879 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2880 struct kv_power_info *pi = kv_get_pi(adev); 2881 u32 current_index = 2882 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & 2883 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> 2884 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; 2885 u32 sclk, tmp; 2886 u16 vddc; 2887 2888 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { 2889 seq_printf(m, "invalid dpm profile %d\n", current_index); 2890 } else { 2891 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); 2892 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & 2893 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 2894 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT; 2895 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); 2896 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); 2897 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); 2898 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 2899 current_index, sclk, vddc); 2900 } 2901 } 2902 2903 static void 2904 kv_dpm_print_power_state(void *handle, void *request_ps) 2905 { 2906 int i; 2907 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 2908 struct kv_ps *ps = kv_get_ps(rps); 2909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2910 2911 amdgpu_dpm_print_class_info(rps->class, rps->class2); 2912 amdgpu_dpm_print_cap_info(rps->caps); 2913 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 2914 for (i = 0; i < ps->num_levels; i++) { 2915 struct kv_pl *pl = &ps->levels[i]; 2916 printk("\t\tpower level %d sclk: %u vddc: %u\n", 2917 i, pl->sclk, 2918 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); 2919 } 2920 amdgpu_dpm_print_ps_status(adev, rps); 2921 } 2922 2923 static void kv_dpm_fini(struct amdgpu_device *adev) 2924 { 2925 int i; 2926 2927 for (i = 0; i < adev->pm.dpm.num_ps; i++) { 2928 kfree(adev->pm.dpm.ps[i].ps_priv); 2929 } 2930 kfree(adev->pm.dpm.ps); 2931 kfree(adev->pm.dpm.priv); 2932 amdgpu_free_extended_power_table(adev); 2933 } 2934 2935 static void kv_dpm_display_configuration_changed(void *handle) 2936 { 2937 2938 } 2939 2940 static u32 kv_dpm_get_sclk(void *handle, bool low) 2941 { 2942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2943 struct kv_power_info *pi = kv_get_pi(adev); 2944 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); 2945 2946 if (low) 2947 return requested_state->levels[0].sclk; 2948 else 2949 return requested_state->levels[requested_state->num_levels - 1].sclk; 2950 } 2951 2952 static u32 kv_dpm_get_mclk(void *handle, bool low) 2953 { 2954 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2955 struct kv_power_info *pi = kv_get_pi(adev); 2956 2957 return pi->sys_info.bootup_uma_clk; 2958 } 2959 2960 /* get temperature in millidegrees */ 2961 static int kv_dpm_get_temp(void *handle) 2962 { 2963 u32 temp; 2964 int actual_temp = 0; 2965 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2966 2967 temp = RREG32_SMC(0xC0300E0C); 2968 2969 if (temp) 2970 actual_temp = (temp / 8) - 49; 2971 else 2972 actual_temp = 0; 2973 2974 actual_temp = actual_temp * 1000; 2975 2976 return actual_temp; 2977 } 2978 2979 static int kv_dpm_early_init(void *handle) 2980 { 2981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2982 2983 adev->powerplay.pp_funcs = &kv_dpm_funcs; 2984 adev->powerplay.pp_handle = adev; 2985 kv_dpm_set_irq_funcs(adev); 2986 2987 return 0; 2988 } 2989 2990 static int kv_dpm_late_init(void *handle) 2991 { 2992 /* powerdown unused blocks for now */ 2993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2994 2995 if (!adev->pm.dpm_enabled) 2996 return 0; 2997 2998 kv_dpm_powergate_acp(adev, true); 2999 kv_dpm_powergate_samu(adev, true); 3000 3001 return 0; 3002 } 3003 3004 static int kv_dpm_sw_init(void *handle) 3005 { 3006 int ret; 3007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3008 3009 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, 3010 &adev->pm.dpm.thermal.irq); 3011 if (ret) 3012 return ret; 3013 3014 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, 3015 &adev->pm.dpm.thermal.irq); 3016 if (ret) 3017 return ret; 3018 3019 /* default to balanced state */ 3020 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 3021 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 3022 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 3023 adev->pm.default_sclk = adev->clock.default_sclk; 3024 adev->pm.default_mclk = adev->clock.default_mclk; 3025 adev->pm.current_sclk = adev->clock.default_sclk; 3026 adev->pm.current_mclk = adev->clock.default_mclk; 3027 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 3028 3029 if (amdgpu_dpm == 0) 3030 return 0; 3031 3032 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 3033 ret = kv_dpm_init(adev); 3034 if (ret) 3035 goto dpm_failed; 3036 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 3037 if (amdgpu_dpm == 1) 3038 amdgpu_pm_print_power_states(adev); 3039 DRM_INFO("amdgpu: dpm initialized\n"); 3040 3041 return 0; 3042 3043 dpm_failed: 3044 kv_dpm_fini(adev); 3045 DRM_ERROR("amdgpu: dpm initialization failed\n"); 3046 return ret; 3047 } 3048 3049 static int kv_dpm_sw_fini(void *handle) 3050 { 3051 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3052 3053 flush_work(&adev->pm.dpm.thermal.work); 3054 3055 kv_dpm_fini(adev); 3056 3057 return 0; 3058 } 3059 3060 static int kv_dpm_hw_init(void *handle) 3061 { 3062 int ret; 3063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3064 3065 if (!amdgpu_dpm) 3066 return 0; 3067 3068 kv_dpm_setup_asic(adev); 3069 ret = kv_dpm_enable(adev); 3070 if (ret) 3071 adev->pm.dpm_enabled = false; 3072 else 3073 adev->pm.dpm_enabled = true; 3074 amdgpu_legacy_dpm_compute_clocks(adev); 3075 return ret; 3076 } 3077 3078 static int kv_dpm_hw_fini(void *handle) 3079 { 3080 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3081 3082 if (adev->pm.dpm_enabled) 3083 kv_dpm_disable(adev); 3084 3085 return 0; 3086 } 3087 3088 static int kv_dpm_suspend(void *handle) 3089 { 3090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3091 3092 if (adev->pm.dpm_enabled) { 3093 /* disable dpm */ 3094 kv_dpm_disable(adev); 3095 /* reset the power state */ 3096 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 3097 } 3098 return 0; 3099 } 3100 3101 static int kv_dpm_resume(void *handle) 3102 { 3103 int ret; 3104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3105 3106 if (adev->pm.dpm_enabled) { 3107 /* asic init will reset to the boot state */ 3108 kv_dpm_setup_asic(adev); 3109 ret = kv_dpm_enable(adev); 3110 if (ret) 3111 adev->pm.dpm_enabled = false; 3112 else 3113 adev->pm.dpm_enabled = true; 3114 if (adev->pm.dpm_enabled) 3115 amdgpu_legacy_dpm_compute_clocks(adev); 3116 } 3117 return 0; 3118 } 3119 3120 static bool kv_dpm_is_idle(void *handle) 3121 { 3122 return true; 3123 } 3124 3125 static int kv_dpm_wait_for_idle(void *handle) 3126 { 3127 return 0; 3128 } 3129 3130 3131 static int kv_dpm_soft_reset(void *handle) 3132 { 3133 return 0; 3134 } 3135 3136 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, 3137 struct amdgpu_irq_src *src, 3138 unsigned type, 3139 enum amdgpu_interrupt_state state) 3140 { 3141 u32 cg_thermal_int; 3142 3143 switch (type) { 3144 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 3145 switch (state) { 3146 case AMDGPU_IRQ_STATE_DISABLE: 3147 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3148 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 3149 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3150 break; 3151 case AMDGPU_IRQ_STATE_ENABLE: 3152 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3153 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 3154 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3155 break; 3156 default: 3157 break; 3158 } 3159 break; 3160 3161 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 3162 switch (state) { 3163 case AMDGPU_IRQ_STATE_DISABLE: 3164 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3165 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 3166 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3167 break; 3168 case AMDGPU_IRQ_STATE_ENABLE: 3169 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3170 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 3171 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3172 break; 3173 default: 3174 break; 3175 } 3176 break; 3177 3178 default: 3179 break; 3180 } 3181 return 0; 3182 } 3183 3184 static int kv_dpm_process_interrupt(struct amdgpu_device *adev, 3185 struct amdgpu_irq_src *source, 3186 struct amdgpu_iv_entry *entry) 3187 { 3188 bool queue_thermal = false; 3189 3190 if (entry == NULL) 3191 return -EINVAL; 3192 3193 switch (entry->src_id) { 3194 case 230: /* thermal low to high */ 3195 DRM_DEBUG("IH: thermal low to high\n"); 3196 adev->pm.dpm.thermal.high_to_low = false; 3197 queue_thermal = true; 3198 break; 3199 case 231: /* thermal high to low */ 3200 DRM_DEBUG("IH: thermal high to low\n"); 3201 adev->pm.dpm.thermal.high_to_low = true; 3202 queue_thermal = true; 3203 break; 3204 default: 3205 break; 3206 } 3207 3208 if (queue_thermal) 3209 schedule_work(&adev->pm.dpm.thermal.work); 3210 3211 return 0; 3212 } 3213 3214 static int kv_dpm_set_clockgating_state(void *handle, 3215 enum amd_clockgating_state state) 3216 { 3217 return 0; 3218 } 3219 3220 static int kv_dpm_set_powergating_state(void *handle, 3221 enum amd_powergating_state state) 3222 { 3223 return 0; 3224 } 3225 3226 static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1, 3227 const struct kv_pl *kv_cpl2) 3228 { 3229 return ((kv_cpl1->sclk == kv_cpl2->sclk) && 3230 (kv_cpl1->vddc_index == kv_cpl2->vddc_index) && 3231 (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) && 3232 (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state)); 3233 } 3234 3235 static int kv_check_state_equal(void *handle, 3236 void *current_ps, 3237 void *request_ps, 3238 bool *equal) 3239 { 3240 struct kv_ps *kv_cps; 3241 struct kv_ps *kv_rps; 3242 int i; 3243 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 3244 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 3245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3246 3247 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 3248 return -EINVAL; 3249 3250 kv_cps = kv_get_ps(cps); 3251 kv_rps = kv_get_ps(rps); 3252 3253 if (kv_cps == NULL) { 3254 *equal = false; 3255 return 0; 3256 } 3257 3258 if (kv_cps->num_levels != kv_rps->num_levels) { 3259 *equal = false; 3260 return 0; 3261 } 3262 3263 for (i = 0; i < kv_cps->num_levels; i++) { 3264 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]), 3265 &(kv_rps->levels[i]))) { 3266 *equal = false; 3267 return 0; 3268 } 3269 } 3270 3271 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 3272 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 3273 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 3274 3275 return 0; 3276 } 3277 3278 static int kv_dpm_read_sensor(void *handle, int idx, 3279 void *value, int *size) 3280 { 3281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3282 struct kv_power_info *pi = kv_get_pi(adev); 3283 uint32_t sclk; 3284 u32 pl_index = 3285 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & 3286 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> 3287 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; 3288 3289 /* size must be at least 4 bytes for all sensors */ 3290 if (*size < 4) 3291 return -EINVAL; 3292 3293 switch (idx) { 3294 case AMDGPU_PP_SENSOR_GFX_SCLK: 3295 if (pl_index < SMU__NUM_SCLK_DPM_STATE) { 3296 sclk = be32_to_cpu( 3297 pi->graphics_level[pl_index].SclkFrequency); 3298 *((uint32_t *)value) = sclk; 3299 *size = 4; 3300 return 0; 3301 } 3302 return -EINVAL; 3303 case AMDGPU_PP_SENSOR_GPU_TEMP: 3304 *((uint32_t *)value) = kv_dpm_get_temp(adev); 3305 *size = 4; 3306 return 0; 3307 default: 3308 return -EOPNOTSUPP; 3309 } 3310 } 3311 3312 static int kv_set_powergating_by_smu(void *handle, 3313 uint32_t block_type, bool gate) 3314 { 3315 switch (block_type) { 3316 case AMD_IP_BLOCK_TYPE_UVD: 3317 kv_dpm_powergate_uvd(handle, gate); 3318 break; 3319 case AMD_IP_BLOCK_TYPE_VCE: 3320 kv_dpm_powergate_vce(handle, gate); 3321 break; 3322 default: 3323 break; 3324 } 3325 return 0; 3326 } 3327 3328 static const struct amd_ip_funcs kv_dpm_ip_funcs = { 3329 .name = "kv_dpm", 3330 .early_init = kv_dpm_early_init, 3331 .late_init = kv_dpm_late_init, 3332 .sw_init = kv_dpm_sw_init, 3333 .sw_fini = kv_dpm_sw_fini, 3334 .hw_init = kv_dpm_hw_init, 3335 .hw_fini = kv_dpm_hw_fini, 3336 .suspend = kv_dpm_suspend, 3337 .resume = kv_dpm_resume, 3338 .is_idle = kv_dpm_is_idle, 3339 .wait_for_idle = kv_dpm_wait_for_idle, 3340 .soft_reset = kv_dpm_soft_reset, 3341 .set_clockgating_state = kv_dpm_set_clockgating_state, 3342 .set_powergating_state = kv_dpm_set_powergating_state, 3343 }; 3344 3345 const struct amdgpu_ip_block_version kv_smu_ip_block = 3346 { 3347 .type = AMD_IP_BLOCK_TYPE_SMC, 3348 .major = 1, 3349 .minor = 0, 3350 .rev = 0, 3351 .funcs = &kv_dpm_ip_funcs, 3352 }; 3353 3354 static const struct amd_pm_funcs kv_dpm_funcs = { 3355 .pre_set_power_state = &kv_dpm_pre_set_power_state, 3356 .set_power_state = &kv_dpm_set_power_state, 3357 .post_set_power_state = &kv_dpm_post_set_power_state, 3358 .display_configuration_changed = &kv_dpm_display_configuration_changed, 3359 .get_sclk = &kv_dpm_get_sclk, 3360 .get_mclk = &kv_dpm_get_mclk, 3361 .print_power_state = &kv_dpm_print_power_state, 3362 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 3363 .force_performance_level = &kv_dpm_force_performance_level, 3364 .set_powergating_by_smu = kv_set_powergating_by_smu, 3365 .enable_bapm = &kv_dpm_enable_bapm, 3366 .get_vce_clock_state = amdgpu_get_vce_clock_state, 3367 .check_state_equal = kv_check_state_equal, 3368 .read_sensor = &kv_dpm_read_sensor, 3369 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 3370 }; 3371 3372 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = { 3373 .set = kv_dpm_set_interrupt_state, 3374 .process = kv_dpm_process_interrupt, 3375 }; 3376 3377 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) 3378 { 3379 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 3380 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; 3381 } 3382