1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "cikd.h" 27 #include "atom.h" 28 #include "amdgpu_atombios.h" 29 #include "amdgpu_dpm.h" 30 #include "kv_dpm.h" 31 #include "gfx_v7_0.h" 32 #include <linux/seq_file.h> 33 34 #include "smu/smu_7_0_0_d.h" 35 #include "smu/smu_7_0_0_sh_mask.h" 36 37 #include "gca/gfx_7_2_d.h" 38 #include "gca/gfx_7_2_sh_mask.h" 39 #include "legacy_dpm.h" 40 41 #define KV_MAX_DEEPSLEEP_DIVIDER_ID 5 42 #define KV_MINIMUM_ENGINE_CLOCK 800 43 #define SMC_RAM_END 0x40000 44 45 static const struct amd_pm_funcs kv_dpm_funcs; 46 47 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev); 48 static int kv_enable_nb_dpm(struct amdgpu_device *adev, 49 bool enable); 50 static void kv_init_graphics_levels(struct amdgpu_device *adev); 51 static int kv_calculate_ds_divider(struct amdgpu_device *adev); 52 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev); 53 static int kv_calculate_dpm_settings(struct amdgpu_device *adev); 54 static void kv_enable_new_levels(struct amdgpu_device *adev); 55 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, 56 struct amdgpu_ps *new_rps); 57 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level); 58 static int kv_set_enabled_levels(struct amdgpu_device *adev); 59 static int kv_force_dpm_highest(struct amdgpu_device *adev); 60 static int kv_force_dpm_lowest(struct amdgpu_device *adev); 61 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, 62 struct amdgpu_ps *new_rps, 63 struct amdgpu_ps *old_rps); 64 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, 65 int min_temp, int max_temp); 66 static int kv_init_fps_limits(struct amdgpu_device *adev); 67 68 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate); 69 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate); 70 71 72 static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev, 73 struct sumo_vid_mapping_table *vid_mapping_table, 74 u32 vid_2bit) 75 { 76 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table = 77 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 78 u32 i; 79 80 if (vddc_sclk_table && vddc_sclk_table->count) { 81 if (vid_2bit < vddc_sclk_table->count) 82 return vddc_sclk_table->entries[vid_2bit].v; 83 else 84 return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v; 85 } else { 86 for (i = 0; i < vid_mapping_table->num_entries; i++) { 87 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) 88 return vid_mapping_table->entries[i].vid_7bit; 89 } 90 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; 91 } 92 } 93 94 static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev, 95 struct sumo_vid_mapping_table *vid_mapping_table, 96 u32 vid_7bit) 97 { 98 struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table = 99 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 100 u32 i; 101 102 if (vddc_sclk_table && vddc_sclk_table->count) { 103 for (i = 0; i < vddc_sclk_table->count; i++) { 104 if (vddc_sclk_table->entries[i].v == vid_7bit) 105 return i; 106 } 107 return vddc_sclk_table->count - 1; 108 } else { 109 for (i = 0; i < vid_mapping_table->num_entries; i++) { 110 if (vid_mapping_table->entries[i].vid_7bit == vid_7bit) 111 return vid_mapping_table->entries[i].vid_2bit; 112 } 113 114 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit; 115 } 116 } 117 118 static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable) 119 { 120 /* This bit selects who handles display phy powergating. 121 * Clear the bit to let atom handle it. 122 * Set it to let the driver handle it. 123 * For now we just let atom handle it. 124 */ 125 #if 0 126 u32 v = RREG32(mmDOUT_SCRATCH3); 127 128 if (enable) 129 v |= 0x4; 130 else 131 v &= 0xFFFFFFFB; 132 133 WREG32(mmDOUT_SCRATCH3, v); 134 #endif 135 } 136 137 static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev, 138 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, 139 ATOM_AVAILABLE_SCLK_LIST *table) 140 { 141 u32 i; 142 u32 n = 0; 143 u32 prev_sclk = 0; 144 145 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { 146 if (table[i].ulSupportedSCLK > prev_sclk) { 147 sclk_voltage_mapping_table->entries[n].sclk_frequency = 148 table[i].ulSupportedSCLK; 149 sclk_voltage_mapping_table->entries[n].vid_2bit = 150 table[i].usVoltageIndex; 151 prev_sclk = table[i].ulSupportedSCLK; 152 n++; 153 } 154 } 155 156 sclk_voltage_mapping_table->num_max_dpm_entries = n; 157 } 158 159 static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev, 160 struct sumo_vid_mapping_table *vid_mapping_table, 161 ATOM_AVAILABLE_SCLK_LIST *table) 162 { 163 u32 i, j; 164 165 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { 166 if (table[i].ulSupportedSCLK != 0) { 167 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = 168 table[i].usVoltageID; 169 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = 170 table[i].usVoltageIndex; 171 } 172 } 173 174 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { 175 if (vid_mapping_table->entries[i].vid_7bit == 0) { 176 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { 177 if (vid_mapping_table->entries[j].vid_7bit != 0) { 178 vid_mapping_table->entries[i] = 179 vid_mapping_table->entries[j]; 180 vid_mapping_table->entries[j].vid_7bit = 0; 181 break; 182 } 183 } 184 185 if (j == SUMO_MAX_NUMBER_VOLTAGES) 186 break; 187 } 188 } 189 190 vid_mapping_table->num_entries = i; 191 } 192 193 #if 0 194 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] = 195 { 196 { 0, 4, 1 }, 197 { 1, 4, 1 }, 198 { 2, 5, 1 }, 199 { 3, 4, 2 }, 200 { 4, 1, 1 }, 201 { 5, 5, 2 }, 202 { 6, 6, 1 }, 203 { 7, 9, 2 }, 204 { 0xffffffff } 205 }; 206 207 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] = 208 { 209 { 0, 4, 1 }, 210 { 0xffffffff } 211 }; 212 213 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] = 214 { 215 { 0, 4, 1 }, 216 { 0xffffffff } 217 }; 218 219 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] = 220 { 221 { 0, 4, 1 }, 222 { 0xffffffff } 223 }; 224 225 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] = 226 { 227 { 0, 4, 1 }, 228 { 0xffffffff } 229 }; 230 231 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] = 232 { 233 { 0, 4, 1 }, 234 { 1, 4, 1 }, 235 { 2, 5, 1 }, 236 { 3, 4, 1 }, 237 { 4, 1, 1 }, 238 { 5, 5, 1 }, 239 { 6, 6, 1 }, 240 { 7, 9, 1 }, 241 { 8, 4, 1 }, 242 { 9, 2, 1 }, 243 { 10, 3, 1 }, 244 { 11, 6, 1 }, 245 { 12, 8, 2 }, 246 { 13, 1, 1 }, 247 { 14, 2, 1 }, 248 { 15, 3, 1 }, 249 { 16, 1, 1 }, 250 { 17, 4, 1 }, 251 { 18, 3, 1 }, 252 { 19, 1, 1 }, 253 { 20, 8, 1 }, 254 { 21, 5, 1 }, 255 { 22, 1, 1 }, 256 { 23, 1, 1 }, 257 { 24, 4, 1 }, 258 { 27, 6, 1 }, 259 { 28, 1, 1 }, 260 { 0xffffffff } 261 }; 262 263 static const struct kv_lcac_config_reg sx0_cac_config_reg[] = 264 { 265 { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 266 }; 267 268 static const struct kv_lcac_config_reg mc0_cac_config_reg[] = 269 { 270 { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 271 }; 272 273 static const struct kv_lcac_config_reg mc1_cac_config_reg[] = 274 { 275 { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 276 }; 277 278 static const struct kv_lcac_config_reg mc2_cac_config_reg[] = 279 { 280 { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 281 }; 282 283 static const struct kv_lcac_config_reg mc3_cac_config_reg[] = 284 { 285 { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 286 }; 287 288 static const struct kv_lcac_config_reg cpl_cac_config_reg[] = 289 { 290 { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 } 291 }; 292 #endif 293 294 static const struct kv_pt_config_reg didt_config_kv[] = 295 { 296 { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 297 { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 298 { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 299 { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 300 { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 301 { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 302 { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 303 { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 304 { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 305 { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 306 { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 307 { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 308 { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 309 { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 310 { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 311 { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 312 { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 313 { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 314 { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 315 { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 316 { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 317 { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 318 { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 319 { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 320 { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 321 { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 322 { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 323 { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 324 { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 325 { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 326 { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 327 { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 328 { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 329 { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 330 { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 331 { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 332 { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 333 { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 334 { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 335 { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 336 { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 337 { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 338 { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 339 { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 340 { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 341 { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 342 { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 343 { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 344 { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 345 { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 346 { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 347 { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 348 { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 349 { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 350 { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 351 { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 352 { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 353 { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 354 { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 355 { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 356 { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 357 { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 358 { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 359 { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND }, 360 { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND }, 361 { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND }, 362 { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND }, 363 { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND }, 364 { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND }, 365 { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 366 { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND }, 367 { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND }, 368 { 0xFFFFFFFF } 369 }; 370 371 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps) 372 { 373 struct kv_ps *ps = rps->ps_priv; 374 375 return ps; 376 } 377 378 static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev) 379 { 380 struct kv_power_info *pi = adev->pm.dpm.priv; 381 382 return pi; 383 } 384 385 #if 0 386 static void kv_program_local_cac_table(struct amdgpu_device *adev, 387 const struct kv_lcac_config_values *local_cac_table, 388 const struct kv_lcac_config_reg *local_cac_reg) 389 { 390 u32 i, count, data; 391 const struct kv_lcac_config_values *values = local_cac_table; 392 393 while (values->block_id != 0xffffffff) { 394 count = values->signal_id; 395 for (i = 0; i < count; i++) { 396 data = ((values->block_id << local_cac_reg->block_shift) & 397 local_cac_reg->block_mask); 398 data |= ((i << local_cac_reg->signal_shift) & 399 local_cac_reg->signal_mask); 400 data |= ((values->t << local_cac_reg->t_shift) & 401 local_cac_reg->t_mask); 402 data |= ((1 << local_cac_reg->enable_shift) & 403 local_cac_reg->enable_mask); 404 WREG32_SMC(local_cac_reg->cntl, data); 405 } 406 values++; 407 } 408 } 409 #endif 410 411 static int kv_program_pt_config_registers(struct amdgpu_device *adev, 412 const struct kv_pt_config_reg *cac_config_regs) 413 { 414 const struct kv_pt_config_reg *config_regs = cac_config_regs; 415 u32 data; 416 u32 cache = 0; 417 418 if (config_regs == NULL) 419 return -EINVAL; 420 421 while (config_regs->offset != 0xFFFFFFFF) { 422 if (config_regs->type == KV_CONFIGREG_CACHE) { 423 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask); 424 } else { 425 switch (config_regs->type) { 426 case KV_CONFIGREG_SMC_IND: 427 data = RREG32_SMC(config_regs->offset); 428 break; 429 case KV_CONFIGREG_DIDT_IND: 430 data = RREG32_DIDT(config_regs->offset); 431 break; 432 default: 433 data = RREG32(config_regs->offset); 434 break; 435 } 436 437 data &= ~config_regs->mask; 438 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 439 data |= cache; 440 cache = 0; 441 442 switch (config_regs->type) { 443 case KV_CONFIGREG_SMC_IND: 444 WREG32_SMC(config_regs->offset, data); 445 break; 446 case KV_CONFIGREG_DIDT_IND: 447 WREG32_DIDT(config_regs->offset, data); 448 break; 449 default: 450 WREG32(config_regs->offset, data); 451 break; 452 } 453 } 454 config_regs++; 455 } 456 457 return 0; 458 } 459 460 static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable) 461 { 462 struct kv_power_info *pi = kv_get_pi(adev); 463 u32 data; 464 465 if (pi->caps_sq_ramping) { 466 data = RREG32_DIDT(ixDIDT_SQ_CTRL0); 467 if (enable) 468 data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; 469 else 470 data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK; 471 WREG32_DIDT(ixDIDT_SQ_CTRL0, data); 472 } 473 474 if (pi->caps_db_ramping) { 475 data = RREG32_DIDT(ixDIDT_DB_CTRL0); 476 if (enable) 477 data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; 478 else 479 data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK; 480 WREG32_DIDT(ixDIDT_DB_CTRL0, data); 481 } 482 483 if (pi->caps_td_ramping) { 484 data = RREG32_DIDT(ixDIDT_TD_CTRL0); 485 if (enable) 486 data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; 487 else 488 data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK; 489 WREG32_DIDT(ixDIDT_TD_CTRL0, data); 490 } 491 492 if (pi->caps_tcp_ramping) { 493 data = RREG32_DIDT(ixDIDT_TCP_CTRL0); 494 if (enable) 495 data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; 496 else 497 data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK; 498 WREG32_DIDT(ixDIDT_TCP_CTRL0, data); 499 } 500 } 501 502 static int kv_enable_didt(struct amdgpu_device *adev, bool enable) 503 { 504 struct kv_power_info *pi = kv_get_pi(adev); 505 int ret; 506 507 if (pi->caps_sq_ramping || 508 pi->caps_db_ramping || 509 pi->caps_td_ramping || 510 pi->caps_tcp_ramping) { 511 amdgpu_gfx_rlc_enter_safe_mode(adev); 512 513 if (enable) { 514 ret = kv_program_pt_config_registers(adev, didt_config_kv); 515 if (ret) { 516 amdgpu_gfx_rlc_exit_safe_mode(adev); 517 return ret; 518 } 519 } 520 521 kv_do_enable_didt(adev, enable); 522 523 amdgpu_gfx_rlc_exit_safe_mode(adev); 524 } 525 526 return 0; 527 } 528 529 #if 0 530 static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev) 531 { 532 struct kv_power_info *pi = kv_get_pi(adev); 533 534 if (pi->caps_cac) { 535 WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0); 536 WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0); 537 kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg); 538 539 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0); 540 WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0); 541 kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg); 542 543 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0); 544 WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0); 545 kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg); 546 547 WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0); 548 WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0); 549 kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg); 550 551 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0); 552 WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0); 553 kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg); 554 555 WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0); 556 WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0); 557 kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg); 558 } 559 } 560 #endif 561 562 static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable) 563 { 564 struct kv_power_info *pi = kv_get_pi(adev); 565 int ret = 0; 566 567 if (pi->caps_cac) { 568 if (enable) { 569 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac); 570 if (ret) 571 pi->cac_enabled = false; 572 else 573 pi->cac_enabled = true; 574 } else if (pi->cac_enabled) { 575 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac); 576 pi->cac_enabled = false; 577 } 578 } 579 580 return ret; 581 } 582 583 static int kv_process_firmware_header(struct amdgpu_device *adev) 584 { 585 struct kv_power_info *pi = kv_get_pi(adev); 586 u32 tmp; 587 int ret; 588 589 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + 590 offsetof(SMU7_Firmware_Header, DpmTable), 591 &tmp, pi->sram_end); 592 593 if (ret == 0) 594 pi->dpm_table_start = tmp; 595 596 ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION + 597 offsetof(SMU7_Firmware_Header, SoftRegisters), 598 &tmp, pi->sram_end); 599 600 if (ret == 0) 601 pi->soft_regs_start = tmp; 602 603 return ret; 604 } 605 606 static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev) 607 { 608 struct kv_power_info *pi = kv_get_pi(adev); 609 int ret; 610 611 pi->graphics_voltage_change_enable = 1; 612 613 ret = amdgpu_kv_copy_bytes_to_smc(adev, 614 pi->dpm_table_start + 615 offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable), 616 &pi->graphics_voltage_change_enable, 617 sizeof(u8), pi->sram_end); 618 619 return ret; 620 } 621 622 static int kv_set_dpm_interval(struct amdgpu_device *adev) 623 { 624 struct kv_power_info *pi = kv_get_pi(adev); 625 int ret; 626 627 pi->graphics_interval = 1; 628 629 ret = amdgpu_kv_copy_bytes_to_smc(adev, 630 pi->dpm_table_start + 631 offsetof(SMU7_Fusion_DpmTable, GraphicsInterval), 632 &pi->graphics_interval, 633 sizeof(u8), pi->sram_end); 634 635 return ret; 636 } 637 638 static int kv_set_dpm_boot_state(struct amdgpu_device *adev) 639 { 640 struct kv_power_info *pi = kv_get_pi(adev); 641 int ret; 642 643 ret = amdgpu_kv_copy_bytes_to_smc(adev, 644 pi->dpm_table_start + 645 offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel), 646 &pi->graphics_boot_level, 647 sizeof(u8), pi->sram_end); 648 649 return ret; 650 } 651 652 static void kv_program_vc(struct amdgpu_device *adev) 653 { 654 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100); 655 } 656 657 static void kv_clear_vc(struct amdgpu_device *adev) 658 { 659 WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0); 660 } 661 662 static int kv_set_divider_value(struct amdgpu_device *adev, 663 u32 index, u32 sclk) 664 { 665 struct kv_power_info *pi = kv_get_pi(adev); 666 struct atom_clock_dividers dividers; 667 int ret; 668 669 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 670 sclk, false, ÷rs); 671 if (ret) 672 return ret; 673 674 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; 675 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); 676 677 return 0; 678 } 679 680 static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev, 681 u16 voltage) 682 { 683 return 6200 - (voltage * 25); 684 } 685 686 static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev, 687 u32 vid_2bit) 688 { 689 struct kv_power_info *pi = kv_get_pi(adev); 690 u32 vid_8bit = kv_convert_vid2_to_vid7(adev, 691 &pi->sys_info.vid_mapping_table, 692 vid_2bit); 693 694 return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit); 695 } 696 697 698 static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid) 699 { 700 struct kv_power_info *pi = kv_get_pi(adev); 701 702 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; 703 pi->graphics_level[index].MinVddNb = 704 cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid)); 705 706 return 0; 707 } 708 709 static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at) 710 { 711 struct kv_power_info *pi = kv_get_pi(adev); 712 713 pi->graphics_level[index].AT = cpu_to_be16((u16)at); 714 715 return 0; 716 } 717 718 static void kv_dpm_power_level_enable(struct amdgpu_device *adev, 719 u32 index, bool enable) 720 { 721 struct kv_power_info *pi = kv_get_pi(adev); 722 723 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; 724 } 725 726 static void kv_start_dpm(struct amdgpu_device *adev) 727 { 728 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); 729 730 tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK; 731 WREG32_SMC(ixGENERAL_PWRMGT, tmp); 732 733 amdgpu_kv_smc_dpm_enable(adev, true); 734 } 735 736 static void kv_stop_dpm(struct amdgpu_device *adev) 737 { 738 amdgpu_kv_smc_dpm_enable(adev, false); 739 } 740 741 static void kv_start_am(struct amdgpu_device *adev) 742 { 743 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); 744 745 sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | 746 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); 747 sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK; 748 749 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 750 } 751 752 static void kv_reset_am(struct amdgpu_device *adev) 753 { 754 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); 755 756 sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | 757 SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK); 758 759 WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); 760 } 761 762 static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze) 763 { 764 return amdgpu_kv_notify_message_to_smu(adev, freeze ? 765 PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel); 766 } 767 768 static int kv_force_lowest_valid(struct amdgpu_device *adev) 769 { 770 return kv_force_dpm_lowest(adev); 771 } 772 773 static int kv_unforce_levels(struct amdgpu_device *adev) 774 { 775 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 776 return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel); 777 else 778 return kv_set_enabled_levels(adev); 779 } 780 781 static int kv_update_sclk_t(struct amdgpu_device *adev) 782 { 783 struct kv_power_info *pi = kv_get_pi(adev); 784 u32 low_sclk_interrupt_t = 0; 785 int ret = 0; 786 787 if (pi->caps_sclk_throttle_low_notification) { 788 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); 789 790 ret = amdgpu_kv_copy_bytes_to_smc(adev, 791 pi->dpm_table_start + 792 offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT), 793 (u8 *)&low_sclk_interrupt_t, 794 sizeof(u32), pi->sram_end); 795 } 796 return ret; 797 } 798 799 static int kv_program_bootup_state(struct amdgpu_device *adev) 800 { 801 struct kv_power_info *pi = kv_get_pi(adev); 802 u32 i; 803 struct amdgpu_clock_voltage_dependency_table *table = 804 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 805 806 if (table && table->count) { 807 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 808 if (table->entries[i].clk == pi->boot_pl.sclk) 809 break; 810 } 811 812 pi->graphics_boot_level = (u8)i; 813 kv_dpm_power_level_enable(adev, i, true); 814 } else { 815 struct sumo_sclk_voltage_mapping_table *table = 816 &pi->sys_info.sclk_voltage_mapping_table; 817 818 if (table->num_max_dpm_entries == 0) 819 return -EINVAL; 820 821 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 822 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) 823 break; 824 } 825 826 pi->graphics_boot_level = (u8)i; 827 kv_dpm_power_level_enable(adev, i, true); 828 } 829 return 0; 830 } 831 832 static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev) 833 { 834 struct kv_power_info *pi = kv_get_pi(adev); 835 int ret; 836 837 pi->graphics_therm_throttle_enable = 1; 838 839 ret = amdgpu_kv_copy_bytes_to_smc(adev, 840 pi->dpm_table_start + 841 offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable), 842 &pi->graphics_therm_throttle_enable, 843 sizeof(u8), pi->sram_end); 844 845 return ret; 846 } 847 848 static int kv_upload_dpm_settings(struct amdgpu_device *adev) 849 { 850 struct kv_power_info *pi = kv_get_pi(adev); 851 int ret; 852 853 ret = amdgpu_kv_copy_bytes_to_smc(adev, 854 pi->dpm_table_start + 855 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel), 856 (u8 *)&pi->graphics_level, 857 sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS, 858 pi->sram_end); 859 860 if (ret) 861 return ret; 862 863 ret = amdgpu_kv_copy_bytes_to_smc(adev, 864 pi->dpm_table_start + 865 offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount), 866 &pi->graphics_dpm_level_count, 867 sizeof(u8), pi->sram_end); 868 869 return ret; 870 } 871 872 static u32 kv_get_clock_difference(u32 a, u32 b) 873 { 874 return (a >= b) ? a - b : b - a; 875 } 876 877 static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk) 878 { 879 struct kv_power_info *pi = kv_get_pi(adev); 880 u32 value; 881 882 if (pi->caps_enable_dfs_bypass) { 883 if (kv_get_clock_difference(clk, 40000) < 200) 884 value = 3; 885 else if (kv_get_clock_difference(clk, 30000) < 200) 886 value = 2; 887 else if (kv_get_clock_difference(clk, 20000) < 200) 888 value = 7; 889 else if (kv_get_clock_difference(clk, 15000) < 200) 890 value = 6; 891 else if (kv_get_clock_difference(clk, 10000) < 200) 892 value = 8; 893 else 894 value = 0; 895 } else { 896 value = 0; 897 } 898 899 return value; 900 } 901 902 static int kv_populate_uvd_table(struct amdgpu_device *adev) 903 { 904 struct kv_power_info *pi = kv_get_pi(adev); 905 struct amdgpu_uvd_clock_voltage_dependency_table *table = 906 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 907 struct atom_clock_dividers dividers; 908 int ret; 909 u32 i; 910 911 if (table == NULL || table->count == 0) 912 return 0; 913 914 pi->uvd_level_count = 0; 915 for (i = 0; i < table->count; i++) { 916 if (pi->high_voltage_t && 917 (pi->high_voltage_t < table->entries[i].v)) 918 break; 919 920 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); 921 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); 922 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); 923 924 pi->uvd_level[i].VClkBypassCntl = 925 (u8)kv_get_clk_bypass(adev, table->entries[i].vclk); 926 pi->uvd_level[i].DClkBypassCntl = 927 (u8)kv_get_clk_bypass(adev, table->entries[i].dclk); 928 929 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 930 table->entries[i].vclk, false, ÷rs); 931 if (ret) 932 return ret; 933 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; 934 935 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 936 table->entries[i].dclk, false, ÷rs); 937 if (ret) 938 return ret; 939 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; 940 941 pi->uvd_level_count++; 942 } 943 944 ret = amdgpu_kv_copy_bytes_to_smc(adev, 945 pi->dpm_table_start + 946 offsetof(SMU7_Fusion_DpmTable, UvdLevelCount), 947 (u8 *)&pi->uvd_level_count, 948 sizeof(u8), pi->sram_end); 949 if (ret) 950 return ret; 951 952 pi->uvd_interval = 1; 953 954 ret = amdgpu_kv_copy_bytes_to_smc(adev, 955 pi->dpm_table_start + 956 offsetof(SMU7_Fusion_DpmTable, UVDInterval), 957 &pi->uvd_interval, 958 sizeof(u8), pi->sram_end); 959 if (ret) 960 return ret; 961 962 ret = amdgpu_kv_copy_bytes_to_smc(adev, 963 pi->dpm_table_start + 964 offsetof(SMU7_Fusion_DpmTable, UvdLevel), 965 (u8 *)&pi->uvd_level, 966 sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD, 967 pi->sram_end); 968 969 return ret; 970 971 } 972 973 static int kv_populate_vce_table(struct amdgpu_device *adev) 974 { 975 struct kv_power_info *pi = kv_get_pi(adev); 976 int ret; 977 u32 i; 978 struct amdgpu_vce_clock_voltage_dependency_table *table = 979 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 980 struct atom_clock_dividers dividers; 981 982 if (table == NULL || table->count == 0) 983 return 0; 984 985 pi->vce_level_count = 0; 986 for (i = 0; i < table->count; i++) { 987 if (pi->high_voltage_t && 988 pi->high_voltage_t < table->entries[i].v) 989 break; 990 991 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); 992 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 993 994 pi->vce_level[i].ClkBypassCntl = 995 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); 996 997 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 998 table->entries[i].evclk, false, ÷rs); 999 if (ret) 1000 return ret; 1001 pi->vce_level[i].Divider = (u8)dividers.post_div; 1002 1003 pi->vce_level_count++; 1004 } 1005 1006 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1007 pi->dpm_table_start + 1008 offsetof(SMU7_Fusion_DpmTable, VceLevelCount), 1009 (u8 *)&pi->vce_level_count, 1010 sizeof(u8), 1011 pi->sram_end); 1012 if (ret) 1013 return ret; 1014 1015 pi->vce_interval = 1; 1016 1017 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1018 pi->dpm_table_start + 1019 offsetof(SMU7_Fusion_DpmTable, VCEInterval), 1020 (u8 *)&pi->vce_interval, 1021 sizeof(u8), 1022 pi->sram_end); 1023 if (ret) 1024 return ret; 1025 1026 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1027 pi->dpm_table_start + 1028 offsetof(SMU7_Fusion_DpmTable, VceLevel), 1029 (u8 *)&pi->vce_level, 1030 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE, 1031 pi->sram_end); 1032 1033 return ret; 1034 } 1035 1036 static int kv_populate_samu_table(struct amdgpu_device *adev) 1037 { 1038 struct kv_power_info *pi = kv_get_pi(adev); 1039 struct amdgpu_clock_voltage_dependency_table *table = 1040 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1041 struct atom_clock_dividers dividers; 1042 int ret; 1043 u32 i; 1044 1045 if (table == NULL || table->count == 0) 1046 return 0; 1047 1048 pi->samu_level_count = 0; 1049 for (i = 0; i < table->count; i++) { 1050 if (pi->high_voltage_t && 1051 pi->high_voltage_t < table->entries[i].v) 1052 break; 1053 1054 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1055 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1056 1057 pi->samu_level[i].ClkBypassCntl = 1058 (u8)kv_get_clk_bypass(adev, table->entries[i].clk); 1059 1060 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 1061 table->entries[i].clk, false, ÷rs); 1062 if (ret) 1063 return ret; 1064 pi->samu_level[i].Divider = (u8)dividers.post_div; 1065 1066 pi->samu_level_count++; 1067 } 1068 1069 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1070 pi->dpm_table_start + 1071 offsetof(SMU7_Fusion_DpmTable, SamuLevelCount), 1072 (u8 *)&pi->samu_level_count, 1073 sizeof(u8), 1074 pi->sram_end); 1075 if (ret) 1076 return ret; 1077 1078 pi->samu_interval = 1; 1079 1080 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1081 pi->dpm_table_start + 1082 offsetof(SMU7_Fusion_DpmTable, SAMUInterval), 1083 (u8 *)&pi->samu_interval, 1084 sizeof(u8), 1085 pi->sram_end); 1086 if (ret) 1087 return ret; 1088 1089 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1090 pi->dpm_table_start + 1091 offsetof(SMU7_Fusion_DpmTable, SamuLevel), 1092 (u8 *)&pi->samu_level, 1093 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU, 1094 pi->sram_end); 1095 if (ret) 1096 return ret; 1097 1098 return ret; 1099 } 1100 1101 1102 static int kv_populate_acp_table(struct amdgpu_device *adev) 1103 { 1104 struct kv_power_info *pi = kv_get_pi(adev); 1105 struct amdgpu_clock_voltage_dependency_table *table = 1106 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1107 struct atom_clock_dividers dividers; 1108 int ret; 1109 u32 i; 1110 1111 if (table == NULL || table->count == 0) 1112 return 0; 1113 1114 pi->acp_level_count = 0; 1115 for (i = 0; i < table->count; i++) { 1116 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); 1117 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); 1118 1119 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 1120 table->entries[i].clk, false, ÷rs); 1121 if (ret) 1122 return ret; 1123 pi->acp_level[i].Divider = (u8)dividers.post_div; 1124 1125 pi->acp_level_count++; 1126 } 1127 1128 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1129 pi->dpm_table_start + 1130 offsetof(SMU7_Fusion_DpmTable, AcpLevelCount), 1131 (u8 *)&pi->acp_level_count, 1132 sizeof(u8), 1133 pi->sram_end); 1134 if (ret) 1135 return ret; 1136 1137 pi->acp_interval = 1; 1138 1139 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1140 pi->dpm_table_start + 1141 offsetof(SMU7_Fusion_DpmTable, ACPInterval), 1142 (u8 *)&pi->acp_interval, 1143 sizeof(u8), 1144 pi->sram_end); 1145 if (ret) 1146 return ret; 1147 1148 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1149 pi->dpm_table_start + 1150 offsetof(SMU7_Fusion_DpmTable, AcpLevel), 1151 (u8 *)&pi->acp_level, 1152 sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP, 1153 pi->sram_end); 1154 if (ret) 1155 return ret; 1156 1157 return ret; 1158 } 1159 1160 static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev) 1161 { 1162 struct kv_power_info *pi = kv_get_pi(adev); 1163 u32 i; 1164 struct amdgpu_clock_voltage_dependency_table *table = 1165 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1166 1167 if (table && table->count) { 1168 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1169 if (pi->caps_enable_dfs_bypass) { 1170 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200) 1171 pi->graphics_level[i].ClkBypassCntl = 3; 1172 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200) 1173 pi->graphics_level[i].ClkBypassCntl = 2; 1174 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200) 1175 pi->graphics_level[i].ClkBypassCntl = 7; 1176 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200) 1177 pi->graphics_level[i].ClkBypassCntl = 6; 1178 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200) 1179 pi->graphics_level[i].ClkBypassCntl = 8; 1180 else 1181 pi->graphics_level[i].ClkBypassCntl = 0; 1182 } else { 1183 pi->graphics_level[i].ClkBypassCntl = 0; 1184 } 1185 } 1186 } else { 1187 struct sumo_sclk_voltage_mapping_table *table = 1188 &pi->sys_info.sclk_voltage_mapping_table; 1189 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1190 if (pi->caps_enable_dfs_bypass) { 1191 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) 1192 pi->graphics_level[i].ClkBypassCntl = 3; 1193 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) 1194 pi->graphics_level[i].ClkBypassCntl = 2; 1195 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) 1196 pi->graphics_level[i].ClkBypassCntl = 7; 1197 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) 1198 pi->graphics_level[i].ClkBypassCntl = 6; 1199 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) 1200 pi->graphics_level[i].ClkBypassCntl = 8; 1201 else 1202 pi->graphics_level[i].ClkBypassCntl = 0; 1203 } else { 1204 pi->graphics_level[i].ClkBypassCntl = 0; 1205 } 1206 } 1207 } 1208 } 1209 1210 static int kv_enable_ulv(struct amdgpu_device *adev, bool enable) 1211 { 1212 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1213 PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV); 1214 } 1215 1216 static void kv_reset_acp_boot_level(struct amdgpu_device *adev) 1217 { 1218 struct kv_power_info *pi = kv_get_pi(adev); 1219 1220 pi->acp_boot_level = 0xff; 1221 } 1222 1223 static void kv_update_current_ps(struct amdgpu_device *adev, 1224 struct amdgpu_ps *rps) 1225 { 1226 struct kv_ps *new_ps = kv_get_ps(rps); 1227 struct kv_power_info *pi = kv_get_pi(adev); 1228 1229 pi->current_rps = *rps; 1230 pi->current_ps = *new_ps; 1231 pi->current_rps.ps_priv = &pi->current_ps; 1232 adev->pm.dpm.current_ps = &pi->current_rps; 1233 } 1234 1235 static void kv_update_requested_ps(struct amdgpu_device *adev, 1236 struct amdgpu_ps *rps) 1237 { 1238 struct kv_ps *new_ps = kv_get_ps(rps); 1239 struct kv_power_info *pi = kv_get_pi(adev); 1240 1241 pi->requested_rps = *rps; 1242 pi->requested_ps = *new_ps; 1243 pi->requested_rps.ps_priv = &pi->requested_ps; 1244 adev->pm.dpm.requested_ps = &pi->requested_rps; 1245 } 1246 1247 static void kv_dpm_enable_bapm(void *handle, bool enable) 1248 { 1249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1250 struct kv_power_info *pi = kv_get_pi(adev); 1251 int ret; 1252 1253 if (pi->bapm_enable) { 1254 ret = amdgpu_kv_smc_bapm_enable(adev, enable); 1255 if (ret) 1256 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1257 } 1258 } 1259 1260 static bool kv_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor) 1261 { 1262 switch (sensor) { 1263 case THERMAL_TYPE_KV: 1264 return true; 1265 case THERMAL_TYPE_NONE: 1266 case THERMAL_TYPE_EXTERNAL: 1267 case THERMAL_TYPE_EXTERNAL_GPIO: 1268 default: 1269 return false; 1270 } 1271 } 1272 1273 static int kv_dpm_enable(struct amdgpu_device *adev) 1274 { 1275 struct kv_power_info *pi = kv_get_pi(adev); 1276 int ret; 1277 1278 ret = kv_process_firmware_header(adev); 1279 if (ret) { 1280 DRM_ERROR("kv_process_firmware_header failed\n"); 1281 return ret; 1282 } 1283 kv_init_fps_limits(adev); 1284 kv_init_graphics_levels(adev); 1285 ret = kv_program_bootup_state(adev); 1286 if (ret) { 1287 DRM_ERROR("kv_program_bootup_state failed\n"); 1288 return ret; 1289 } 1290 kv_calculate_dfs_bypass_settings(adev); 1291 ret = kv_upload_dpm_settings(adev); 1292 if (ret) { 1293 DRM_ERROR("kv_upload_dpm_settings failed\n"); 1294 return ret; 1295 } 1296 ret = kv_populate_uvd_table(adev); 1297 if (ret) { 1298 DRM_ERROR("kv_populate_uvd_table failed\n"); 1299 return ret; 1300 } 1301 ret = kv_populate_vce_table(adev); 1302 if (ret) { 1303 DRM_ERROR("kv_populate_vce_table failed\n"); 1304 return ret; 1305 } 1306 ret = kv_populate_samu_table(adev); 1307 if (ret) { 1308 DRM_ERROR("kv_populate_samu_table failed\n"); 1309 return ret; 1310 } 1311 ret = kv_populate_acp_table(adev); 1312 if (ret) { 1313 DRM_ERROR("kv_populate_acp_table failed\n"); 1314 return ret; 1315 } 1316 kv_program_vc(adev); 1317 #if 0 1318 kv_initialize_hardware_cac_manager(adev); 1319 #endif 1320 kv_start_am(adev); 1321 if (pi->enable_auto_thermal_throttling) { 1322 ret = kv_enable_auto_thermal_throttling(adev); 1323 if (ret) { 1324 DRM_ERROR("kv_enable_auto_thermal_throttling failed\n"); 1325 return ret; 1326 } 1327 } 1328 ret = kv_enable_dpm_voltage_scaling(adev); 1329 if (ret) { 1330 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n"); 1331 return ret; 1332 } 1333 ret = kv_set_dpm_interval(adev); 1334 if (ret) { 1335 DRM_ERROR("kv_set_dpm_interval failed\n"); 1336 return ret; 1337 } 1338 ret = kv_set_dpm_boot_state(adev); 1339 if (ret) { 1340 DRM_ERROR("kv_set_dpm_boot_state failed\n"); 1341 return ret; 1342 } 1343 ret = kv_enable_ulv(adev, true); 1344 if (ret) { 1345 DRM_ERROR("kv_enable_ulv failed\n"); 1346 return ret; 1347 } 1348 kv_start_dpm(adev); 1349 ret = kv_enable_didt(adev, true); 1350 if (ret) { 1351 DRM_ERROR("kv_enable_didt failed\n"); 1352 return ret; 1353 } 1354 ret = kv_enable_smc_cac(adev, true); 1355 if (ret) { 1356 DRM_ERROR("kv_enable_smc_cac failed\n"); 1357 return ret; 1358 } 1359 1360 kv_reset_acp_boot_level(adev); 1361 1362 ret = amdgpu_kv_smc_bapm_enable(adev, false); 1363 if (ret) { 1364 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1365 return ret; 1366 } 1367 1368 if (adev->irq.installed && 1369 kv_is_internal_thermal_sensor(adev->pm.int_thermal_type)) { 1370 ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX); 1371 if (ret) { 1372 DRM_ERROR("kv_set_thermal_temperature_range failed\n"); 1373 return ret; 1374 } 1375 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, 1376 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); 1377 amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq, 1378 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); 1379 } 1380 1381 return ret; 1382 } 1383 1384 static void kv_dpm_disable(struct amdgpu_device *adev) 1385 { 1386 struct kv_power_info *pi = kv_get_pi(adev); 1387 int err; 1388 1389 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, 1390 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH); 1391 amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq, 1392 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW); 1393 1394 err = amdgpu_kv_smc_bapm_enable(adev, false); 1395 if (err) 1396 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1397 1398 if (adev->asic_type == CHIP_MULLINS) 1399 kv_enable_nb_dpm(adev, false); 1400 1401 /* powerup blocks */ 1402 kv_dpm_powergate_acp(adev, false); 1403 kv_dpm_powergate_samu(adev, false); 1404 if (pi->caps_vce_pg) /* power on the VCE block */ 1405 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1406 if (pi->caps_uvd_pg) /* power on the UVD block */ 1407 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1408 1409 kv_enable_smc_cac(adev, false); 1410 kv_enable_didt(adev, false); 1411 kv_clear_vc(adev); 1412 kv_stop_dpm(adev); 1413 kv_enable_ulv(adev, false); 1414 kv_reset_am(adev); 1415 1416 kv_update_current_ps(adev, adev->pm.dpm.boot_ps); 1417 } 1418 1419 #if 0 1420 static int kv_write_smc_soft_register(struct amdgpu_device *adev, 1421 u16 reg_offset, u32 value) 1422 { 1423 struct kv_power_info *pi = kv_get_pi(adev); 1424 1425 return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset, 1426 (u8 *)&value, sizeof(u16), pi->sram_end); 1427 } 1428 1429 static int kv_read_smc_soft_register(struct amdgpu_device *adev, 1430 u16 reg_offset, u32 *value) 1431 { 1432 struct kv_power_info *pi = kv_get_pi(adev); 1433 1434 return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset, 1435 value, pi->sram_end); 1436 } 1437 #endif 1438 1439 static void kv_init_sclk_t(struct amdgpu_device *adev) 1440 { 1441 struct kv_power_info *pi = kv_get_pi(adev); 1442 1443 pi->low_sclk_interrupt_t = 0; 1444 } 1445 1446 static int kv_init_fps_limits(struct amdgpu_device *adev) 1447 { 1448 struct kv_power_info *pi = kv_get_pi(adev); 1449 int ret = 0; 1450 1451 if (pi->caps_fps) { 1452 u16 tmp; 1453 1454 tmp = 45; 1455 pi->fps_high_t = cpu_to_be16(tmp); 1456 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1457 pi->dpm_table_start + 1458 offsetof(SMU7_Fusion_DpmTable, FpsHighT), 1459 (u8 *)&pi->fps_high_t, 1460 sizeof(u16), pi->sram_end); 1461 1462 tmp = 30; 1463 pi->fps_low_t = cpu_to_be16(tmp); 1464 1465 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1466 pi->dpm_table_start + 1467 offsetof(SMU7_Fusion_DpmTable, FpsLowT), 1468 (u8 *)&pi->fps_low_t, 1469 sizeof(u16), pi->sram_end); 1470 1471 } 1472 return ret; 1473 } 1474 1475 static void kv_init_powergate_state(struct amdgpu_device *adev) 1476 { 1477 struct kv_power_info *pi = kv_get_pi(adev); 1478 1479 pi->uvd_power_gated = false; 1480 pi->vce_power_gated = false; 1481 pi->samu_power_gated = false; 1482 pi->acp_power_gated = false; 1483 1484 } 1485 1486 static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable) 1487 { 1488 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1489 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); 1490 } 1491 1492 static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable) 1493 { 1494 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1495 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); 1496 } 1497 1498 static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable) 1499 { 1500 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1501 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); 1502 } 1503 1504 static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable) 1505 { 1506 return amdgpu_kv_notify_message_to_smu(adev, enable ? 1507 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable); 1508 } 1509 1510 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) 1511 { 1512 struct kv_power_info *pi = kv_get_pi(adev); 1513 struct amdgpu_uvd_clock_voltage_dependency_table *table = 1514 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 1515 int ret; 1516 u32 mask; 1517 1518 if (!gate) { 1519 if (table->count) 1520 pi->uvd_boot_level = table->count - 1; 1521 else 1522 pi->uvd_boot_level = 0; 1523 1524 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { 1525 mask = 1 << pi->uvd_boot_level; 1526 } else { 1527 mask = 0x1f; 1528 } 1529 1530 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1531 pi->dpm_table_start + 1532 offsetof(SMU7_Fusion_DpmTable, UvdBootLevel), 1533 (uint8_t *)&pi->uvd_boot_level, 1534 sizeof(u8), pi->sram_end); 1535 if (ret) 1536 return ret; 1537 1538 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1539 PPSMC_MSG_UVDDPM_SetEnabledMask, 1540 mask); 1541 } 1542 1543 return kv_enable_uvd_dpm(adev, !gate); 1544 } 1545 1546 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) 1547 { 1548 u8 i; 1549 struct amdgpu_vce_clock_voltage_dependency_table *table = 1550 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1551 1552 for (i = 0; i < table->count; i++) { 1553 if (table->entries[i].evclk >= evclk) 1554 break; 1555 } 1556 1557 return i; 1558 } 1559 1560 static int kv_update_vce_dpm(struct amdgpu_device *adev, 1561 struct amdgpu_ps *amdgpu_new_state, 1562 struct amdgpu_ps *amdgpu_current_state) 1563 { 1564 struct kv_power_info *pi = kv_get_pi(adev); 1565 struct amdgpu_vce_clock_voltage_dependency_table *table = 1566 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 1567 int ret; 1568 1569 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { 1570 if (pi->caps_stable_p_state) 1571 pi->vce_boot_level = table->count - 1; 1572 else 1573 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); 1574 1575 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1576 pi->dpm_table_start + 1577 offsetof(SMU7_Fusion_DpmTable, VceBootLevel), 1578 (u8 *)&pi->vce_boot_level, 1579 sizeof(u8), 1580 pi->sram_end); 1581 if (ret) 1582 return ret; 1583 1584 if (pi->caps_stable_p_state) 1585 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1586 PPSMC_MSG_VCEDPM_SetEnabledMask, 1587 (1 << pi->vce_boot_level)); 1588 kv_enable_vce_dpm(adev, true); 1589 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { 1590 kv_enable_vce_dpm(adev, false); 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) 1597 { 1598 struct kv_power_info *pi = kv_get_pi(adev); 1599 struct amdgpu_clock_voltage_dependency_table *table = 1600 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 1601 int ret; 1602 1603 if (!gate) { 1604 if (pi->caps_stable_p_state) 1605 pi->samu_boot_level = table->count - 1; 1606 else 1607 pi->samu_boot_level = 0; 1608 1609 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1610 pi->dpm_table_start + 1611 offsetof(SMU7_Fusion_DpmTable, SamuBootLevel), 1612 (u8 *)&pi->samu_boot_level, 1613 sizeof(u8), 1614 pi->sram_end); 1615 if (ret) 1616 return ret; 1617 1618 if (pi->caps_stable_p_state) 1619 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1620 PPSMC_MSG_SAMUDPM_SetEnabledMask, 1621 (1 << pi->samu_boot_level)); 1622 } 1623 1624 return kv_enable_samu_dpm(adev, !gate); 1625 } 1626 1627 static u8 kv_get_acp_boot_level(struct amdgpu_device *adev) 1628 { 1629 return 0; 1630 } 1631 1632 static void kv_update_acp_boot_level(struct amdgpu_device *adev) 1633 { 1634 struct kv_power_info *pi = kv_get_pi(adev); 1635 u8 acp_boot_level; 1636 1637 if (!pi->caps_stable_p_state) { 1638 acp_boot_level = kv_get_acp_boot_level(adev); 1639 if (acp_boot_level != pi->acp_boot_level) { 1640 pi->acp_boot_level = acp_boot_level; 1641 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1642 PPSMC_MSG_ACPDPM_SetEnabledMask, 1643 (1 << pi->acp_boot_level)); 1644 } 1645 } 1646 } 1647 1648 static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate) 1649 { 1650 struct kv_power_info *pi = kv_get_pi(adev); 1651 struct amdgpu_clock_voltage_dependency_table *table = 1652 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 1653 int ret; 1654 1655 if (!gate) { 1656 if (pi->caps_stable_p_state) 1657 pi->acp_boot_level = table->count - 1; 1658 else 1659 pi->acp_boot_level = kv_get_acp_boot_level(adev); 1660 1661 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1662 pi->dpm_table_start + 1663 offsetof(SMU7_Fusion_DpmTable, AcpBootLevel), 1664 (u8 *)&pi->acp_boot_level, 1665 sizeof(u8), 1666 pi->sram_end); 1667 if (ret) 1668 return ret; 1669 1670 if (pi->caps_stable_p_state) 1671 amdgpu_kv_send_msg_to_smc_with_parameter(adev, 1672 PPSMC_MSG_ACPDPM_SetEnabledMask, 1673 (1 << pi->acp_boot_level)); 1674 } 1675 1676 return kv_enable_acp_dpm(adev, !gate); 1677 } 1678 1679 static void kv_dpm_powergate_uvd(void *handle, bool gate) 1680 { 1681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1682 struct kv_power_info *pi = kv_get_pi(adev); 1683 1684 pi->uvd_power_gated = gate; 1685 1686 if (gate) { 1687 /* stop the UVD block */ 1688 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1689 AMD_PG_STATE_GATE); 1690 kv_update_uvd_dpm(adev, gate); 1691 if (pi->caps_uvd_pg) 1692 /* power off the UVD block */ 1693 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF); 1694 } else { 1695 if (pi->caps_uvd_pg) 1696 /* power on the UVD block */ 1697 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON); 1698 /* re-init the UVD block */ 1699 kv_update_uvd_dpm(adev, gate); 1700 1701 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1702 AMD_PG_STATE_UNGATE); 1703 } 1704 } 1705 1706 static void kv_dpm_powergate_vce(void *handle, bool gate) 1707 { 1708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1709 struct kv_power_info *pi = kv_get_pi(adev); 1710 1711 pi->vce_power_gated = gate; 1712 1713 if (gate) { 1714 /* stop the VCE block */ 1715 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1716 AMD_PG_STATE_GATE); 1717 kv_enable_vce_dpm(adev, false); 1718 if (pi->caps_vce_pg) /* power off the VCE block */ 1719 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF); 1720 } else { 1721 if (pi->caps_vce_pg) /* power on the VCE block */ 1722 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON); 1723 kv_enable_vce_dpm(adev, true); 1724 /* re-init the VCE block */ 1725 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1726 AMD_PG_STATE_UNGATE); 1727 } 1728 } 1729 1730 1731 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate) 1732 { 1733 struct kv_power_info *pi = kv_get_pi(adev); 1734 1735 if (pi->samu_power_gated == gate) 1736 return; 1737 1738 pi->samu_power_gated = gate; 1739 1740 if (gate) { 1741 kv_update_samu_dpm(adev, true); 1742 if (pi->caps_samu_pg) 1743 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF); 1744 } else { 1745 if (pi->caps_samu_pg) 1746 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON); 1747 kv_update_samu_dpm(adev, false); 1748 } 1749 } 1750 1751 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate) 1752 { 1753 struct kv_power_info *pi = kv_get_pi(adev); 1754 1755 if (pi->acp_power_gated == gate) 1756 return; 1757 1758 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 1759 return; 1760 1761 pi->acp_power_gated = gate; 1762 1763 if (gate) { 1764 kv_update_acp_dpm(adev, true); 1765 if (pi->caps_acp_pg) 1766 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF); 1767 } else { 1768 if (pi->caps_acp_pg) 1769 amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON); 1770 kv_update_acp_dpm(adev, false); 1771 } 1772 } 1773 1774 static void kv_set_valid_clock_range(struct amdgpu_device *adev, 1775 struct amdgpu_ps *new_rps) 1776 { 1777 struct kv_ps *new_ps = kv_get_ps(new_rps); 1778 struct kv_power_info *pi = kv_get_pi(adev); 1779 u32 i; 1780 struct amdgpu_clock_voltage_dependency_table *table = 1781 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 1782 1783 if (table && table->count) { 1784 for (i = 0; i < pi->graphics_dpm_level_count; i++) { 1785 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || 1786 (i == (pi->graphics_dpm_level_count - 1))) { 1787 pi->lowest_valid = i; 1788 break; 1789 } 1790 } 1791 1792 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1793 if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) 1794 break; 1795 } 1796 pi->highest_valid = i; 1797 1798 if (pi->lowest_valid > pi->highest_valid) { 1799 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > 1800 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) 1801 pi->highest_valid = pi->lowest_valid; 1802 else 1803 pi->lowest_valid = pi->highest_valid; 1804 } 1805 } else { 1806 struct sumo_sclk_voltage_mapping_table *table = 1807 &pi->sys_info.sclk_voltage_mapping_table; 1808 1809 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { 1810 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || 1811 i == (int)(pi->graphics_dpm_level_count - 1)) { 1812 pi->lowest_valid = i; 1813 break; 1814 } 1815 } 1816 1817 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { 1818 if (table->entries[i].sclk_frequency <= 1819 new_ps->levels[new_ps->num_levels - 1].sclk) 1820 break; 1821 } 1822 pi->highest_valid = i; 1823 1824 if (pi->lowest_valid > pi->highest_valid) { 1825 if ((new_ps->levels[0].sclk - 1826 table->entries[pi->highest_valid].sclk_frequency) > 1827 (table->entries[pi->lowest_valid].sclk_frequency - 1828 new_ps->levels[new_ps->num_levels -1].sclk)) 1829 pi->highest_valid = pi->lowest_valid; 1830 else 1831 pi->lowest_valid = pi->highest_valid; 1832 } 1833 } 1834 } 1835 1836 static int kv_update_dfs_bypass_settings(struct amdgpu_device *adev, 1837 struct amdgpu_ps *new_rps) 1838 { 1839 struct kv_ps *new_ps = kv_get_ps(new_rps); 1840 struct kv_power_info *pi = kv_get_pi(adev); 1841 int ret = 0; 1842 u8 clk_bypass_cntl; 1843 1844 if (pi->caps_enable_dfs_bypass) { 1845 clk_bypass_cntl = new_ps->need_dfs_bypass ? 1846 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; 1847 ret = amdgpu_kv_copy_bytes_to_smc(adev, 1848 (pi->dpm_table_start + 1849 offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) + 1850 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + 1851 offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)), 1852 &clk_bypass_cntl, 1853 sizeof(u8), pi->sram_end); 1854 } 1855 1856 return ret; 1857 } 1858 1859 static int kv_enable_nb_dpm(struct amdgpu_device *adev, 1860 bool enable) 1861 { 1862 struct kv_power_info *pi = kv_get_pi(adev); 1863 int ret = 0; 1864 1865 if (enable) { 1866 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { 1867 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Enable); 1868 if (ret == 0) 1869 pi->nb_dpm_enabled = true; 1870 } 1871 } else { 1872 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { 1873 ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NBDPM_Disable); 1874 if (ret == 0) 1875 pi->nb_dpm_enabled = false; 1876 } 1877 } 1878 1879 return ret; 1880 } 1881 1882 static int kv_dpm_force_performance_level(void *handle, 1883 enum amd_dpm_forced_level level) 1884 { 1885 int ret; 1886 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1887 1888 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 1889 ret = kv_force_dpm_highest(adev); 1890 if (ret) 1891 return ret; 1892 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 1893 ret = kv_force_dpm_lowest(adev); 1894 if (ret) 1895 return ret; 1896 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 1897 ret = kv_unforce_levels(adev); 1898 if (ret) 1899 return ret; 1900 } 1901 1902 adev->pm.dpm.forced_level = level; 1903 1904 return 0; 1905 } 1906 1907 static int kv_dpm_pre_set_power_state(void *handle) 1908 { 1909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1910 struct kv_power_info *pi = kv_get_pi(adev); 1911 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 1912 struct amdgpu_ps *new_ps = &requested_ps; 1913 1914 kv_update_requested_ps(adev, new_ps); 1915 1916 kv_apply_state_adjust_rules(adev, 1917 &pi->requested_rps, 1918 &pi->current_rps); 1919 1920 return 0; 1921 } 1922 1923 static int kv_dpm_set_power_state(void *handle) 1924 { 1925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1926 struct kv_power_info *pi = kv_get_pi(adev); 1927 struct amdgpu_ps *new_ps = &pi->requested_rps; 1928 struct amdgpu_ps *old_ps = &pi->current_rps; 1929 int ret; 1930 1931 if (pi->bapm_enable) { 1932 ret = amdgpu_kv_smc_bapm_enable(adev, adev->pm.ac_power); 1933 if (ret) { 1934 DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n"); 1935 return ret; 1936 } 1937 } 1938 1939 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 1940 if (pi->enable_dpm) { 1941 kv_set_valid_clock_range(adev, new_ps); 1942 kv_update_dfs_bypass_settings(adev, new_ps); 1943 ret = kv_calculate_ds_divider(adev); 1944 if (ret) { 1945 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1946 return ret; 1947 } 1948 kv_calculate_nbps_level_settings(adev); 1949 kv_calculate_dpm_settings(adev); 1950 kv_force_lowest_valid(adev); 1951 kv_enable_new_levels(adev); 1952 kv_upload_dpm_settings(adev); 1953 kv_program_nbps_index_settings(adev, new_ps); 1954 kv_unforce_levels(adev); 1955 kv_set_enabled_levels(adev); 1956 kv_force_lowest_valid(adev); 1957 kv_unforce_levels(adev); 1958 1959 ret = kv_update_vce_dpm(adev, new_ps, old_ps); 1960 if (ret) { 1961 DRM_ERROR("kv_update_vce_dpm failed\n"); 1962 return ret; 1963 } 1964 kv_update_sclk_t(adev); 1965 if (adev->asic_type == CHIP_MULLINS) 1966 kv_enable_nb_dpm(adev, true); 1967 } 1968 } else { 1969 if (pi->enable_dpm) { 1970 kv_set_valid_clock_range(adev, new_ps); 1971 kv_update_dfs_bypass_settings(adev, new_ps); 1972 ret = kv_calculate_ds_divider(adev); 1973 if (ret) { 1974 DRM_ERROR("kv_calculate_ds_divider failed\n"); 1975 return ret; 1976 } 1977 kv_calculate_nbps_level_settings(adev); 1978 kv_calculate_dpm_settings(adev); 1979 kv_freeze_sclk_dpm(adev, true); 1980 kv_upload_dpm_settings(adev); 1981 kv_program_nbps_index_settings(adev, new_ps); 1982 kv_freeze_sclk_dpm(adev, false); 1983 kv_set_enabled_levels(adev); 1984 ret = kv_update_vce_dpm(adev, new_ps, old_ps); 1985 if (ret) { 1986 DRM_ERROR("kv_update_vce_dpm failed\n"); 1987 return ret; 1988 } 1989 kv_update_acp_boot_level(adev); 1990 kv_update_sclk_t(adev); 1991 kv_enable_nb_dpm(adev, true); 1992 } 1993 } 1994 1995 return 0; 1996 } 1997 1998 static void kv_dpm_post_set_power_state(void *handle) 1999 { 2000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2001 struct kv_power_info *pi = kv_get_pi(adev); 2002 struct amdgpu_ps *new_ps = &pi->requested_rps; 2003 2004 kv_update_current_ps(adev, new_ps); 2005 } 2006 2007 static void kv_dpm_setup_asic(struct amdgpu_device *adev) 2008 { 2009 sumo_take_smu_control(adev, true); 2010 kv_init_powergate_state(adev); 2011 kv_init_sclk_t(adev); 2012 } 2013 2014 #if 0 2015 static void kv_dpm_reset_asic(struct amdgpu_device *adev) 2016 { 2017 struct kv_power_info *pi = kv_get_pi(adev); 2018 2019 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 2020 kv_force_lowest_valid(adev); 2021 kv_init_graphics_levels(adev); 2022 kv_program_bootup_state(adev); 2023 kv_upload_dpm_settings(adev); 2024 kv_force_lowest_valid(adev); 2025 kv_unforce_levels(adev); 2026 } else { 2027 kv_init_graphics_levels(adev); 2028 kv_program_bootup_state(adev); 2029 kv_freeze_sclk_dpm(adev, true); 2030 kv_upload_dpm_settings(adev); 2031 kv_freeze_sclk_dpm(adev, false); 2032 kv_set_enabled_level(adev, pi->graphics_boot_level); 2033 } 2034 } 2035 #endif 2036 2037 static void kv_construct_max_power_limits_table(struct amdgpu_device *adev, 2038 struct amdgpu_clock_and_voltage_limits *table) 2039 { 2040 struct kv_power_info *pi = kv_get_pi(adev); 2041 2042 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { 2043 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; 2044 table->sclk = 2045 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; 2046 table->vddc = 2047 kv_convert_2bit_index_to_voltage(adev, 2048 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); 2049 } 2050 2051 table->mclk = pi->sys_info.nbp_memory_clock[0]; 2052 } 2053 2054 static void kv_patch_voltage_values(struct amdgpu_device *adev) 2055 { 2056 int i; 2057 struct amdgpu_uvd_clock_voltage_dependency_table *uvd_table = 2058 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; 2059 struct amdgpu_vce_clock_voltage_dependency_table *vce_table = 2060 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2061 struct amdgpu_clock_voltage_dependency_table *samu_table = 2062 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; 2063 struct amdgpu_clock_voltage_dependency_table *acp_table = 2064 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; 2065 2066 if (uvd_table->count) { 2067 for (i = 0; i < uvd_table->count; i++) 2068 uvd_table->entries[i].v = 2069 kv_convert_8bit_index_to_voltage(adev, 2070 uvd_table->entries[i].v); 2071 } 2072 2073 if (vce_table->count) { 2074 for (i = 0; i < vce_table->count; i++) 2075 vce_table->entries[i].v = 2076 kv_convert_8bit_index_to_voltage(adev, 2077 vce_table->entries[i].v); 2078 } 2079 2080 if (samu_table->count) { 2081 for (i = 0; i < samu_table->count; i++) 2082 samu_table->entries[i].v = 2083 kv_convert_8bit_index_to_voltage(adev, 2084 samu_table->entries[i].v); 2085 } 2086 2087 if (acp_table->count) { 2088 for (i = 0; i < acp_table->count; i++) 2089 acp_table->entries[i].v = 2090 kv_convert_8bit_index_to_voltage(adev, 2091 acp_table->entries[i].v); 2092 } 2093 2094 } 2095 2096 static void kv_construct_boot_state(struct amdgpu_device *adev) 2097 { 2098 struct kv_power_info *pi = kv_get_pi(adev); 2099 2100 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; 2101 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; 2102 pi->boot_pl.ds_divider_index = 0; 2103 pi->boot_pl.ss_divider_index = 0; 2104 pi->boot_pl.allow_gnb_slow = 1; 2105 pi->boot_pl.force_nbp_state = 0; 2106 pi->boot_pl.display_wm = 0; 2107 pi->boot_pl.vce_wm = 0; 2108 } 2109 2110 static int kv_force_dpm_highest(struct amdgpu_device *adev) 2111 { 2112 int ret; 2113 u32 enable_mask, i; 2114 2115 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); 2116 if (ret) 2117 return ret; 2118 2119 for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) { 2120 if (enable_mask & (1 << i)) 2121 break; 2122 } 2123 2124 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 2125 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); 2126 else 2127 return kv_set_enabled_level(adev, i); 2128 } 2129 2130 static int kv_force_dpm_lowest(struct amdgpu_device *adev) 2131 { 2132 int ret; 2133 u32 enable_mask, i; 2134 2135 ret = amdgpu_kv_dpm_get_enable_mask(adev, &enable_mask); 2136 if (ret) 2137 return ret; 2138 2139 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2140 if (enable_mask & (1 << i)) 2141 break; 2142 } 2143 2144 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 2145 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_DPM_ForceState, i); 2146 else 2147 return kv_set_enabled_level(adev, i); 2148 } 2149 2150 static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev, 2151 u32 sclk, u32 min_sclk_in_sr) 2152 { 2153 struct kv_power_info *pi = kv_get_pi(adev); 2154 u32 i; 2155 u32 temp; 2156 u32 min = max(min_sclk_in_sr, (u32)KV_MINIMUM_ENGINE_CLOCK); 2157 2158 if (sclk < min) 2159 return 0; 2160 2161 if (!pi->caps_sclk_ds) 2162 return 0; 2163 2164 for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) { 2165 temp = sclk >> i; 2166 if (temp >= min) 2167 break; 2168 } 2169 2170 return (u8)i; 2171 } 2172 2173 static int kv_get_high_voltage_limit(struct amdgpu_device *adev, int *limit) 2174 { 2175 struct kv_power_info *pi = kv_get_pi(adev); 2176 struct amdgpu_clock_voltage_dependency_table *table = 2177 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2178 int i; 2179 2180 if (table && table->count) { 2181 for (i = table->count - 1; i >= 0; i--) { 2182 if (pi->high_voltage_t && 2183 (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <= 2184 pi->high_voltage_t)) { 2185 *limit = i; 2186 return 0; 2187 } 2188 } 2189 } else { 2190 struct sumo_sclk_voltage_mapping_table *table = 2191 &pi->sys_info.sclk_voltage_mapping_table; 2192 2193 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) { 2194 if (pi->high_voltage_t && 2195 (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <= 2196 pi->high_voltage_t)) { 2197 *limit = i; 2198 return 0; 2199 } 2200 } 2201 } 2202 2203 *limit = 0; 2204 return 0; 2205 } 2206 2207 static void kv_apply_state_adjust_rules(struct amdgpu_device *adev, 2208 struct amdgpu_ps *new_rps, 2209 struct amdgpu_ps *old_rps) 2210 { 2211 struct kv_ps *ps = kv_get_ps(new_rps); 2212 struct kv_power_info *pi = kv_get_pi(adev); 2213 u32 min_sclk = 10000; /* ??? */ 2214 u32 sclk, mclk = 0; 2215 int i, limit; 2216 bool force_high; 2217 struct amdgpu_clock_voltage_dependency_table *table = 2218 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2219 u32 stable_p_state_sclk = 0; 2220 struct amdgpu_clock_and_voltage_limits *max_limits = 2221 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2222 2223 if (new_rps->vce_active) { 2224 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 2225 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 2226 } else { 2227 new_rps->evclk = 0; 2228 new_rps->ecclk = 0; 2229 } 2230 2231 mclk = max_limits->mclk; 2232 sclk = min_sclk; 2233 2234 if (pi->caps_stable_p_state) { 2235 stable_p_state_sclk = (max_limits->sclk * 75) / 100; 2236 2237 for (i = table->count - 1; i >= 0; i--) { 2238 if (stable_p_state_sclk >= table->entries[i].clk) { 2239 stable_p_state_sclk = table->entries[i].clk; 2240 break; 2241 } 2242 } 2243 2244 if (i > 0) 2245 stable_p_state_sclk = table->entries[0].clk; 2246 2247 sclk = stable_p_state_sclk; 2248 } 2249 2250 if (new_rps->vce_active) { 2251 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 2252 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 2253 } 2254 2255 ps->need_dfs_bypass = true; 2256 2257 for (i = 0; i < ps->num_levels; i++) { 2258 if (ps->levels[i].sclk < sclk) 2259 ps->levels[i].sclk = sclk; 2260 } 2261 2262 if (table && table->count) { 2263 for (i = 0; i < ps->num_levels; i++) { 2264 if (pi->high_voltage_t && 2265 (pi->high_voltage_t < 2266 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { 2267 kv_get_high_voltage_limit(adev, &limit); 2268 ps->levels[i].sclk = table->entries[limit].clk; 2269 } 2270 } 2271 } else { 2272 struct sumo_sclk_voltage_mapping_table *table = 2273 &pi->sys_info.sclk_voltage_mapping_table; 2274 2275 for (i = 0; i < ps->num_levels; i++) { 2276 if (pi->high_voltage_t && 2277 (pi->high_voltage_t < 2278 kv_convert_8bit_index_to_voltage(adev, ps->levels[i].vddc_index))) { 2279 kv_get_high_voltage_limit(adev, &limit); 2280 ps->levels[i].sclk = table->entries[limit].sclk_frequency; 2281 } 2282 } 2283 } 2284 2285 if (pi->caps_stable_p_state) { 2286 for (i = 0; i < ps->num_levels; i++) { 2287 ps->levels[i].sclk = stable_p_state_sclk; 2288 } 2289 } 2290 2291 pi->video_start = new_rps->dclk || new_rps->vclk || 2292 new_rps->evclk || new_rps->ecclk; 2293 2294 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2295 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 2296 pi->battery_state = true; 2297 else 2298 pi->battery_state = false; 2299 2300 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 2301 ps->dpm0_pg_nb_ps_lo = 0x1; 2302 ps->dpm0_pg_nb_ps_hi = 0x0; 2303 ps->dpmx_nb_ps_lo = 0x1; 2304 ps->dpmx_nb_ps_hi = 0x0; 2305 } else { 2306 ps->dpm0_pg_nb_ps_lo = 0x3; 2307 ps->dpm0_pg_nb_ps_hi = 0x0; 2308 ps->dpmx_nb_ps_lo = 0x3; 2309 ps->dpmx_nb_ps_hi = 0x0; 2310 2311 if (pi->sys_info.nb_dpm_enable) { 2312 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || 2313 pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) || 2314 pi->disable_nb_ps3_in_battery; 2315 ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3; 2316 ps->dpm0_pg_nb_ps_hi = 0x2; 2317 ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3; 2318 ps->dpmx_nb_ps_hi = 0x2; 2319 } 2320 } 2321 } 2322 2323 static void kv_dpm_power_level_enabled_for_throttle(struct amdgpu_device *adev, 2324 u32 index, bool enable) 2325 { 2326 struct kv_power_info *pi = kv_get_pi(adev); 2327 2328 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; 2329 } 2330 2331 static int kv_calculate_ds_divider(struct amdgpu_device *adev) 2332 { 2333 struct kv_power_info *pi = kv_get_pi(adev); 2334 u32 sclk_in_sr = 10000; /* ??? */ 2335 u32 i; 2336 2337 if (pi->lowest_valid > pi->highest_valid) 2338 return -EINVAL; 2339 2340 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2341 pi->graphics_level[i].DeepSleepDivId = 2342 kv_get_sleep_divider_id_from_clock(adev, 2343 be32_to_cpu(pi->graphics_level[i].SclkFrequency), 2344 sclk_in_sr); 2345 } 2346 return 0; 2347 } 2348 2349 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev) 2350 { 2351 struct kv_power_info *pi = kv_get_pi(adev); 2352 u32 i; 2353 bool force_high; 2354 struct amdgpu_clock_and_voltage_limits *max_limits = 2355 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2356 u32 mclk = max_limits->mclk; 2357 2358 if (pi->lowest_valid > pi->highest_valid) 2359 return -EINVAL; 2360 2361 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { 2362 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2363 pi->graphics_level[i].GnbSlow = 1; 2364 pi->graphics_level[i].ForceNbPs1 = 0; 2365 pi->graphics_level[i].UpH = 0; 2366 } 2367 2368 if (!pi->sys_info.nb_dpm_enable) 2369 return 0; 2370 2371 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || 2372 (adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); 2373 2374 if (force_high) { 2375 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2376 pi->graphics_level[i].GnbSlow = 0; 2377 } else { 2378 if (pi->battery_state) 2379 pi->graphics_level[0].ForceNbPs1 = 1; 2380 2381 pi->graphics_level[1].GnbSlow = 0; 2382 pi->graphics_level[2].GnbSlow = 0; 2383 pi->graphics_level[3].GnbSlow = 0; 2384 pi->graphics_level[4].GnbSlow = 0; 2385 } 2386 } else { 2387 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { 2388 pi->graphics_level[i].GnbSlow = 1; 2389 pi->graphics_level[i].ForceNbPs1 = 0; 2390 pi->graphics_level[i].UpH = 0; 2391 } 2392 2393 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { 2394 pi->graphics_level[pi->lowest_valid].UpH = 0x28; 2395 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; 2396 if (pi->lowest_valid != pi->highest_valid) 2397 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; 2398 } 2399 } 2400 return 0; 2401 } 2402 2403 static int kv_calculate_dpm_settings(struct amdgpu_device *adev) 2404 { 2405 struct kv_power_info *pi = kv_get_pi(adev); 2406 u32 i; 2407 2408 if (pi->lowest_valid > pi->highest_valid) 2409 return -EINVAL; 2410 2411 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2412 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; 2413 2414 return 0; 2415 } 2416 2417 static void kv_init_graphics_levels(struct amdgpu_device *adev) 2418 { 2419 struct kv_power_info *pi = kv_get_pi(adev); 2420 u32 i; 2421 struct amdgpu_clock_voltage_dependency_table *table = 2422 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; 2423 2424 if (table && table->count) { 2425 u32 vid_2bit; 2426 2427 pi->graphics_dpm_level_count = 0; 2428 for (i = 0; i < table->count; i++) { 2429 if (pi->high_voltage_t && 2430 (pi->high_voltage_t < 2431 kv_convert_8bit_index_to_voltage(adev, table->entries[i].v))) 2432 break; 2433 2434 kv_set_divider_value(adev, i, table->entries[i].clk); 2435 vid_2bit = kv_convert_vid7_to_vid2(adev, 2436 &pi->sys_info.vid_mapping_table, 2437 table->entries[i].v); 2438 kv_set_vid(adev, i, vid_2bit); 2439 kv_set_at(adev, i, pi->at[i]); 2440 kv_dpm_power_level_enabled_for_throttle(adev, i, true); 2441 pi->graphics_dpm_level_count++; 2442 } 2443 } else { 2444 struct sumo_sclk_voltage_mapping_table *table = 2445 &pi->sys_info.sclk_voltage_mapping_table; 2446 2447 pi->graphics_dpm_level_count = 0; 2448 for (i = 0; i < table->num_max_dpm_entries; i++) { 2449 if (pi->high_voltage_t && 2450 pi->high_voltage_t < 2451 kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit)) 2452 break; 2453 2454 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); 2455 kv_set_vid(adev, i, table->entries[i].vid_2bit); 2456 kv_set_at(adev, i, pi->at[i]); 2457 kv_dpm_power_level_enabled_for_throttle(adev, i, true); 2458 pi->graphics_dpm_level_count++; 2459 } 2460 } 2461 2462 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) 2463 kv_dpm_power_level_enable(adev, i, false); 2464 } 2465 2466 static void kv_enable_new_levels(struct amdgpu_device *adev) 2467 { 2468 struct kv_power_info *pi = kv_get_pi(adev); 2469 u32 i; 2470 2471 for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) { 2472 if (i >= pi->lowest_valid && i <= pi->highest_valid) 2473 kv_dpm_power_level_enable(adev, i, true); 2474 } 2475 } 2476 2477 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level) 2478 { 2479 u32 new_mask = (1 << level); 2480 2481 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, 2482 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2483 new_mask); 2484 } 2485 2486 static int kv_set_enabled_levels(struct amdgpu_device *adev) 2487 { 2488 struct kv_power_info *pi = kv_get_pi(adev); 2489 u32 i, new_mask = 0; 2490 2491 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) 2492 new_mask |= (1 << i); 2493 2494 return amdgpu_kv_send_msg_to_smc_with_parameter(adev, 2495 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2496 new_mask); 2497 } 2498 2499 static void kv_program_nbps_index_settings(struct amdgpu_device *adev, 2500 struct amdgpu_ps *new_rps) 2501 { 2502 struct kv_ps *new_ps = kv_get_ps(new_rps); 2503 struct kv_power_info *pi = kv_get_pi(adev); 2504 u32 nbdpmconfig1; 2505 2506 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) 2507 return; 2508 2509 if (pi->sys_info.nb_dpm_enable) { 2510 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); 2511 nbdpmconfig1 &= ~(NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK | 2512 NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK | 2513 NB_DPM_CONFIG_1__DpmXNbPsLo_MASK | 2514 NB_DPM_CONFIG_1__DpmXNbPsHi_MASK); 2515 nbdpmconfig1 |= (new_ps->dpm0_pg_nb_ps_lo << NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT) | 2516 (new_ps->dpm0_pg_nb_ps_hi << NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT) | 2517 (new_ps->dpmx_nb_ps_lo << NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT) | 2518 (new_ps->dpmx_nb_ps_hi << NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT); 2519 WREG32_SMC(ixNB_DPM_CONFIG_1, nbdpmconfig1); 2520 } 2521 } 2522 2523 static int kv_set_thermal_temperature_range(struct amdgpu_device *adev, 2524 int min_temp, int max_temp) 2525 { 2526 int low_temp = 0 * 1000; 2527 int high_temp = 255 * 1000; 2528 u32 tmp; 2529 2530 if (low_temp < min_temp) 2531 low_temp = min_temp; 2532 if (high_temp > max_temp) 2533 high_temp = max_temp; 2534 if (high_temp < low_temp) { 2535 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 2536 return -EINVAL; 2537 } 2538 2539 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 2540 tmp &= ~(CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK | 2541 CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK); 2542 tmp |= ((49 + (high_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT) | 2543 ((49 + (low_temp / 1000)) << CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT); 2544 WREG32_SMC(ixCG_THERMAL_INT_CTRL, tmp); 2545 2546 adev->pm.dpm.thermal.min_temp = low_temp; 2547 adev->pm.dpm.thermal.max_temp = high_temp; 2548 2549 return 0; 2550 } 2551 2552 union igp_info { 2553 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 2554 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 2555 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; 2556 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 2557 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 2558 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 2559 }; 2560 2561 static int kv_parse_sys_info_table(struct amdgpu_device *adev) 2562 { 2563 struct kv_power_info *pi = kv_get_pi(adev); 2564 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2565 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 2566 union igp_info *igp_info; 2567 u8 frev, crev; 2568 u16 data_offset; 2569 int i; 2570 2571 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 2572 &frev, &crev, &data_offset)) { 2573 igp_info = (union igp_info *)(mode_info->atom_context->bios + 2574 data_offset); 2575 2576 if (crev != 8) { 2577 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 2578 return -EINVAL; 2579 } 2580 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); 2581 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); 2582 pi->sys_info.bootup_nb_voltage_index = 2583 le16_to_cpu(igp_info->info_8.usBootUpNBVoltage); 2584 if (igp_info->info_8.ucHtcTmpLmt == 0) 2585 pi->sys_info.htc_tmp_lmt = 203; 2586 else 2587 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; 2588 if (igp_info->info_8.ucHtcHystLmt == 0) 2589 pi->sys_info.htc_hyst_lmt = 5; 2590 else 2591 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; 2592 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { 2593 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); 2594 } 2595 2596 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3)) 2597 pi->sys_info.nb_dpm_enable = true; 2598 else 2599 pi->sys_info.nb_dpm_enable = false; 2600 2601 for (i = 0; i < KV_NUM_NBPSTATES; i++) { 2602 pi->sys_info.nbp_memory_clock[i] = 2603 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]); 2604 pi->sys_info.nbp_n_clock[i] = 2605 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]); 2606 } 2607 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) & 2608 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) 2609 pi->caps_enable_dfs_bypass = true; 2610 2611 sumo_construct_sclk_voltage_mapping_table(adev, 2612 &pi->sys_info.sclk_voltage_mapping_table, 2613 igp_info->info_8.sAvail_SCLK); 2614 2615 sumo_construct_vid_mapping_table(adev, 2616 &pi->sys_info.vid_mapping_table, 2617 igp_info->info_8.sAvail_SCLK); 2618 2619 kv_construct_max_power_limits_table(adev, 2620 &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac); 2621 } 2622 return 0; 2623 } 2624 2625 union power_info { 2626 struct _ATOM_POWERPLAY_INFO info; 2627 struct _ATOM_POWERPLAY_INFO_V2 info_2; 2628 struct _ATOM_POWERPLAY_INFO_V3 info_3; 2629 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 2630 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 2631 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 2632 }; 2633 2634 union pplib_clock_info { 2635 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 2636 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 2637 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 2638 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 2639 }; 2640 2641 union pplib_power_state { 2642 struct _ATOM_PPLIB_STATE v1; 2643 struct _ATOM_PPLIB_STATE_V2 v2; 2644 }; 2645 2646 static void kv_patch_boot_state(struct amdgpu_device *adev, 2647 struct kv_ps *ps) 2648 { 2649 struct kv_power_info *pi = kv_get_pi(adev); 2650 2651 ps->num_levels = 1; 2652 ps->levels[0] = pi->boot_pl; 2653 } 2654 2655 static void kv_parse_pplib_non_clock_info(struct amdgpu_device *adev, 2656 struct amdgpu_ps *rps, 2657 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 2658 u8 table_rev) 2659 { 2660 struct kv_ps *ps = kv_get_ps(rps); 2661 2662 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 2663 rps->class = le16_to_cpu(non_clock_info->usClassification); 2664 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 2665 2666 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 2667 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 2668 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 2669 } else { 2670 rps->vclk = 0; 2671 rps->dclk = 0; 2672 } 2673 2674 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 2675 adev->pm.dpm.boot_ps = rps; 2676 kv_patch_boot_state(adev, ps); 2677 } 2678 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 2679 adev->pm.dpm.uvd_ps = rps; 2680 } 2681 2682 static void kv_parse_pplib_clock_info(struct amdgpu_device *adev, 2683 struct amdgpu_ps *rps, int index, 2684 union pplib_clock_info *clock_info) 2685 { 2686 struct kv_power_info *pi = kv_get_pi(adev); 2687 struct kv_ps *ps = kv_get_ps(rps); 2688 struct kv_pl *pl = &ps->levels[index]; 2689 u32 sclk; 2690 2691 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2692 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2693 pl->sclk = sclk; 2694 pl->vddc_index = clock_info->sumo.vddcIndex; 2695 2696 ps->num_levels = index + 1; 2697 2698 if (pi->caps_sclk_ds) { 2699 pl->ds_divider_index = 5; 2700 pl->ss_divider_index = 5; 2701 } 2702 } 2703 2704 static int kv_parse_power_table(struct amdgpu_device *adev) 2705 { 2706 struct amdgpu_mode_info *mode_info = &adev->mode_info; 2707 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 2708 union pplib_power_state *power_state; 2709 int i, j, k, non_clock_array_index, clock_array_index; 2710 union pplib_clock_info *clock_info; 2711 struct _StateArray *state_array; 2712 struct _ClockInfoArray *clock_info_array; 2713 struct _NonClockInfoArray *non_clock_info_array; 2714 union power_info *power_info; 2715 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 2716 u16 data_offset; 2717 u8 frev, crev; 2718 u8 *power_state_offset; 2719 struct kv_ps *ps; 2720 2721 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 2722 &frev, &crev, &data_offset)) 2723 return -EINVAL; 2724 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 2725 2726 amdgpu_add_thermal_controller(adev); 2727 2728 state_array = (struct _StateArray *) 2729 (mode_info->atom_context->bios + data_offset + 2730 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 2731 clock_info_array = (struct _ClockInfoArray *) 2732 (mode_info->atom_context->bios + data_offset + 2733 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 2734 non_clock_info_array = (struct _NonClockInfoArray *) 2735 (mode_info->atom_context->bios + data_offset + 2736 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 2737 2738 adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 2739 sizeof(struct amdgpu_ps), 2740 GFP_KERNEL); 2741 if (!adev->pm.dpm.ps) 2742 return -ENOMEM; 2743 power_state_offset = (u8 *)state_array->states; 2744 for (i = 0; i < state_array->ucNumEntries; i++) { 2745 u8 *idx; 2746 power_state = (union pplib_power_state *)power_state_offset; 2747 non_clock_array_index = power_state->v2.nonClockInfoIndex; 2748 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2749 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2750 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL); 2751 if (ps == NULL) { 2752 kfree(adev->pm.dpm.ps); 2753 return -ENOMEM; 2754 } 2755 adev->pm.dpm.ps[i].ps_priv = ps; 2756 k = 0; 2757 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 2758 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2759 clock_array_index = idx[j]; 2760 if (clock_array_index >= clock_info_array->ucNumEntries) 2761 continue; 2762 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) 2763 break; 2764 clock_info = (union pplib_clock_info *) 2765 ((u8 *)&clock_info_array->clockInfo[0] + 2766 (clock_array_index * clock_info_array->ucEntrySize)); 2767 kv_parse_pplib_clock_info(adev, 2768 &adev->pm.dpm.ps[i], k, 2769 clock_info); 2770 k++; 2771 } 2772 kv_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 2773 non_clock_info, 2774 non_clock_info_array->ucEntrySize); 2775 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 2776 } 2777 adev->pm.dpm.num_ps = state_array->ucNumEntries; 2778 2779 /* fill in the vce power states */ 2780 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 2781 u32 sclk; 2782 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 2783 clock_info = (union pplib_clock_info *) 2784 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 2785 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); 2786 sclk |= clock_info->sumo.ucEngineClockHigh << 16; 2787 adev->pm.dpm.vce_states[i].sclk = sclk; 2788 adev->pm.dpm.vce_states[i].mclk = 0; 2789 } 2790 2791 return 0; 2792 } 2793 2794 static int kv_dpm_init(struct amdgpu_device *adev) 2795 { 2796 struct kv_power_info *pi; 2797 int ret, i; 2798 2799 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); 2800 if (pi == NULL) 2801 return -ENOMEM; 2802 adev->pm.dpm.priv = pi; 2803 2804 ret = amdgpu_get_platform_caps(adev); 2805 if (ret) 2806 return ret; 2807 2808 ret = amdgpu_parse_extended_power_table(adev); 2809 if (ret) 2810 return ret; 2811 2812 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) 2813 pi->at[i] = TRINITY_AT_DFLT; 2814 2815 pi->sram_end = SMC_RAM_END; 2816 2817 pi->enable_nb_dpm = true; 2818 2819 pi->caps_power_containment = true; 2820 pi->caps_cac = true; 2821 pi->enable_didt = false; 2822 if (pi->enable_didt) { 2823 pi->caps_sq_ramping = true; 2824 pi->caps_db_ramping = true; 2825 pi->caps_td_ramping = true; 2826 pi->caps_tcp_ramping = true; 2827 } 2828 2829 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) 2830 pi->caps_sclk_ds = true; 2831 else 2832 pi->caps_sclk_ds = false; 2833 2834 pi->enable_auto_thermal_throttling = true; 2835 pi->disable_nb_ps3_in_battery = false; 2836 if (amdgpu_bapm == 0) 2837 pi->bapm_enable = false; 2838 else 2839 pi->bapm_enable = true; 2840 pi->voltage_drop_t = 0; 2841 pi->caps_sclk_throttle_low_notification = false; 2842 pi->caps_fps = false; /* true? */ 2843 pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false; 2844 pi->caps_uvd_dpm = true; 2845 pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false; 2846 pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false; 2847 pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false; 2848 pi->caps_stable_p_state = false; 2849 2850 ret = kv_parse_sys_info_table(adev); 2851 if (ret) 2852 return ret; 2853 2854 kv_patch_voltage_values(adev); 2855 kv_construct_boot_state(adev); 2856 2857 ret = kv_parse_power_table(adev); 2858 if (ret) 2859 return ret; 2860 2861 pi->enable_dpm = true; 2862 2863 return 0; 2864 } 2865 2866 static void 2867 kv_dpm_debugfs_print_current_performance_level(void *handle, 2868 struct seq_file *m) 2869 { 2870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2871 struct kv_power_info *pi = kv_get_pi(adev); 2872 u32 current_index = 2873 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & 2874 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> 2875 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; 2876 u32 sclk, tmp; 2877 u16 vddc; 2878 2879 if (current_index >= SMU__NUM_SCLK_DPM_STATE) { 2880 seq_printf(m, "invalid dpm profile %d\n", current_index); 2881 } else { 2882 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); 2883 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & 2884 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> 2885 SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT; 2886 vddc = kv_convert_8bit_index_to_voltage(adev, (u16)tmp); 2887 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); 2888 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); 2889 seq_printf(m, "power level %d sclk: %u vddc: %u\n", 2890 current_index, sclk, vddc); 2891 } 2892 } 2893 2894 static void 2895 kv_dpm_print_power_state(void *handle, void *request_ps) 2896 { 2897 int i; 2898 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 2899 struct kv_ps *ps = kv_get_ps(rps); 2900 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2901 2902 amdgpu_dpm_print_class_info(rps->class, rps->class2); 2903 amdgpu_dpm_print_cap_info(rps->caps); 2904 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 2905 for (i = 0; i < ps->num_levels; i++) { 2906 struct kv_pl *pl = &ps->levels[i]; 2907 printk("\t\tpower level %d sclk: %u vddc: %u\n", 2908 i, pl->sclk, 2909 kv_convert_8bit_index_to_voltage(adev, pl->vddc_index)); 2910 } 2911 amdgpu_dpm_print_ps_status(adev, rps); 2912 } 2913 2914 static void kv_dpm_fini(struct amdgpu_device *adev) 2915 { 2916 int i; 2917 2918 for (i = 0; i < adev->pm.dpm.num_ps; i++) { 2919 kfree(adev->pm.dpm.ps[i].ps_priv); 2920 } 2921 kfree(adev->pm.dpm.ps); 2922 kfree(adev->pm.dpm.priv); 2923 amdgpu_free_extended_power_table(adev); 2924 } 2925 2926 static void kv_dpm_display_configuration_changed(void *handle) 2927 { 2928 2929 } 2930 2931 static u32 kv_dpm_get_sclk(void *handle, bool low) 2932 { 2933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2934 struct kv_power_info *pi = kv_get_pi(adev); 2935 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); 2936 2937 if (low) 2938 return requested_state->levels[0].sclk; 2939 else 2940 return requested_state->levels[requested_state->num_levels - 1].sclk; 2941 } 2942 2943 static u32 kv_dpm_get_mclk(void *handle, bool low) 2944 { 2945 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2946 struct kv_power_info *pi = kv_get_pi(adev); 2947 2948 return pi->sys_info.bootup_uma_clk; 2949 } 2950 2951 /* get temperature in millidegrees */ 2952 static int kv_dpm_get_temp(void *handle) 2953 { 2954 u32 temp; 2955 int actual_temp = 0; 2956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2957 2958 temp = RREG32_SMC(0xC0300E0C); 2959 2960 if (temp) 2961 actual_temp = (temp / 8) - 49; 2962 else 2963 actual_temp = 0; 2964 2965 actual_temp = actual_temp * 1000; 2966 2967 return actual_temp; 2968 } 2969 2970 static int kv_dpm_early_init(void *handle) 2971 { 2972 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2973 2974 adev->powerplay.pp_funcs = &kv_dpm_funcs; 2975 adev->powerplay.pp_handle = adev; 2976 kv_dpm_set_irq_funcs(adev); 2977 2978 return 0; 2979 } 2980 2981 static int kv_dpm_late_init(void *handle) 2982 { 2983 /* powerdown unused blocks for now */ 2984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2985 2986 if (!adev->pm.dpm_enabled) 2987 return 0; 2988 2989 kv_dpm_powergate_acp(adev, true); 2990 kv_dpm_powergate_samu(adev, true); 2991 2992 return 0; 2993 } 2994 2995 static int kv_dpm_sw_init(void *handle) 2996 { 2997 int ret; 2998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2999 3000 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, 3001 &adev->pm.dpm.thermal.irq); 3002 if (ret) 3003 return ret; 3004 3005 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, 3006 &adev->pm.dpm.thermal.irq); 3007 if (ret) 3008 return ret; 3009 3010 /* default to balanced state */ 3011 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 3012 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 3013 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 3014 adev->pm.default_sclk = adev->clock.default_sclk; 3015 adev->pm.default_mclk = adev->clock.default_mclk; 3016 adev->pm.current_sclk = adev->clock.default_sclk; 3017 adev->pm.current_mclk = adev->clock.default_mclk; 3018 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 3019 3020 if (amdgpu_dpm == 0) 3021 return 0; 3022 3023 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 3024 ret = kv_dpm_init(adev); 3025 if (ret) 3026 goto dpm_failed; 3027 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 3028 if (amdgpu_dpm == 1) 3029 amdgpu_pm_print_power_states(adev); 3030 DRM_INFO("amdgpu: dpm initialized\n"); 3031 3032 return 0; 3033 3034 dpm_failed: 3035 kv_dpm_fini(adev); 3036 DRM_ERROR("amdgpu: dpm initialization failed\n"); 3037 return ret; 3038 } 3039 3040 static int kv_dpm_sw_fini(void *handle) 3041 { 3042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3043 3044 flush_work(&adev->pm.dpm.thermal.work); 3045 3046 kv_dpm_fini(adev); 3047 3048 return 0; 3049 } 3050 3051 static int kv_dpm_hw_init(void *handle) 3052 { 3053 int ret; 3054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3055 3056 if (!amdgpu_dpm) 3057 return 0; 3058 3059 kv_dpm_setup_asic(adev); 3060 ret = kv_dpm_enable(adev); 3061 if (ret) 3062 adev->pm.dpm_enabled = false; 3063 else 3064 adev->pm.dpm_enabled = true; 3065 amdgpu_legacy_dpm_compute_clocks(adev); 3066 return ret; 3067 } 3068 3069 static int kv_dpm_hw_fini(void *handle) 3070 { 3071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3072 3073 if (adev->pm.dpm_enabled) 3074 kv_dpm_disable(adev); 3075 3076 return 0; 3077 } 3078 3079 static int kv_dpm_suspend(void *handle) 3080 { 3081 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3082 3083 if (adev->pm.dpm_enabled) { 3084 /* disable dpm */ 3085 kv_dpm_disable(adev); 3086 /* reset the power state */ 3087 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 3088 } 3089 return 0; 3090 } 3091 3092 static int kv_dpm_resume(void *handle) 3093 { 3094 int ret; 3095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3096 3097 if (adev->pm.dpm_enabled) { 3098 /* asic init will reset to the boot state */ 3099 kv_dpm_setup_asic(adev); 3100 ret = kv_dpm_enable(adev); 3101 if (ret) 3102 adev->pm.dpm_enabled = false; 3103 else 3104 adev->pm.dpm_enabled = true; 3105 if (adev->pm.dpm_enabled) 3106 amdgpu_legacy_dpm_compute_clocks(adev); 3107 } 3108 return 0; 3109 } 3110 3111 static bool kv_dpm_is_idle(void *handle) 3112 { 3113 return true; 3114 } 3115 3116 static int kv_dpm_wait_for_idle(void *handle) 3117 { 3118 return 0; 3119 } 3120 3121 3122 static int kv_dpm_soft_reset(void *handle) 3123 { 3124 return 0; 3125 } 3126 3127 static int kv_dpm_set_interrupt_state(struct amdgpu_device *adev, 3128 struct amdgpu_irq_src *src, 3129 unsigned type, 3130 enum amdgpu_interrupt_state state) 3131 { 3132 u32 cg_thermal_int; 3133 3134 switch (type) { 3135 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 3136 switch (state) { 3137 case AMDGPU_IRQ_STATE_DISABLE: 3138 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3139 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 3140 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3141 break; 3142 case AMDGPU_IRQ_STATE_ENABLE: 3143 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3144 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK; 3145 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3146 break; 3147 default: 3148 break; 3149 } 3150 break; 3151 3152 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 3153 switch (state) { 3154 case AMDGPU_IRQ_STATE_DISABLE: 3155 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3156 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 3157 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3158 break; 3159 case AMDGPU_IRQ_STATE_ENABLE: 3160 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); 3161 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK; 3162 WREG32_SMC(ixCG_THERMAL_INT_CTRL, cg_thermal_int); 3163 break; 3164 default: 3165 break; 3166 } 3167 break; 3168 3169 default: 3170 break; 3171 } 3172 return 0; 3173 } 3174 3175 static int kv_dpm_process_interrupt(struct amdgpu_device *adev, 3176 struct amdgpu_irq_src *source, 3177 struct amdgpu_iv_entry *entry) 3178 { 3179 bool queue_thermal = false; 3180 3181 if (entry == NULL) 3182 return -EINVAL; 3183 3184 switch (entry->src_id) { 3185 case 230: /* thermal low to high */ 3186 DRM_DEBUG("IH: thermal low to high\n"); 3187 adev->pm.dpm.thermal.high_to_low = false; 3188 queue_thermal = true; 3189 break; 3190 case 231: /* thermal high to low */ 3191 DRM_DEBUG("IH: thermal high to low\n"); 3192 adev->pm.dpm.thermal.high_to_low = true; 3193 queue_thermal = true; 3194 break; 3195 default: 3196 break; 3197 } 3198 3199 if (queue_thermal) 3200 schedule_work(&adev->pm.dpm.thermal.work); 3201 3202 return 0; 3203 } 3204 3205 static int kv_dpm_set_clockgating_state(void *handle, 3206 enum amd_clockgating_state state) 3207 { 3208 return 0; 3209 } 3210 3211 static int kv_dpm_set_powergating_state(void *handle, 3212 enum amd_powergating_state state) 3213 { 3214 return 0; 3215 } 3216 3217 static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1, 3218 const struct kv_pl *kv_cpl2) 3219 { 3220 return ((kv_cpl1->sclk == kv_cpl2->sclk) && 3221 (kv_cpl1->vddc_index == kv_cpl2->vddc_index) && 3222 (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) && 3223 (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state)); 3224 } 3225 3226 static int kv_check_state_equal(void *handle, 3227 void *current_ps, 3228 void *request_ps, 3229 bool *equal) 3230 { 3231 struct kv_ps *kv_cps; 3232 struct kv_ps *kv_rps; 3233 int i; 3234 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 3235 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 3236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3237 3238 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 3239 return -EINVAL; 3240 3241 kv_cps = kv_get_ps(cps); 3242 kv_rps = kv_get_ps(rps); 3243 3244 if (kv_cps == NULL) { 3245 *equal = false; 3246 return 0; 3247 } 3248 3249 if (kv_cps->num_levels != kv_rps->num_levels) { 3250 *equal = false; 3251 return 0; 3252 } 3253 3254 for (i = 0; i < kv_cps->num_levels; i++) { 3255 if (!kv_are_power_levels_equal(&(kv_cps->levels[i]), 3256 &(kv_rps->levels[i]))) { 3257 *equal = false; 3258 return 0; 3259 } 3260 } 3261 3262 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 3263 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 3264 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 3265 3266 return 0; 3267 } 3268 3269 static int kv_dpm_read_sensor(void *handle, int idx, 3270 void *value, int *size) 3271 { 3272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3273 struct kv_power_info *pi = kv_get_pi(adev); 3274 uint32_t sclk; 3275 u32 pl_index = 3276 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & 3277 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >> 3278 TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT; 3279 3280 /* size must be at least 4 bytes for all sensors */ 3281 if (*size < 4) 3282 return -EINVAL; 3283 3284 switch (idx) { 3285 case AMDGPU_PP_SENSOR_GFX_SCLK: 3286 if (pl_index < SMU__NUM_SCLK_DPM_STATE) { 3287 sclk = be32_to_cpu( 3288 pi->graphics_level[pl_index].SclkFrequency); 3289 *((uint32_t *)value) = sclk; 3290 *size = 4; 3291 return 0; 3292 } 3293 return -EINVAL; 3294 case AMDGPU_PP_SENSOR_GPU_TEMP: 3295 *((uint32_t *)value) = kv_dpm_get_temp(adev); 3296 *size = 4; 3297 return 0; 3298 default: 3299 return -EOPNOTSUPP; 3300 } 3301 } 3302 3303 static int kv_set_powergating_by_smu(void *handle, 3304 uint32_t block_type, bool gate) 3305 { 3306 switch (block_type) { 3307 case AMD_IP_BLOCK_TYPE_UVD: 3308 kv_dpm_powergate_uvd(handle, gate); 3309 break; 3310 case AMD_IP_BLOCK_TYPE_VCE: 3311 kv_dpm_powergate_vce(handle, gate); 3312 break; 3313 default: 3314 break; 3315 } 3316 return 0; 3317 } 3318 3319 static const struct amd_ip_funcs kv_dpm_ip_funcs = { 3320 .name = "kv_dpm", 3321 .early_init = kv_dpm_early_init, 3322 .late_init = kv_dpm_late_init, 3323 .sw_init = kv_dpm_sw_init, 3324 .sw_fini = kv_dpm_sw_fini, 3325 .hw_init = kv_dpm_hw_init, 3326 .hw_fini = kv_dpm_hw_fini, 3327 .suspend = kv_dpm_suspend, 3328 .resume = kv_dpm_resume, 3329 .is_idle = kv_dpm_is_idle, 3330 .wait_for_idle = kv_dpm_wait_for_idle, 3331 .soft_reset = kv_dpm_soft_reset, 3332 .set_clockgating_state = kv_dpm_set_clockgating_state, 3333 .set_powergating_state = kv_dpm_set_powergating_state, 3334 }; 3335 3336 const struct amdgpu_ip_block_version kv_smu_ip_block = 3337 { 3338 .type = AMD_IP_BLOCK_TYPE_SMC, 3339 .major = 1, 3340 .minor = 0, 3341 .rev = 0, 3342 .funcs = &kv_dpm_ip_funcs, 3343 }; 3344 3345 static const struct amd_pm_funcs kv_dpm_funcs = { 3346 .pre_set_power_state = &kv_dpm_pre_set_power_state, 3347 .set_power_state = &kv_dpm_set_power_state, 3348 .post_set_power_state = &kv_dpm_post_set_power_state, 3349 .display_configuration_changed = &kv_dpm_display_configuration_changed, 3350 .get_sclk = &kv_dpm_get_sclk, 3351 .get_mclk = &kv_dpm_get_mclk, 3352 .print_power_state = &kv_dpm_print_power_state, 3353 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level, 3354 .force_performance_level = &kv_dpm_force_performance_level, 3355 .set_powergating_by_smu = kv_set_powergating_by_smu, 3356 .enable_bapm = &kv_dpm_enable_bapm, 3357 .get_vce_clock_state = amdgpu_get_vce_clock_state, 3358 .check_state_equal = kv_check_state_equal, 3359 .read_sensor = &kv_dpm_read_sensor, 3360 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 3361 }; 3362 3363 static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = { 3364 .set = kv_dpm_set_interrupt_state, 3365 .process = kv_dpm_process_interrupt, 3366 }; 3367 3368 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev) 3369 { 3370 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 3371 adev->pm.dpm.thermal.irq.funcs = &kv_dpm_irq_funcs; 3372 } 3373