1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 static const struct cg_flag_name clocks[] = { 39 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 40 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 41 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 42 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 43 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 44 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 45 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 46 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 47 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 48 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 49 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 50 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 51 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 52 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 53 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 54 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 55 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 56 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 57 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 58 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 59 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 60 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 61 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 62 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 63 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 64 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 65 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 66 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 67 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 68 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 69 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 70 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 71 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 72 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 73 {0, NULL}, 74 }; 75 76 static const struct hwmon_temp_label { 77 enum PP_HWMON_TEMP channel; 78 const char *label; 79 } temp_label[] = { 80 {PP_TEMP_EDGE, "edge"}, 81 {PP_TEMP_JUNCTION, "junction"}, 82 {PP_TEMP_MEM, "mem"}, 83 }; 84 85 const char * const amdgpu_pp_profile_name[] = { 86 "BOOTUP_DEFAULT", 87 "3D_FULL_SCREEN", 88 "POWER_SAVING", 89 "VIDEO", 90 "VR", 91 "COMPUTE", 92 "CUSTOM", 93 "WINDOW_3D", 94 }; 95 96 /** 97 * DOC: power_dpm_state 98 * 99 * The power_dpm_state file is a legacy interface and is only provided for 100 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 101 * certain power related parameters. The file power_dpm_state is used for this. 102 * It accepts the following arguments: 103 * 104 * - battery 105 * 106 * - balanced 107 * 108 * - performance 109 * 110 * battery 111 * 112 * On older GPUs, the vbios provided a special power state for battery 113 * operation. Selecting battery switched to this state. This is no 114 * longer provided on newer GPUs so the option does nothing in that case. 115 * 116 * balanced 117 * 118 * On older GPUs, the vbios provided a special power state for balanced 119 * operation. Selecting balanced switched to this state. This is no 120 * longer provided on newer GPUs so the option does nothing in that case. 121 * 122 * performance 123 * 124 * On older GPUs, the vbios provided a special power state for performance 125 * operation. Selecting performance switched to this state. This is no 126 * longer provided on newer GPUs so the option does nothing in that case. 127 * 128 */ 129 130 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 131 struct device_attribute *attr, 132 char *buf) 133 { 134 struct drm_device *ddev = dev_get_drvdata(dev); 135 struct amdgpu_device *adev = drm_to_adev(ddev); 136 enum amd_pm_state_type pm; 137 int ret; 138 139 if (amdgpu_in_reset(adev)) 140 return -EPERM; 141 if (adev->in_suspend && !adev->in_runpm) 142 return -EPERM; 143 144 ret = pm_runtime_get_sync(ddev->dev); 145 if (ret < 0) { 146 pm_runtime_put_autosuspend(ddev->dev); 147 return ret; 148 } 149 150 amdgpu_dpm_get_current_power_state(adev, &pm); 151 152 pm_runtime_mark_last_busy(ddev->dev); 153 pm_runtime_put_autosuspend(ddev->dev); 154 155 return sysfs_emit(buf, "%s\n", 156 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 157 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 158 } 159 160 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 161 struct device_attribute *attr, 162 const char *buf, 163 size_t count) 164 { 165 struct drm_device *ddev = dev_get_drvdata(dev); 166 struct amdgpu_device *adev = drm_to_adev(ddev); 167 enum amd_pm_state_type state; 168 int ret; 169 170 if (amdgpu_in_reset(adev)) 171 return -EPERM; 172 if (adev->in_suspend && !adev->in_runpm) 173 return -EPERM; 174 175 if (strncmp("battery", buf, strlen("battery")) == 0) 176 state = POWER_STATE_TYPE_BATTERY; 177 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 178 state = POWER_STATE_TYPE_BALANCED; 179 else if (strncmp("performance", buf, strlen("performance")) == 0) 180 state = POWER_STATE_TYPE_PERFORMANCE; 181 else 182 return -EINVAL; 183 184 ret = pm_runtime_get_sync(ddev->dev); 185 if (ret < 0) { 186 pm_runtime_put_autosuspend(ddev->dev); 187 return ret; 188 } 189 190 amdgpu_dpm_set_power_state(adev, state); 191 192 pm_runtime_mark_last_busy(ddev->dev); 193 pm_runtime_put_autosuspend(ddev->dev); 194 195 return count; 196 } 197 198 199 /** 200 * DOC: power_dpm_force_performance_level 201 * 202 * The amdgpu driver provides a sysfs API for adjusting certain power 203 * related parameters. The file power_dpm_force_performance_level is 204 * used for this. It accepts the following arguments: 205 * 206 * - auto 207 * 208 * - low 209 * 210 * - high 211 * 212 * - manual 213 * 214 * - profile_standard 215 * 216 * - profile_min_sclk 217 * 218 * - profile_min_mclk 219 * 220 * - profile_peak 221 * 222 * auto 223 * 224 * When auto is selected, the driver will attempt to dynamically select 225 * the optimal power profile for current conditions in the driver. 226 * 227 * low 228 * 229 * When low is selected, the clocks are forced to the lowest power state. 230 * 231 * high 232 * 233 * When high is selected, the clocks are forced to the highest power state. 234 * 235 * manual 236 * 237 * When manual is selected, the user can manually adjust which power states 238 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 239 * and pp_dpm_pcie files and adjust the power state transition heuristics 240 * via the pp_power_profile_mode sysfs file. 241 * 242 * profile_standard 243 * profile_min_sclk 244 * profile_min_mclk 245 * profile_peak 246 * 247 * When the profiling modes are selected, clock and power gating are 248 * disabled and the clocks are set for different profiling cases. This 249 * mode is recommended for profiling specific work loads where you do 250 * not want clock or power gating for clock fluctuation to interfere 251 * with your results. profile_standard sets the clocks to a fixed clock 252 * level which varies from asic to asic. profile_min_sclk forces the sclk 253 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 254 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 255 * 256 */ 257 258 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 259 struct device_attribute *attr, 260 char *buf) 261 { 262 struct drm_device *ddev = dev_get_drvdata(dev); 263 struct amdgpu_device *adev = drm_to_adev(ddev); 264 enum amd_dpm_forced_level level = 0xff; 265 int ret; 266 267 if (amdgpu_in_reset(adev)) 268 return -EPERM; 269 if (adev->in_suspend && !adev->in_runpm) 270 return -EPERM; 271 272 ret = pm_runtime_get_sync(ddev->dev); 273 if (ret < 0) { 274 pm_runtime_put_autosuspend(ddev->dev); 275 return ret; 276 } 277 278 level = amdgpu_dpm_get_performance_level(adev); 279 280 pm_runtime_mark_last_busy(ddev->dev); 281 pm_runtime_put_autosuspend(ddev->dev); 282 283 return sysfs_emit(buf, "%s\n", 284 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 285 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 286 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 287 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 288 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 289 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 290 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 291 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 292 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 293 "unknown"); 294 } 295 296 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 297 struct device_attribute *attr, 298 const char *buf, 299 size_t count) 300 { 301 struct drm_device *ddev = dev_get_drvdata(dev); 302 struct amdgpu_device *adev = drm_to_adev(ddev); 303 enum amd_dpm_forced_level level; 304 int ret = 0; 305 306 if (amdgpu_in_reset(adev)) 307 return -EPERM; 308 if (adev->in_suspend && !adev->in_runpm) 309 return -EPERM; 310 311 if (strncmp("low", buf, strlen("low")) == 0) { 312 level = AMD_DPM_FORCED_LEVEL_LOW; 313 } else if (strncmp("high", buf, strlen("high")) == 0) { 314 level = AMD_DPM_FORCED_LEVEL_HIGH; 315 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_AUTO; 317 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_MANUAL; 319 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 321 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 323 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 325 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 327 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 328 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 329 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 330 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 331 } else { 332 return -EINVAL; 333 } 334 335 ret = pm_runtime_get_sync(ddev->dev); 336 if (ret < 0) { 337 pm_runtime_put_autosuspend(ddev->dev); 338 return ret; 339 } 340 341 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 342 if (amdgpu_dpm_force_performance_level(adev, level)) { 343 pm_runtime_mark_last_busy(ddev->dev); 344 pm_runtime_put_autosuspend(ddev->dev); 345 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 346 return -EINVAL; 347 } 348 /* override whatever a user ctx may have set */ 349 adev->pm.stable_pstate_ctx = NULL; 350 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 351 352 pm_runtime_mark_last_busy(ddev->dev); 353 pm_runtime_put_autosuspend(ddev->dev); 354 355 return count; 356 } 357 358 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 359 struct device_attribute *attr, 360 char *buf) 361 { 362 struct drm_device *ddev = dev_get_drvdata(dev); 363 struct amdgpu_device *adev = drm_to_adev(ddev); 364 struct pp_states_info data; 365 uint32_t i; 366 int buf_len, ret; 367 368 if (amdgpu_in_reset(adev)) 369 return -EPERM; 370 if (adev->in_suspend && !adev->in_runpm) 371 return -EPERM; 372 373 ret = pm_runtime_get_sync(ddev->dev); 374 if (ret < 0) { 375 pm_runtime_put_autosuspend(ddev->dev); 376 return ret; 377 } 378 379 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 380 memset(&data, 0, sizeof(data)); 381 382 pm_runtime_mark_last_busy(ddev->dev); 383 pm_runtime_put_autosuspend(ddev->dev); 384 385 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 386 for (i = 0; i < data.nums; i++) 387 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 388 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 389 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 390 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 391 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 392 393 return buf_len; 394 } 395 396 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 397 struct device_attribute *attr, 398 char *buf) 399 { 400 struct drm_device *ddev = dev_get_drvdata(dev); 401 struct amdgpu_device *adev = drm_to_adev(ddev); 402 struct pp_states_info data = {0}; 403 enum amd_pm_state_type pm = 0; 404 int i = 0, ret = 0; 405 406 if (amdgpu_in_reset(adev)) 407 return -EPERM; 408 if (adev->in_suspend && !adev->in_runpm) 409 return -EPERM; 410 411 ret = pm_runtime_get_sync(ddev->dev); 412 if (ret < 0) { 413 pm_runtime_put_autosuspend(ddev->dev); 414 return ret; 415 } 416 417 amdgpu_dpm_get_current_power_state(adev, &pm); 418 419 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 420 421 pm_runtime_mark_last_busy(ddev->dev); 422 pm_runtime_put_autosuspend(ddev->dev); 423 424 if (ret) 425 return ret; 426 427 for (i = 0; i < data.nums; i++) { 428 if (pm == data.states[i]) 429 break; 430 } 431 432 if (i == data.nums) 433 i = -EINVAL; 434 435 return sysfs_emit(buf, "%d\n", i); 436 } 437 438 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 439 struct device_attribute *attr, 440 char *buf) 441 { 442 struct drm_device *ddev = dev_get_drvdata(dev); 443 struct amdgpu_device *adev = drm_to_adev(ddev); 444 445 if (amdgpu_in_reset(adev)) 446 return -EPERM; 447 if (adev->in_suspend && !adev->in_runpm) 448 return -EPERM; 449 450 if (adev->pm.pp_force_state_enabled) 451 return amdgpu_get_pp_cur_state(dev, attr, buf); 452 else 453 return sysfs_emit(buf, "\n"); 454 } 455 456 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 457 struct device_attribute *attr, 458 const char *buf, 459 size_t count) 460 { 461 struct drm_device *ddev = dev_get_drvdata(dev); 462 struct amdgpu_device *adev = drm_to_adev(ddev); 463 enum amd_pm_state_type state = 0; 464 struct pp_states_info data; 465 unsigned long idx; 466 int ret; 467 468 if (amdgpu_in_reset(adev)) 469 return -EPERM; 470 if (adev->in_suspend && !adev->in_runpm) 471 return -EPERM; 472 473 adev->pm.pp_force_state_enabled = false; 474 475 if (strlen(buf) == 1) 476 return count; 477 478 ret = kstrtoul(buf, 0, &idx); 479 if (ret || idx >= ARRAY_SIZE(data.states)) 480 return -EINVAL; 481 482 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 483 484 ret = pm_runtime_get_sync(ddev->dev); 485 if (ret < 0) { 486 pm_runtime_put_autosuspend(ddev->dev); 487 return ret; 488 } 489 490 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 491 if (ret) 492 goto err_out; 493 494 state = data.states[idx]; 495 496 /* only set user selected power states */ 497 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 498 state != POWER_STATE_TYPE_DEFAULT) { 499 ret = amdgpu_dpm_dispatch_task(adev, 500 AMD_PP_TASK_ENABLE_USER_STATE, &state); 501 if (ret) 502 goto err_out; 503 504 adev->pm.pp_force_state_enabled = true; 505 } 506 507 pm_runtime_mark_last_busy(ddev->dev); 508 pm_runtime_put_autosuspend(ddev->dev); 509 510 return count; 511 512 err_out: 513 pm_runtime_mark_last_busy(ddev->dev); 514 pm_runtime_put_autosuspend(ddev->dev); 515 return ret; 516 } 517 518 /** 519 * DOC: pp_table 520 * 521 * The amdgpu driver provides a sysfs API for uploading new powerplay 522 * tables. The file pp_table is used for this. Reading the file 523 * will dump the current power play table. Writing to the file 524 * will attempt to upload a new powerplay table and re-initialize 525 * powerplay using that new table. 526 * 527 */ 528 529 static ssize_t amdgpu_get_pp_table(struct device *dev, 530 struct device_attribute *attr, 531 char *buf) 532 { 533 struct drm_device *ddev = dev_get_drvdata(dev); 534 struct amdgpu_device *adev = drm_to_adev(ddev); 535 char *table = NULL; 536 int size, ret; 537 538 if (amdgpu_in_reset(adev)) 539 return -EPERM; 540 if (adev->in_suspend && !adev->in_runpm) 541 return -EPERM; 542 543 ret = pm_runtime_get_sync(ddev->dev); 544 if (ret < 0) { 545 pm_runtime_put_autosuspend(ddev->dev); 546 return ret; 547 } 548 549 size = amdgpu_dpm_get_pp_table(adev, &table); 550 551 pm_runtime_mark_last_busy(ddev->dev); 552 pm_runtime_put_autosuspend(ddev->dev); 553 554 if (size <= 0) 555 return size; 556 557 if (size >= PAGE_SIZE) 558 size = PAGE_SIZE - 1; 559 560 memcpy(buf, table, size); 561 562 return size; 563 } 564 565 static ssize_t amdgpu_set_pp_table(struct device *dev, 566 struct device_attribute *attr, 567 const char *buf, 568 size_t count) 569 { 570 struct drm_device *ddev = dev_get_drvdata(dev); 571 struct amdgpu_device *adev = drm_to_adev(ddev); 572 int ret = 0; 573 574 if (amdgpu_in_reset(adev)) 575 return -EPERM; 576 if (adev->in_suspend && !adev->in_runpm) 577 return -EPERM; 578 579 ret = pm_runtime_get_sync(ddev->dev); 580 if (ret < 0) { 581 pm_runtime_put_autosuspend(ddev->dev); 582 return ret; 583 } 584 585 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 586 587 pm_runtime_mark_last_busy(ddev->dev); 588 pm_runtime_put_autosuspend(ddev->dev); 589 590 if (ret) 591 return ret; 592 593 return count; 594 } 595 596 /** 597 * DOC: pp_od_clk_voltage 598 * 599 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 600 * in each power level within a power state. The pp_od_clk_voltage is used for 601 * this. 602 * 603 * Note that the actual memory controller clock rate are exposed, not 604 * the effective memory clock of the DRAMs. To translate it, use the 605 * following formula: 606 * 607 * Clock conversion (Mhz): 608 * 609 * HBM: effective_memory_clock = memory_controller_clock * 1 610 * 611 * G5: effective_memory_clock = memory_controller_clock * 1 612 * 613 * G6: effective_memory_clock = memory_controller_clock * 2 614 * 615 * DRAM data rate (MT/s): 616 * 617 * HBM: effective_memory_clock * 2 = data_rate 618 * 619 * G5: effective_memory_clock * 4 = data_rate 620 * 621 * G6: effective_memory_clock * 8 = data_rate 622 * 623 * Bandwidth (MB/s): 624 * 625 * data_rate * vram_bit_width / 8 = memory_bandwidth 626 * 627 * Some examples: 628 * 629 * G5 on RX460: 630 * 631 * memory_controller_clock = 1750 Mhz 632 * 633 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 634 * 635 * data rate = 1750 * 4 = 7000 MT/s 636 * 637 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 638 * 639 * G6 on RX5700: 640 * 641 * memory_controller_clock = 875 Mhz 642 * 643 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 644 * 645 * data rate = 1750 * 8 = 14000 MT/s 646 * 647 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 648 * 649 * < For Vega10 and previous ASICs > 650 * 651 * Reading the file will display: 652 * 653 * - a list of engine clock levels and voltages labeled OD_SCLK 654 * 655 * - a list of memory clock levels and voltages labeled OD_MCLK 656 * 657 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 658 * 659 * To manually adjust these settings, first select manual using 660 * power_dpm_force_performance_level. Enter a new value for each 661 * level by writing a string that contains "s/m level clock voltage" to 662 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 663 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 664 * 810 mV. When you have edited all of the states as needed, write 665 * "c" (commit) to the file to commit your changes. If you want to reset to the 666 * default power levels, write "r" (reset) to the file to reset them. 667 * 668 * 669 * < For Vega20 and newer ASICs > 670 * 671 * Reading the file will display: 672 * 673 * - minimum and maximum engine clock labeled OD_SCLK 674 * 675 * - minimum(not available for Vega20 and Navi1x) and maximum memory 676 * clock labeled OD_MCLK 677 * 678 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 679 * They can be used to calibrate the sclk voltage curve. 680 * 681 * - voltage offset(in mV) applied on target voltage calculation. 682 * This is available for Sienna Cichlid, Navy Flounder and Dimgrey 683 * Cavefish. For these ASICs, the target voltage calculation can be 684 * illustrated by "voltage = voltage calculated from v/f curve + 685 * overdrive vddgfx offset" 686 * 687 * - a list of valid ranges for sclk, mclk, and voltage curve points 688 * labeled OD_RANGE 689 * 690 * < For APUs > 691 * 692 * Reading the file will display: 693 * 694 * - minimum and maximum engine clock labeled OD_SCLK 695 * 696 * - a list of valid ranges for sclk labeled OD_RANGE 697 * 698 * < For VanGogh > 699 * 700 * Reading the file will display: 701 * 702 * - minimum and maximum engine clock labeled OD_SCLK 703 * - minimum and maximum core clocks labeled OD_CCLK 704 * 705 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 706 * 707 * To manually adjust these settings: 708 * 709 * - First select manual using power_dpm_force_performance_level 710 * 711 * - For clock frequency setting, enter a new value by writing a 712 * string that contains "s/m index clock" to the file. The index 713 * should be 0 if to set minimum clock. And 1 if to set maximum 714 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 715 * "m 1 800" will update maximum mclk to be 800Mhz. For core 716 * clocks on VanGogh, the string contains "p core index clock". 717 * E.g., "p 2 0 800" would set the minimum core clock on core 718 * 2 to 800Mhz. 719 * 720 * For sclk voltage curve, enter the new values by writing a 721 * string that contains "vc point clock voltage" to the file. The 722 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will 723 * update point1 with clock set as 300Mhz and voltage as 724 * 600mV. "vc 2 1000 1000" will update point3 with clock set 725 * as 1000Mhz and voltage 1000mV. 726 * 727 * To update the voltage offset applied for gfxclk/voltage calculation, 728 * enter the new value by writing a string that contains "vo offset". 729 * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. 730 * And the offset can be a positive or negative value. 731 * 732 * - When you have edited all of the states as needed, write "c" (commit) 733 * to the file to commit your changes 734 * 735 * - If you want to reset to the default power levels, write "r" (reset) 736 * to the file to reset them 737 * 738 */ 739 740 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 741 struct device_attribute *attr, 742 const char *buf, 743 size_t count) 744 { 745 struct drm_device *ddev = dev_get_drvdata(dev); 746 struct amdgpu_device *adev = drm_to_adev(ddev); 747 int ret; 748 uint32_t parameter_size = 0; 749 long parameter[64]; 750 char buf_cpy[128]; 751 char *tmp_str; 752 char *sub_str; 753 const char delimiter[3] = {' ', '\n', '\0'}; 754 uint32_t type; 755 756 if (amdgpu_in_reset(adev)) 757 return -EPERM; 758 if (adev->in_suspend && !adev->in_runpm) 759 return -EPERM; 760 761 if (count > 127) 762 return -EINVAL; 763 764 if (*buf == 's') 765 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 766 else if (*buf == 'p') 767 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 768 else if (*buf == 'm') 769 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 770 else if(*buf == 'r') 771 type = PP_OD_RESTORE_DEFAULT_TABLE; 772 else if (*buf == 'c') 773 type = PP_OD_COMMIT_DPM_TABLE; 774 else if (!strncmp(buf, "vc", 2)) 775 type = PP_OD_EDIT_VDDC_CURVE; 776 else if (!strncmp(buf, "vo", 2)) 777 type = PP_OD_EDIT_VDDGFX_OFFSET; 778 else 779 return -EINVAL; 780 781 memcpy(buf_cpy, buf, count+1); 782 783 tmp_str = buf_cpy; 784 785 if ((type == PP_OD_EDIT_VDDC_CURVE) || 786 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 787 tmp_str++; 788 while (isspace(*++tmp_str)); 789 790 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 791 if (strlen(sub_str) == 0) 792 continue; 793 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 794 if (ret) 795 return -EINVAL; 796 parameter_size++; 797 798 while (isspace(*tmp_str)) 799 tmp_str++; 800 } 801 802 ret = pm_runtime_get_sync(ddev->dev); 803 if (ret < 0) { 804 pm_runtime_put_autosuspend(ddev->dev); 805 return ret; 806 } 807 808 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 809 type, 810 parameter, 811 parameter_size)) 812 goto err_out; 813 814 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 815 parameter, parameter_size)) 816 goto err_out; 817 818 if (type == PP_OD_COMMIT_DPM_TABLE) { 819 if (amdgpu_dpm_dispatch_task(adev, 820 AMD_PP_TASK_READJUST_POWER_STATE, 821 NULL)) 822 goto err_out; 823 } 824 825 pm_runtime_mark_last_busy(ddev->dev); 826 pm_runtime_put_autosuspend(ddev->dev); 827 828 return count; 829 830 err_out: 831 pm_runtime_mark_last_busy(ddev->dev); 832 pm_runtime_put_autosuspend(ddev->dev); 833 return -EINVAL; 834 } 835 836 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 837 struct device_attribute *attr, 838 char *buf) 839 { 840 struct drm_device *ddev = dev_get_drvdata(dev); 841 struct amdgpu_device *adev = drm_to_adev(ddev); 842 int size = 0; 843 int ret; 844 enum pp_clock_type od_clocks[6] = { 845 OD_SCLK, 846 OD_MCLK, 847 OD_VDDC_CURVE, 848 OD_RANGE, 849 OD_VDDGFX_OFFSET, 850 OD_CCLK, 851 }; 852 uint clk_index; 853 854 if (amdgpu_in_reset(adev)) 855 return -EPERM; 856 if (adev->in_suspend && !adev->in_runpm) 857 return -EPERM; 858 859 ret = pm_runtime_get_sync(ddev->dev); 860 if (ret < 0) { 861 pm_runtime_put_autosuspend(ddev->dev); 862 return ret; 863 } 864 865 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 866 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 867 if (ret) 868 break; 869 } 870 if (ret == -ENOENT) { 871 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 872 if (size > 0) { 873 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 874 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 875 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 876 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 877 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 878 } 879 } 880 881 if (size == 0) 882 size = sysfs_emit(buf, "\n"); 883 884 pm_runtime_mark_last_busy(ddev->dev); 885 pm_runtime_put_autosuspend(ddev->dev); 886 887 return size; 888 } 889 890 /** 891 * DOC: pp_features 892 * 893 * The amdgpu driver provides a sysfs API for adjusting what powerplay 894 * features to be enabled. The file pp_features is used for this. And 895 * this is only available for Vega10 and later dGPUs. 896 * 897 * Reading back the file will show you the followings: 898 * - Current ppfeature masks 899 * - List of the all supported powerplay features with their naming, 900 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 901 * 902 * To manually enable or disable a specific feature, just set or clear 903 * the corresponding bit from original ppfeature masks and input the 904 * new ppfeature masks. 905 */ 906 static ssize_t amdgpu_set_pp_features(struct device *dev, 907 struct device_attribute *attr, 908 const char *buf, 909 size_t count) 910 { 911 struct drm_device *ddev = dev_get_drvdata(dev); 912 struct amdgpu_device *adev = drm_to_adev(ddev); 913 uint64_t featuremask; 914 int ret; 915 916 if (amdgpu_in_reset(adev)) 917 return -EPERM; 918 if (adev->in_suspend && !adev->in_runpm) 919 return -EPERM; 920 921 ret = kstrtou64(buf, 0, &featuremask); 922 if (ret) 923 return -EINVAL; 924 925 ret = pm_runtime_get_sync(ddev->dev); 926 if (ret < 0) { 927 pm_runtime_put_autosuspend(ddev->dev); 928 return ret; 929 } 930 931 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 932 933 pm_runtime_mark_last_busy(ddev->dev); 934 pm_runtime_put_autosuspend(ddev->dev); 935 936 if (ret) 937 return -EINVAL; 938 939 return count; 940 } 941 942 static ssize_t amdgpu_get_pp_features(struct device *dev, 943 struct device_attribute *attr, 944 char *buf) 945 { 946 struct drm_device *ddev = dev_get_drvdata(dev); 947 struct amdgpu_device *adev = drm_to_adev(ddev); 948 ssize_t size; 949 int ret; 950 951 if (amdgpu_in_reset(adev)) 952 return -EPERM; 953 if (adev->in_suspend && !adev->in_runpm) 954 return -EPERM; 955 956 ret = pm_runtime_get_sync(ddev->dev); 957 if (ret < 0) { 958 pm_runtime_put_autosuspend(ddev->dev); 959 return ret; 960 } 961 962 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 963 if (size <= 0) 964 size = sysfs_emit(buf, "\n"); 965 966 pm_runtime_mark_last_busy(ddev->dev); 967 pm_runtime_put_autosuspend(ddev->dev); 968 969 return size; 970 } 971 972 /** 973 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 974 * 975 * The amdgpu driver provides a sysfs API for adjusting what power levels 976 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 977 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 978 * this. 979 * 980 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 981 * Vega10 and later ASICs. 982 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 983 * 984 * Reading back the files will show you the available power levels within 985 * the power state and the clock information for those levels. 986 * 987 * To manually adjust these states, first select manual using 988 * power_dpm_force_performance_level. 989 * Secondly, enter a new value for each level by inputing a string that 990 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 991 * E.g., 992 * 993 * .. code-block:: bash 994 * 995 * echo "4 5 6" > pp_dpm_sclk 996 * 997 * will enable sclk levels 4, 5, and 6. 998 * 999 * NOTE: change to the dcefclk max dpm level is not supported now 1000 */ 1001 1002 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 1003 enum pp_clock_type type, 1004 char *buf) 1005 { 1006 struct drm_device *ddev = dev_get_drvdata(dev); 1007 struct amdgpu_device *adev = drm_to_adev(ddev); 1008 int size = 0; 1009 int ret = 0; 1010 1011 if (amdgpu_in_reset(adev)) 1012 return -EPERM; 1013 if (adev->in_suspend && !adev->in_runpm) 1014 return -EPERM; 1015 1016 ret = pm_runtime_get_sync(ddev->dev); 1017 if (ret < 0) { 1018 pm_runtime_put_autosuspend(ddev->dev); 1019 return ret; 1020 } 1021 1022 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1023 if (ret == -ENOENT) 1024 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1025 1026 if (size == 0) 1027 size = sysfs_emit(buf, "\n"); 1028 1029 pm_runtime_mark_last_busy(ddev->dev); 1030 pm_runtime_put_autosuspend(ddev->dev); 1031 1032 return size; 1033 } 1034 1035 /* 1036 * Worst case: 32 bits individually specified, in octal at 12 characters 1037 * per line (+1 for \n). 1038 */ 1039 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1040 1041 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1042 { 1043 int ret; 1044 unsigned long level; 1045 char *sub_str = NULL; 1046 char *tmp; 1047 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1048 const char delimiter[3] = {' ', '\n', '\0'}; 1049 size_t bytes; 1050 1051 *mask = 0; 1052 1053 bytes = min(count, sizeof(buf_cpy) - 1); 1054 memcpy(buf_cpy, buf, bytes); 1055 buf_cpy[bytes] = '\0'; 1056 tmp = buf_cpy; 1057 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1058 if (strlen(sub_str)) { 1059 ret = kstrtoul(sub_str, 0, &level); 1060 if (ret || level > 31) 1061 return -EINVAL; 1062 *mask |= 1 << level; 1063 } else 1064 break; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1071 enum pp_clock_type type, 1072 const char *buf, 1073 size_t count) 1074 { 1075 struct drm_device *ddev = dev_get_drvdata(dev); 1076 struct amdgpu_device *adev = drm_to_adev(ddev); 1077 int ret; 1078 uint32_t mask = 0; 1079 1080 if (amdgpu_in_reset(adev)) 1081 return -EPERM; 1082 if (adev->in_suspend && !adev->in_runpm) 1083 return -EPERM; 1084 1085 ret = amdgpu_read_mask(buf, count, &mask); 1086 if (ret) 1087 return ret; 1088 1089 ret = pm_runtime_get_sync(ddev->dev); 1090 if (ret < 0) { 1091 pm_runtime_put_autosuspend(ddev->dev); 1092 return ret; 1093 } 1094 1095 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1096 1097 pm_runtime_mark_last_busy(ddev->dev); 1098 pm_runtime_put_autosuspend(ddev->dev); 1099 1100 if (ret) 1101 return -EINVAL; 1102 1103 return count; 1104 } 1105 1106 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1107 struct device_attribute *attr, 1108 char *buf) 1109 { 1110 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1111 } 1112 1113 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1114 struct device_attribute *attr, 1115 const char *buf, 1116 size_t count) 1117 { 1118 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1119 } 1120 1121 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1122 struct device_attribute *attr, 1123 char *buf) 1124 { 1125 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1126 } 1127 1128 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1129 struct device_attribute *attr, 1130 const char *buf, 1131 size_t count) 1132 { 1133 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1134 } 1135 1136 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1137 struct device_attribute *attr, 1138 char *buf) 1139 { 1140 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1141 } 1142 1143 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1144 struct device_attribute *attr, 1145 const char *buf, 1146 size_t count) 1147 { 1148 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1149 } 1150 1151 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1152 struct device_attribute *attr, 1153 char *buf) 1154 { 1155 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1156 } 1157 1158 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1159 struct device_attribute *attr, 1160 const char *buf, 1161 size_t count) 1162 { 1163 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1164 } 1165 1166 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1167 struct device_attribute *attr, 1168 char *buf) 1169 { 1170 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1171 } 1172 1173 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1174 struct device_attribute *attr, 1175 const char *buf, 1176 size_t count) 1177 { 1178 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1179 } 1180 1181 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1182 struct device_attribute *attr, 1183 char *buf) 1184 { 1185 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1186 } 1187 1188 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1189 struct device_attribute *attr, 1190 const char *buf, 1191 size_t count) 1192 { 1193 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1194 } 1195 1196 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1197 struct device_attribute *attr, 1198 char *buf) 1199 { 1200 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1201 } 1202 1203 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1204 struct device_attribute *attr, 1205 const char *buf, 1206 size_t count) 1207 { 1208 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1209 } 1210 1211 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1212 struct device_attribute *attr, 1213 char *buf) 1214 { 1215 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1216 } 1217 1218 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1219 struct device_attribute *attr, 1220 const char *buf, 1221 size_t count) 1222 { 1223 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1224 } 1225 1226 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1227 struct device_attribute *attr, 1228 char *buf) 1229 { 1230 struct drm_device *ddev = dev_get_drvdata(dev); 1231 struct amdgpu_device *adev = drm_to_adev(ddev); 1232 uint32_t value = 0; 1233 int ret; 1234 1235 if (amdgpu_in_reset(adev)) 1236 return -EPERM; 1237 if (adev->in_suspend && !adev->in_runpm) 1238 return -EPERM; 1239 1240 ret = pm_runtime_get_sync(ddev->dev); 1241 if (ret < 0) { 1242 pm_runtime_put_autosuspend(ddev->dev); 1243 return ret; 1244 } 1245 1246 value = amdgpu_dpm_get_sclk_od(adev); 1247 1248 pm_runtime_mark_last_busy(ddev->dev); 1249 pm_runtime_put_autosuspend(ddev->dev); 1250 1251 return sysfs_emit(buf, "%d\n", value); 1252 } 1253 1254 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1255 struct device_attribute *attr, 1256 const char *buf, 1257 size_t count) 1258 { 1259 struct drm_device *ddev = dev_get_drvdata(dev); 1260 struct amdgpu_device *adev = drm_to_adev(ddev); 1261 int ret; 1262 long int value; 1263 1264 if (amdgpu_in_reset(adev)) 1265 return -EPERM; 1266 if (adev->in_suspend && !adev->in_runpm) 1267 return -EPERM; 1268 1269 ret = kstrtol(buf, 0, &value); 1270 1271 if (ret) 1272 return -EINVAL; 1273 1274 ret = pm_runtime_get_sync(ddev->dev); 1275 if (ret < 0) { 1276 pm_runtime_put_autosuspend(ddev->dev); 1277 return ret; 1278 } 1279 1280 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1281 1282 pm_runtime_mark_last_busy(ddev->dev); 1283 pm_runtime_put_autosuspend(ddev->dev); 1284 1285 return count; 1286 } 1287 1288 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1289 struct device_attribute *attr, 1290 char *buf) 1291 { 1292 struct drm_device *ddev = dev_get_drvdata(dev); 1293 struct amdgpu_device *adev = drm_to_adev(ddev); 1294 uint32_t value = 0; 1295 int ret; 1296 1297 if (amdgpu_in_reset(adev)) 1298 return -EPERM; 1299 if (adev->in_suspend && !adev->in_runpm) 1300 return -EPERM; 1301 1302 ret = pm_runtime_get_sync(ddev->dev); 1303 if (ret < 0) { 1304 pm_runtime_put_autosuspend(ddev->dev); 1305 return ret; 1306 } 1307 1308 value = amdgpu_dpm_get_mclk_od(adev); 1309 1310 pm_runtime_mark_last_busy(ddev->dev); 1311 pm_runtime_put_autosuspend(ddev->dev); 1312 1313 return sysfs_emit(buf, "%d\n", value); 1314 } 1315 1316 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1317 struct device_attribute *attr, 1318 const char *buf, 1319 size_t count) 1320 { 1321 struct drm_device *ddev = dev_get_drvdata(dev); 1322 struct amdgpu_device *adev = drm_to_adev(ddev); 1323 int ret; 1324 long int value; 1325 1326 if (amdgpu_in_reset(adev)) 1327 return -EPERM; 1328 if (adev->in_suspend && !adev->in_runpm) 1329 return -EPERM; 1330 1331 ret = kstrtol(buf, 0, &value); 1332 1333 if (ret) 1334 return -EINVAL; 1335 1336 ret = pm_runtime_get_sync(ddev->dev); 1337 if (ret < 0) { 1338 pm_runtime_put_autosuspend(ddev->dev); 1339 return ret; 1340 } 1341 1342 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1343 1344 pm_runtime_mark_last_busy(ddev->dev); 1345 pm_runtime_put_autosuspend(ddev->dev); 1346 1347 return count; 1348 } 1349 1350 /** 1351 * DOC: pp_power_profile_mode 1352 * 1353 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1354 * related to switching between power levels in a power state. The file 1355 * pp_power_profile_mode is used for this. 1356 * 1357 * Reading this file outputs a list of all of the predefined power profiles 1358 * and the relevant heuristics settings for that profile. 1359 * 1360 * To select a profile or create a custom profile, first select manual using 1361 * power_dpm_force_performance_level. Writing the number of a predefined 1362 * profile to pp_power_profile_mode will enable those heuristics. To 1363 * create a custom set of heuristics, write a string of numbers to the file 1364 * starting with the number of the custom profile along with a setting 1365 * for each heuristic parameter. Due to differences across asic families 1366 * the heuristic parameters vary from family to family. 1367 * 1368 */ 1369 1370 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1371 struct device_attribute *attr, 1372 char *buf) 1373 { 1374 struct drm_device *ddev = dev_get_drvdata(dev); 1375 struct amdgpu_device *adev = drm_to_adev(ddev); 1376 ssize_t size; 1377 int ret; 1378 1379 if (amdgpu_in_reset(adev)) 1380 return -EPERM; 1381 if (adev->in_suspend && !adev->in_runpm) 1382 return -EPERM; 1383 1384 ret = pm_runtime_get_sync(ddev->dev); 1385 if (ret < 0) { 1386 pm_runtime_put_autosuspend(ddev->dev); 1387 return ret; 1388 } 1389 1390 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1391 if (size <= 0) 1392 size = sysfs_emit(buf, "\n"); 1393 1394 pm_runtime_mark_last_busy(ddev->dev); 1395 pm_runtime_put_autosuspend(ddev->dev); 1396 1397 return size; 1398 } 1399 1400 1401 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1402 struct device_attribute *attr, 1403 const char *buf, 1404 size_t count) 1405 { 1406 int ret; 1407 struct drm_device *ddev = dev_get_drvdata(dev); 1408 struct amdgpu_device *adev = drm_to_adev(ddev); 1409 uint32_t parameter_size = 0; 1410 long parameter[64]; 1411 char *sub_str, buf_cpy[128]; 1412 char *tmp_str; 1413 uint32_t i = 0; 1414 char tmp[2]; 1415 long int profile_mode = 0; 1416 const char delimiter[3] = {' ', '\n', '\0'}; 1417 1418 if (amdgpu_in_reset(adev)) 1419 return -EPERM; 1420 if (adev->in_suspend && !adev->in_runpm) 1421 return -EPERM; 1422 1423 tmp[0] = *(buf); 1424 tmp[1] = '\0'; 1425 ret = kstrtol(tmp, 0, &profile_mode); 1426 if (ret) 1427 return -EINVAL; 1428 1429 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1430 if (count < 2 || count > 127) 1431 return -EINVAL; 1432 while (isspace(*++buf)) 1433 i++; 1434 memcpy(buf_cpy, buf, count-i); 1435 tmp_str = buf_cpy; 1436 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1437 if (strlen(sub_str) == 0) 1438 continue; 1439 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1440 if (ret) 1441 return -EINVAL; 1442 parameter_size++; 1443 while (isspace(*tmp_str)) 1444 tmp_str++; 1445 } 1446 } 1447 parameter[parameter_size] = profile_mode; 1448 1449 ret = pm_runtime_get_sync(ddev->dev); 1450 if (ret < 0) { 1451 pm_runtime_put_autosuspend(ddev->dev); 1452 return ret; 1453 } 1454 1455 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1456 1457 pm_runtime_mark_last_busy(ddev->dev); 1458 pm_runtime_put_autosuspend(ddev->dev); 1459 1460 if (!ret) 1461 return count; 1462 1463 return -EINVAL; 1464 } 1465 1466 /** 1467 * DOC: gpu_busy_percent 1468 * 1469 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1470 * is as a percentage. The file gpu_busy_percent is used for this. 1471 * The SMU firmware computes a percentage of load based on the 1472 * aggregate activity level in the IP cores. 1473 */ 1474 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1475 struct device_attribute *attr, 1476 char *buf) 1477 { 1478 struct drm_device *ddev = dev_get_drvdata(dev); 1479 struct amdgpu_device *adev = drm_to_adev(ddev); 1480 int r, value, size = sizeof(value); 1481 1482 if (amdgpu_in_reset(adev)) 1483 return -EPERM; 1484 if (adev->in_suspend && !adev->in_runpm) 1485 return -EPERM; 1486 1487 r = pm_runtime_get_sync(ddev->dev); 1488 if (r < 0) { 1489 pm_runtime_put_autosuspend(ddev->dev); 1490 return r; 1491 } 1492 1493 /* read the IP busy sensor */ 1494 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, 1495 (void *)&value, &size); 1496 1497 pm_runtime_mark_last_busy(ddev->dev); 1498 pm_runtime_put_autosuspend(ddev->dev); 1499 1500 if (r) 1501 return r; 1502 1503 return sysfs_emit(buf, "%d\n", value); 1504 } 1505 1506 /** 1507 * DOC: mem_busy_percent 1508 * 1509 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1510 * is as a percentage. The file mem_busy_percent is used for this. 1511 * The SMU firmware computes a percentage of load based on the 1512 * aggregate activity level in the IP cores. 1513 */ 1514 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1515 struct device_attribute *attr, 1516 char *buf) 1517 { 1518 struct drm_device *ddev = dev_get_drvdata(dev); 1519 struct amdgpu_device *adev = drm_to_adev(ddev); 1520 int r, value, size = sizeof(value); 1521 1522 if (amdgpu_in_reset(adev)) 1523 return -EPERM; 1524 if (adev->in_suspend && !adev->in_runpm) 1525 return -EPERM; 1526 1527 r = pm_runtime_get_sync(ddev->dev); 1528 if (r < 0) { 1529 pm_runtime_put_autosuspend(ddev->dev); 1530 return r; 1531 } 1532 1533 /* read the IP busy sensor */ 1534 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, 1535 (void *)&value, &size); 1536 1537 pm_runtime_mark_last_busy(ddev->dev); 1538 pm_runtime_put_autosuspend(ddev->dev); 1539 1540 if (r) 1541 return r; 1542 1543 return sysfs_emit(buf, "%d\n", value); 1544 } 1545 1546 /** 1547 * DOC: pcie_bw 1548 * 1549 * The amdgpu driver provides a sysfs API for estimating how much data 1550 * has been received and sent by the GPU in the last second through PCIe. 1551 * The file pcie_bw is used for this. 1552 * The Perf counters count the number of received and sent messages and return 1553 * those values, as well as the maximum payload size of a PCIe packet (mps). 1554 * Note that it is not possible to easily and quickly obtain the size of each 1555 * packet transmitted, so we output the max payload size (mps) to allow for 1556 * quick estimation of the PCIe bandwidth usage 1557 */ 1558 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1559 struct device_attribute *attr, 1560 char *buf) 1561 { 1562 struct drm_device *ddev = dev_get_drvdata(dev); 1563 struct amdgpu_device *adev = drm_to_adev(ddev); 1564 uint64_t count0 = 0, count1 = 0; 1565 int ret; 1566 1567 if (amdgpu_in_reset(adev)) 1568 return -EPERM; 1569 if (adev->in_suspend && !adev->in_runpm) 1570 return -EPERM; 1571 1572 if (adev->flags & AMD_IS_APU) 1573 return -ENODATA; 1574 1575 if (!adev->asic_funcs->get_pcie_usage) 1576 return -ENODATA; 1577 1578 ret = pm_runtime_get_sync(ddev->dev); 1579 if (ret < 0) { 1580 pm_runtime_put_autosuspend(ddev->dev); 1581 return ret; 1582 } 1583 1584 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1585 1586 pm_runtime_mark_last_busy(ddev->dev); 1587 pm_runtime_put_autosuspend(ddev->dev); 1588 1589 return sysfs_emit(buf, "%llu %llu %i\n", 1590 count0, count1, pcie_get_mps(adev->pdev)); 1591 } 1592 1593 /** 1594 * DOC: unique_id 1595 * 1596 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1597 * The file unique_id is used for this. 1598 * This will provide a Unique ID that will persist from machine to machine 1599 * 1600 * NOTE: This will only work for GFX9 and newer. This file will be absent 1601 * on unsupported ASICs (GFX8 and older) 1602 */ 1603 static ssize_t amdgpu_get_unique_id(struct device *dev, 1604 struct device_attribute *attr, 1605 char *buf) 1606 { 1607 struct drm_device *ddev = dev_get_drvdata(dev); 1608 struct amdgpu_device *adev = drm_to_adev(ddev); 1609 1610 if (amdgpu_in_reset(adev)) 1611 return -EPERM; 1612 if (adev->in_suspend && !adev->in_runpm) 1613 return -EPERM; 1614 1615 if (adev->unique_id) 1616 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1617 1618 return 0; 1619 } 1620 1621 /** 1622 * DOC: thermal_throttling_logging 1623 * 1624 * Thermal throttling pulls down the clock frequency and thus the performance. 1625 * It's an useful mechanism to protect the chip from overheating. Since it 1626 * impacts performance, the user controls whether it is enabled and if so, 1627 * the log frequency. 1628 * 1629 * Reading back the file shows you the status(enabled or disabled) and 1630 * the interval(in seconds) between each thermal logging. 1631 * 1632 * Writing an integer to the file, sets a new logging interval, in seconds. 1633 * The value should be between 1 and 3600. If the value is less than 1, 1634 * thermal logging is disabled. Values greater than 3600 are ignored. 1635 */ 1636 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1637 struct device_attribute *attr, 1638 char *buf) 1639 { 1640 struct drm_device *ddev = dev_get_drvdata(dev); 1641 struct amdgpu_device *adev = drm_to_adev(ddev); 1642 1643 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1644 adev_to_drm(adev)->unique, 1645 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1646 adev->throttling_logging_rs.interval / HZ + 1); 1647 } 1648 1649 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1650 struct device_attribute *attr, 1651 const char *buf, 1652 size_t count) 1653 { 1654 struct drm_device *ddev = dev_get_drvdata(dev); 1655 struct amdgpu_device *adev = drm_to_adev(ddev); 1656 long throttling_logging_interval; 1657 unsigned long flags; 1658 int ret = 0; 1659 1660 ret = kstrtol(buf, 0, &throttling_logging_interval); 1661 if (ret) 1662 return ret; 1663 1664 if (throttling_logging_interval > 3600) 1665 return -EINVAL; 1666 1667 if (throttling_logging_interval > 0) { 1668 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1669 /* 1670 * Reset the ratelimit timer internals. 1671 * This can effectively restart the timer. 1672 */ 1673 adev->throttling_logging_rs.interval = 1674 (throttling_logging_interval - 1) * HZ; 1675 adev->throttling_logging_rs.begin = 0; 1676 adev->throttling_logging_rs.printed = 0; 1677 adev->throttling_logging_rs.missed = 0; 1678 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1679 1680 atomic_set(&adev->throttling_logging_enabled, 1); 1681 } else { 1682 atomic_set(&adev->throttling_logging_enabled, 0); 1683 } 1684 1685 return count; 1686 } 1687 1688 /** 1689 * DOC: gpu_metrics 1690 * 1691 * The amdgpu driver provides a sysfs API for retrieving current gpu 1692 * metrics data. The file gpu_metrics is used for this. Reading the 1693 * file will dump all the current gpu metrics data. 1694 * 1695 * These data include temperature, frequency, engines utilization, 1696 * power consume, throttler status, fan speed and cpu core statistics( 1697 * available for APU only). That's it will give a snapshot of all sensors 1698 * at the same time. 1699 */ 1700 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1701 struct device_attribute *attr, 1702 char *buf) 1703 { 1704 struct drm_device *ddev = dev_get_drvdata(dev); 1705 struct amdgpu_device *adev = drm_to_adev(ddev); 1706 void *gpu_metrics; 1707 ssize_t size = 0; 1708 int ret; 1709 1710 if (amdgpu_in_reset(adev)) 1711 return -EPERM; 1712 if (adev->in_suspend && !adev->in_runpm) 1713 return -EPERM; 1714 1715 ret = pm_runtime_get_sync(ddev->dev); 1716 if (ret < 0) { 1717 pm_runtime_put_autosuspend(ddev->dev); 1718 return ret; 1719 } 1720 1721 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1722 if (size <= 0) 1723 goto out; 1724 1725 if (size >= PAGE_SIZE) 1726 size = PAGE_SIZE - 1; 1727 1728 memcpy(buf, gpu_metrics, size); 1729 1730 out: 1731 pm_runtime_mark_last_busy(ddev->dev); 1732 pm_runtime_put_autosuspend(ddev->dev); 1733 1734 return size; 1735 } 1736 1737 /** 1738 * DOC: smartshift_apu_power 1739 * 1740 * The amdgpu driver provides a sysfs API for reporting APU power 1741 * share if it supports smartshift. The value is expressed as 1742 * the proportion of stapm limit where stapm limit is the total APU 1743 * power limit. The result is in percentage. If APU power is 130% of 1744 * STAPM, then APU is using 30% of the dGPU's headroom. 1745 */ 1746 1747 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1748 char *buf) 1749 { 1750 struct drm_device *ddev = dev_get_drvdata(dev); 1751 struct amdgpu_device *adev = drm_to_adev(ddev); 1752 uint32_t ss_power, size; 1753 int r = 0; 1754 1755 if (amdgpu_in_reset(adev)) 1756 return -EPERM; 1757 if (adev->in_suspend && !adev->in_runpm) 1758 return -EPERM; 1759 1760 r = pm_runtime_get_sync(ddev->dev); 1761 if (r < 0) { 1762 pm_runtime_put_autosuspend(ddev->dev); 1763 return r; 1764 } 1765 1766 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1767 (void *)&ss_power, &size); 1768 if (r) 1769 goto out; 1770 1771 r = sysfs_emit(buf, "%u%%\n", ss_power); 1772 1773 out: 1774 pm_runtime_mark_last_busy(ddev->dev); 1775 pm_runtime_put_autosuspend(ddev->dev); 1776 return r; 1777 } 1778 1779 /** 1780 * DOC: smartshift_dgpu_power 1781 * 1782 * The amdgpu driver provides a sysfs API for reporting the dGPU power 1783 * share if the device is in HG and supports smartshift. The value 1784 * is expressed as the proportion of stapm limit where stapm limit 1785 * is the total APU power limit. The value is in percentage. If dGPU 1786 * power is 20% higher than STAPM power(120%), it's using 20% of the 1787 * APU's power headroom. 1788 */ 1789 1790 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1791 char *buf) 1792 { 1793 struct drm_device *ddev = dev_get_drvdata(dev); 1794 struct amdgpu_device *adev = drm_to_adev(ddev); 1795 uint32_t ss_power, size; 1796 int r = 0; 1797 1798 if (amdgpu_in_reset(adev)) 1799 return -EPERM; 1800 if (adev->in_suspend && !adev->in_runpm) 1801 return -EPERM; 1802 1803 r = pm_runtime_get_sync(ddev->dev); 1804 if (r < 0) { 1805 pm_runtime_put_autosuspend(ddev->dev); 1806 return r; 1807 } 1808 1809 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1810 (void *)&ss_power, &size); 1811 1812 if (r) 1813 goto out; 1814 1815 r = sysfs_emit(buf, "%u%%\n", ss_power); 1816 1817 out: 1818 pm_runtime_mark_last_busy(ddev->dev); 1819 pm_runtime_put_autosuspend(ddev->dev); 1820 return r; 1821 } 1822 1823 /** 1824 * DOC: smartshift_bias 1825 * 1826 * The amdgpu driver provides a sysfs API for reporting the 1827 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1828 * and the default is 0. -100 sets maximum preference to APU 1829 * and 100 sets max perference to dGPU. 1830 */ 1831 1832 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1833 struct device_attribute *attr, 1834 char *buf) 1835 { 1836 int r = 0; 1837 1838 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1839 1840 return r; 1841 } 1842 1843 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1844 struct device_attribute *attr, 1845 const char *buf, size_t count) 1846 { 1847 struct drm_device *ddev = dev_get_drvdata(dev); 1848 struct amdgpu_device *adev = drm_to_adev(ddev); 1849 int r = 0; 1850 int bias = 0; 1851 1852 if (amdgpu_in_reset(adev)) 1853 return -EPERM; 1854 if (adev->in_suspend && !adev->in_runpm) 1855 return -EPERM; 1856 1857 r = pm_runtime_get_sync(ddev->dev); 1858 if (r < 0) { 1859 pm_runtime_put_autosuspend(ddev->dev); 1860 return r; 1861 } 1862 1863 r = kstrtoint(buf, 10, &bias); 1864 if (r) 1865 goto out; 1866 1867 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 1868 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 1869 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 1870 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 1871 1872 amdgpu_smartshift_bias = bias; 1873 r = count; 1874 1875 /* TODO: update bias level with SMU message */ 1876 1877 out: 1878 pm_runtime_mark_last_busy(ddev->dev); 1879 pm_runtime_put_autosuspend(ddev->dev); 1880 return r; 1881 } 1882 1883 1884 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1885 uint32_t mask, enum amdgpu_device_attr_states *states) 1886 { 1887 uint32_t ss_power, size; 1888 1889 if (!amdgpu_acpi_is_power_shift_control_supported()) 1890 *states = ATTR_STATE_UNSUPPORTED; 1891 else if ((adev->flags & AMD_IS_PX) && 1892 !amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1893 *states = ATTR_STATE_UNSUPPORTED; 1894 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1895 (void *)&ss_power, &size)) 1896 *states = ATTR_STATE_UNSUPPORTED; 1897 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1898 (void *)&ss_power, &size)) 1899 *states = ATTR_STATE_UNSUPPORTED; 1900 1901 return 0; 1902 } 1903 1904 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1905 uint32_t mask, enum amdgpu_device_attr_states *states) 1906 { 1907 uint32_t ss_power, size; 1908 1909 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1910 *states = ATTR_STATE_UNSUPPORTED; 1911 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1912 (void *)&ss_power, &size)) 1913 *states = ATTR_STATE_UNSUPPORTED; 1914 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1915 (void *)&ss_power, &size)) 1916 *states = ATTR_STATE_UNSUPPORTED; 1917 1918 return 0; 1919 } 1920 1921 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 1922 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1923 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1924 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1925 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1926 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1927 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1928 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1929 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1930 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1931 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1932 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1933 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1934 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1935 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1936 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 1937 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 1938 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1939 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), 1940 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1941 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1942 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 1943 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1944 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1945 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1946 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1947 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 1948 .attr_update = ss_power_attr_update), 1949 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 1950 .attr_update = ss_power_attr_update), 1951 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 1952 .attr_update = ss_bias_attr_update), 1953 }; 1954 1955 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1956 uint32_t mask, enum amdgpu_device_attr_states *states) 1957 { 1958 struct device_attribute *dev_attr = &attr->dev_attr; 1959 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 1960 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 1961 const char *attr_name = dev_attr->attr.name; 1962 1963 if (!(attr->flags & mask)) { 1964 *states = ATTR_STATE_UNSUPPORTED; 1965 return 0; 1966 } 1967 1968 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 1969 1970 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 1971 if (gc_ver < IP_VERSION(9, 0, 0)) 1972 *states = ATTR_STATE_UNSUPPORTED; 1973 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 1974 if (gc_ver < IP_VERSION(9, 0, 0) || 1975 gc_ver == IP_VERSION(9, 4, 1) || 1976 gc_ver == IP_VERSION(9, 4, 2)) 1977 *states = ATTR_STATE_UNSUPPORTED; 1978 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 1979 if (mp1_ver < IP_VERSION(10, 0, 0)) 1980 *states = ATTR_STATE_UNSUPPORTED; 1981 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { 1982 *states = ATTR_STATE_UNSUPPORTED; 1983 if (amdgpu_dpm_is_overdrive_supported(adev)) 1984 *states = ATTR_STATE_SUPPORTED; 1985 } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 1986 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1)) 1987 *states = ATTR_STATE_UNSUPPORTED; 1988 } else if (DEVICE_ATTR_IS(pcie_bw)) { 1989 /* PCIe Perf counters won't work on APU nodes */ 1990 if (adev->flags & AMD_IS_APU) 1991 *states = ATTR_STATE_UNSUPPORTED; 1992 } else if (DEVICE_ATTR_IS(unique_id)) { 1993 switch (gc_ver) { 1994 case IP_VERSION(9, 0, 1): 1995 case IP_VERSION(9, 4, 0): 1996 case IP_VERSION(9, 4, 1): 1997 case IP_VERSION(9, 4, 2): 1998 case IP_VERSION(10, 3, 0): 1999 case IP_VERSION(11, 0, 0): 2000 *states = ATTR_STATE_SUPPORTED; 2001 break; 2002 default: 2003 *states = ATTR_STATE_UNSUPPORTED; 2004 } 2005 } else if (DEVICE_ATTR_IS(pp_features)) { 2006 if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0)) 2007 *states = ATTR_STATE_UNSUPPORTED; 2008 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2009 if (gc_ver < IP_VERSION(9, 1, 0)) 2010 *states = ATTR_STATE_UNSUPPORTED; 2011 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2012 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2013 gc_ver == IP_VERSION(10, 3, 0) || 2014 gc_ver == IP_VERSION(10, 1, 2) || 2015 gc_ver == IP_VERSION(11, 0, 0) || 2016 gc_ver == IP_VERSION(11, 0, 2))) 2017 *states = ATTR_STATE_UNSUPPORTED; 2018 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2019 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2020 gc_ver == IP_VERSION(10, 3, 0) || 2021 gc_ver == IP_VERSION(10, 1, 2) || 2022 gc_ver == IP_VERSION(11, 0, 0) || 2023 gc_ver == IP_VERSION(11, 0, 2))) 2024 *states = ATTR_STATE_UNSUPPORTED; 2025 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2026 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2027 *states = ATTR_STATE_UNSUPPORTED; 2028 } 2029 2030 switch (gc_ver) { 2031 case IP_VERSION(9, 4, 1): 2032 case IP_VERSION(9, 4, 2): 2033 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2034 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2035 DEVICE_ATTR_IS(pp_dpm_socclk) || 2036 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2037 dev_attr->attr.mode &= ~S_IWUGO; 2038 dev_attr->store = NULL; 2039 } 2040 break; 2041 default: 2042 break; 2043 } 2044 2045 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2046 /* SMU MP1 does not support dcefclk level setting */ 2047 if (gc_ver >= IP_VERSION(10, 0, 0)) { 2048 dev_attr->attr.mode &= ~S_IWUGO; 2049 dev_attr->store = NULL; 2050 } 2051 } 2052 2053 /* setting should not be allowed from VF if not in one VF mode */ 2054 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 2055 dev_attr->attr.mode &= ~S_IWUGO; 2056 dev_attr->store = NULL; 2057 } 2058 2059 #undef DEVICE_ATTR_IS 2060 2061 return 0; 2062 } 2063 2064 2065 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2066 struct amdgpu_device_attr *attr, 2067 uint32_t mask, struct list_head *attr_list) 2068 { 2069 int ret = 0; 2070 struct device_attribute *dev_attr = &attr->dev_attr; 2071 const char *name = dev_attr->attr.name; 2072 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2073 struct amdgpu_device_attr_entry *attr_entry; 2074 2075 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2076 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2077 2078 BUG_ON(!attr); 2079 2080 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2081 2082 ret = attr_update(adev, attr, mask, &attr_states); 2083 if (ret) { 2084 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2085 name, ret); 2086 return ret; 2087 } 2088 2089 if (attr_states == ATTR_STATE_UNSUPPORTED) 2090 return 0; 2091 2092 ret = device_create_file(adev->dev, dev_attr); 2093 if (ret) { 2094 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2095 name, ret); 2096 } 2097 2098 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2099 if (!attr_entry) 2100 return -ENOMEM; 2101 2102 attr_entry->attr = attr; 2103 INIT_LIST_HEAD(&attr_entry->entry); 2104 2105 list_add_tail(&attr_entry->entry, attr_list); 2106 2107 return ret; 2108 } 2109 2110 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2111 { 2112 struct device_attribute *dev_attr = &attr->dev_attr; 2113 2114 device_remove_file(adev->dev, dev_attr); 2115 } 2116 2117 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2118 struct list_head *attr_list); 2119 2120 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2121 struct amdgpu_device_attr *attrs, 2122 uint32_t counts, 2123 uint32_t mask, 2124 struct list_head *attr_list) 2125 { 2126 int ret = 0; 2127 uint32_t i = 0; 2128 2129 for (i = 0; i < counts; i++) { 2130 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2131 if (ret) 2132 goto failed; 2133 } 2134 2135 return 0; 2136 2137 failed: 2138 amdgpu_device_attr_remove_groups(adev, attr_list); 2139 2140 return ret; 2141 } 2142 2143 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2144 struct list_head *attr_list) 2145 { 2146 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2147 2148 if (list_empty(attr_list)) 2149 return ; 2150 2151 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2152 amdgpu_device_attr_remove(adev, entry->attr); 2153 list_del(&entry->entry); 2154 kfree(entry); 2155 } 2156 } 2157 2158 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2159 struct device_attribute *attr, 2160 char *buf) 2161 { 2162 struct amdgpu_device *adev = dev_get_drvdata(dev); 2163 int channel = to_sensor_dev_attr(attr)->index; 2164 int r, temp = 0, size = sizeof(temp); 2165 2166 if (amdgpu_in_reset(adev)) 2167 return -EPERM; 2168 if (adev->in_suspend && !adev->in_runpm) 2169 return -EPERM; 2170 2171 if (channel >= PP_TEMP_MAX) 2172 return -EINVAL; 2173 2174 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2175 if (r < 0) { 2176 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2177 return r; 2178 } 2179 2180 switch (channel) { 2181 case PP_TEMP_JUNCTION: 2182 /* get current junction temperature */ 2183 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2184 (void *)&temp, &size); 2185 break; 2186 case PP_TEMP_EDGE: 2187 /* get current edge temperature */ 2188 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2189 (void *)&temp, &size); 2190 break; 2191 case PP_TEMP_MEM: 2192 /* get current memory temperature */ 2193 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2194 (void *)&temp, &size); 2195 break; 2196 default: 2197 r = -EINVAL; 2198 break; 2199 } 2200 2201 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2202 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2203 2204 if (r) 2205 return r; 2206 2207 return sysfs_emit(buf, "%d\n", temp); 2208 } 2209 2210 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2211 struct device_attribute *attr, 2212 char *buf) 2213 { 2214 struct amdgpu_device *adev = dev_get_drvdata(dev); 2215 int hyst = to_sensor_dev_attr(attr)->index; 2216 int temp; 2217 2218 if (hyst) 2219 temp = adev->pm.dpm.thermal.min_temp; 2220 else 2221 temp = adev->pm.dpm.thermal.max_temp; 2222 2223 return sysfs_emit(buf, "%d\n", temp); 2224 } 2225 2226 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2227 struct device_attribute *attr, 2228 char *buf) 2229 { 2230 struct amdgpu_device *adev = dev_get_drvdata(dev); 2231 int hyst = to_sensor_dev_attr(attr)->index; 2232 int temp; 2233 2234 if (hyst) 2235 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2236 else 2237 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2238 2239 return sysfs_emit(buf, "%d\n", temp); 2240 } 2241 2242 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2243 struct device_attribute *attr, 2244 char *buf) 2245 { 2246 struct amdgpu_device *adev = dev_get_drvdata(dev); 2247 int hyst = to_sensor_dev_attr(attr)->index; 2248 int temp; 2249 2250 if (hyst) 2251 temp = adev->pm.dpm.thermal.min_mem_temp; 2252 else 2253 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2254 2255 return sysfs_emit(buf, "%d\n", temp); 2256 } 2257 2258 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2259 struct device_attribute *attr, 2260 char *buf) 2261 { 2262 int channel = to_sensor_dev_attr(attr)->index; 2263 2264 if (channel >= PP_TEMP_MAX) 2265 return -EINVAL; 2266 2267 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2268 } 2269 2270 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2271 struct device_attribute *attr, 2272 char *buf) 2273 { 2274 struct amdgpu_device *adev = dev_get_drvdata(dev); 2275 int channel = to_sensor_dev_attr(attr)->index; 2276 int temp = 0; 2277 2278 if (channel >= PP_TEMP_MAX) 2279 return -EINVAL; 2280 2281 switch (channel) { 2282 case PP_TEMP_JUNCTION: 2283 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2284 break; 2285 case PP_TEMP_EDGE: 2286 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2287 break; 2288 case PP_TEMP_MEM: 2289 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2290 break; 2291 } 2292 2293 return sysfs_emit(buf, "%d\n", temp); 2294 } 2295 2296 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2297 struct device_attribute *attr, 2298 char *buf) 2299 { 2300 struct amdgpu_device *adev = dev_get_drvdata(dev); 2301 u32 pwm_mode = 0; 2302 int ret; 2303 2304 if (amdgpu_in_reset(adev)) 2305 return -EPERM; 2306 if (adev->in_suspend && !adev->in_runpm) 2307 return -EPERM; 2308 2309 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2310 if (ret < 0) { 2311 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2312 return ret; 2313 } 2314 2315 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2316 2317 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2318 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2319 2320 if (ret) 2321 return -EINVAL; 2322 2323 return sysfs_emit(buf, "%u\n", pwm_mode); 2324 } 2325 2326 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2327 struct device_attribute *attr, 2328 const char *buf, 2329 size_t count) 2330 { 2331 struct amdgpu_device *adev = dev_get_drvdata(dev); 2332 int err, ret; 2333 int value; 2334 2335 if (amdgpu_in_reset(adev)) 2336 return -EPERM; 2337 if (adev->in_suspend && !adev->in_runpm) 2338 return -EPERM; 2339 2340 err = kstrtoint(buf, 10, &value); 2341 if (err) 2342 return err; 2343 2344 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2345 if (ret < 0) { 2346 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2347 return ret; 2348 } 2349 2350 ret = amdgpu_dpm_set_fan_control_mode(adev, value); 2351 2352 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2353 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2354 2355 if (ret) 2356 return -EINVAL; 2357 2358 return count; 2359 } 2360 2361 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2362 struct device_attribute *attr, 2363 char *buf) 2364 { 2365 return sysfs_emit(buf, "%i\n", 0); 2366 } 2367 2368 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2369 struct device_attribute *attr, 2370 char *buf) 2371 { 2372 return sysfs_emit(buf, "%i\n", 255); 2373 } 2374 2375 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2376 struct device_attribute *attr, 2377 const char *buf, size_t count) 2378 { 2379 struct amdgpu_device *adev = dev_get_drvdata(dev); 2380 int err; 2381 u32 value; 2382 u32 pwm_mode; 2383 2384 if (amdgpu_in_reset(adev)) 2385 return -EPERM; 2386 if (adev->in_suspend && !adev->in_runpm) 2387 return -EPERM; 2388 2389 err = kstrtou32(buf, 10, &value); 2390 if (err) 2391 return err; 2392 2393 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2394 if (err < 0) { 2395 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2396 return err; 2397 } 2398 2399 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2400 if (err) 2401 goto out; 2402 2403 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2404 pr_info("manual fan speed control should be enabled first\n"); 2405 err = -EINVAL; 2406 goto out; 2407 } 2408 2409 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2410 2411 out: 2412 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2413 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2414 2415 if (err) 2416 return err; 2417 2418 return count; 2419 } 2420 2421 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2422 struct device_attribute *attr, 2423 char *buf) 2424 { 2425 struct amdgpu_device *adev = dev_get_drvdata(dev); 2426 int err; 2427 u32 speed = 0; 2428 2429 if (amdgpu_in_reset(adev)) 2430 return -EPERM; 2431 if (adev->in_suspend && !adev->in_runpm) 2432 return -EPERM; 2433 2434 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2435 if (err < 0) { 2436 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2437 return err; 2438 } 2439 2440 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2441 2442 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2443 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2444 2445 if (err) 2446 return err; 2447 2448 return sysfs_emit(buf, "%i\n", speed); 2449 } 2450 2451 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2452 struct device_attribute *attr, 2453 char *buf) 2454 { 2455 struct amdgpu_device *adev = dev_get_drvdata(dev); 2456 int err; 2457 u32 speed = 0; 2458 2459 if (amdgpu_in_reset(adev)) 2460 return -EPERM; 2461 if (adev->in_suspend && !adev->in_runpm) 2462 return -EPERM; 2463 2464 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2465 if (err < 0) { 2466 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2467 return err; 2468 } 2469 2470 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2471 2472 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2473 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2474 2475 if (err) 2476 return err; 2477 2478 return sysfs_emit(buf, "%i\n", speed); 2479 } 2480 2481 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2482 struct device_attribute *attr, 2483 char *buf) 2484 { 2485 struct amdgpu_device *adev = dev_get_drvdata(dev); 2486 u32 min_rpm = 0; 2487 u32 size = sizeof(min_rpm); 2488 int r; 2489 2490 if (amdgpu_in_reset(adev)) 2491 return -EPERM; 2492 if (adev->in_suspend && !adev->in_runpm) 2493 return -EPERM; 2494 2495 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2496 if (r < 0) { 2497 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2498 return r; 2499 } 2500 2501 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2502 (void *)&min_rpm, &size); 2503 2504 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2505 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2506 2507 if (r) 2508 return r; 2509 2510 return sysfs_emit(buf, "%d\n", min_rpm); 2511 } 2512 2513 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2514 struct device_attribute *attr, 2515 char *buf) 2516 { 2517 struct amdgpu_device *adev = dev_get_drvdata(dev); 2518 u32 max_rpm = 0; 2519 u32 size = sizeof(max_rpm); 2520 int r; 2521 2522 if (amdgpu_in_reset(adev)) 2523 return -EPERM; 2524 if (adev->in_suspend && !adev->in_runpm) 2525 return -EPERM; 2526 2527 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2528 if (r < 0) { 2529 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2530 return r; 2531 } 2532 2533 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2534 (void *)&max_rpm, &size); 2535 2536 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2537 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2538 2539 if (r) 2540 return r; 2541 2542 return sysfs_emit(buf, "%d\n", max_rpm); 2543 } 2544 2545 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2546 struct device_attribute *attr, 2547 char *buf) 2548 { 2549 struct amdgpu_device *adev = dev_get_drvdata(dev); 2550 int err; 2551 u32 rpm = 0; 2552 2553 if (amdgpu_in_reset(adev)) 2554 return -EPERM; 2555 if (adev->in_suspend && !adev->in_runpm) 2556 return -EPERM; 2557 2558 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2559 if (err < 0) { 2560 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2561 return err; 2562 } 2563 2564 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2565 2566 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2567 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2568 2569 if (err) 2570 return err; 2571 2572 return sysfs_emit(buf, "%i\n", rpm); 2573 } 2574 2575 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2576 struct device_attribute *attr, 2577 const char *buf, size_t count) 2578 { 2579 struct amdgpu_device *adev = dev_get_drvdata(dev); 2580 int err; 2581 u32 value; 2582 u32 pwm_mode; 2583 2584 if (amdgpu_in_reset(adev)) 2585 return -EPERM; 2586 if (adev->in_suspend && !adev->in_runpm) 2587 return -EPERM; 2588 2589 err = kstrtou32(buf, 10, &value); 2590 if (err) 2591 return err; 2592 2593 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2594 if (err < 0) { 2595 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2596 return err; 2597 } 2598 2599 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2600 if (err) 2601 goto out; 2602 2603 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2604 err = -ENODATA; 2605 goto out; 2606 } 2607 2608 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2609 2610 out: 2611 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2612 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2613 2614 if (err) 2615 return err; 2616 2617 return count; 2618 } 2619 2620 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2621 struct device_attribute *attr, 2622 char *buf) 2623 { 2624 struct amdgpu_device *adev = dev_get_drvdata(dev); 2625 u32 pwm_mode = 0; 2626 int ret; 2627 2628 if (amdgpu_in_reset(adev)) 2629 return -EPERM; 2630 if (adev->in_suspend && !adev->in_runpm) 2631 return -EPERM; 2632 2633 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2634 if (ret < 0) { 2635 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2636 return ret; 2637 } 2638 2639 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2640 2641 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2642 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2643 2644 if (ret) 2645 return -EINVAL; 2646 2647 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2648 } 2649 2650 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2651 struct device_attribute *attr, 2652 const char *buf, 2653 size_t count) 2654 { 2655 struct amdgpu_device *adev = dev_get_drvdata(dev); 2656 int err; 2657 int value; 2658 u32 pwm_mode; 2659 2660 if (amdgpu_in_reset(adev)) 2661 return -EPERM; 2662 if (adev->in_suspend && !adev->in_runpm) 2663 return -EPERM; 2664 2665 err = kstrtoint(buf, 10, &value); 2666 if (err) 2667 return err; 2668 2669 if (value == 0) 2670 pwm_mode = AMD_FAN_CTRL_AUTO; 2671 else if (value == 1) 2672 pwm_mode = AMD_FAN_CTRL_MANUAL; 2673 else 2674 return -EINVAL; 2675 2676 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2677 if (err < 0) { 2678 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2679 return err; 2680 } 2681 2682 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2683 2684 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2685 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2686 2687 if (err) 2688 return -EINVAL; 2689 2690 return count; 2691 } 2692 2693 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2694 struct device_attribute *attr, 2695 char *buf) 2696 { 2697 struct amdgpu_device *adev = dev_get_drvdata(dev); 2698 u32 vddgfx; 2699 int r, size = sizeof(vddgfx); 2700 2701 if (amdgpu_in_reset(adev)) 2702 return -EPERM; 2703 if (adev->in_suspend && !adev->in_runpm) 2704 return -EPERM; 2705 2706 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2707 if (r < 0) { 2708 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2709 return r; 2710 } 2711 2712 /* get the voltage */ 2713 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, 2714 (void *)&vddgfx, &size); 2715 2716 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2717 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2718 2719 if (r) 2720 return r; 2721 2722 return sysfs_emit(buf, "%d\n", vddgfx); 2723 } 2724 2725 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2726 struct device_attribute *attr, 2727 char *buf) 2728 { 2729 return sysfs_emit(buf, "vddgfx\n"); 2730 } 2731 2732 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2733 struct device_attribute *attr, 2734 char *buf) 2735 { 2736 struct amdgpu_device *adev = dev_get_drvdata(dev); 2737 u32 vddnb; 2738 int r, size = sizeof(vddnb); 2739 2740 if (amdgpu_in_reset(adev)) 2741 return -EPERM; 2742 if (adev->in_suspend && !adev->in_runpm) 2743 return -EPERM; 2744 2745 /* only APUs have vddnb */ 2746 if (!(adev->flags & AMD_IS_APU)) 2747 return -EINVAL; 2748 2749 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2750 if (r < 0) { 2751 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2752 return r; 2753 } 2754 2755 /* get the voltage */ 2756 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, 2757 (void *)&vddnb, &size); 2758 2759 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2760 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2761 2762 if (r) 2763 return r; 2764 2765 return sysfs_emit(buf, "%d\n", vddnb); 2766 } 2767 2768 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2769 struct device_attribute *attr, 2770 char *buf) 2771 { 2772 return sysfs_emit(buf, "vddnb\n"); 2773 } 2774 2775 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2776 struct device_attribute *attr, 2777 char *buf) 2778 { 2779 struct amdgpu_device *adev = dev_get_drvdata(dev); 2780 u32 query = 0; 2781 int r, size = sizeof(u32); 2782 unsigned uw; 2783 2784 if (amdgpu_in_reset(adev)) 2785 return -EPERM; 2786 if (adev->in_suspend && !adev->in_runpm) 2787 return -EPERM; 2788 2789 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2790 if (r < 0) { 2791 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2792 return r; 2793 } 2794 2795 /* get the voltage */ 2796 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, 2797 (void *)&query, &size); 2798 2799 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2800 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2801 2802 if (r) 2803 return r; 2804 2805 /* convert to microwatts */ 2806 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2807 2808 return sysfs_emit(buf, "%u\n", uw); 2809 } 2810 2811 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 2812 struct device_attribute *attr, 2813 char *buf) 2814 { 2815 return sysfs_emit(buf, "%i\n", 0); 2816 } 2817 2818 2819 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 2820 struct device_attribute *attr, 2821 char *buf, 2822 enum pp_power_limit_level pp_limit_level) 2823 { 2824 struct amdgpu_device *adev = dev_get_drvdata(dev); 2825 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 2826 uint32_t limit; 2827 ssize_t size; 2828 int r; 2829 2830 if (amdgpu_in_reset(adev)) 2831 return -EPERM; 2832 if (adev->in_suspend && !adev->in_runpm) 2833 return -EPERM; 2834 2835 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2836 if (r < 0) { 2837 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2838 return r; 2839 } 2840 2841 r = amdgpu_dpm_get_power_limit(adev, &limit, 2842 pp_limit_level, power_type); 2843 2844 if (!r) 2845 size = sysfs_emit(buf, "%u\n", limit * 1000000); 2846 else 2847 size = sysfs_emit(buf, "\n"); 2848 2849 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2850 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2851 2852 return size; 2853 } 2854 2855 2856 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 2857 struct device_attribute *attr, 2858 char *buf) 2859 { 2860 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 2861 2862 } 2863 2864 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 2865 struct device_attribute *attr, 2866 char *buf) 2867 { 2868 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 2869 2870 } 2871 2872 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 2873 struct device_attribute *attr, 2874 char *buf) 2875 { 2876 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 2877 2878 } 2879 2880 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 2881 struct device_attribute *attr, 2882 char *buf) 2883 { 2884 struct amdgpu_device *adev = dev_get_drvdata(dev); 2885 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 2886 2887 if (gc_ver == IP_VERSION(10, 3, 1)) 2888 return sysfs_emit(buf, "%s\n", 2889 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 2890 "fastPPT" : "slowPPT"); 2891 else 2892 return sysfs_emit(buf, "PPT\n"); 2893 } 2894 2895 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 2896 struct device_attribute *attr, 2897 const char *buf, 2898 size_t count) 2899 { 2900 struct amdgpu_device *adev = dev_get_drvdata(dev); 2901 int limit_type = to_sensor_dev_attr(attr)->index; 2902 int err; 2903 u32 value; 2904 2905 if (amdgpu_in_reset(adev)) 2906 return -EPERM; 2907 if (adev->in_suspend && !adev->in_runpm) 2908 return -EPERM; 2909 2910 if (amdgpu_sriov_vf(adev)) 2911 return -EINVAL; 2912 2913 err = kstrtou32(buf, 10, &value); 2914 if (err) 2915 return err; 2916 2917 value = value / 1000000; /* convert to Watt */ 2918 value |= limit_type << 24; 2919 2920 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2921 if (err < 0) { 2922 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2923 return err; 2924 } 2925 2926 err = amdgpu_dpm_set_power_limit(adev, value); 2927 2928 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2929 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2930 2931 if (err) 2932 return err; 2933 2934 return count; 2935 } 2936 2937 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 2938 struct device_attribute *attr, 2939 char *buf) 2940 { 2941 struct amdgpu_device *adev = dev_get_drvdata(dev); 2942 uint32_t sclk; 2943 int r, size = sizeof(sclk); 2944 2945 if (amdgpu_in_reset(adev)) 2946 return -EPERM; 2947 if (adev->in_suspend && !adev->in_runpm) 2948 return -EPERM; 2949 2950 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2951 if (r < 0) { 2952 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2953 return r; 2954 } 2955 2956 /* get the sclk */ 2957 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 2958 (void *)&sclk, &size); 2959 2960 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2961 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2962 2963 if (r) 2964 return r; 2965 2966 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 2967 } 2968 2969 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 2970 struct device_attribute *attr, 2971 char *buf) 2972 { 2973 return sysfs_emit(buf, "sclk\n"); 2974 } 2975 2976 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 2977 struct device_attribute *attr, 2978 char *buf) 2979 { 2980 struct amdgpu_device *adev = dev_get_drvdata(dev); 2981 uint32_t mclk; 2982 int r, size = sizeof(mclk); 2983 2984 if (amdgpu_in_reset(adev)) 2985 return -EPERM; 2986 if (adev->in_suspend && !adev->in_runpm) 2987 return -EPERM; 2988 2989 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2990 if (r < 0) { 2991 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2992 return r; 2993 } 2994 2995 /* get the sclk */ 2996 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 2997 (void *)&mclk, &size); 2998 2999 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3000 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3001 3002 if (r) 3003 return r; 3004 3005 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3006 } 3007 3008 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3009 struct device_attribute *attr, 3010 char *buf) 3011 { 3012 return sysfs_emit(buf, "mclk\n"); 3013 } 3014 3015 /** 3016 * DOC: hwmon 3017 * 3018 * The amdgpu driver exposes the following sensor interfaces: 3019 * 3020 * - GPU temperature (via the on-die sensor) 3021 * 3022 * - GPU voltage 3023 * 3024 * - Northbridge voltage (APUs only) 3025 * 3026 * - GPU power 3027 * 3028 * - GPU fan 3029 * 3030 * - GPU gfx/compute engine clock 3031 * 3032 * - GPU memory clock (dGPU only) 3033 * 3034 * hwmon interfaces for GPU temperature: 3035 * 3036 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3037 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3038 * 3039 * - temp[1-3]_label: temperature channel label 3040 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3041 * 3042 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3043 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3044 * 3045 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3046 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3047 * 3048 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3049 * - these are supported on SOC15 dGPUs only 3050 * 3051 * hwmon interfaces for GPU voltage: 3052 * 3053 * - in0_input: the voltage on the GPU in millivolts 3054 * 3055 * - in1_input: the voltage on the Northbridge in millivolts 3056 * 3057 * hwmon interfaces for GPU power: 3058 * 3059 * - power1_average: average power used by the GPU in microWatts 3060 * 3061 * - power1_cap_min: minimum cap supported in microWatts 3062 * 3063 * - power1_cap_max: maximum cap supported in microWatts 3064 * 3065 * - power1_cap: selected power cap in microWatts 3066 * 3067 * hwmon interfaces for GPU fan: 3068 * 3069 * - pwm1: pulse width modulation fan level (0-255) 3070 * 3071 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3072 * 3073 * - pwm1_min: pulse width modulation fan control minimum level (0) 3074 * 3075 * - pwm1_max: pulse width modulation fan control maximum level (255) 3076 * 3077 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3078 * 3079 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3080 * 3081 * - fan1_input: fan speed in RPM 3082 * 3083 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3084 * 3085 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3086 * 3087 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3088 * That will get the former one overridden. 3089 * 3090 * hwmon interfaces for GPU clocks: 3091 * 3092 * - freq1_input: the gfx/compute clock in hertz 3093 * 3094 * - freq2_input: the memory clock in hertz 3095 * 3096 * You can use hwmon tools like sensors to view this information on your system. 3097 * 3098 */ 3099 3100 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3101 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3102 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3103 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3104 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3105 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3106 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3107 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3108 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3109 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3110 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3111 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3112 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3113 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3114 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3115 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3116 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3117 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3118 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3119 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3120 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3121 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3122 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3123 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3124 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3125 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3126 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3127 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3128 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3129 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3130 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3131 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3132 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3133 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3134 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3135 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3136 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3137 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3138 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3139 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3140 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3141 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3142 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3143 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3144 3145 static struct attribute *hwmon_attributes[] = { 3146 &sensor_dev_attr_temp1_input.dev_attr.attr, 3147 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3148 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3149 &sensor_dev_attr_temp2_input.dev_attr.attr, 3150 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3151 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3152 &sensor_dev_attr_temp3_input.dev_attr.attr, 3153 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3154 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3155 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3156 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3157 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3158 &sensor_dev_attr_temp1_label.dev_attr.attr, 3159 &sensor_dev_attr_temp2_label.dev_attr.attr, 3160 &sensor_dev_attr_temp3_label.dev_attr.attr, 3161 &sensor_dev_attr_pwm1.dev_attr.attr, 3162 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3163 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3164 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3165 &sensor_dev_attr_fan1_input.dev_attr.attr, 3166 &sensor_dev_attr_fan1_min.dev_attr.attr, 3167 &sensor_dev_attr_fan1_max.dev_attr.attr, 3168 &sensor_dev_attr_fan1_target.dev_attr.attr, 3169 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3170 &sensor_dev_attr_in0_input.dev_attr.attr, 3171 &sensor_dev_attr_in0_label.dev_attr.attr, 3172 &sensor_dev_attr_in1_input.dev_attr.attr, 3173 &sensor_dev_attr_in1_label.dev_attr.attr, 3174 &sensor_dev_attr_power1_average.dev_attr.attr, 3175 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3176 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3177 &sensor_dev_attr_power1_cap.dev_attr.attr, 3178 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3179 &sensor_dev_attr_power1_label.dev_attr.attr, 3180 &sensor_dev_attr_power2_average.dev_attr.attr, 3181 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3182 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3183 &sensor_dev_attr_power2_cap.dev_attr.attr, 3184 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3185 &sensor_dev_attr_power2_label.dev_attr.attr, 3186 &sensor_dev_attr_freq1_input.dev_attr.attr, 3187 &sensor_dev_attr_freq1_label.dev_attr.attr, 3188 &sensor_dev_attr_freq2_input.dev_attr.attr, 3189 &sensor_dev_attr_freq2_label.dev_attr.attr, 3190 NULL 3191 }; 3192 3193 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3194 struct attribute *attr, int index) 3195 { 3196 struct device *dev = kobj_to_dev(kobj); 3197 struct amdgpu_device *adev = dev_get_drvdata(dev); 3198 umode_t effective_mode = attr->mode; 3199 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3200 3201 /* under multi-vf mode, the hwmon attributes are all not supported */ 3202 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 3203 return 0; 3204 3205 /* under pp one vf mode manage of hwmon attributes is not supported */ 3206 if (amdgpu_sriov_is_pp_one_vf(adev)) 3207 effective_mode &= ~S_IWUSR; 3208 3209 /* Skip fan attributes if fan is not present */ 3210 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3211 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3212 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3213 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3214 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3215 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3216 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3217 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3218 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3219 return 0; 3220 3221 /* Skip fan attributes on APU */ 3222 if ((adev->flags & AMD_IS_APU) && 3223 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3224 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3225 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3226 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3227 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3228 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3229 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3230 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3231 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3232 return 0; 3233 3234 /* Skip crit temp on APU */ 3235 if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) && 3236 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3237 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3238 return 0; 3239 3240 /* Skip limit attributes if DPM is not enabled */ 3241 if (!adev->pm.dpm_enabled && 3242 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3243 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3244 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3245 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3246 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3247 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3248 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3249 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3250 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3251 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3252 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3253 return 0; 3254 3255 /* mask fan attributes if we have no bindings for this asic to expose */ 3256 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3257 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3258 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3259 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3260 effective_mode &= ~S_IRUGO; 3261 3262 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3263 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3264 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3265 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3266 effective_mode &= ~S_IWUSR; 3267 3268 /* not implemented yet for GC 10.3.1 APUs */ 3269 if (((adev->family == AMDGPU_FAMILY_SI) || 3270 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) && 3271 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3272 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3273 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3274 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3275 return 0; 3276 3277 /* not implemented yet for APUs having <= GC 9.3.0 */ 3278 if (((adev->family == AMDGPU_FAMILY_SI) || 3279 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3280 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3281 return 0; 3282 3283 /* hide max/min values if we can't both query and manage the fan */ 3284 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3285 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3286 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3287 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3288 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3289 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3290 return 0; 3291 3292 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3293 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3294 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3295 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3296 return 0; 3297 3298 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3299 adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ 3300 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3301 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3302 return 0; 3303 3304 /* only APUs have vddnb */ 3305 if (!(adev->flags & AMD_IS_APU) && 3306 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3307 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3308 return 0; 3309 3310 /* no mclk on APUs */ 3311 if ((adev->flags & AMD_IS_APU) && 3312 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3313 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3314 return 0; 3315 3316 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3317 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3318 (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3319 attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3320 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr || 3321 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3322 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3323 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3324 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr || 3325 attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3326 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3327 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3328 attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) 3329 return 0; 3330 3331 /* only Vangogh has fast PPT limit and power labels */ 3332 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3333 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3334 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3335 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3336 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3337 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3338 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3339 return 0; 3340 3341 return effective_mode; 3342 } 3343 3344 static const struct attribute_group hwmon_attrgroup = { 3345 .attrs = hwmon_attributes, 3346 .is_visible = hwmon_attributes_visible, 3347 }; 3348 3349 static const struct attribute_group *hwmon_groups[] = { 3350 &hwmon_attrgroup, 3351 NULL 3352 }; 3353 3354 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 3355 { 3356 int ret; 3357 uint32_t mask = 0; 3358 3359 if (adev->pm.sysfs_initialized) 3360 return 0; 3361 3362 if (adev->pm.dpm_enabled == 0) 3363 return 0; 3364 3365 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 3366 3367 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 3368 DRIVER_NAME, adev, 3369 hwmon_groups); 3370 if (IS_ERR(adev->pm.int_hwmon_dev)) { 3371 ret = PTR_ERR(adev->pm.int_hwmon_dev); 3372 dev_err(adev->dev, 3373 "Unable to register hwmon device: %d\n", ret); 3374 return ret; 3375 } 3376 3377 switch (amdgpu_virt_get_sriov_vf_mode(adev)) { 3378 case SRIOV_VF_MODE_ONE_VF: 3379 mask = ATTR_FLAG_ONEVF; 3380 break; 3381 case SRIOV_VF_MODE_MULTI_VF: 3382 mask = 0; 3383 break; 3384 case SRIOV_VF_MODE_BARE_METAL: 3385 default: 3386 mask = ATTR_FLAG_MASK_ALL; 3387 break; 3388 } 3389 3390 ret = amdgpu_device_attr_create_groups(adev, 3391 amdgpu_device_attrs, 3392 ARRAY_SIZE(amdgpu_device_attrs), 3393 mask, 3394 &adev->pm.pm_attr_list); 3395 if (ret) 3396 return ret; 3397 3398 adev->pm.sysfs_initialized = true; 3399 3400 return 0; 3401 } 3402 3403 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 3404 { 3405 if (adev->pm.dpm_enabled == 0) 3406 return; 3407 3408 if (adev->pm.int_hwmon_dev) 3409 hwmon_device_unregister(adev->pm.int_hwmon_dev); 3410 3411 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 3412 } 3413 3414 /* 3415 * Debugfs info 3416 */ 3417 #if defined(CONFIG_DEBUG_FS) 3418 3419 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 3420 struct amdgpu_device *adev) { 3421 uint16_t *p_val; 3422 uint32_t size; 3423 int i; 3424 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 3425 3426 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 3427 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 3428 GFP_KERNEL); 3429 3430 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 3431 (void *)p_val, &size)) { 3432 for (i = 0; i < num_cpu_cores; i++) 3433 seq_printf(m, "\t%u MHz (CPU%d)\n", 3434 *(p_val + i), i); 3435 } 3436 3437 kfree(p_val); 3438 } 3439 } 3440 3441 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 3442 { 3443 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 3444 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3445 uint32_t value; 3446 uint64_t value64 = 0; 3447 uint32_t query = 0; 3448 int size; 3449 3450 /* GPU Clocks */ 3451 size = sizeof(value); 3452 seq_printf(m, "GFX Clocks and Power:\n"); 3453 3454 amdgpu_debugfs_prints_cpu_info(m, adev); 3455 3456 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 3457 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 3458 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 3459 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 3460 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 3461 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 3462 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 3463 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 3464 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 3465 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 3466 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 3467 seq_printf(m, "\t%u mV (VDDNB)\n", value); 3468 size = sizeof(uint32_t); 3469 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) 3470 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 3471 size = sizeof(value); 3472 seq_printf(m, "\n"); 3473 3474 /* GPU Temp */ 3475 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 3476 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 3477 3478 /* GPU Load */ 3479 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 3480 seq_printf(m, "GPU Load: %u %%\n", value); 3481 /* MEM Load */ 3482 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 3483 seq_printf(m, "MEM Load: %u %%\n", value); 3484 3485 seq_printf(m, "\n"); 3486 3487 /* SMC feature mask */ 3488 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 3489 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 3490 3491 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 3492 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 3493 /* VCN clocks */ 3494 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 3495 if (!value) { 3496 seq_printf(m, "VCN: Disabled\n"); 3497 } else { 3498 seq_printf(m, "VCN: Enabled\n"); 3499 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3500 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3501 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3502 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3503 } 3504 } 3505 seq_printf(m, "\n"); 3506 } else { 3507 /* UVD clocks */ 3508 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 3509 if (!value) { 3510 seq_printf(m, "UVD: Disabled\n"); 3511 } else { 3512 seq_printf(m, "UVD: Enabled\n"); 3513 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3514 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3515 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3516 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3517 } 3518 } 3519 seq_printf(m, "\n"); 3520 3521 /* VCE clocks */ 3522 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 3523 if (!value) { 3524 seq_printf(m, "VCE: Disabled\n"); 3525 } else { 3526 seq_printf(m, "VCE: Enabled\n"); 3527 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 3528 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 3529 } 3530 } 3531 } 3532 3533 return 0; 3534 } 3535 3536 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 3537 { 3538 int i; 3539 3540 for (i = 0; clocks[i].flag; i++) 3541 seq_printf(m, "\t%s: %s\n", clocks[i].name, 3542 (flags & clocks[i].flag) ? "On" : "Off"); 3543 } 3544 3545 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 3546 { 3547 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3548 struct drm_device *dev = adev_to_drm(adev); 3549 u64 flags = 0; 3550 int r; 3551 3552 if (amdgpu_in_reset(adev)) 3553 return -EPERM; 3554 if (adev->in_suspend && !adev->in_runpm) 3555 return -EPERM; 3556 3557 r = pm_runtime_get_sync(dev->dev); 3558 if (r < 0) { 3559 pm_runtime_put_autosuspend(dev->dev); 3560 return r; 3561 } 3562 3563 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 3564 r = amdgpu_debugfs_pm_info_pp(m, adev); 3565 if (r) 3566 goto out; 3567 } 3568 3569 amdgpu_device_ip_get_clockgating_state(adev, &flags); 3570 3571 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 3572 amdgpu_parse_cg_state(m, flags); 3573 seq_printf(m, "\n"); 3574 3575 out: 3576 pm_runtime_mark_last_busy(dev->dev); 3577 pm_runtime_put_autosuspend(dev->dev); 3578 3579 return r; 3580 } 3581 3582 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 3583 3584 /* 3585 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 3586 * 3587 * Reads debug memory region allocated to PMFW 3588 */ 3589 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 3590 size_t size, loff_t *pos) 3591 { 3592 struct amdgpu_device *adev = file_inode(f)->i_private; 3593 size_t smu_prv_buf_size; 3594 void *smu_prv_buf; 3595 int ret = 0; 3596 3597 if (amdgpu_in_reset(adev)) 3598 return -EPERM; 3599 if (adev->in_suspend && !adev->in_runpm) 3600 return -EPERM; 3601 3602 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 3603 if (ret) 3604 return ret; 3605 3606 if (!smu_prv_buf || !smu_prv_buf_size) 3607 return -EINVAL; 3608 3609 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 3610 smu_prv_buf_size); 3611 } 3612 3613 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 3614 .owner = THIS_MODULE, 3615 .open = simple_open, 3616 .read = amdgpu_pm_prv_buffer_read, 3617 .llseek = default_llseek, 3618 }; 3619 3620 #endif 3621 3622 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 3623 { 3624 #if defined(CONFIG_DEBUG_FS) 3625 struct drm_minor *minor = adev_to_drm(adev)->primary; 3626 struct dentry *root = minor->debugfs_root; 3627 3628 if (!adev->pm.dpm_enabled) 3629 return; 3630 3631 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 3632 &amdgpu_debugfs_pm_info_fops); 3633 3634 if (adev->pm.smu_prv_buffer_size > 0) 3635 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 3636 adev, 3637 &amdgpu_debugfs_pm_prv_buffer_fops, 3638 adev->pm.smu_prv_buffer_size); 3639 3640 amdgpu_dpm_stb_debug_fs_init(adev); 3641 #endif 3642 } 3643