1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/pci.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 #include <linux/pm_runtime.h> 36 #include <asm/processor.h> 37 38 static const struct cg_flag_name clocks[] = { 39 {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"}, 40 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 41 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 42 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 43 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 44 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 45 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 46 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 47 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 48 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 49 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 50 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 51 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 52 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 53 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 54 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 55 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 56 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 57 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 58 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 59 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 60 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 61 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 62 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 63 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 64 {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"}, 65 {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"}, 66 {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"}, 67 {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"}, 68 {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"}, 69 {AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"}, 70 {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"}, 71 {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"}, 72 {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"}, 73 {0, NULL}, 74 }; 75 76 static const struct hwmon_temp_label { 77 enum PP_HWMON_TEMP channel; 78 const char *label; 79 } temp_label[] = { 80 {PP_TEMP_EDGE, "edge"}, 81 {PP_TEMP_JUNCTION, "junction"}, 82 {PP_TEMP_MEM, "mem"}, 83 }; 84 85 const char * const amdgpu_pp_profile_name[] = { 86 "BOOTUP_DEFAULT", 87 "3D_FULL_SCREEN", 88 "POWER_SAVING", 89 "VIDEO", 90 "VR", 91 "COMPUTE", 92 "CUSTOM", 93 "WINDOW_3D", 94 "CAPPED", 95 "UNCAPPED", 96 }; 97 98 /** 99 * DOC: power_dpm_state 100 * 101 * The power_dpm_state file is a legacy interface and is only provided for 102 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 103 * certain power related parameters. The file power_dpm_state is used for this. 104 * It accepts the following arguments: 105 * 106 * - battery 107 * 108 * - balanced 109 * 110 * - performance 111 * 112 * battery 113 * 114 * On older GPUs, the vbios provided a special power state for battery 115 * operation. Selecting battery switched to this state. This is no 116 * longer provided on newer GPUs so the option does nothing in that case. 117 * 118 * balanced 119 * 120 * On older GPUs, the vbios provided a special power state for balanced 121 * operation. Selecting balanced switched to this state. This is no 122 * longer provided on newer GPUs so the option does nothing in that case. 123 * 124 * performance 125 * 126 * On older GPUs, the vbios provided a special power state for performance 127 * operation. Selecting performance switched to this state. This is no 128 * longer provided on newer GPUs so the option does nothing in that case. 129 * 130 */ 131 132 static ssize_t amdgpu_get_power_dpm_state(struct device *dev, 133 struct device_attribute *attr, 134 char *buf) 135 { 136 struct drm_device *ddev = dev_get_drvdata(dev); 137 struct amdgpu_device *adev = drm_to_adev(ddev); 138 enum amd_pm_state_type pm; 139 int ret; 140 141 if (amdgpu_in_reset(adev)) 142 return -EPERM; 143 if (adev->in_suspend && !adev->in_runpm) 144 return -EPERM; 145 146 ret = pm_runtime_get_sync(ddev->dev); 147 if (ret < 0) { 148 pm_runtime_put_autosuspend(ddev->dev); 149 return ret; 150 } 151 152 amdgpu_dpm_get_current_power_state(adev, &pm); 153 154 pm_runtime_mark_last_busy(ddev->dev); 155 pm_runtime_put_autosuspend(ddev->dev); 156 157 return sysfs_emit(buf, "%s\n", 158 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 159 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 160 } 161 162 static ssize_t amdgpu_set_power_dpm_state(struct device *dev, 163 struct device_attribute *attr, 164 const char *buf, 165 size_t count) 166 { 167 struct drm_device *ddev = dev_get_drvdata(dev); 168 struct amdgpu_device *adev = drm_to_adev(ddev); 169 enum amd_pm_state_type state; 170 int ret; 171 172 if (amdgpu_in_reset(adev)) 173 return -EPERM; 174 if (adev->in_suspend && !adev->in_runpm) 175 return -EPERM; 176 177 if (strncmp("battery", buf, strlen("battery")) == 0) 178 state = POWER_STATE_TYPE_BATTERY; 179 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 180 state = POWER_STATE_TYPE_BALANCED; 181 else if (strncmp("performance", buf, strlen("performance")) == 0) 182 state = POWER_STATE_TYPE_PERFORMANCE; 183 else 184 return -EINVAL; 185 186 ret = pm_runtime_get_sync(ddev->dev); 187 if (ret < 0) { 188 pm_runtime_put_autosuspend(ddev->dev); 189 return ret; 190 } 191 192 amdgpu_dpm_set_power_state(adev, state); 193 194 pm_runtime_mark_last_busy(ddev->dev); 195 pm_runtime_put_autosuspend(ddev->dev); 196 197 return count; 198 } 199 200 201 /** 202 * DOC: power_dpm_force_performance_level 203 * 204 * The amdgpu driver provides a sysfs API for adjusting certain power 205 * related parameters. The file power_dpm_force_performance_level is 206 * used for this. It accepts the following arguments: 207 * 208 * - auto 209 * 210 * - low 211 * 212 * - high 213 * 214 * - manual 215 * 216 * - profile_standard 217 * 218 * - profile_min_sclk 219 * 220 * - profile_min_mclk 221 * 222 * - profile_peak 223 * 224 * auto 225 * 226 * When auto is selected, the driver will attempt to dynamically select 227 * the optimal power profile for current conditions in the driver. 228 * 229 * low 230 * 231 * When low is selected, the clocks are forced to the lowest power state. 232 * 233 * high 234 * 235 * When high is selected, the clocks are forced to the highest power state. 236 * 237 * manual 238 * 239 * When manual is selected, the user can manually adjust which power states 240 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 241 * and pp_dpm_pcie files and adjust the power state transition heuristics 242 * via the pp_power_profile_mode sysfs file. 243 * 244 * profile_standard 245 * profile_min_sclk 246 * profile_min_mclk 247 * profile_peak 248 * 249 * When the profiling modes are selected, clock and power gating are 250 * disabled and the clocks are set for different profiling cases. This 251 * mode is recommended for profiling specific work loads where you do 252 * not want clock or power gating for clock fluctuation to interfere 253 * with your results. profile_standard sets the clocks to a fixed clock 254 * level which varies from asic to asic. profile_min_sclk forces the sclk 255 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 256 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 257 * 258 */ 259 260 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev, 261 struct device_attribute *attr, 262 char *buf) 263 { 264 struct drm_device *ddev = dev_get_drvdata(dev); 265 struct amdgpu_device *adev = drm_to_adev(ddev); 266 enum amd_dpm_forced_level level = 0xff; 267 int ret; 268 269 if (amdgpu_in_reset(adev)) 270 return -EPERM; 271 if (adev->in_suspend && !adev->in_runpm) 272 return -EPERM; 273 274 ret = pm_runtime_get_sync(ddev->dev); 275 if (ret < 0) { 276 pm_runtime_put_autosuspend(ddev->dev); 277 return ret; 278 } 279 280 level = amdgpu_dpm_get_performance_level(adev); 281 282 pm_runtime_mark_last_busy(ddev->dev); 283 pm_runtime_put_autosuspend(ddev->dev); 284 285 return sysfs_emit(buf, "%s\n", 286 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 287 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 288 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 289 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 290 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 291 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 292 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 293 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 294 (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" : 295 "unknown"); 296 } 297 298 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, 299 struct device_attribute *attr, 300 const char *buf, 301 size_t count) 302 { 303 struct drm_device *ddev = dev_get_drvdata(dev); 304 struct amdgpu_device *adev = drm_to_adev(ddev); 305 enum amd_dpm_forced_level level; 306 int ret = 0; 307 308 if (amdgpu_in_reset(adev)) 309 return -EPERM; 310 if (adev->in_suspend && !adev->in_runpm) 311 return -EPERM; 312 313 if (strncmp("low", buf, strlen("low")) == 0) { 314 level = AMD_DPM_FORCED_LEVEL_LOW; 315 } else if (strncmp("high", buf, strlen("high")) == 0) { 316 level = AMD_DPM_FORCED_LEVEL_HIGH; 317 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 318 level = AMD_DPM_FORCED_LEVEL_AUTO; 319 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 320 level = AMD_DPM_FORCED_LEVEL_MANUAL; 321 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 322 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 323 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 324 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 325 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 326 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 327 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 328 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 329 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 330 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 331 } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { 332 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; 333 } else { 334 return -EINVAL; 335 } 336 337 ret = pm_runtime_get_sync(ddev->dev); 338 if (ret < 0) { 339 pm_runtime_put_autosuspend(ddev->dev); 340 return ret; 341 } 342 343 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 344 if (amdgpu_dpm_force_performance_level(adev, level)) { 345 pm_runtime_mark_last_busy(ddev->dev); 346 pm_runtime_put_autosuspend(ddev->dev); 347 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 348 return -EINVAL; 349 } 350 /* override whatever a user ctx may have set */ 351 adev->pm.stable_pstate_ctx = NULL; 352 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 353 354 pm_runtime_mark_last_busy(ddev->dev); 355 pm_runtime_put_autosuspend(ddev->dev); 356 357 return count; 358 } 359 360 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 361 struct device_attribute *attr, 362 char *buf) 363 { 364 struct drm_device *ddev = dev_get_drvdata(dev); 365 struct amdgpu_device *adev = drm_to_adev(ddev); 366 struct pp_states_info data; 367 uint32_t i; 368 int buf_len, ret; 369 370 if (amdgpu_in_reset(adev)) 371 return -EPERM; 372 if (adev->in_suspend && !adev->in_runpm) 373 return -EPERM; 374 375 ret = pm_runtime_get_sync(ddev->dev); 376 if (ret < 0) { 377 pm_runtime_put_autosuspend(ddev->dev); 378 return ret; 379 } 380 381 if (amdgpu_dpm_get_pp_num_states(adev, &data)) 382 memset(&data, 0, sizeof(data)); 383 384 pm_runtime_mark_last_busy(ddev->dev); 385 pm_runtime_put_autosuspend(ddev->dev); 386 387 buf_len = sysfs_emit(buf, "states: %d\n", data.nums); 388 for (i = 0; i < data.nums; i++) 389 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i, 390 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 391 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 392 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 393 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 394 395 return buf_len; 396 } 397 398 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 399 struct device_attribute *attr, 400 char *buf) 401 { 402 struct drm_device *ddev = dev_get_drvdata(dev); 403 struct amdgpu_device *adev = drm_to_adev(ddev); 404 struct pp_states_info data = {0}; 405 enum amd_pm_state_type pm = 0; 406 int i = 0, ret = 0; 407 408 if (amdgpu_in_reset(adev)) 409 return -EPERM; 410 if (adev->in_suspend && !adev->in_runpm) 411 return -EPERM; 412 413 ret = pm_runtime_get_sync(ddev->dev); 414 if (ret < 0) { 415 pm_runtime_put_autosuspend(ddev->dev); 416 return ret; 417 } 418 419 amdgpu_dpm_get_current_power_state(adev, &pm); 420 421 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 422 423 pm_runtime_mark_last_busy(ddev->dev); 424 pm_runtime_put_autosuspend(ddev->dev); 425 426 if (ret) 427 return ret; 428 429 for (i = 0; i < data.nums; i++) { 430 if (pm == data.states[i]) 431 break; 432 } 433 434 if (i == data.nums) 435 i = -EINVAL; 436 437 return sysfs_emit(buf, "%d\n", i); 438 } 439 440 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 441 struct device_attribute *attr, 442 char *buf) 443 { 444 struct drm_device *ddev = dev_get_drvdata(dev); 445 struct amdgpu_device *adev = drm_to_adev(ddev); 446 447 if (amdgpu_in_reset(adev)) 448 return -EPERM; 449 if (adev->in_suspend && !adev->in_runpm) 450 return -EPERM; 451 452 if (adev->pm.pp_force_state_enabled) 453 return amdgpu_get_pp_cur_state(dev, attr, buf); 454 else 455 return sysfs_emit(buf, "\n"); 456 } 457 458 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 459 struct device_attribute *attr, 460 const char *buf, 461 size_t count) 462 { 463 struct drm_device *ddev = dev_get_drvdata(dev); 464 struct amdgpu_device *adev = drm_to_adev(ddev); 465 enum amd_pm_state_type state = 0; 466 struct pp_states_info data; 467 unsigned long idx; 468 int ret; 469 470 if (amdgpu_in_reset(adev)) 471 return -EPERM; 472 if (adev->in_suspend && !adev->in_runpm) 473 return -EPERM; 474 475 adev->pm.pp_force_state_enabled = false; 476 477 if (strlen(buf) == 1) 478 return count; 479 480 ret = kstrtoul(buf, 0, &idx); 481 if (ret || idx >= ARRAY_SIZE(data.states)) 482 return -EINVAL; 483 484 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 485 486 ret = pm_runtime_get_sync(ddev->dev); 487 if (ret < 0) { 488 pm_runtime_put_autosuspend(ddev->dev); 489 return ret; 490 } 491 492 ret = amdgpu_dpm_get_pp_num_states(adev, &data); 493 if (ret) 494 goto err_out; 495 496 state = data.states[idx]; 497 498 /* only set user selected power states */ 499 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 500 state != POWER_STATE_TYPE_DEFAULT) { 501 ret = amdgpu_dpm_dispatch_task(adev, 502 AMD_PP_TASK_ENABLE_USER_STATE, &state); 503 if (ret) 504 goto err_out; 505 506 adev->pm.pp_force_state_enabled = true; 507 } 508 509 pm_runtime_mark_last_busy(ddev->dev); 510 pm_runtime_put_autosuspend(ddev->dev); 511 512 return count; 513 514 err_out: 515 pm_runtime_mark_last_busy(ddev->dev); 516 pm_runtime_put_autosuspend(ddev->dev); 517 return ret; 518 } 519 520 /** 521 * DOC: pp_table 522 * 523 * The amdgpu driver provides a sysfs API for uploading new powerplay 524 * tables. The file pp_table is used for this. Reading the file 525 * will dump the current power play table. Writing to the file 526 * will attempt to upload a new powerplay table and re-initialize 527 * powerplay using that new table. 528 * 529 */ 530 531 static ssize_t amdgpu_get_pp_table(struct device *dev, 532 struct device_attribute *attr, 533 char *buf) 534 { 535 struct drm_device *ddev = dev_get_drvdata(dev); 536 struct amdgpu_device *adev = drm_to_adev(ddev); 537 char *table = NULL; 538 int size, ret; 539 540 if (amdgpu_in_reset(adev)) 541 return -EPERM; 542 if (adev->in_suspend && !adev->in_runpm) 543 return -EPERM; 544 545 ret = pm_runtime_get_sync(ddev->dev); 546 if (ret < 0) { 547 pm_runtime_put_autosuspend(ddev->dev); 548 return ret; 549 } 550 551 size = amdgpu_dpm_get_pp_table(adev, &table); 552 553 pm_runtime_mark_last_busy(ddev->dev); 554 pm_runtime_put_autosuspend(ddev->dev); 555 556 if (size <= 0) 557 return size; 558 559 if (size >= PAGE_SIZE) 560 size = PAGE_SIZE - 1; 561 562 memcpy(buf, table, size); 563 564 return size; 565 } 566 567 static ssize_t amdgpu_set_pp_table(struct device *dev, 568 struct device_attribute *attr, 569 const char *buf, 570 size_t count) 571 { 572 struct drm_device *ddev = dev_get_drvdata(dev); 573 struct amdgpu_device *adev = drm_to_adev(ddev); 574 int ret = 0; 575 576 if (amdgpu_in_reset(adev)) 577 return -EPERM; 578 if (adev->in_suspend && !adev->in_runpm) 579 return -EPERM; 580 581 ret = pm_runtime_get_sync(ddev->dev); 582 if (ret < 0) { 583 pm_runtime_put_autosuspend(ddev->dev); 584 return ret; 585 } 586 587 ret = amdgpu_dpm_set_pp_table(adev, buf, count); 588 589 pm_runtime_mark_last_busy(ddev->dev); 590 pm_runtime_put_autosuspend(ddev->dev); 591 592 if (ret) 593 return ret; 594 595 return count; 596 } 597 598 /** 599 * DOC: pp_od_clk_voltage 600 * 601 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 602 * in each power level within a power state. The pp_od_clk_voltage is used for 603 * this. 604 * 605 * Note that the actual memory controller clock rate are exposed, not 606 * the effective memory clock of the DRAMs. To translate it, use the 607 * following formula: 608 * 609 * Clock conversion (Mhz): 610 * 611 * HBM: effective_memory_clock = memory_controller_clock * 1 612 * 613 * G5: effective_memory_clock = memory_controller_clock * 1 614 * 615 * G6: effective_memory_clock = memory_controller_clock * 2 616 * 617 * DRAM data rate (MT/s): 618 * 619 * HBM: effective_memory_clock * 2 = data_rate 620 * 621 * G5: effective_memory_clock * 4 = data_rate 622 * 623 * G6: effective_memory_clock * 8 = data_rate 624 * 625 * Bandwidth (MB/s): 626 * 627 * data_rate * vram_bit_width / 8 = memory_bandwidth 628 * 629 * Some examples: 630 * 631 * G5 on RX460: 632 * 633 * memory_controller_clock = 1750 Mhz 634 * 635 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz 636 * 637 * data rate = 1750 * 4 = 7000 MT/s 638 * 639 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s 640 * 641 * G6 on RX5700: 642 * 643 * memory_controller_clock = 875 Mhz 644 * 645 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz 646 * 647 * data rate = 1750 * 8 = 14000 MT/s 648 * 649 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s 650 * 651 * < For Vega10 and previous ASICs > 652 * 653 * Reading the file will display: 654 * 655 * - a list of engine clock levels and voltages labeled OD_SCLK 656 * 657 * - a list of memory clock levels and voltages labeled OD_MCLK 658 * 659 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 660 * 661 * To manually adjust these settings, first select manual using 662 * power_dpm_force_performance_level. Enter a new value for each 663 * level by writing a string that contains "s/m level clock voltage" to 664 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 665 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 666 * 810 mV. When you have edited all of the states as needed, write 667 * "c" (commit) to the file to commit your changes. If you want to reset to the 668 * default power levels, write "r" (reset) to the file to reset them. 669 * 670 * 671 * < For Vega20 and newer ASICs > 672 * 673 * Reading the file will display: 674 * 675 * - minimum and maximum engine clock labeled OD_SCLK 676 * 677 * - minimum(not available for Vega20 and Navi1x) and maximum memory 678 * clock labeled OD_MCLK 679 * 680 * - three <frequency, voltage> points labeled OD_VDDC_CURVE. 681 * They can be used to calibrate the sclk voltage curve. 682 * 683 * - voltage offset(in mV) applied on target voltage calculation. 684 * This is available for Sienna Cichlid, Navy Flounder and Dimgrey 685 * Cavefish. For these ASICs, the target voltage calculation can be 686 * illustrated by "voltage = voltage calculated from v/f curve + 687 * overdrive vddgfx offset" 688 * 689 * - a list of valid ranges for sclk, mclk, and voltage curve points 690 * labeled OD_RANGE 691 * 692 * < For APUs > 693 * 694 * Reading the file will display: 695 * 696 * - minimum and maximum engine clock labeled OD_SCLK 697 * 698 * - a list of valid ranges for sclk labeled OD_RANGE 699 * 700 * < For VanGogh > 701 * 702 * Reading the file will display: 703 * 704 * - minimum and maximum engine clock labeled OD_SCLK 705 * - minimum and maximum core clocks labeled OD_CCLK 706 * 707 * - a list of valid ranges for sclk and cclk labeled OD_RANGE 708 * 709 * To manually adjust these settings: 710 * 711 * - First select manual using power_dpm_force_performance_level 712 * 713 * - For clock frequency setting, enter a new value by writing a 714 * string that contains "s/m index clock" to the file. The index 715 * should be 0 if to set minimum clock. And 1 if to set maximum 716 * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. 717 * "m 1 800" will update maximum mclk to be 800Mhz. For core 718 * clocks on VanGogh, the string contains "p core index clock". 719 * E.g., "p 2 0 800" would set the minimum core clock on core 720 * 2 to 800Mhz. 721 * 722 * For sclk voltage curve, enter the new values by writing a 723 * string that contains "vc point clock voltage" to the file. The 724 * points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will 725 * update point1 with clock set as 300Mhz and voltage as 726 * 600mV. "vc 2 1000 1000" will update point3 with clock set 727 * as 1000Mhz and voltage 1000mV. 728 * 729 * To update the voltage offset applied for gfxclk/voltage calculation, 730 * enter the new value by writing a string that contains "vo offset". 731 * This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish. 732 * And the offset can be a positive or negative value. 733 * 734 * - When you have edited all of the states as needed, write "c" (commit) 735 * to the file to commit your changes 736 * 737 * - If you want to reset to the default power levels, write "r" (reset) 738 * to the file to reset them 739 * 740 */ 741 742 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 743 struct device_attribute *attr, 744 const char *buf, 745 size_t count) 746 { 747 struct drm_device *ddev = dev_get_drvdata(dev); 748 struct amdgpu_device *adev = drm_to_adev(ddev); 749 int ret; 750 uint32_t parameter_size = 0; 751 long parameter[64]; 752 char buf_cpy[128]; 753 char *tmp_str; 754 char *sub_str; 755 const char delimiter[3] = {' ', '\n', '\0'}; 756 uint32_t type; 757 758 if (amdgpu_in_reset(adev)) 759 return -EPERM; 760 if (adev->in_suspend && !adev->in_runpm) 761 return -EPERM; 762 763 if (count > 127) 764 return -EINVAL; 765 766 if (*buf == 's') 767 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 768 else if (*buf == 'p') 769 type = PP_OD_EDIT_CCLK_VDDC_TABLE; 770 else if (*buf == 'm') 771 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 772 else if(*buf == 'r') 773 type = PP_OD_RESTORE_DEFAULT_TABLE; 774 else if (*buf == 'c') 775 type = PP_OD_COMMIT_DPM_TABLE; 776 else if (!strncmp(buf, "vc", 2)) 777 type = PP_OD_EDIT_VDDC_CURVE; 778 else if (!strncmp(buf, "vo", 2)) 779 type = PP_OD_EDIT_VDDGFX_OFFSET; 780 else 781 return -EINVAL; 782 783 memcpy(buf_cpy, buf, count+1); 784 785 tmp_str = buf_cpy; 786 787 if ((type == PP_OD_EDIT_VDDC_CURVE) || 788 (type == PP_OD_EDIT_VDDGFX_OFFSET)) 789 tmp_str++; 790 while (isspace(*++tmp_str)); 791 792 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 793 if (strlen(sub_str) == 0) 794 continue; 795 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 796 if (ret) 797 return -EINVAL; 798 parameter_size++; 799 800 while (isspace(*tmp_str)) 801 tmp_str++; 802 } 803 804 ret = pm_runtime_get_sync(ddev->dev); 805 if (ret < 0) { 806 pm_runtime_put_autosuspend(ddev->dev); 807 return ret; 808 } 809 810 if (amdgpu_dpm_set_fine_grain_clk_vol(adev, 811 type, 812 parameter, 813 parameter_size)) 814 goto err_out; 815 816 if (amdgpu_dpm_odn_edit_dpm_table(adev, type, 817 parameter, parameter_size)) 818 goto err_out; 819 820 if (type == PP_OD_COMMIT_DPM_TABLE) { 821 if (amdgpu_dpm_dispatch_task(adev, 822 AMD_PP_TASK_READJUST_POWER_STATE, 823 NULL)) 824 goto err_out; 825 } 826 827 pm_runtime_mark_last_busy(ddev->dev); 828 pm_runtime_put_autosuspend(ddev->dev); 829 830 return count; 831 832 err_out: 833 pm_runtime_mark_last_busy(ddev->dev); 834 pm_runtime_put_autosuspend(ddev->dev); 835 return -EINVAL; 836 } 837 838 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 839 struct device_attribute *attr, 840 char *buf) 841 { 842 struct drm_device *ddev = dev_get_drvdata(dev); 843 struct amdgpu_device *adev = drm_to_adev(ddev); 844 int size = 0; 845 int ret; 846 enum pp_clock_type od_clocks[6] = { 847 OD_SCLK, 848 OD_MCLK, 849 OD_VDDC_CURVE, 850 OD_RANGE, 851 OD_VDDGFX_OFFSET, 852 OD_CCLK, 853 }; 854 uint clk_index; 855 856 if (amdgpu_in_reset(adev)) 857 return -EPERM; 858 if (adev->in_suspend && !adev->in_runpm) 859 return -EPERM; 860 861 ret = pm_runtime_get_sync(ddev->dev); 862 if (ret < 0) { 863 pm_runtime_put_autosuspend(ddev->dev); 864 return ret; 865 } 866 867 for (clk_index = 0 ; clk_index < 6 ; clk_index++) { 868 ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); 869 if (ret) 870 break; 871 } 872 if (ret == -ENOENT) { 873 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 874 if (size > 0) { 875 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); 876 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); 877 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); 878 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); 879 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); 880 } 881 } 882 883 if (size == 0) 884 size = sysfs_emit(buf, "\n"); 885 886 pm_runtime_mark_last_busy(ddev->dev); 887 pm_runtime_put_autosuspend(ddev->dev); 888 889 return size; 890 } 891 892 /** 893 * DOC: pp_features 894 * 895 * The amdgpu driver provides a sysfs API for adjusting what powerplay 896 * features to be enabled. The file pp_features is used for this. And 897 * this is only available for Vega10 and later dGPUs. 898 * 899 * Reading back the file will show you the followings: 900 * - Current ppfeature masks 901 * - List of the all supported powerplay features with their naming, 902 * bitmasks and enablement status('Y'/'N' means "enabled"/"disabled"). 903 * 904 * To manually enable or disable a specific feature, just set or clear 905 * the corresponding bit from original ppfeature masks and input the 906 * new ppfeature masks. 907 */ 908 static ssize_t amdgpu_set_pp_features(struct device *dev, 909 struct device_attribute *attr, 910 const char *buf, 911 size_t count) 912 { 913 struct drm_device *ddev = dev_get_drvdata(dev); 914 struct amdgpu_device *adev = drm_to_adev(ddev); 915 uint64_t featuremask; 916 int ret; 917 918 if (amdgpu_in_reset(adev)) 919 return -EPERM; 920 if (adev->in_suspend && !adev->in_runpm) 921 return -EPERM; 922 923 ret = kstrtou64(buf, 0, &featuremask); 924 if (ret) 925 return -EINVAL; 926 927 ret = pm_runtime_get_sync(ddev->dev); 928 if (ret < 0) { 929 pm_runtime_put_autosuspend(ddev->dev); 930 return ret; 931 } 932 933 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask); 934 935 pm_runtime_mark_last_busy(ddev->dev); 936 pm_runtime_put_autosuspend(ddev->dev); 937 938 if (ret) 939 return -EINVAL; 940 941 return count; 942 } 943 944 static ssize_t amdgpu_get_pp_features(struct device *dev, 945 struct device_attribute *attr, 946 char *buf) 947 { 948 struct drm_device *ddev = dev_get_drvdata(dev); 949 struct amdgpu_device *adev = drm_to_adev(ddev); 950 ssize_t size; 951 int ret; 952 953 if (amdgpu_in_reset(adev)) 954 return -EPERM; 955 if (adev->in_suspend && !adev->in_runpm) 956 return -EPERM; 957 958 ret = pm_runtime_get_sync(ddev->dev); 959 if (ret < 0) { 960 pm_runtime_put_autosuspend(ddev->dev); 961 return ret; 962 } 963 964 size = amdgpu_dpm_get_ppfeature_status(adev, buf); 965 if (size <= 0) 966 size = sysfs_emit(buf, "\n"); 967 968 pm_runtime_mark_last_busy(ddev->dev); 969 pm_runtime_put_autosuspend(ddev->dev); 970 971 return size; 972 } 973 974 /** 975 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie 976 * 977 * The amdgpu driver provides a sysfs API for adjusting what power levels 978 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 979 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for 980 * this. 981 * 982 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for 983 * Vega10 and later ASICs. 984 * pp_dpm_fclk interface is only available for Vega20 and later ASICs. 985 * 986 * Reading back the files will show you the available power levels within 987 * the power state and the clock information for those levels. 988 * 989 * To manually adjust these states, first select manual using 990 * power_dpm_force_performance_level. 991 * Secondly, enter a new value for each level by inputing a string that 992 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 993 * E.g., 994 * 995 * .. code-block:: bash 996 * 997 * echo "4 5 6" > pp_dpm_sclk 998 * 999 * will enable sclk levels 4, 5, and 6. 1000 * 1001 * NOTE: change to the dcefclk max dpm level is not supported now 1002 */ 1003 1004 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, 1005 enum pp_clock_type type, 1006 char *buf) 1007 { 1008 struct drm_device *ddev = dev_get_drvdata(dev); 1009 struct amdgpu_device *adev = drm_to_adev(ddev); 1010 int size = 0; 1011 int ret = 0; 1012 1013 if (amdgpu_in_reset(adev)) 1014 return -EPERM; 1015 if (adev->in_suspend && !adev->in_runpm) 1016 return -EPERM; 1017 1018 ret = pm_runtime_get_sync(ddev->dev); 1019 if (ret < 0) { 1020 pm_runtime_put_autosuspend(ddev->dev); 1021 return ret; 1022 } 1023 1024 ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); 1025 if (ret == -ENOENT) 1026 size = amdgpu_dpm_print_clock_levels(adev, type, buf); 1027 1028 if (size == 0) 1029 size = sysfs_emit(buf, "\n"); 1030 1031 pm_runtime_mark_last_busy(ddev->dev); 1032 pm_runtime_put_autosuspend(ddev->dev); 1033 1034 return size; 1035 } 1036 1037 /* 1038 * Worst case: 32 bits individually specified, in octal at 12 characters 1039 * per line (+1 for \n). 1040 */ 1041 #define AMDGPU_MASK_BUF_MAX (32 * 13) 1042 1043 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 1044 { 1045 int ret; 1046 unsigned long level; 1047 char *sub_str = NULL; 1048 char *tmp; 1049 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 1050 const char delimiter[3] = {' ', '\n', '\0'}; 1051 size_t bytes; 1052 1053 *mask = 0; 1054 1055 bytes = min(count, sizeof(buf_cpy) - 1); 1056 memcpy(buf_cpy, buf, bytes); 1057 buf_cpy[bytes] = '\0'; 1058 tmp = buf_cpy; 1059 while ((sub_str = strsep(&tmp, delimiter)) != NULL) { 1060 if (strlen(sub_str)) { 1061 ret = kstrtoul(sub_str, 0, &level); 1062 if (ret || level > 31) 1063 return -EINVAL; 1064 *mask |= 1 << level; 1065 } else 1066 break; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev, 1073 enum pp_clock_type type, 1074 const char *buf, 1075 size_t count) 1076 { 1077 struct drm_device *ddev = dev_get_drvdata(dev); 1078 struct amdgpu_device *adev = drm_to_adev(ddev); 1079 int ret; 1080 uint32_t mask = 0; 1081 1082 if (amdgpu_in_reset(adev)) 1083 return -EPERM; 1084 if (adev->in_suspend && !adev->in_runpm) 1085 return -EPERM; 1086 1087 ret = amdgpu_read_mask(buf, count, &mask); 1088 if (ret) 1089 return ret; 1090 1091 ret = pm_runtime_get_sync(ddev->dev); 1092 if (ret < 0) { 1093 pm_runtime_put_autosuspend(ddev->dev); 1094 return ret; 1095 } 1096 1097 ret = amdgpu_dpm_force_clock_level(adev, type, mask); 1098 1099 pm_runtime_mark_last_busy(ddev->dev); 1100 pm_runtime_put_autosuspend(ddev->dev); 1101 1102 if (ret) 1103 return -EINVAL; 1104 1105 return count; 1106 } 1107 1108 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 1109 struct device_attribute *attr, 1110 char *buf) 1111 { 1112 return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf); 1113 } 1114 1115 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 1116 struct device_attribute *attr, 1117 const char *buf, 1118 size_t count) 1119 { 1120 return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count); 1121 } 1122 1123 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 1124 struct device_attribute *attr, 1125 char *buf) 1126 { 1127 return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf); 1128 } 1129 1130 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 1131 struct device_attribute *attr, 1132 const char *buf, 1133 size_t count) 1134 { 1135 return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count); 1136 } 1137 1138 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev, 1139 struct device_attribute *attr, 1140 char *buf) 1141 { 1142 return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf); 1143 } 1144 1145 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev, 1146 struct device_attribute *attr, 1147 const char *buf, 1148 size_t count) 1149 { 1150 return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count); 1151 } 1152 1153 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev, 1154 struct device_attribute *attr, 1155 char *buf) 1156 { 1157 return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf); 1158 } 1159 1160 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev, 1161 struct device_attribute *attr, 1162 const char *buf, 1163 size_t count) 1164 { 1165 return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count); 1166 } 1167 1168 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, 1169 struct device_attribute *attr, 1170 char *buf) 1171 { 1172 return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf); 1173 } 1174 1175 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, 1176 struct device_attribute *attr, 1177 const char *buf, 1178 size_t count) 1179 { 1180 return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count); 1181 } 1182 1183 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, 1184 struct device_attribute *attr, 1185 char *buf) 1186 { 1187 return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf); 1188 } 1189 1190 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, 1191 struct device_attribute *attr, 1192 const char *buf, 1193 size_t count) 1194 { 1195 return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count); 1196 } 1197 1198 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev, 1199 struct device_attribute *attr, 1200 char *buf) 1201 { 1202 return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf); 1203 } 1204 1205 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev, 1206 struct device_attribute *attr, 1207 const char *buf, 1208 size_t count) 1209 { 1210 return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count); 1211 } 1212 1213 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 1214 struct device_attribute *attr, 1215 char *buf) 1216 { 1217 return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf); 1218 } 1219 1220 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 1221 struct device_attribute *attr, 1222 const char *buf, 1223 size_t count) 1224 { 1225 return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count); 1226 } 1227 1228 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 1229 struct device_attribute *attr, 1230 char *buf) 1231 { 1232 struct drm_device *ddev = dev_get_drvdata(dev); 1233 struct amdgpu_device *adev = drm_to_adev(ddev); 1234 uint32_t value = 0; 1235 int ret; 1236 1237 if (amdgpu_in_reset(adev)) 1238 return -EPERM; 1239 if (adev->in_suspend && !adev->in_runpm) 1240 return -EPERM; 1241 1242 ret = pm_runtime_get_sync(ddev->dev); 1243 if (ret < 0) { 1244 pm_runtime_put_autosuspend(ddev->dev); 1245 return ret; 1246 } 1247 1248 value = amdgpu_dpm_get_sclk_od(adev); 1249 1250 pm_runtime_mark_last_busy(ddev->dev); 1251 pm_runtime_put_autosuspend(ddev->dev); 1252 1253 return sysfs_emit(buf, "%d\n", value); 1254 } 1255 1256 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 1257 struct device_attribute *attr, 1258 const char *buf, 1259 size_t count) 1260 { 1261 struct drm_device *ddev = dev_get_drvdata(dev); 1262 struct amdgpu_device *adev = drm_to_adev(ddev); 1263 int ret; 1264 long int value; 1265 1266 if (amdgpu_in_reset(adev)) 1267 return -EPERM; 1268 if (adev->in_suspend && !adev->in_runpm) 1269 return -EPERM; 1270 1271 ret = kstrtol(buf, 0, &value); 1272 1273 if (ret) 1274 return -EINVAL; 1275 1276 ret = pm_runtime_get_sync(ddev->dev); 1277 if (ret < 0) { 1278 pm_runtime_put_autosuspend(ddev->dev); 1279 return ret; 1280 } 1281 1282 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 1283 1284 pm_runtime_mark_last_busy(ddev->dev); 1285 pm_runtime_put_autosuspend(ddev->dev); 1286 1287 return count; 1288 } 1289 1290 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 1291 struct device_attribute *attr, 1292 char *buf) 1293 { 1294 struct drm_device *ddev = dev_get_drvdata(dev); 1295 struct amdgpu_device *adev = drm_to_adev(ddev); 1296 uint32_t value = 0; 1297 int ret; 1298 1299 if (amdgpu_in_reset(adev)) 1300 return -EPERM; 1301 if (adev->in_suspend && !adev->in_runpm) 1302 return -EPERM; 1303 1304 ret = pm_runtime_get_sync(ddev->dev); 1305 if (ret < 0) { 1306 pm_runtime_put_autosuspend(ddev->dev); 1307 return ret; 1308 } 1309 1310 value = amdgpu_dpm_get_mclk_od(adev); 1311 1312 pm_runtime_mark_last_busy(ddev->dev); 1313 pm_runtime_put_autosuspend(ddev->dev); 1314 1315 return sysfs_emit(buf, "%d\n", value); 1316 } 1317 1318 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 1319 struct device_attribute *attr, 1320 const char *buf, 1321 size_t count) 1322 { 1323 struct drm_device *ddev = dev_get_drvdata(dev); 1324 struct amdgpu_device *adev = drm_to_adev(ddev); 1325 int ret; 1326 long int value; 1327 1328 if (amdgpu_in_reset(adev)) 1329 return -EPERM; 1330 if (adev->in_suspend && !adev->in_runpm) 1331 return -EPERM; 1332 1333 ret = kstrtol(buf, 0, &value); 1334 1335 if (ret) 1336 return -EINVAL; 1337 1338 ret = pm_runtime_get_sync(ddev->dev); 1339 if (ret < 0) { 1340 pm_runtime_put_autosuspend(ddev->dev); 1341 return ret; 1342 } 1343 1344 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 1345 1346 pm_runtime_mark_last_busy(ddev->dev); 1347 pm_runtime_put_autosuspend(ddev->dev); 1348 1349 return count; 1350 } 1351 1352 /** 1353 * DOC: pp_power_profile_mode 1354 * 1355 * The amdgpu driver provides a sysfs API for adjusting the heuristics 1356 * related to switching between power levels in a power state. The file 1357 * pp_power_profile_mode is used for this. 1358 * 1359 * Reading this file outputs a list of all of the predefined power profiles 1360 * and the relevant heuristics settings for that profile. 1361 * 1362 * To select a profile or create a custom profile, first select manual using 1363 * power_dpm_force_performance_level. Writing the number of a predefined 1364 * profile to pp_power_profile_mode will enable those heuristics. To 1365 * create a custom set of heuristics, write a string of numbers to the file 1366 * starting with the number of the custom profile along with a setting 1367 * for each heuristic parameter. Due to differences across asic families 1368 * the heuristic parameters vary from family to family. 1369 * 1370 */ 1371 1372 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 1373 struct device_attribute *attr, 1374 char *buf) 1375 { 1376 struct drm_device *ddev = dev_get_drvdata(dev); 1377 struct amdgpu_device *adev = drm_to_adev(ddev); 1378 ssize_t size; 1379 int ret; 1380 1381 if (amdgpu_in_reset(adev)) 1382 return -EPERM; 1383 if (adev->in_suspend && !adev->in_runpm) 1384 return -EPERM; 1385 1386 ret = pm_runtime_get_sync(ddev->dev); 1387 if (ret < 0) { 1388 pm_runtime_put_autosuspend(ddev->dev); 1389 return ret; 1390 } 1391 1392 size = amdgpu_dpm_get_power_profile_mode(adev, buf); 1393 if (size <= 0) 1394 size = sysfs_emit(buf, "\n"); 1395 1396 pm_runtime_mark_last_busy(ddev->dev); 1397 pm_runtime_put_autosuspend(ddev->dev); 1398 1399 return size; 1400 } 1401 1402 1403 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 1404 struct device_attribute *attr, 1405 const char *buf, 1406 size_t count) 1407 { 1408 int ret; 1409 struct drm_device *ddev = dev_get_drvdata(dev); 1410 struct amdgpu_device *adev = drm_to_adev(ddev); 1411 uint32_t parameter_size = 0; 1412 long parameter[64]; 1413 char *sub_str, buf_cpy[128]; 1414 char *tmp_str; 1415 uint32_t i = 0; 1416 char tmp[2]; 1417 long int profile_mode = 0; 1418 const char delimiter[3] = {' ', '\n', '\0'}; 1419 1420 if (amdgpu_in_reset(adev)) 1421 return -EPERM; 1422 if (adev->in_suspend && !adev->in_runpm) 1423 return -EPERM; 1424 1425 tmp[0] = *(buf); 1426 tmp[1] = '\0'; 1427 ret = kstrtol(tmp, 0, &profile_mode); 1428 if (ret) 1429 return -EINVAL; 1430 1431 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 1432 if (count < 2 || count > 127) 1433 return -EINVAL; 1434 while (isspace(*++buf)) 1435 i++; 1436 memcpy(buf_cpy, buf, count-i); 1437 tmp_str = buf_cpy; 1438 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) { 1439 if (strlen(sub_str) == 0) 1440 continue; 1441 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 1442 if (ret) 1443 return -EINVAL; 1444 parameter_size++; 1445 while (isspace(*tmp_str)) 1446 tmp_str++; 1447 } 1448 } 1449 parameter[parameter_size] = profile_mode; 1450 1451 ret = pm_runtime_get_sync(ddev->dev); 1452 if (ret < 0) { 1453 pm_runtime_put_autosuspend(ddev->dev); 1454 return ret; 1455 } 1456 1457 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 1458 1459 pm_runtime_mark_last_busy(ddev->dev); 1460 pm_runtime_put_autosuspend(ddev->dev); 1461 1462 if (!ret) 1463 return count; 1464 1465 return -EINVAL; 1466 } 1467 1468 /** 1469 * DOC: gpu_busy_percent 1470 * 1471 * The amdgpu driver provides a sysfs API for reading how busy the GPU 1472 * is as a percentage. The file gpu_busy_percent is used for this. 1473 * The SMU firmware computes a percentage of load based on the 1474 * aggregate activity level in the IP cores. 1475 */ 1476 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev, 1477 struct device_attribute *attr, 1478 char *buf) 1479 { 1480 struct drm_device *ddev = dev_get_drvdata(dev); 1481 struct amdgpu_device *adev = drm_to_adev(ddev); 1482 int r, value, size = sizeof(value); 1483 1484 if (amdgpu_in_reset(adev)) 1485 return -EPERM; 1486 if (adev->in_suspend && !adev->in_runpm) 1487 return -EPERM; 1488 1489 r = pm_runtime_get_sync(ddev->dev); 1490 if (r < 0) { 1491 pm_runtime_put_autosuspend(ddev->dev); 1492 return r; 1493 } 1494 1495 /* read the IP busy sensor */ 1496 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, 1497 (void *)&value, &size); 1498 1499 pm_runtime_mark_last_busy(ddev->dev); 1500 pm_runtime_put_autosuspend(ddev->dev); 1501 1502 if (r) 1503 return r; 1504 1505 return sysfs_emit(buf, "%d\n", value); 1506 } 1507 1508 /** 1509 * DOC: mem_busy_percent 1510 * 1511 * The amdgpu driver provides a sysfs API for reading how busy the VRAM 1512 * is as a percentage. The file mem_busy_percent is used for this. 1513 * The SMU firmware computes a percentage of load based on the 1514 * aggregate activity level in the IP cores. 1515 */ 1516 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev, 1517 struct device_attribute *attr, 1518 char *buf) 1519 { 1520 struct drm_device *ddev = dev_get_drvdata(dev); 1521 struct amdgpu_device *adev = drm_to_adev(ddev); 1522 int r, value, size = sizeof(value); 1523 1524 if (amdgpu_in_reset(adev)) 1525 return -EPERM; 1526 if (adev->in_suspend && !adev->in_runpm) 1527 return -EPERM; 1528 1529 r = pm_runtime_get_sync(ddev->dev); 1530 if (r < 0) { 1531 pm_runtime_put_autosuspend(ddev->dev); 1532 return r; 1533 } 1534 1535 /* read the IP busy sensor */ 1536 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, 1537 (void *)&value, &size); 1538 1539 pm_runtime_mark_last_busy(ddev->dev); 1540 pm_runtime_put_autosuspend(ddev->dev); 1541 1542 if (r) 1543 return r; 1544 1545 return sysfs_emit(buf, "%d\n", value); 1546 } 1547 1548 /** 1549 * DOC: pcie_bw 1550 * 1551 * The amdgpu driver provides a sysfs API for estimating how much data 1552 * has been received and sent by the GPU in the last second through PCIe. 1553 * The file pcie_bw is used for this. 1554 * The Perf counters count the number of received and sent messages and return 1555 * those values, as well as the maximum payload size of a PCIe packet (mps). 1556 * Note that it is not possible to easily and quickly obtain the size of each 1557 * packet transmitted, so we output the max payload size (mps) to allow for 1558 * quick estimation of the PCIe bandwidth usage 1559 */ 1560 static ssize_t amdgpu_get_pcie_bw(struct device *dev, 1561 struct device_attribute *attr, 1562 char *buf) 1563 { 1564 struct drm_device *ddev = dev_get_drvdata(dev); 1565 struct amdgpu_device *adev = drm_to_adev(ddev); 1566 uint64_t count0 = 0, count1 = 0; 1567 int ret; 1568 1569 if (amdgpu_in_reset(adev)) 1570 return -EPERM; 1571 if (adev->in_suspend && !adev->in_runpm) 1572 return -EPERM; 1573 1574 if (adev->flags & AMD_IS_APU) 1575 return -ENODATA; 1576 1577 if (!adev->asic_funcs->get_pcie_usage) 1578 return -ENODATA; 1579 1580 ret = pm_runtime_get_sync(ddev->dev); 1581 if (ret < 0) { 1582 pm_runtime_put_autosuspend(ddev->dev); 1583 return ret; 1584 } 1585 1586 amdgpu_asic_get_pcie_usage(adev, &count0, &count1); 1587 1588 pm_runtime_mark_last_busy(ddev->dev); 1589 pm_runtime_put_autosuspend(ddev->dev); 1590 1591 return sysfs_emit(buf, "%llu %llu %i\n", 1592 count0, count1, pcie_get_mps(adev->pdev)); 1593 } 1594 1595 /** 1596 * DOC: unique_id 1597 * 1598 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU 1599 * The file unique_id is used for this. 1600 * This will provide a Unique ID that will persist from machine to machine 1601 * 1602 * NOTE: This will only work for GFX9 and newer. This file will be absent 1603 * on unsupported ASICs (GFX8 and older) 1604 */ 1605 static ssize_t amdgpu_get_unique_id(struct device *dev, 1606 struct device_attribute *attr, 1607 char *buf) 1608 { 1609 struct drm_device *ddev = dev_get_drvdata(dev); 1610 struct amdgpu_device *adev = drm_to_adev(ddev); 1611 1612 if (amdgpu_in_reset(adev)) 1613 return -EPERM; 1614 if (adev->in_suspend && !adev->in_runpm) 1615 return -EPERM; 1616 1617 if (adev->unique_id) 1618 return sysfs_emit(buf, "%016llx\n", adev->unique_id); 1619 1620 return 0; 1621 } 1622 1623 /** 1624 * DOC: thermal_throttling_logging 1625 * 1626 * Thermal throttling pulls down the clock frequency and thus the performance. 1627 * It's an useful mechanism to protect the chip from overheating. Since it 1628 * impacts performance, the user controls whether it is enabled and if so, 1629 * the log frequency. 1630 * 1631 * Reading back the file shows you the status(enabled or disabled) and 1632 * the interval(in seconds) between each thermal logging. 1633 * 1634 * Writing an integer to the file, sets a new logging interval, in seconds. 1635 * The value should be between 1 and 3600. If the value is less than 1, 1636 * thermal logging is disabled. Values greater than 3600 are ignored. 1637 */ 1638 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev, 1639 struct device_attribute *attr, 1640 char *buf) 1641 { 1642 struct drm_device *ddev = dev_get_drvdata(dev); 1643 struct amdgpu_device *adev = drm_to_adev(ddev); 1644 1645 return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n", 1646 adev_to_drm(adev)->unique, 1647 atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled", 1648 adev->throttling_logging_rs.interval / HZ + 1); 1649 } 1650 1651 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev, 1652 struct device_attribute *attr, 1653 const char *buf, 1654 size_t count) 1655 { 1656 struct drm_device *ddev = dev_get_drvdata(dev); 1657 struct amdgpu_device *adev = drm_to_adev(ddev); 1658 long throttling_logging_interval; 1659 unsigned long flags; 1660 int ret = 0; 1661 1662 ret = kstrtol(buf, 0, &throttling_logging_interval); 1663 if (ret) 1664 return ret; 1665 1666 if (throttling_logging_interval > 3600) 1667 return -EINVAL; 1668 1669 if (throttling_logging_interval > 0) { 1670 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags); 1671 /* 1672 * Reset the ratelimit timer internals. 1673 * This can effectively restart the timer. 1674 */ 1675 adev->throttling_logging_rs.interval = 1676 (throttling_logging_interval - 1) * HZ; 1677 adev->throttling_logging_rs.begin = 0; 1678 adev->throttling_logging_rs.printed = 0; 1679 adev->throttling_logging_rs.missed = 0; 1680 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags); 1681 1682 atomic_set(&adev->throttling_logging_enabled, 1); 1683 } else { 1684 atomic_set(&adev->throttling_logging_enabled, 0); 1685 } 1686 1687 return count; 1688 } 1689 1690 /** 1691 * DOC: apu_thermal_cap 1692 * 1693 * The amdgpu driver provides a sysfs API for retrieving/updating thermal 1694 * limit temperature in millidegrees Celsius 1695 * 1696 * Reading back the file shows you core limit value 1697 * 1698 * Writing an integer to the file, sets a new thermal limit. The value 1699 * should be between 0 and 100. If the value is less than 0 or greater 1700 * than 100, then the write request will be ignored. 1701 */ 1702 static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev, 1703 struct device_attribute *attr, 1704 char *buf) 1705 { 1706 int ret, size; 1707 u32 limit; 1708 struct drm_device *ddev = dev_get_drvdata(dev); 1709 struct amdgpu_device *adev = drm_to_adev(ddev); 1710 1711 ret = pm_runtime_get_sync(ddev->dev); 1712 if (ret < 0) { 1713 pm_runtime_put_autosuspend(ddev->dev); 1714 return ret; 1715 } 1716 1717 ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit); 1718 if (!ret) 1719 size = sysfs_emit(buf, "%u\n", limit); 1720 else 1721 size = sysfs_emit(buf, "failed to get thermal limit\n"); 1722 1723 pm_runtime_mark_last_busy(ddev->dev); 1724 pm_runtime_put_autosuspend(ddev->dev); 1725 1726 return size; 1727 } 1728 1729 static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev, 1730 struct device_attribute *attr, 1731 const char *buf, 1732 size_t count) 1733 { 1734 int ret; 1735 u32 value; 1736 struct drm_device *ddev = dev_get_drvdata(dev); 1737 struct amdgpu_device *adev = drm_to_adev(ddev); 1738 1739 ret = kstrtou32(buf, 10, &value); 1740 if (ret) 1741 return ret; 1742 1743 if (value > 100) { 1744 dev_err(dev, "Invalid argument !\n"); 1745 return -EINVAL; 1746 } 1747 1748 ret = pm_runtime_get_sync(ddev->dev); 1749 if (ret < 0) { 1750 pm_runtime_put_autosuspend(ddev->dev); 1751 return ret; 1752 } 1753 1754 ret = amdgpu_dpm_set_apu_thermal_limit(adev, value); 1755 if (ret) { 1756 dev_err(dev, "failed to update thermal limit\n"); 1757 return ret; 1758 } 1759 1760 pm_runtime_mark_last_busy(ddev->dev); 1761 pm_runtime_put_autosuspend(ddev->dev); 1762 1763 return count; 1764 } 1765 1766 /** 1767 * DOC: gpu_metrics 1768 * 1769 * The amdgpu driver provides a sysfs API for retrieving current gpu 1770 * metrics data. The file gpu_metrics is used for this. Reading the 1771 * file will dump all the current gpu metrics data. 1772 * 1773 * These data include temperature, frequency, engines utilization, 1774 * power consume, throttler status, fan speed and cpu core statistics( 1775 * available for APU only). That's it will give a snapshot of all sensors 1776 * at the same time. 1777 */ 1778 static ssize_t amdgpu_get_gpu_metrics(struct device *dev, 1779 struct device_attribute *attr, 1780 char *buf) 1781 { 1782 struct drm_device *ddev = dev_get_drvdata(dev); 1783 struct amdgpu_device *adev = drm_to_adev(ddev); 1784 void *gpu_metrics; 1785 ssize_t size = 0; 1786 int ret; 1787 1788 if (amdgpu_in_reset(adev)) 1789 return -EPERM; 1790 if (adev->in_suspend && !adev->in_runpm) 1791 return -EPERM; 1792 1793 ret = pm_runtime_get_sync(ddev->dev); 1794 if (ret < 0) { 1795 pm_runtime_put_autosuspend(ddev->dev); 1796 return ret; 1797 } 1798 1799 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics); 1800 if (size <= 0) 1801 goto out; 1802 1803 if (size >= PAGE_SIZE) 1804 size = PAGE_SIZE - 1; 1805 1806 memcpy(buf, gpu_metrics, size); 1807 1808 out: 1809 pm_runtime_mark_last_busy(ddev->dev); 1810 pm_runtime_put_autosuspend(ddev->dev); 1811 1812 return size; 1813 } 1814 1815 static int amdgpu_device_read_powershift(struct amdgpu_device *adev, 1816 uint32_t *ss_power, bool dgpu_share) 1817 { 1818 struct drm_device *ddev = adev_to_drm(adev); 1819 uint32_t size; 1820 int r = 0; 1821 1822 if (amdgpu_in_reset(adev)) 1823 return -EPERM; 1824 if (adev->in_suspend && !adev->in_runpm) 1825 return -EPERM; 1826 1827 r = pm_runtime_get_sync(ddev->dev); 1828 if (r < 0) { 1829 pm_runtime_put_autosuspend(ddev->dev); 1830 return r; 1831 } 1832 1833 if (dgpu_share) 1834 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1835 (void *)ss_power, &size); 1836 else 1837 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1838 (void *)ss_power, &size); 1839 1840 pm_runtime_mark_last_busy(ddev->dev); 1841 pm_runtime_put_autosuspend(ddev->dev); 1842 return r; 1843 } 1844 1845 static int amdgpu_show_powershift_percent(struct device *dev, 1846 char *buf, bool dgpu_share) 1847 { 1848 struct drm_device *ddev = dev_get_drvdata(dev); 1849 struct amdgpu_device *adev = drm_to_adev(ddev); 1850 uint32_t ss_power; 1851 int r = 0, i; 1852 1853 r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share); 1854 if (r == -EOPNOTSUPP) { 1855 /* sensor not available on dGPU, try to read from APU */ 1856 adev = NULL; 1857 mutex_lock(&mgpu_info.mutex); 1858 for (i = 0; i < mgpu_info.num_gpu; i++) { 1859 if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) { 1860 adev = mgpu_info.gpu_ins[i].adev; 1861 break; 1862 } 1863 } 1864 mutex_unlock(&mgpu_info.mutex); 1865 if (adev) 1866 r = amdgpu_device_read_powershift(adev, &ss_power, dgpu_share); 1867 } 1868 1869 if (!r) 1870 r = sysfs_emit(buf, "%u%%\n", ss_power); 1871 1872 return r; 1873 } 1874 /** 1875 * DOC: smartshift_apu_power 1876 * 1877 * The amdgpu driver provides a sysfs API for reporting APU power 1878 * shift in percentage if platform supports smartshift. Value 0 means that 1879 * there is no powershift and values between [1-100] means that the power 1880 * is shifted to APU, the percentage of boost is with respect to APU power 1881 * limit on the platform. 1882 */ 1883 1884 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr, 1885 char *buf) 1886 { 1887 return amdgpu_show_powershift_percent(dev, buf, false); 1888 } 1889 1890 /** 1891 * DOC: smartshift_dgpu_power 1892 * 1893 * The amdgpu driver provides a sysfs API for reporting dGPU power 1894 * shift in percentage if platform supports smartshift. Value 0 means that 1895 * there is no powershift and values between [1-100] means that the power is 1896 * shifted to dGPU, the percentage of boost is with respect to dGPU power 1897 * limit on the platform. 1898 */ 1899 1900 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr, 1901 char *buf) 1902 { 1903 return amdgpu_show_powershift_percent(dev, buf, true); 1904 } 1905 1906 /** 1907 * DOC: smartshift_bias 1908 * 1909 * The amdgpu driver provides a sysfs API for reporting the 1910 * smartshift(SS2.0) bias level. The value ranges from -100 to 100 1911 * and the default is 0. -100 sets maximum preference to APU 1912 * and 100 sets max perference to dGPU. 1913 */ 1914 1915 static ssize_t amdgpu_get_smartshift_bias(struct device *dev, 1916 struct device_attribute *attr, 1917 char *buf) 1918 { 1919 int r = 0; 1920 1921 r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias); 1922 1923 return r; 1924 } 1925 1926 static ssize_t amdgpu_set_smartshift_bias(struct device *dev, 1927 struct device_attribute *attr, 1928 const char *buf, size_t count) 1929 { 1930 struct drm_device *ddev = dev_get_drvdata(dev); 1931 struct amdgpu_device *adev = drm_to_adev(ddev); 1932 int r = 0; 1933 int bias = 0; 1934 1935 if (amdgpu_in_reset(adev)) 1936 return -EPERM; 1937 if (adev->in_suspend && !adev->in_runpm) 1938 return -EPERM; 1939 1940 r = pm_runtime_get_sync(ddev->dev); 1941 if (r < 0) { 1942 pm_runtime_put_autosuspend(ddev->dev); 1943 return r; 1944 } 1945 1946 r = kstrtoint(buf, 10, &bias); 1947 if (r) 1948 goto out; 1949 1950 if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS) 1951 bias = AMDGPU_SMARTSHIFT_MAX_BIAS; 1952 else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS) 1953 bias = AMDGPU_SMARTSHIFT_MIN_BIAS; 1954 1955 amdgpu_smartshift_bias = bias; 1956 r = count; 1957 1958 /* TODO: update bias level with SMU message */ 1959 1960 out: 1961 pm_runtime_mark_last_busy(ddev->dev); 1962 pm_runtime_put_autosuspend(ddev->dev); 1963 return r; 1964 } 1965 1966 1967 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1968 uint32_t mask, enum amdgpu_device_attr_states *states) 1969 { 1970 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1971 *states = ATTR_STATE_UNSUPPORTED; 1972 1973 return 0; 1974 } 1975 1976 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 1977 uint32_t mask, enum amdgpu_device_attr_states *states) 1978 { 1979 uint32_t ss_power, size; 1980 1981 if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev))) 1982 *states = ATTR_STATE_UNSUPPORTED; 1983 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE, 1984 (void *)&ss_power, &size)) 1985 *states = ATTR_STATE_UNSUPPORTED; 1986 else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 1987 (void *)&ss_power, &size)) 1988 *states = ATTR_STATE_UNSUPPORTED; 1989 1990 return 0; 1991 } 1992 1993 static struct amdgpu_device_attr amdgpu_device_attrs[] = { 1994 AMDGPU_DEVICE_ATTR_RW(power_dpm_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1995 AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1996 AMDGPU_DEVICE_ATTR_RO(pp_num_states, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1997 AMDGPU_DEVICE_ATTR_RO(pp_cur_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1998 AMDGPU_DEVICE_ATTR_RW(pp_force_state, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 1999 AMDGPU_DEVICE_ATTR_RW(pp_table, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2000 AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2001 AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2002 AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2003 AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2004 AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2005 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2006 AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2007 AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2008 AMDGPU_DEVICE_ATTR_RW(pp_sclk_od, ATTR_FLAG_BASIC), 2009 AMDGPU_DEVICE_ATTR_RW(pp_mclk_od, ATTR_FLAG_BASIC), 2010 AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2011 AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage, ATTR_FLAG_BASIC), 2012 AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2013 AMDGPU_DEVICE_ATTR_RO(mem_busy_percent, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2014 AMDGPU_DEVICE_ATTR_RO(pcie_bw, ATTR_FLAG_BASIC), 2015 AMDGPU_DEVICE_ATTR_RW(pp_features, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2016 AMDGPU_DEVICE_ATTR_RO(unique_id, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2017 AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2018 AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2019 AMDGPU_DEVICE_ATTR_RO(gpu_metrics, ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF), 2020 AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power, ATTR_FLAG_BASIC, 2021 .attr_update = ss_power_attr_update), 2022 AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power, ATTR_FLAG_BASIC, 2023 .attr_update = ss_power_attr_update), 2024 AMDGPU_DEVICE_ATTR_RW(smartshift_bias, ATTR_FLAG_BASIC, 2025 .attr_update = ss_bias_attr_update), 2026 }; 2027 2028 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2029 uint32_t mask, enum amdgpu_device_attr_states *states) 2030 { 2031 struct device_attribute *dev_attr = &attr->dev_attr; 2032 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 2033 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 2034 const char *attr_name = dev_attr->attr.name; 2035 2036 if (!(attr->flags & mask)) { 2037 *states = ATTR_STATE_UNSUPPORTED; 2038 return 0; 2039 } 2040 2041 #define DEVICE_ATTR_IS(_name) (!strcmp(attr_name, #_name)) 2042 2043 if (DEVICE_ATTR_IS(pp_dpm_socclk)) { 2044 if (gc_ver < IP_VERSION(9, 0, 0)) 2045 *states = ATTR_STATE_UNSUPPORTED; 2046 } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2047 if (gc_ver < IP_VERSION(9, 0, 0) || 2048 gc_ver == IP_VERSION(9, 4, 1) || 2049 gc_ver == IP_VERSION(9, 4, 2)) 2050 *states = ATTR_STATE_UNSUPPORTED; 2051 } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) { 2052 if (mp1_ver < IP_VERSION(10, 0, 0)) 2053 *states = ATTR_STATE_UNSUPPORTED; 2054 } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) { 2055 *states = ATTR_STATE_UNSUPPORTED; 2056 if (amdgpu_dpm_is_overdrive_supported(adev)) 2057 *states = ATTR_STATE_SUPPORTED; 2058 } else if (DEVICE_ATTR_IS(mem_busy_percent)) { 2059 if (adev->flags & AMD_IS_APU || gc_ver == IP_VERSION(9, 0, 1)) 2060 *states = ATTR_STATE_UNSUPPORTED; 2061 } else if (DEVICE_ATTR_IS(pcie_bw)) { 2062 /* PCIe Perf counters won't work on APU nodes */ 2063 if (adev->flags & AMD_IS_APU) 2064 *states = ATTR_STATE_UNSUPPORTED; 2065 } else if (DEVICE_ATTR_IS(unique_id)) { 2066 switch (gc_ver) { 2067 case IP_VERSION(9, 0, 1): 2068 case IP_VERSION(9, 4, 0): 2069 case IP_VERSION(9, 4, 1): 2070 case IP_VERSION(9, 4, 2): 2071 case IP_VERSION(10, 3, 0): 2072 case IP_VERSION(11, 0, 0): 2073 case IP_VERSION(11, 0, 1): 2074 case IP_VERSION(11, 0, 2): 2075 *states = ATTR_STATE_SUPPORTED; 2076 break; 2077 default: 2078 *states = ATTR_STATE_UNSUPPORTED; 2079 } 2080 } else if (DEVICE_ATTR_IS(pp_features)) { 2081 if (adev->flags & AMD_IS_APU || gc_ver < IP_VERSION(9, 0, 0)) 2082 *states = ATTR_STATE_UNSUPPORTED; 2083 } else if (DEVICE_ATTR_IS(gpu_metrics)) { 2084 if (gc_ver < IP_VERSION(9, 1, 0)) 2085 *states = ATTR_STATE_UNSUPPORTED; 2086 } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) { 2087 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2088 gc_ver == IP_VERSION(10, 3, 0) || 2089 gc_ver == IP_VERSION(10, 1, 2) || 2090 gc_ver == IP_VERSION(11, 0, 0) || 2091 gc_ver == IP_VERSION(11, 0, 2) || 2092 gc_ver == IP_VERSION(11, 0, 3))) 2093 *states = ATTR_STATE_UNSUPPORTED; 2094 } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) { 2095 if (!(gc_ver == IP_VERSION(10, 3, 1) || 2096 gc_ver == IP_VERSION(10, 3, 0) || 2097 gc_ver == IP_VERSION(10, 1, 2) || 2098 gc_ver == IP_VERSION(11, 0, 0) || 2099 gc_ver == IP_VERSION(11, 0, 2) || 2100 gc_ver == IP_VERSION(11, 0, 3))) 2101 *states = ATTR_STATE_UNSUPPORTED; 2102 } else if (DEVICE_ATTR_IS(pp_power_profile_mode)) { 2103 if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP) 2104 *states = ATTR_STATE_UNSUPPORTED; 2105 else if (gc_ver == IP_VERSION(10, 3, 0) && amdgpu_sriov_vf(adev)) 2106 *states = ATTR_STATE_UNSUPPORTED; 2107 } 2108 2109 switch (gc_ver) { 2110 case IP_VERSION(9, 4, 1): 2111 case IP_VERSION(9, 4, 2): 2112 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */ 2113 if (DEVICE_ATTR_IS(pp_dpm_mclk) || 2114 DEVICE_ATTR_IS(pp_dpm_socclk) || 2115 DEVICE_ATTR_IS(pp_dpm_fclk)) { 2116 dev_attr->attr.mode &= ~S_IWUGO; 2117 dev_attr->store = NULL; 2118 } 2119 break; 2120 case IP_VERSION(10, 3, 0): 2121 if (DEVICE_ATTR_IS(power_dpm_force_performance_level) && 2122 amdgpu_sriov_vf(adev)) { 2123 dev_attr->attr.mode &= ~0222; 2124 dev_attr->store = NULL; 2125 } 2126 break; 2127 default: 2128 break; 2129 } 2130 2131 if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) { 2132 /* SMU MP1 does not support dcefclk level setting */ 2133 if (gc_ver >= IP_VERSION(10, 0, 0)) { 2134 dev_attr->attr.mode &= ~S_IWUGO; 2135 dev_attr->store = NULL; 2136 } 2137 } 2138 2139 /* setting should not be allowed from VF if not in one VF mode */ 2140 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { 2141 dev_attr->attr.mode &= ~S_IWUGO; 2142 dev_attr->store = NULL; 2143 } 2144 2145 #undef DEVICE_ATTR_IS 2146 2147 return 0; 2148 } 2149 2150 2151 static int amdgpu_device_attr_create(struct amdgpu_device *adev, 2152 struct amdgpu_device_attr *attr, 2153 uint32_t mask, struct list_head *attr_list) 2154 { 2155 int ret = 0; 2156 struct device_attribute *dev_attr = &attr->dev_attr; 2157 const char *name = dev_attr->attr.name; 2158 enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED; 2159 struct amdgpu_device_attr_entry *attr_entry; 2160 2161 int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, 2162 uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update; 2163 2164 BUG_ON(!attr); 2165 2166 attr_update = attr->attr_update ? attr->attr_update : default_attr_update; 2167 2168 ret = attr_update(adev, attr, mask, &attr_states); 2169 if (ret) { 2170 dev_err(adev->dev, "failed to update device file %s, ret = %d\n", 2171 name, ret); 2172 return ret; 2173 } 2174 2175 if (attr_states == ATTR_STATE_UNSUPPORTED) 2176 return 0; 2177 2178 ret = device_create_file(adev->dev, dev_attr); 2179 if (ret) { 2180 dev_err(adev->dev, "failed to create device file %s, ret = %d\n", 2181 name, ret); 2182 } 2183 2184 attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL); 2185 if (!attr_entry) 2186 return -ENOMEM; 2187 2188 attr_entry->attr = attr; 2189 INIT_LIST_HEAD(&attr_entry->entry); 2190 2191 list_add_tail(&attr_entry->entry, attr_list); 2192 2193 return ret; 2194 } 2195 2196 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr) 2197 { 2198 struct device_attribute *dev_attr = &attr->dev_attr; 2199 2200 device_remove_file(adev->dev, dev_attr); 2201 } 2202 2203 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2204 struct list_head *attr_list); 2205 2206 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev, 2207 struct amdgpu_device_attr *attrs, 2208 uint32_t counts, 2209 uint32_t mask, 2210 struct list_head *attr_list) 2211 { 2212 int ret = 0; 2213 uint32_t i = 0; 2214 2215 for (i = 0; i < counts; i++) { 2216 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list); 2217 if (ret) 2218 goto failed; 2219 } 2220 2221 return 0; 2222 2223 failed: 2224 amdgpu_device_attr_remove_groups(adev, attr_list); 2225 2226 return ret; 2227 } 2228 2229 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev, 2230 struct list_head *attr_list) 2231 { 2232 struct amdgpu_device_attr_entry *entry, *entry_tmp; 2233 2234 if (list_empty(attr_list)) 2235 return ; 2236 2237 list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) { 2238 amdgpu_device_attr_remove(adev, entry->attr); 2239 list_del(&entry->entry); 2240 kfree(entry); 2241 } 2242 } 2243 2244 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 2245 struct device_attribute *attr, 2246 char *buf) 2247 { 2248 struct amdgpu_device *adev = dev_get_drvdata(dev); 2249 int channel = to_sensor_dev_attr(attr)->index; 2250 int r, temp = 0, size = sizeof(temp); 2251 2252 if (amdgpu_in_reset(adev)) 2253 return -EPERM; 2254 if (adev->in_suspend && !adev->in_runpm) 2255 return -EPERM; 2256 2257 if (channel >= PP_TEMP_MAX) 2258 return -EINVAL; 2259 2260 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2261 if (r < 0) { 2262 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2263 return r; 2264 } 2265 2266 switch (channel) { 2267 case PP_TEMP_JUNCTION: 2268 /* get current junction temperature */ 2269 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 2270 (void *)&temp, &size); 2271 break; 2272 case PP_TEMP_EDGE: 2273 /* get current edge temperature */ 2274 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP, 2275 (void *)&temp, &size); 2276 break; 2277 case PP_TEMP_MEM: 2278 /* get current memory temperature */ 2279 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP, 2280 (void *)&temp, &size); 2281 break; 2282 default: 2283 r = -EINVAL; 2284 break; 2285 } 2286 2287 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2288 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2289 2290 if (r) 2291 return r; 2292 2293 return sysfs_emit(buf, "%d\n", temp); 2294 } 2295 2296 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 2297 struct device_attribute *attr, 2298 char *buf) 2299 { 2300 struct amdgpu_device *adev = dev_get_drvdata(dev); 2301 int hyst = to_sensor_dev_attr(attr)->index; 2302 int temp; 2303 2304 if (hyst) 2305 temp = adev->pm.dpm.thermal.min_temp; 2306 else 2307 temp = adev->pm.dpm.thermal.max_temp; 2308 2309 return sysfs_emit(buf, "%d\n", temp); 2310 } 2311 2312 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev, 2313 struct device_attribute *attr, 2314 char *buf) 2315 { 2316 struct amdgpu_device *adev = dev_get_drvdata(dev); 2317 int hyst = to_sensor_dev_attr(attr)->index; 2318 int temp; 2319 2320 if (hyst) 2321 temp = adev->pm.dpm.thermal.min_hotspot_temp; 2322 else 2323 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp; 2324 2325 return sysfs_emit(buf, "%d\n", temp); 2326 } 2327 2328 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev, 2329 struct device_attribute *attr, 2330 char *buf) 2331 { 2332 struct amdgpu_device *adev = dev_get_drvdata(dev); 2333 int hyst = to_sensor_dev_attr(attr)->index; 2334 int temp; 2335 2336 if (hyst) 2337 temp = adev->pm.dpm.thermal.min_mem_temp; 2338 else 2339 temp = adev->pm.dpm.thermal.max_mem_crit_temp; 2340 2341 return sysfs_emit(buf, "%d\n", temp); 2342 } 2343 2344 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev, 2345 struct device_attribute *attr, 2346 char *buf) 2347 { 2348 int channel = to_sensor_dev_attr(attr)->index; 2349 2350 if (channel >= PP_TEMP_MAX) 2351 return -EINVAL; 2352 2353 return sysfs_emit(buf, "%s\n", temp_label[channel].label); 2354 } 2355 2356 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev, 2357 struct device_attribute *attr, 2358 char *buf) 2359 { 2360 struct amdgpu_device *adev = dev_get_drvdata(dev); 2361 int channel = to_sensor_dev_attr(attr)->index; 2362 int temp = 0; 2363 2364 if (channel >= PP_TEMP_MAX) 2365 return -EINVAL; 2366 2367 switch (channel) { 2368 case PP_TEMP_JUNCTION: 2369 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp; 2370 break; 2371 case PP_TEMP_EDGE: 2372 temp = adev->pm.dpm.thermal.max_edge_emergency_temp; 2373 break; 2374 case PP_TEMP_MEM: 2375 temp = adev->pm.dpm.thermal.max_mem_emergency_temp; 2376 break; 2377 } 2378 2379 return sysfs_emit(buf, "%d\n", temp); 2380 } 2381 2382 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 2383 struct device_attribute *attr, 2384 char *buf) 2385 { 2386 struct amdgpu_device *adev = dev_get_drvdata(dev); 2387 u32 pwm_mode = 0; 2388 int ret; 2389 2390 if (amdgpu_in_reset(adev)) 2391 return -EPERM; 2392 if (adev->in_suspend && !adev->in_runpm) 2393 return -EPERM; 2394 2395 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2396 if (ret < 0) { 2397 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2398 return ret; 2399 } 2400 2401 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2402 2403 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2404 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2405 2406 if (ret) 2407 return -EINVAL; 2408 2409 return sysfs_emit(buf, "%u\n", pwm_mode); 2410 } 2411 2412 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 2413 struct device_attribute *attr, 2414 const char *buf, 2415 size_t count) 2416 { 2417 struct amdgpu_device *adev = dev_get_drvdata(dev); 2418 int err, ret; 2419 int value; 2420 2421 if (amdgpu_in_reset(adev)) 2422 return -EPERM; 2423 if (adev->in_suspend && !adev->in_runpm) 2424 return -EPERM; 2425 2426 err = kstrtoint(buf, 10, &value); 2427 if (err) 2428 return err; 2429 2430 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2431 if (ret < 0) { 2432 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2433 return ret; 2434 } 2435 2436 ret = amdgpu_dpm_set_fan_control_mode(adev, value); 2437 2438 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2439 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2440 2441 if (ret) 2442 return -EINVAL; 2443 2444 return count; 2445 } 2446 2447 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 2448 struct device_attribute *attr, 2449 char *buf) 2450 { 2451 return sysfs_emit(buf, "%i\n", 0); 2452 } 2453 2454 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 2455 struct device_attribute *attr, 2456 char *buf) 2457 { 2458 return sysfs_emit(buf, "%i\n", 255); 2459 } 2460 2461 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 2462 struct device_attribute *attr, 2463 const char *buf, size_t count) 2464 { 2465 struct amdgpu_device *adev = dev_get_drvdata(dev); 2466 int err; 2467 u32 value; 2468 u32 pwm_mode; 2469 2470 if (amdgpu_in_reset(adev)) 2471 return -EPERM; 2472 if (adev->in_suspend && !adev->in_runpm) 2473 return -EPERM; 2474 2475 err = kstrtou32(buf, 10, &value); 2476 if (err) 2477 return err; 2478 2479 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2480 if (err < 0) { 2481 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2482 return err; 2483 } 2484 2485 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2486 if (err) 2487 goto out; 2488 2489 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2490 pr_info("manual fan speed control should be enabled first\n"); 2491 err = -EINVAL; 2492 goto out; 2493 } 2494 2495 err = amdgpu_dpm_set_fan_speed_pwm(adev, value); 2496 2497 out: 2498 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2499 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2500 2501 if (err) 2502 return err; 2503 2504 return count; 2505 } 2506 2507 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 2508 struct device_attribute *attr, 2509 char *buf) 2510 { 2511 struct amdgpu_device *adev = dev_get_drvdata(dev); 2512 int err; 2513 u32 speed = 0; 2514 2515 if (amdgpu_in_reset(adev)) 2516 return -EPERM; 2517 if (adev->in_suspend && !adev->in_runpm) 2518 return -EPERM; 2519 2520 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2521 if (err < 0) { 2522 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2523 return err; 2524 } 2525 2526 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed); 2527 2528 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2529 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2530 2531 if (err) 2532 return err; 2533 2534 return sysfs_emit(buf, "%i\n", speed); 2535 } 2536 2537 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 2538 struct device_attribute *attr, 2539 char *buf) 2540 { 2541 struct amdgpu_device *adev = dev_get_drvdata(dev); 2542 int err; 2543 u32 speed = 0; 2544 2545 if (amdgpu_in_reset(adev)) 2546 return -EPERM; 2547 if (adev->in_suspend && !adev->in_runpm) 2548 return -EPERM; 2549 2550 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2551 if (err < 0) { 2552 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2553 return err; 2554 } 2555 2556 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 2557 2558 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2559 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2560 2561 if (err) 2562 return err; 2563 2564 return sysfs_emit(buf, "%i\n", speed); 2565 } 2566 2567 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev, 2568 struct device_attribute *attr, 2569 char *buf) 2570 { 2571 struct amdgpu_device *adev = dev_get_drvdata(dev); 2572 u32 min_rpm = 0; 2573 u32 size = sizeof(min_rpm); 2574 int r; 2575 2576 if (amdgpu_in_reset(adev)) 2577 return -EPERM; 2578 if (adev->in_suspend && !adev->in_runpm) 2579 return -EPERM; 2580 2581 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2582 if (r < 0) { 2583 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2584 return r; 2585 } 2586 2587 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM, 2588 (void *)&min_rpm, &size); 2589 2590 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2591 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2592 2593 if (r) 2594 return r; 2595 2596 return sysfs_emit(buf, "%d\n", min_rpm); 2597 } 2598 2599 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev, 2600 struct device_attribute *attr, 2601 char *buf) 2602 { 2603 struct amdgpu_device *adev = dev_get_drvdata(dev); 2604 u32 max_rpm = 0; 2605 u32 size = sizeof(max_rpm); 2606 int r; 2607 2608 if (amdgpu_in_reset(adev)) 2609 return -EPERM; 2610 if (adev->in_suspend && !adev->in_runpm) 2611 return -EPERM; 2612 2613 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2614 if (r < 0) { 2615 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2616 return r; 2617 } 2618 2619 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM, 2620 (void *)&max_rpm, &size); 2621 2622 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2623 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2624 2625 if (r) 2626 return r; 2627 2628 return sysfs_emit(buf, "%d\n", max_rpm); 2629 } 2630 2631 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev, 2632 struct device_attribute *attr, 2633 char *buf) 2634 { 2635 struct amdgpu_device *adev = dev_get_drvdata(dev); 2636 int err; 2637 u32 rpm = 0; 2638 2639 if (amdgpu_in_reset(adev)) 2640 return -EPERM; 2641 if (adev->in_suspend && !adev->in_runpm) 2642 return -EPERM; 2643 2644 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2645 if (err < 0) { 2646 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2647 return err; 2648 } 2649 2650 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm); 2651 2652 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2653 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2654 2655 if (err) 2656 return err; 2657 2658 return sysfs_emit(buf, "%i\n", rpm); 2659 } 2660 2661 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev, 2662 struct device_attribute *attr, 2663 const char *buf, size_t count) 2664 { 2665 struct amdgpu_device *adev = dev_get_drvdata(dev); 2666 int err; 2667 u32 value; 2668 u32 pwm_mode; 2669 2670 if (amdgpu_in_reset(adev)) 2671 return -EPERM; 2672 if (adev->in_suspend && !adev->in_runpm) 2673 return -EPERM; 2674 2675 err = kstrtou32(buf, 10, &value); 2676 if (err) 2677 return err; 2678 2679 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2680 if (err < 0) { 2681 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2682 return err; 2683 } 2684 2685 err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2686 if (err) 2687 goto out; 2688 2689 if (pwm_mode != AMD_FAN_CTRL_MANUAL) { 2690 err = -ENODATA; 2691 goto out; 2692 } 2693 2694 err = amdgpu_dpm_set_fan_speed_rpm(adev, value); 2695 2696 out: 2697 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2698 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2699 2700 if (err) 2701 return err; 2702 2703 return count; 2704 } 2705 2706 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev, 2707 struct device_attribute *attr, 2708 char *buf) 2709 { 2710 struct amdgpu_device *adev = dev_get_drvdata(dev); 2711 u32 pwm_mode = 0; 2712 int ret; 2713 2714 if (amdgpu_in_reset(adev)) 2715 return -EPERM; 2716 if (adev->in_suspend && !adev->in_runpm) 2717 return -EPERM; 2718 2719 ret = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2720 if (ret < 0) { 2721 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2722 return ret; 2723 } 2724 2725 ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode); 2726 2727 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2728 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2729 2730 if (ret) 2731 return -EINVAL; 2732 2733 return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1); 2734 } 2735 2736 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev, 2737 struct device_attribute *attr, 2738 const char *buf, 2739 size_t count) 2740 { 2741 struct amdgpu_device *adev = dev_get_drvdata(dev); 2742 int err; 2743 int value; 2744 u32 pwm_mode; 2745 2746 if (amdgpu_in_reset(adev)) 2747 return -EPERM; 2748 if (adev->in_suspend && !adev->in_runpm) 2749 return -EPERM; 2750 2751 err = kstrtoint(buf, 10, &value); 2752 if (err) 2753 return err; 2754 2755 if (value == 0) 2756 pwm_mode = AMD_FAN_CTRL_AUTO; 2757 else if (value == 1) 2758 pwm_mode = AMD_FAN_CTRL_MANUAL; 2759 else 2760 return -EINVAL; 2761 2762 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2763 if (err < 0) { 2764 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2765 return err; 2766 } 2767 2768 err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode); 2769 2770 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2771 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2772 2773 if (err) 2774 return -EINVAL; 2775 2776 return count; 2777 } 2778 2779 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 2780 struct device_attribute *attr, 2781 char *buf) 2782 { 2783 struct amdgpu_device *adev = dev_get_drvdata(dev); 2784 u32 vddgfx; 2785 int r, size = sizeof(vddgfx); 2786 2787 if (amdgpu_in_reset(adev)) 2788 return -EPERM; 2789 if (adev->in_suspend && !adev->in_runpm) 2790 return -EPERM; 2791 2792 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2793 if (r < 0) { 2794 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2795 return r; 2796 } 2797 2798 /* get the voltage */ 2799 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, 2800 (void *)&vddgfx, &size); 2801 2802 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2803 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2804 2805 if (r) 2806 return r; 2807 2808 return sysfs_emit(buf, "%d\n", vddgfx); 2809 } 2810 2811 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 2812 struct device_attribute *attr, 2813 char *buf) 2814 { 2815 return sysfs_emit(buf, "vddgfx\n"); 2816 } 2817 2818 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 2819 struct device_attribute *attr, 2820 char *buf) 2821 { 2822 struct amdgpu_device *adev = dev_get_drvdata(dev); 2823 u32 vddnb; 2824 int r, size = sizeof(vddnb); 2825 2826 if (amdgpu_in_reset(adev)) 2827 return -EPERM; 2828 if (adev->in_suspend && !adev->in_runpm) 2829 return -EPERM; 2830 2831 /* only APUs have vddnb */ 2832 if (!(adev->flags & AMD_IS_APU)) 2833 return -EINVAL; 2834 2835 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2836 if (r < 0) { 2837 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2838 return r; 2839 } 2840 2841 /* get the voltage */ 2842 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, 2843 (void *)&vddnb, &size); 2844 2845 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2846 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2847 2848 if (r) 2849 return r; 2850 2851 return sysfs_emit(buf, "%d\n", vddnb); 2852 } 2853 2854 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 2855 struct device_attribute *attr, 2856 char *buf) 2857 { 2858 return sysfs_emit(buf, "vddnb\n"); 2859 } 2860 2861 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 2862 struct device_attribute *attr, 2863 char *buf) 2864 { 2865 struct amdgpu_device *adev = dev_get_drvdata(dev); 2866 u32 query = 0; 2867 int r, size = sizeof(u32); 2868 unsigned uw; 2869 2870 if (amdgpu_in_reset(adev)) 2871 return -EPERM; 2872 if (adev->in_suspend && !adev->in_runpm) 2873 return -EPERM; 2874 2875 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2876 if (r < 0) { 2877 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2878 return r; 2879 } 2880 2881 /* get the voltage */ 2882 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, 2883 (void *)&query, &size); 2884 2885 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2886 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2887 2888 if (r) 2889 return r; 2890 2891 /* convert to microwatts */ 2892 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 2893 2894 return sysfs_emit(buf, "%u\n", uw); 2895 } 2896 2897 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 2898 struct device_attribute *attr, 2899 char *buf) 2900 { 2901 return sysfs_emit(buf, "%i\n", 0); 2902 } 2903 2904 2905 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev, 2906 struct device_attribute *attr, 2907 char *buf, 2908 enum pp_power_limit_level pp_limit_level) 2909 { 2910 struct amdgpu_device *adev = dev_get_drvdata(dev); 2911 enum pp_power_type power_type = to_sensor_dev_attr(attr)->index; 2912 uint32_t limit; 2913 ssize_t size; 2914 int r; 2915 2916 if (amdgpu_in_reset(adev)) 2917 return -EPERM; 2918 if (adev->in_suspend && !adev->in_runpm) 2919 return -EPERM; 2920 2921 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 2922 if (r < 0) { 2923 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2924 return r; 2925 } 2926 2927 r = amdgpu_dpm_get_power_limit(adev, &limit, 2928 pp_limit_level, power_type); 2929 2930 if (!r) 2931 size = sysfs_emit(buf, "%u\n", limit * 1000000); 2932 else 2933 size = sysfs_emit(buf, "\n"); 2934 2935 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 2936 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 2937 2938 return size; 2939 } 2940 2941 2942 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 2943 struct device_attribute *attr, 2944 char *buf) 2945 { 2946 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX); 2947 2948 } 2949 2950 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 2951 struct device_attribute *attr, 2952 char *buf) 2953 { 2954 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT); 2955 2956 } 2957 2958 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev, 2959 struct device_attribute *attr, 2960 char *buf) 2961 { 2962 return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT); 2963 2964 } 2965 2966 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, 2967 struct device_attribute *attr, 2968 char *buf) 2969 { 2970 struct amdgpu_device *adev = dev_get_drvdata(dev); 2971 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 2972 2973 if (gc_ver == IP_VERSION(10, 3, 1)) 2974 return sysfs_emit(buf, "%s\n", 2975 to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ? 2976 "fastPPT" : "slowPPT"); 2977 else 2978 return sysfs_emit(buf, "PPT\n"); 2979 } 2980 2981 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 2982 struct device_attribute *attr, 2983 const char *buf, 2984 size_t count) 2985 { 2986 struct amdgpu_device *adev = dev_get_drvdata(dev); 2987 int limit_type = to_sensor_dev_attr(attr)->index; 2988 int err; 2989 u32 value; 2990 2991 if (amdgpu_in_reset(adev)) 2992 return -EPERM; 2993 if (adev->in_suspend && !adev->in_runpm) 2994 return -EPERM; 2995 2996 if (amdgpu_sriov_vf(adev)) 2997 return -EINVAL; 2998 2999 err = kstrtou32(buf, 10, &value); 3000 if (err) 3001 return err; 3002 3003 value = value / 1000000; /* convert to Watt */ 3004 value |= limit_type << 24; 3005 3006 err = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3007 if (err < 0) { 3008 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3009 return err; 3010 } 3011 3012 err = amdgpu_dpm_set_power_limit(adev, value); 3013 3014 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3015 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3016 3017 if (err) 3018 return err; 3019 3020 return count; 3021 } 3022 3023 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev, 3024 struct device_attribute *attr, 3025 char *buf) 3026 { 3027 struct amdgpu_device *adev = dev_get_drvdata(dev); 3028 uint32_t sclk; 3029 int r, size = sizeof(sclk); 3030 3031 if (amdgpu_in_reset(adev)) 3032 return -EPERM; 3033 if (adev->in_suspend && !adev->in_runpm) 3034 return -EPERM; 3035 3036 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3037 if (r < 0) { 3038 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3039 return r; 3040 } 3041 3042 /* get the sclk */ 3043 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, 3044 (void *)&sclk, &size); 3045 3046 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3047 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3048 3049 if (r) 3050 return r; 3051 3052 return sysfs_emit(buf, "%u\n", sclk * 10 * 1000); 3053 } 3054 3055 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev, 3056 struct device_attribute *attr, 3057 char *buf) 3058 { 3059 return sysfs_emit(buf, "sclk\n"); 3060 } 3061 3062 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev, 3063 struct device_attribute *attr, 3064 char *buf) 3065 { 3066 struct amdgpu_device *adev = dev_get_drvdata(dev); 3067 uint32_t mclk; 3068 int r, size = sizeof(mclk); 3069 3070 if (amdgpu_in_reset(adev)) 3071 return -EPERM; 3072 if (adev->in_suspend && !adev->in_runpm) 3073 return -EPERM; 3074 3075 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); 3076 if (r < 0) { 3077 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3078 return r; 3079 } 3080 3081 /* get the sclk */ 3082 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, 3083 (void *)&mclk, &size); 3084 3085 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); 3086 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); 3087 3088 if (r) 3089 return r; 3090 3091 return sysfs_emit(buf, "%u\n", mclk * 10 * 1000); 3092 } 3093 3094 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev, 3095 struct device_attribute *attr, 3096 char *buf) 3097 { 3098 return sysfs_emit(buf, "mclk\n"); 3099 } 3100 3101 /** 3102 * DOC: hwmon 3103 * 3104 * The amdgpu driver exposes the following sensor interfaces: 3105 * 3106 * - GPU temperature (via the on-die sensor) 3107 * 3108 * - GPU voltage 3109 * 3110 * - Northbridge voltage (APUs only) 3111 * 3112 * - GPU power 3113 * 3114 * - GPU fan 3115 * 3116 * - GPU gfx/compute engine clock 3117 * 3118 * - GPU memory clock (dGPU only) 3119 * 3120 * hwmon interfaces for GPU temperature: 3121 * 3122 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius 3123 * - temp2_input and temp3_input are supported on SOC15 dGPUs only 3124 * 3125 * - temp[1-3]_label: temperature channel label 3126 * - temp2_label and temp3_label are supported on SOC15 dGPUs only 3127 * 3128 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius 3129 * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only 3130 * 3131 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 3132 * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only 3133 * 3134 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius 3135 * - these are supported on SOC15 dGPUs only 3136 * 3137 * hwmon interfaces for GPU voltage: 3138 * 3139 * - in0_input: the voltage on the GPU in millivolts 3140 * 3141 * - in1_input: the voltage on the Northbridge in millivolts 3142 * 3143 * hwmon interfaces for GPU power: 3144 * 3145 * - power1_average: average power used by the SoC in microWatts. On APUs this includes the CPU. 3146 * 3147 * - power1_cap_min: minimum cap supported in microWatts 3148 * 3149 * - power1_cap_max: maximum cap supported in microWatts 3150 * 3151 * - power1_cap: selected power cap in microWatts 3152 * 3153 * hwmon interfaces for GPU fan: 3154 * 3155 * - pwm1: pulse width modulation fan level (0-255) 3156 * 3157 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 3158 * 3159 * - pwm1_min: pulse width modulation fan control minimum level (0) 3160 * 3161 * - pwm1_max: pulse width modulation fan control maximum level (255) 3162 * 3163 * - fan1_min: a minimum value Unit: revolution/min (RPM) 3164 * 3165 * - fan1_max: a maximum value Unit: revolution/max (RPM) 3166 * 3167 * - fan1_input: fan speed in RPM 3168 * 3169 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM) 3170 * 3171 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable 3172 * 3173 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time. 3174 * That will get the former one overridden. 3175 * 3176 * hwmon interfaces for GPU clocks: 3177 * 3178 * - freq1_input: the gfx/compute clock in hertz 3179 * 3180 * - freq2_input: the memory clock in hertz 3181 * 3182 * You can use hwmon tools like sensors to view this information on your system. 3183 * 3184 */ 3185 3186 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE); 3187 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 3188 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 3189 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE); 3190 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION); 3191 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0); 3192 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1); 3193 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION); 3194 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM); 3195 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0); 3196 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1); 3197 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM); 3198 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE); 3199 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION); 3200 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM); 3201 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 3202 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 3203 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 3204 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 3205 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 3206 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0); 3207 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0); 3208 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0); 3209 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0); 3210 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 3211 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 3212 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 3213 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 3214 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 3215 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 3216 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 3217 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 3218 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0); 3219 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0); 3220 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1); 3221 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1); 3222 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1); 3223 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); 3224 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1); 3225 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1); 3226 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0); 3227 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0); 3228 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0); 3229 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0); 3230 3231 static struct attribute *hwmon_attributes[] = { 3232 &sensor_dev_attr_temp1_input.dev_attr.attr, 3233 &sensor_dev_attr_temp1_crit.dev_attr.attr, 3234 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 3235 &sensor_dev_attr_temp2_input.dev_attr.attr, 3236 &sensor_dev_attr_temp2_crit.dev_attr.attr, 3237 &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, 3238 &sensor_dev_attr_temp3_input.dev_attr.attr, 3239 &sensor_dev_attr_temp3_crit.dev_attr.attr, 3240 &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, 3241 &sensor_dev_attr_temp1_emergency.dev_attr.attr, 3242 &sensor_dev_attr_temp2_emergency.dev_attr.attr, 3243 &sensor_dev_attr_temp3_emergency.dev_attr.attr, 3244 &sensor_dev_attr_temp1_label.dev_attr.attr, 3245 &sensor_dev_attr_temp2_label.dev_attr.attr, 3246 &sensor_dev_attr_temp3_label.dev_attr.attr, 3247 &sensor_dev_attr_pwm1.dev_attr.attr, 3248 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 3249 &sensor_dev_attr_pwm1_min.dev_attr.attr, 3250 &sensor_dev_attr_pwm1_max.dev_attr.attr, 3251 &sensor_dev_attr_fan1_input.dev_attr.attr, 3252 &sensor_dev_attr_fan1_min.dev_attr.attr, 3253 &sensor_dev_attr_fan1_max.dev_attr.attr, 3254 &sensor_dev_attr_fan1_target.dev_attr.attr, 3255 &sensor_dev_attr_fan1_enable.dev_attr.attr, 3256 &sensor_dev_attr_in0_input.dev_attr.attr, 3257 &sensor_dev_attr_in0_label.dev_attr.attr, 3258 &sensor_dev_attr_in1_input.dev_attr.attr, 3259 &sensor_dev_attr_in1_label.dev_attr.attr, 3260 &sensor_dev_attr_power1_average.dev_attr.attr, 3261 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 3262 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 3263 &sensor_dev_attr_power1_cap.dev_attr.attr, 3264 &sensor_dev_attr_power1_cap_default.dev_attr.attr, 3265 &sensor_dev_attr_power1_label.dev_attr.attr, 3266 &sensor_dev_attr_power2_average.dev_attr.attr, 3267 &sensor_dev_attr_power2_cap_max.dev_attr.attr, 3268 &sensor_dev_attr_power2_cap_min.dev_attr.attr, 3269 &sensor_dev_attr_power2_cap.dev_attr.attr, 3270 &sensor_dev_attr_power2_cap_default.dev_attr.attr, 3271 &sensor_dev_attr_power2_label.dev_attr.attr, 3272 &sensor_dev_attr_freq1_input.dev_attr.attr, 3273 &sensor_dev_attr_freq1_label.dev_attr.attr, 3274 &sensor_dev_attr_freq2_input.dev_attr.attr, 3275 &sensor_dev_attr_freq2_label.dev_attr.attr, 3276 NULL 3277 }; 3278 3279 static umode_t hwmon_attributes_visible(struct kobject *kobj, 3280 struct attribute *attr, int index) 3281 { 3282 struct device *dev = kobj_to_dev(kobj); 3283 struct amdgpu_device *adev = dev_get_drvdata(dev); 3284 umode_t effective_mode = attr->mode; 3285 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3286 3287 /* under multi-vf mode, the hwmon attributes are all not supported */ 3288 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 3289 return 0; 3290 3291 /* under pp one vf mode manage of hwmon attributes is not supported */ 3292 if (amdgpu_sriov_is_pp_one_vf(adev)) 3293 effective_mode &= ~S_IWUSR; 3294 3295 /* Skip fan attributes if fan is not present */ 3296 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3297 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3298 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3299 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3300 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3301 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3302 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3303 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3304 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3305 return 0; 3306 3307 /* Skip fan attributes on APU */ 3308 if ((adev->flags & AMD_IS_APU) && 3309 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3310 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3311 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3312 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3313 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3314 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3315 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3316 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3317 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3318 return 0; 3319 3320 /* Skip crit temp on APU */ 3321 if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) && 3322 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3323 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) 3324 return 0; 3325 3326 /* Skip limit attributes if DPM is not enabled */ 3327 if (!adev->pm.dpm_enabled && 3328 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 3329 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 3330 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 3331 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 3332 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3333 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 3334 attr == &sensor_dev_attr_fan1_input.dev_attr.attr || 3335 attr == &sensor_dev_attr_fan1_min.dev_attr.attr || 3336 attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3337 attr == &sensor_dev_attr_fan1_target.dev_attr.attr || 3338 attr == &sensor_dev_attr_fan1_enable.dev_attr.attr)) 3339 return 0; 3340 3341 /* mask fan attributes if we have no bindings for this asic to expose */ 3342 if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3343 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 3344 ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) && 3345 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 3346 effective_mode &= ~S_IRUGO; 3347 3348 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3349 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 3350 ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) && 3351 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 3352 effective_mode &= ~S_IWUSR; 3353 3354 /* not implemented yet for GC 10.3.1 APUs */ 3355 if (((adev->family == AMDGPU_FAMILY_SI) || 3356 ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)))) && 3357 (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 3358 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr || 3359 attr == &sensor_dev_attr_power1_cap.dev_attr.attr || 3360 attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr)) 3361 return 0; 3362 3363 /* not implemented yet for APUs having <= GC 9.3.0 */ 3364 if (((adev->family == AMDGPU_FAMILY_SI) || 3365 ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) && 3366 (attr == &sensor_dev_attr_power1_average.dev_attr.attr)) 3367 return 0; 3368 3369 /* hide max/min values if we can't both query and manage the fan */ 3370 if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) && 3371 (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) && 3372 (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3373 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) && 3374 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 3375 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 3376 return 0; 3377 3378 if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) && 3379 (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) && 3380 (attr == &sensor_dev_attr_fan1_max.dev_attr.attr || 3381 attr == &sensor_dev_attr_fan1_min.dev_attr.attr)) 3382 return 0; 3383 3384 if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ 3385 adev->family == AMDGPU_FAMILY_KV) && /* not implemented yet */ 3386 (attr == &sensor_dev_attr_in0_input.dev_attr.attr || 3387 attr == &sensor_dev_attr_in0_label.dev_attr.attr)) 3388 return 0; 3389 3390 /* only APUs have vddnb */ 3391 if (!(adev->flags & AMD_IS_APU) && 3392 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 3393 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 3394 return 0; 3395 3396 /* no mclk on APUs */ 3397 if ((adev->flags & AMD_IS_APU) && 3398 (attr == &sensor_dev_attr_freq2_input.dev_attr.attr || 3399 attr == &sensor_dev_attr_freq2_label.dev_attr.attr)) 3400 return 0; 3401 3402 /* only SOC15 dGPUs support hotspot and mem temperatures */ 3403 if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) && 3404 (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || 3405 attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || 3406 attr == &sensor_dev_attr_temp3_crit.dev_attr.attr || 3407 attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || 3408 attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || 3409 attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || 3410 attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr || 3411 attr == &sensor_dev_attr_temp2_input.dev_attr.attr || 3412 attr == &sensor_dev_attr_temp3_input.dev_attr.attr || 3413 attr == &sensor_dev_attr_temp2_label.dev_attr.attr || 3414 attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) 3415 return 0; 3416 3417 /* only Vangogh has fast PPT limit and power labels */ 3418 if (!(gc_ver == IP_VERSION(10, 3, 1)) && 3419 (attr == &sensor_dev_attr_power2_average.dev_attr.attr || 3420 attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || 3421 attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || 3422 attr == &sensor_dev_attr_power2_cap.dev_attr.attr || 3423 attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr || 3424 attr == &sensor_dev_attr_power2_label.dev_attr.attr)) 3425 return 0; 3426 3427 return effective_mode; 3428 } 3429 3430 static const struct attribute_group hwmon_attrgroup = { 3431 .attrs = hwmon_attributes, 3432 .is_visible = hwmon_attributes_visible, 3433 }; 3434 3435 static const struct attribute_group *hwmon_groups[] = { 3436 &hwmon_attrgroup, 3437 NULL 3438 }; 3439 3440 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 3441 { 3442 int ret; 3443 uint32_t mask = 0; 3444 3445 if (adev->pm.sysfs_initialized) 3446 return 0; 3447 3448 INIT_LIST_HEAD(&adev->pm.pm_attr_list); 3449 3450 if (adev->pm.dpm_enabled == 0) 3451 return 0; 3452 3453 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 3454 DRIVER_NAME, adev, 3455 hwmon_groups); 3456 if (IS_ERR(adev->pm.int_hwmon_dev)) { 3457 ret = PTR_ERR(adev->pm.int_hwmon_dev); 3458 dev_err(adev->dev, 3459 "Unable to register hwmon device: %d\n", ret); 3460 return ret; 3461 } 3462 3463 switch (amdgpu_virt_get_sriov_vf_mode(adev)) { 3464 case SRIOV_VF_MODE_ONE_VF: 3465 mask = ATTR_FLAG_ONEVF; 3466 break; 3467 case SRIOV_VF_MODE_MULTI_VF: 3468 mask = 0; 3469 break; 3470 case SRIOV_VF_MODE_BARE_METAL: 3471 default: 3472 mask = ATTR_FLAG_MASK_ALL; 3473 break; 3474 } 3475 3476 ret = amdgpu_device_attr_create_groups(adev, 3477 amdgpu_device_attrs, 3478 ARRAY_SIZE(amdgpu_device_attrs), 3479 mask, 3480 &adev->pm.pm_attr_list); 3481 if (ret) 3482 return ret; 3483 3484 adev->pm.sysfs_initialized = true; 3485 3486 return 0; 3487 } 3488 3489 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 3490 { 3491 if (adev->pm.int_hwmon_dev) 3492 hwmon_device_unregister(adev->pm.int_hwmon_dev); 3493 3494 amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list); 3495 } 3496 3497 /* 3498 * Debugfs info 3499 */ 3500 #if defined(CONFIG_DEBUG_FS) 3501 3502 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m, 3503 struct amdgpu_device *adev) { 3504 uint16_t *p_val; 3505 uint32_t size; 3506 int i; 3507 uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev); 3508 3509 if (amdgpu_dpm_is_cclk_dpm_supported(adev)) { 3510 p_val = kcalloc(num_cpu_cores, sizeof(uint16_t), 3511 GFP_KERNEL); 3512 3513 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK, 3514 (void *)p_val, &size)) { 3515 for (i = 0; i < num_cpu_cores; i++) 3516 seq_printf(m, "\t%u MHz (CPU%d)\n", 3517 *(p_val + i), i); 3518 } 3519 3520 kfree(p_val); 3521 } 3522 } 3523 3524 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 3525 { 3526 uint32_t mp1_ver = adev->ip_versions[MP1_HWIP][0]; 3527 uint32_t gc_ver = adev->ip_versions[GC_HWIP][0]; 3528 uint32_t value; 3529 uint64_t value64 = 0; 3530 uint32_t query = 0; 3531 int size; 3532 3533 /* GPU Clocks */ 3534 size = sizeof(value); 3535 seq_printf(m, "GFX Clocks and Power:\n"); 3536 3537 amdgpu_debugfs_prints_cpu_info(m, adev); 3538 3539 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 3540 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 3541 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 3542 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 3543 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 3544 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 3545 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 3546 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 3547 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 3548 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 3549 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 3550 seq_printf(m, "\t%u mV (VDDNB)\n", value); 3551 size = sizeof(uint32_t); 3552 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) 3553 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 3554 size = sizeof(value); 3555 seq_printf(m, "\n"); 3556 3557 /* GPU Temp */ 3558 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 3559 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 3560 3561 /* GPU Load */ 3562 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 3563 seq_printf(m, "GPU Load: %u %%\n", value); 3564 /* MEM Load */ 3565 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size)) 3566 seq_printf(m, "MEM Load: %u %%\n", value); 3567 3568 seq_printf(m, "\n"); 3569 3570 /* SMC feature mask */ 3571 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size)) 3572 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64); 3573 3574 /* ASICs greater than CHIP_VEGA20 supports these sensors */ 3575 if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) { 3576 /* VCN clocks */ 3577 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) { 3578 if (!value) { 3579 seq_printf(m, "VCN: Disabled\n"); 3580 } else { 3581 seq_printf(m, "VCN: Enabled\n"); 3582 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3583 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3584 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3585 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3586 } 3587 } 3588 seq_printf(m, "\n"); 3589 } else { 3590 /* UVD clocks */ 3591 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 3592 if (!value) { 3593 seq_printf(m, "UVD: Disabled\n"); 3594 } else { 3595 seq_printf(m, "UVD: Enabled\n"); 3596 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 3597 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 3598 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 3599 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 3600 } 3601 } 3602 seq_printf(m, "\n"); 3603 3604 /* VCE clocks */ 3605 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 3606 if (!value) { 3607 seq_printf(m, "VCE: Disabled\n"); 3608 } else { 3609 seq_printf(m, "VCE: Enabled\n"); 3610 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 3611 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 3612 } 3613 } 3614 } 3615 3616 return 0; 3617 } 3618 3619 static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags) 3620 { 3621 int i; 3622 3623 for (i = 0; clocks[i].flag; i++) 3624 seq_printf(m, "\t%s: %s\n", clocks[i].name, 3625 (flags & clocks[i].flag) ? "On" : "Off"); 3626 } 3627 3628 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused) 3629 { 3630 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 3631 struct drm_device *dev = adev_to_drm(adev); 3632 u64 flags = 0; 3633 int r; 3634 3635 if (amdgpu_in_reset(adev)) 3636 return -EPERM; 3637 if (adev->in_suspend && !adev->in_runpm) 3638 return -EPERM; 3639 3640 r = pm_runtime_get_sync(dev->dev); 3641 if (r < 0) { 3642 pm_runtime_put_autosuspend(dev->dev); 3643 return r; 3644 } 3645 3646 if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) { 3647 r = amdgpu_debugfs_pm_info_pp(m, adev); 3648 if (r) 3649 goto out; 3650 } 3651 3652 amdgpu_device_ip_get_clockgating_state(adev, &flags); 3653 3654 seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags); 3655 amdgpu_parse_cg_state(m, flags); 3656 seq_printf(m, "\n"); 3657 3658 out: 3659 pm_runtime_mark_last_busy(dev->dev); 3660 pm_runtime_put_autosuspend(dev->dev); 3661 3662 return r; 3663 } 3664 3665 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info); 3666 3667 /* 3668 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW 3669 * 3670 * Reads debug memory region allocated to PMFW 3671 */ 3672 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf, 3673 size_t size, loff_t *pos) 3674 { 3675 struct amdgpu_device *adev = file_inode(f)->i_private; 3676 size_t smu_prv_buf_size; 3677 void *smu_prv_buf; 3678 int ret = 0; 3679 3680 if (amdgpu_in_reset(adev)) 3681 return -EPERM; 3682 if (adev->in_suspend && !adev->in_runpm) 3683 return -EPERM; 3684 3685 ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size); 3686 if (ret) 3687 return ret; 3688 3689 if (!smu_prv_buf || !smu_prv_buf_size) 3690 return -EINVAL; 3691 3692 return simple_read_from_buffer(buf, size, pos, smu_prv_buf, 3693 smu_prv_buf_size); 3694 } 3695 3696 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = { 3697 .owner = THIS_MODULE, 3698 .open = simple_open, 3699 .read = amdgpu_pm_prv_buffer_read, 3700 .llseek = default_llseek, 3701 }; 3702 3703 #endif 3704 3705 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 3706 { 3707 #if defined(CONFIG_DEBUG_FS) 3708 struct drm_minor *minor = adev_to_drm(adev)->primary; 3709 struct dentry *root = minor->debugfs_root; 3710 3711 if (!adev->pm.dpm_enabled) 3712 return; 3713 3714 debugfs_create_file("amdgpu_pm_info", 0444, root, adev, 3715 &amdgpu_debugfs_pm_info_fops); 3716 3717 if (adev->pm.smu_prv_buffer_size > 0) 3718 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root, 3719 adev, 3720 &amdgpu_debugfs_pm_prv_buffer_fops, 3721 adev->pm.smu_prv_buffer_size); 3722 3723 amdgpu_dpm_stb_debug_fs_init(adev); 3724 #endif 3725 } 3726